Converter valve trigger pulse control method when active signal is abnormal

Abstract

The invention discloses a converter valve trigger pulse control method during active signal abnormity, and relates to the field of power system control. The method comprises the steps that after a valid active signal received by first valve control equipment is changed into an abnormal active signal, an invalid VCEOK signal is sent to a first pole control system, and the first valve control equipment continues to maintain an active state for first preset time and then enters a standby state; after the effective VCEOK signal received by the first pole control system is changed into an invalid VCEOK signal, a bypass signal is sent to the first valve control equipment; the first valve control equipment executes the bypass signal when receiving the bypass signal and sends a corresponding trigger pulse to the thyristor-level loop, and the first preset time is greater than the sum of the first delay time and the effective time of the bypass signal; the first delay time is the time from the time when the effective active signal received by the first valve control equipment becomes the abnormal active signal to the time when the bypass signal is received. And safe and stable operation of a power system can be ensured.

Description

Technical Field

[0001] This application relates to the field of power system control, and in particular to a method for controlling the trigger pulse of a converter valve when an active signal is abnormal. Background Technology

[0002] In a high-voltage direct current (HVDC) transmission control system, the converter valves (composed of thyristor-level circuits) and valve control equipment are core components. Their stable and reliable operation is crucial to the safety and stability of the entire HVDC transmission control system. Two sets of valve control equipment are typically configured. During normal HVDC operation, to prevent both sets from sending trigger pulses and causing triggering disorder in the thyristor-level circuit, only the primary valve control equipment sends trigger pulses to the thyristor-level circuit; the backup valve control equipment does not send trigger pulses. The primary / backup relationship between the two sets of valve control equipment is determined by the higher-level pole control system. Normally, the pole control system sends a valid active signal to one set of valve control equipment; the valve control equipment receiving the valid active signal becomes the primary valve control equipment.

[0003] However, the active signals sent by the polar control system to both valve control devices may malfunction simultaneously. In this case, both valve control devices enter standby mode, and neither sends trigger pulses to the thyristor stage circuit. Consequently, the bypass signal sent by the polar control system to the valve control devices will not be executed by the valve control devices. That is, neither valve control device will send the corresponding trigger pulse to the thyristor stage circuit, leading to unreliable locking of the converter valve and jeopardizing the safe and stable operation of the power system. Summary of the Invention

[0004] The purpose of this application is to provide a converter valve trigger pulse control method when the active signal is abnormal, which can ensure the safe and stable operation of the power system.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a converter valve trigger pulse control method when an active signal is abnormal, applied to a high-voltage direct current (HVDC) transmission control system. The HVDC transmission control system includes a first pole control system, a second pole control system, a first valve control device, a second valve control device, and a thyristor-level circuit. The converter valve trigger pulse control method when an active signal is abnormal includes: The first valve control device receives a valid active signal sent by the first polar control system and is in the active state. The second valve control device receives an invalid active signal sent by the second polar control system and is in the standby state. When the first valve control device is in the active state, it continuously sends trigger pulses to the thyristor stage circuit and sends a valid VCEOK signal to the first polar control system. When the second valve control device is in the standby state, it does not send trigger pulses to the thyristor stage circuit or send an invalid VCEOK signal to the second polar control system. After the valid active signal received by the first valve control device becomes an abnormal active signal, it sends an invalid VCEOK signal to the first polar control system and continues to maintain the active state for a first preset time before entering the standby state. After the valid VCEOK signal received by the first polar control system becomes an invalid VCEOK signal, it sends a bypass signal to the first valve control device. When the first valve control device receives a bypass signal, it executes the bypass signal and sends a corresponding trigger pulse to the thyristor stage circuit. The first preset time is greater than the sum of the first delay time and the effective time of the bypass signal. The first delay time is the time from when the effective active signal received by the first valve control device becomes an abnormal active signal to when the bypass signal is received.

[0006] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a method for controlling the trigger pulse of a converter valve when the active signal is abnormal. When the valid active signal received by the primary valve control device changes to an abnormal active signal, it will not immediately exit the primary state, but will continue to maintain it for a period of time before exiting. During this period, the active valve control device can continue to execute the bypass signal sent by the polar control system, thereby exiting the primary state after the converter valve is reliably locked, ensuring the safe and stable operation of the power system. Furthermore, maintaining the signal for a period of time before exiting also avoids two valve control devices being in the primary state simultaneously. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the architecture of a high-voltage direct current transmission control system according to one embodiment of this application; Figure 2 This is a timing diagram of various signals during the execution of the converter valve trigger pulse control method when the active signal is abnormal, according to one embodiment of this application. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0010] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0011] Reference Figure 1 In a high-voltage direct current transmission control system, there are typically two pole control systems ( Figure 1 Extreme control system 1 and extreme control system 2) and two valve control devices (corresponding to Figure 1 The valve control system 1 and valve control system 2, as well as the thyristor stage circuit, are all connected by optical fiber.

[0012] In order to ensure reliable triggering of the converter valves during DC system operation, the two polar control systems send control signals to their respective valve control devices in real time. These control signals include, but are not limited to, active signals, charging signals, unlocking signals, bypass signals, and CP signals.

[0013] Both valve control devices simultaneously receive control signals from their respective connected polar control systems. Typically, only one polar control system sends a valid active signal to its corresponding valve control device. The valve control device receiving the valid active signal is the primary valve control device, and the other is the backup valve control device. Only the primary valve control device executes other control signals sent by the polar control system and sends corresponding trigger pulses to the thyristor stage circuit. The two valve control devices exchange active signals to confirm each other's operating status. For example, if the primary valve control device sends a valid active signal to the backup valve control device, and the backup valve control device sends an invalid active signal to the primary valve control device, then the primary valve control device can determine that the other is in a backup state, and the backup valve control device can also determine that the other is in a primary state. Both valve control devices also return VCEOK signals to their respective polar control systems. The primary valve control device returns a valid VCEOK signal, and the backup valve control device returns an invalid VCEOK signal.

[0014] The thyristor stage circuit receives trigger pulses (pulse signals) from the master valve control system and simultaneously returns thyristor status information (reporting signals) to the master valve control system.

[0015] Generally speaking, when a valve-controlled device receives an invalid active signal from the polar control system, it is treated as an invalid active signal, that is, it exits the primary state and enters the standby state.

[0016] During normal operation of a high-voltage direct current (HVDC) transmission control system, one of the valve control devices receives a valid active signal from one of the polar control systems and enters a primary state. At this time, the valve control device executes various control commands sent by the polar control system and sends corresponding trigger pulses to the thyristor stage circuit. If the valid active signal suddenly becomes abnormal, the valve control device will exit the primary state and enter a standby state. With both valve control devices in standby state, no valve control device will execute the bypass signal, resulting in unreliable interlocking of the converter valve and jeopardizing the safe and stable operation of the power system.

[0017] To address the aforementioned issues, this application employs a strategy of delayed exit from the primary operating state. That is, when the valid active signal received by the primary valve control device changes to an abnormal active signal, it does not immediately exit the primary operating state but continues to maintain it for a period of time before exiting. During this period, the active valve control device can continue to execute the bypass signal sent by the polar control system, thereby exiting the primary operating state after the converter valve is reliably locked, ensuring the safe and stable operation of the power system. Furthermore, maintaining the state for a period of time before exiting also avoids two valve control devices simultaneously being in the primary operating state. Specifically, please refer to the description of the converter valve trigger pulse control method when the active signal is abnormal in the embodiments of this application.

[0018] In an exemplary embodiment, a converter valve trigger pulse control method is provided when an active signal is abnormal. This method is applied to a high-voltage direct current (HVDC) transmission control system. The HVDC transmission control system includes a first pole control system, a second pole control system, a first valve control device, a second valve control device, and a thyristor-level circuit. The converter valve trigger pulse control method when an active signal is abnormal includes: Step 110: The first valve control device receives a valid active signal sent by the first polar control system and thus enters the active state; the second valve control device receives an invalid active signal sent by the second polar control system and thus enters the standby state. During the active state, the first valve control device continuously sends trigger pulses to the thyristor stage circuit and sends a valid VCEOK signal to the first polar control system. During the standby state, the second valve control device does not send trigger pulses to the thyristor stage circuit or send an invalid VCEOK signal to the second polar control system.

[0019] Step 120: After the valid active signal received by the first valve control device becomes an abnormal active signal, it sends an invalid VCEOK signal to the first polar control system and continues to maintain the active state for a first preset time before entering the standby state.

[0020] Step 130: After the valid VCEOK signal received by the first polar control system becomes an invalid VCEOK signal, a bypass signal is sent to the first valve control device.

[0021] Step 140: When the first valve control device receives the bypass signal, it executes the bypass signal and sends a corresponding trigger pulse to the thyristor stage circuit. The first preset time is greater than the sum of the first delay time and the effective time of the bypass signal. The first delay time is the time from when the effective active signal received by the first valve control device becomes an abnormal active signal to when the bypass signal is received.

[0022] Preferably, after the valid active signal received by the first valve control device becomes an abnormal active signal, it sends an invalid VCEOK signal to the first polar control system. Specifically, this includes: immediately sending an invalid VCEOK signal to the first polar control system after the valid active signal received by the first valve control device becomes an abnormal active signal.

[0023] After the valid VCEOK signal received by the first polar control system becomes an invalid VCEOK signal, it sends a bypass signal to the first valve control device. Specifically, after the valid VCEOK signal received by the first polar control system becomes an invalid VCEOK signal, it immediately sends a bypass signal to the first valve control device.

[0024] Sending immediately can shorten the first preset time as much as possible, avoid the first valve control device from remaining in the active state for a long time, and reduce the probability or time that both valve control devices are in the active state at the same time.

[0025] Specifically, the formula for calculating the first preset time is: T1 = Δ1 + (T2 - T1) + Δ3; where T1 is the first preset time, Δ1 is the first delay time, T1 and T2 are the effective time and effective time of the bypass signal, and Δ3 is the time margin.

[0026] The above describes the handling steps for an abnormal active signal when the first valve control device acts as the primary valve control device. Correspondingly, the converter valve trigger pulse control method for abnormal active signals also includes: Step 210: The second valve control device receives a valid active signal sent by the second polar control system and thus enters the active state; the first valve control device receives an invalid active signal sent by the first polar control system and thus enters the standby state; during the active state, the second valve control device continuously sends trigger pulses to the thyristor stage circuit and sends a valid VCEOK signal to the second polar control system; during the standby state, the first valve control device does not send trigger pulses to the thyristor stage circuit or send an invalid VCEOK signal to the first polar control system. Step 220: After the valid active signal received by the second valve control device becomes an abnormal active signal, it sends an invalid VCEOK signal to the second polar control system and continues to maintain the main state for a second preset time before entering the standby state. Step 230: After the valid VCEOK signal received by the second polar control system becomes an invalid VCEOK signal, a bypass signal is sent to the second valve control device. Step 240: When the second valve control device receives the bypass signal, it executes the bypass signal and sends a corresponding trigger pulse to the thyristor stage circuit. The second preset time is greater than the sum of the second delay time and the effective time of the bypass signal. The second delay time is the time from when the effective active signal received by the second valve control device becomes an abnormal active signal to when the bypass signal is received.

[0027] Preferably, after the valid active signal received by the second valve control device becomes an abnormal active signal, it sends an invalid VCEOK signal to the second polar control system. Specifically, this includes: immediately sending an invalid VCEOK signal to the second polar control system after the valid active signal received by the second valve control device becomes an abnormal active signal. After the valid VCEOK signal received by the second polar control system becomes an invalid VCEOK signal, it sends a bypass signal to the second valve control device. Specifically, this includes: immediately sending a bypass signal to the second valve control device after the valid VCEOK signal received by the second polar control system becomes an invalid VCEOK signal.

[0028] Sending immediately can shorten the second preset time as much as possible, avoid the first valve control device from continuing to be in the main operation state for a long time, and reduce the probability or time that both valve control devices are in the main operation state at the same time.

[0029] Specifically, the formula for calculating the second preset time is: T2 = Δ2 + (T2 - T1) + Δ3; where T2 is the second preset time, Δ2 is the second delay time, T1 and T2 are the effective time and duration of the bypass signal, and Δ3 is the time margin.

[0030] If the signal transmission time between the first valve control device and the first polar control system is exactly the same as the signal transmission time between the second valve control device and the second polar control system, then the same first preset time and second preset time can be set.

[0031] Generally, the transmission delay between the valve-controlled device and the polarity control system is relatively low, meaning the first and second delay times are relatively small. This is because the effective duration of the bypass signal dominates within the first and second preset times, and this effective duration is typically greater than one transmission cycle of the trigger pulse but less than two transmission cycles. To improve fault tolerance, a time margin is set to round up to two transmission cycles of the trigger pulse. Therefore, preferably, the first and second preset times include at least two transmission cycles of the trigger pulse.

[0032] For example, if the first delay time and the second delay time are both 500µs, the effective duration of the bypass signal (T2-T1) is 29ms, and one transmission cycle of the trigger signal is 20ms, then the first preset time and the second preset time can both be set to 40ms.

[0033] Specifically, valid active signals, invalid active signals, and abnormal active signals are distinguished by frequency and are all optically modulated signals. The frequency of valid active signals is a first frequency, the frequency of invalid active signals is a second frequency, and active signals other than the first and second frequencies are abnormal active signals. The first frequency is different from the second frequency. For example, the first frequency is 1MHz and the second frequency is 10kHz.

[0034] For example, refer to Figure 2 ,exist Figure 2 In the diagram: Polar control system 1 is the first polar control system, polar control system 2 is the second polar control system, valve control system 1 is the first valve control device, and valve control system 2 is the second valve control device. Figure 2 This example demonstrates how the various signals change when a valid active signal becomes abnormal.

[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0036] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An active signal abnormality commutation voltage valve trigger pulse control method applied to a high voltage direct current transmission control system, the high voltage direct current transmission control system comprising a first pole control system, a second pole control system, a first valve control device, a second valve control device, and a thyristor level loop, characterized in that, The active signal abnormality time thyristor trigger pulse control method comprises: The first valve control device receives the valid active signal sent by the first pole control system to be in a main state, the second valve control device receives the invalid active signal sent by the second pole control system to be in a standby state, the first valve control device continuously sends trigger pulses to the thyristor level loop and sends a valid VCEOK signal to the first pole control system during the main state, and the second valve control device does not send trigger pulses to the thyristor level loop and sends an invalid VCEOK signal to the second pole control system during the standby state; After the valid active signal received by the first valve control device becomes an abnormal active signal, the first valve control device sends an invalid VCEOK signal to the first pole control system and continues to maintain the main state for a first preset time and then enters the standby state; After the valid VCEOK signal received by the first pole control system becomes an invalid VCEOK signal, the first pole control system sends a side communication signal to the first valve control device; The first valve control device executes the side communication signal and sends corresponding trigger pulses to the thyristor level loop when the side communication signal is received, the first preset time is greater than the sum of a first delay time and the effective time of the side communication signal, and the first delay time is the time from when the valid active signal received by the first valve control device becomes the abnormal active signal to when the side communication signal is received.

2. The active signal abnormality commutation inverter valve trigger pulse control method of claim 1, characterized by, After the valid active signal received by the first valve control device becomes an abnormal active signal, the first valve control device sends an invalid VCEOK signal to the first pole control system, specifically comprising: The first valve control device sends an invalid VCEOK signal to the first pole control system immediately after the valid active signal received by the first valve control device becomes an abnormal active signal; After the valid VCEOK signal received by the first pole control system becomes an invalid VCEOK signal, the first pole control system sends a side communication signal to the first valve control device, specifically comprising: The first pole control system sends a side communication signal to the first valve control device immediately after the valid VCEOK signal received by the first pole control system becomes an invalid VCEOK signal.

3. The active signal abnormality commutation inverter valve trigger pulse control method of claim 1, characterized by, The active signal abnormality time thyristor trigger pulse control method further comprises: The second valve control device receives the valid active signal sent by the second pole control system to be in a main state, the first valve control device receives the invalid active signal sent by the first pole control system to be in a standby state, the second valve control device continuously sends trigger pulses to the thyristor level loop and sends a valid VCEOK signal to the second pole control system during the main state, and the first valve control device does not send trigger pulses to the thyristor level loop and sends an invalid VCEOK signal to the first pole control system during the standby state; After the valid active signal received by the second valve control device becomes an abnormal active signal, the second valve control device sends an invalid VCEOK signal to the second pole control system and continues to maintain the main state for a second preset time and then enters the standby state; After the valid VCEOK signal received by the second pole control system becomes an invalid VCEOK signal, the second pole control system sends a side communication signal to the second valve control device; The second valve control device executes the side communication signal and sends corresponding trigger pulses to the thyristor level loop when the side communication signal is received, the second preset time is greater than the sum of a second delay time and the effective time of the side communication signal, and the second delay time is the time from when the valid active signal received by the second valve control device becomes the abnormal active signal to when the side communication signal is received. The second valve control device executes the side communication signal and sends a corresponding trigger pulse to the thyristor level circuit when receiving the side communication signal, the second preset time is greater than the sum of a second delay time and an effective time of the side communication signal, and the second delay time is a time from when the effective active signal received by the second valve control device becomes an abnormal active signal to when the side communication signal is received.

4. The method of claim 3, wherein the method further comprises: The second valve control device sends an invalid VCEOK signal to the second pole control system after the effective active signal received by the second valve control device becomes the abnormal active signal, and specifically includes: The second valve control device sends an invalid VCEOK signal to the second pole control system immediately after the effective active signal received by the second valve control device becomes the abnormal active signal. The second pole control system sends a side communication signal to the second valve control device after the effective VCEOK signal received by the second pole control system becomes the invalid VCEOK signal, and specifically includes: The second pole control system sends a side communication signal to the second valve control device immediately after the effective VCEOK signal received by the second pole control system becomes the invalid VCEOK signal.

5. The method of claim 2, wherein the method further comprises: The calculation formula of the first preset time is T1=Δ1+(T2-T1)+Δ3. Wherein, T1 is the first preset time, Δ1 is the first delay time, T1 and T2 are the effective time and time limit of the side communication signal, and Δ3 is the time margin.

6. The method of claim 4, wherein the method further comprises: The calculation formula of the second preset time is T2=Δ2+(T2-T1)+Δ3. Wherein, T2 is the second preset time, Δ2 is the second delay time, T1 and T2 are the effective time and time limit of the side communication signal, and Δ3 is the time margin.

7. The method according to claim 5 or 6, characterized in that The first preset time and the second preset time include at least two emission periods of the trigger pulse.

8. The active signal abnormality commutation inverter valve trigger pulse control method of claim 1, wherein, The effective active signal, the invalid active signal and the abnormal active signal are distinguished according to frequency and are all optical modulation signals.

9. The method of claim 8, wherein the method further comprises: The frequency of the effective active signal is a first frequency, the frequency of the invalid active signal is a second frequency, and active signals other than the first frequency and the second frequency are the abnormal active signals, and the first frequency is different from the second frequency.

10. The method of claim 9, wherein the method further comprises: The first frequency is 1MH, and the second frequency is 10kHz.

Images