Ultra-low power consumption body-driven four-stage differential operation transconductance amplifier

Abstract

The invention discloses an ultra-low power consumption body-driven four-stage differential operation transconductance amplifier, which belongs to the technical field of CMOS (Complementary Metal Oxide Semiconductor) analog integrated circuits, and comprises a biasing circuit, a body-driven differential input circuit, a composite differential amplification circuit, a frequency compensation circuit and a common-mode feedback circuit. The bias circuit provides stable bias under the ultra-low voltage of 0.3 V; the body-driven differential input circuit takes a PMOS tube body end as a differential signal input end, and improves equivalent transconductance in combination with a cross positive feedback structure; the composite differential amplification circuit realizes signal multi-stage amplification and rail-to-rail output through a two-stage differential common-source amplification unit and a feedforward AB type output unit; the frequency compensation circuit optimizes the frequency stability in a mode of combining a Miller capacitor and an RC (Resistance-Capacitance) compensation network; and the common-mode feedback circuit stably outputs a common-mode level. The amplifier is suitable for ultra-low power consumption application scenes such as implantable medical electronics and wearable equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of CMOS integrated circuits, and particularly relates to a bulk-driven four-stage differential operational transconductance amplifier suitable for ultra-low voltage and ultra-low power consumption applications. BACKGROUND

[0002] With the rapid development of the Internet of Things, wearable devices and implantable medical electronics, ultra-low power analog front-end circuits have become a research hotspot. However, under the background of the increasing requirements of low-power electronic devices on power voltage and energy efficiency, the design of operational transconductance amplifiers faces multiple constraints. The existing mainstream technical solutions have obvious shortcomings: for example, the differential pair transistor driven by the traditional gate needs at least one threshold voltage plus an overdrive voltage, and it is difficult to work normally at low voltage; the operational transconductance amplifier driven by a single-stage gain has low gain, and it is difficult to balance the design requirements of high gain and wide bandwidth, limiting its applicability in high-performance signal processing applications; and although the multi-stage gain driving structure can improve the gain, the traditional cascade gain enhancement technology has limited effect on the improvement of bandwidth under low voltage working conditions, and the overall frequency response efficiency is low. In addition, current mirrors or tail current source structures are often used in existing solutions to improve gain and stability, but under sub-threshold and ultra-low voltage working modes, insufficient bias current leads to degradation of transconductance characteristics and decrease of common-mode stability, affecting the linearity and energy efficiency of the system. Especially in low-voltage and low-power consumption application scenarios, the traditional operational transconductance amplifier based on gate driving is difficult to achieve a good balance between gain, bandwidth and power consumption. Therefore, the existing technology generally has the problem of being difficult to simultaneously balance high gain, wide bandwidth and low power consumption under low voltage conditions, and there is an urgent need for an operational transconductance amplifier structure that can achieve high gain, high stability and low power consumption under ultra-low voltage.

[0003] The prior art

Ferreira, IEEE TCAS2 2007

[0004] The existing operational transconductance amplifier generally faces the technical bottleneck of being difficult to balance high gain, wide frequency stability and ultra-low power consumption in the application scenario of ultra-low voltage: the traditional gate driving structure cannot work normally due to the threshold voltage limitation, the two-stage amplification architecture is insufficient in gain, the multi-stage architecture causes insufficient phase margin due to pole superposition, and the design of level shifting unit and single frequency compensation further causes problems such as operating point drift and poor dynamic response, which is difficult to meet the comprehensive performance requirements of analog front end such as ultra-low power consumption, high gain, high stability and rail-to-rail output for Internet of Things edge nodes, wearable health monitoring devices and implantable medical electronics.

[0005] Therefore, there is an urgent need for an operational transconductance amplifier capable of stable operation at ultra-low voltage, realizing high DC gain, wide phase margin, rail-to-rail output dynamic range and nanowatt-level power consumption, to adapt to application scenarios such as implantable electrocardio / electroencephalogram signal acquisition, ultra-low power sensor interface, energy harvesting system analog front end, which have strict requirements on circuit performance and energy efficiency. SUMMARY

[0006] Based on the above technical problems, the application discloses an ultra-low power body-driven four-stage differential operational transconductance amplifier, comprising a bias circuit, a body-driven differential input circuit, a composite differential amplification circuit, a frequency compensation circuit and a common-mode feedback circuit.

[0007] The bias circuit provides stable bias voltage for each circuit, sets a common-mode voltage input port VB1, output ports VB2 and VB3; the common-mode voltage input port VB1 of the bias circuit and the voltage input port Vop of the common-mode feedback circuit are both connected to the common-mode voltage VDD / 2.

[0008] The body-driven differential input circuit takes the bulk terminal (Bulk) of the PMOS tube as the differential signal input terminals Vin+ and Vin-, and adopts a cross positive feedback structure to improve the equivalent transconductance, sets differential signal input ports Vin+, Vin-, input ports a and b, and output ports c and c'.

[0009] The composite differential amplification circuit further amplifies the output signal of the body-driven differential input circuit through a two-stage differential common-source amplification unit, and the output stage adopts a feedforward AB class output unit, which is connected to the input terminal of the two-stage differential common-source amplification unit by connecting the gate of the output unit PMOS tube to the input terminal, realizes rapid response to input changes, and realizes rail-to-rail differential output at the same time, sets input ports d, d' and e, and differential signal output ports Vout+ and Vout-.

[0010] The frequency compensation circuit realizes stable frequency compensation by combining the Miller capacitor connected across the input and output terminals of the composite differential amplification circuit and the RC compensation network connected in parallel at the output terminal of the differential common-source amplification unit.

[0011] The common-mode feedback circuit is used for stabilizing the output common-mode level, and sets a voltage input port Vop, input ports f and f', and an output port g;

[0012] The body-driven differential input circuit input port a is connected with the bias circuit output port VB2, the body-driven differential input circuit input port b is connected with the common-mode feedback circuit output port g, the body-driven differential input circuit output port c is connected with the composite differential amplification circuit input port d, and the body-driven differential input circuit output port c' is connected with the composite differential amplification circuit input port d';

[0013] The composite differential amplification circuit input port e is connected with the bias circuit output port VB3, the composite differential amplification circuit differential signal output port Vout+ is connected with the common-mode feedback circuit input port f, and the composite differential amplification circuit differential signal output port Vout- is connected with the common-mode feedback circuit input port f'.

[0014] Preferably, the bias circuit comprises a current source IB, a PMOS tube MB3, an NMOS tube MB1, and an NMOS tube MB2.

[0015] The bias circuit comprises ports VB1, VB2, and VB3.

[0016] The NMOS tube MB1 and the NMOS tube MB2 form a current mirror, and the gate and the drain of the MB3 are connected to realize a diode characteristic.

[0017] The bias circuit provides stable bias at 0.3V ultra-low voltage through bulk voltage modulation and current mirror replication.

[0018] The drain and the gate of the NMOS tube MB1 are connected with the gate of the NMOS tube MB2 and one end of the current source IB, to form the port VB3 of the bias circuit; the bulk of the PMOS tube MB3 serves as the common-mode voltage input port VB1 of the bias circuit; the drain and the gate of the PMOS tube MB3 are connected with the drain of the NMOS tube MB2, to form the port VB2 of the bias circuit; the other end of the current source IB and the source of the PMOS tube MB3 are both connected with a power supply voltage VDD; and the sources of the NMOS tubes MB1 and MB2 are both grounded.

[0019] Preferably, the body-driven differential input circuit comprises a body-driven unit, a cross local positive feedback unit, and a current mirror load unit.

[0020] The body-driven differential input circuit comprises ports Vin+, Vin-, a, b, c, and c'.

[0021] The body driving unit comprises PMOS tube M1 and PMOS tube M2, the bulk of the M1 constitutes a positive input terminal Vin+, and the bulk of the M2 constitutes a negative input terminal Vin-; the gates of the PMOS tubes M1 and M2 are commonly connected to a bias port a, and the sources are connected to VDD;

[0022] The NMOS tubes M3, M4, M5, M6, PMOS tubes M7 and M8 constitute a current mirror load unit, the gates of the PMOS tubes M7 and M8 are connected to constitute a bias port b, and the sources are connected to VDD; the drains of the NMOS tube M5 and the PMOS tube M7 are connected to constitute an output terminal c, and the drains of the NMOS tube M6 and the PMOS tube M8 are connected to constitute an output terminal c'; the drain of the PMOS tube M1 is connected to the drain and gate of the NMOS tube M3, and the drain of the PMOS tube M2 is connected to the drain and gate of the NMOS tube M4, so that the NMOS tubes M3 and M4 constitute a diode load; the sources of the NMOS tubes M3, M4, M5 and M6 are grounded.

[0023] Preferably, the cross local positive feedback unit comprises NMOS tube MX1 and NMOS tube MX2, the gate of the MX1 is connected to the drain of the M2, and the drain is connected to the drain of the M1; the gate of the MX2 is connected to the drain of the M1, and the drain is connected to the drain of the M2; the sources of the MX1 and MX2 are grounded; the two are cross-connected to form a local positive feedback, which improves the equivalent transconductance of the input stage; the gates of the NMOS tubes M5 and M6 are connected to the gates of the M3 and M4 respectively to constitute a current mirror copy, and the gate and drain of the NMOS tubes M3 and M4 are short-circuited.

[0024] Preferably, the composite differential amplification circuit comprises a two-stage differential common-source amplification unit and a feed-forward AB class output unit.

[0025] The composite differential amplification circuit comprises ports d, d', e, Vout+, and Vout-.

[0026] The two-stage differential common-source amplification unit comprises PMOS tube M9, PMOS tube M10, PMOS tube M13, PMOS tube M14, NMOS tube M11, NMOS tube M12, NMOS tube M15, and NMOS tube M16, which further amplify the output signal of the body driving differential input circuit through cascading.

[0027] The input port d of the composite differential amplification circuit is composed of the connection of the gate of the PMOS M9 and the gate of the PMOS M17; the drain of the PMOS M9, the drain of the NMOS M11 and the gate of the PMOS M13 are connected; the drain of the PMOS M13, the drain of the NMOS M15 and the gate of the NMOS M19 are connected; the input port e of the composite differential amplification circuit is composed of the connection of the gate of the NMOS M11, the gate of the NMOS M12, the gate of the NMOS M15 and the gate of the NMOS M16; the sources of the NMOS M11, M15, M19 are grounded; the sources of the PMOS M9, M13, M17 are connected to the power supply voltage VDD.

[0028] Preferably, the feedforward AB class output unit includes the PMOS M17, the PMOS M18, the NMOS M19, the NMOS M20, the capacitor CL1 and the capacitor CL2; the gates of the PMOS M17 and the PMOS M18 are connected to the input node of the two-stage differential common-source amplification unit in a feedforward manner, so that the output stage can quickly respond to the input voltage change when the input changes;

[0029] The input port d' of the composite differential amplification circuit is composed of the connection of the gate of the PMOS M10 and the gate of the PMOS M18; the drain of the PMOS M10, the drain of the NMOS M12 and the gate of the PMOS M14 are connected; the drain of the PMOS M14, the drain of the NMOS M16 and the gate of the NMOS M20 are connected; the output port Vout+ of the composite differential amplification circuit is composed of the connection of the drain of the PMOS M17, the drain of the NMOS M19 and one end of the capacitor CL1; the other end of the capacitor CL1 is grounded; the output port Vout- of the composite differential amplification circuit is composed of the connection of the drain of the PMOS M18, the drain of the NMOS M20 and one end of the capacitor CL2; the sources of the NMOS M12, M16, M20 are grounded; the other end of the capacitor CL2 is grounded; the sources of the PMOS M10, M14, M18 are connected to the power supply voltage VDD.

[0030] Preferably, the frequency compensation circuit includes the capacitors CC1, CC2, CC3, CC4 and the resistors RC1, RC2.

[0031] The capacitors CC3 and CC4 are Miller compensation capacitors, which disperse the poles of the amplifier, so that the output pole of the first stage becomes the dominant pole, avoiding the superposition with other poles to cause phase mutation, thereby reserving sufficient phase margin for the circuit stability;

[0032] The compensation capacitor CC3 is connected between the input end d of the composite differential amplification circuit and the output end Vout+; the compensation capacitor CC4 is connected between the input end d' of the composite differential amplification circuit and the output end Vout-; one end of the resistor RC1 is connected with the drain of the NMOS tube M15; one end of the resistor RC2 is connected with the drain of the NMOS tube M16; the other end of the resistor RC1 is connected with one end of the capacitor CC1; the other end of the resistor RC2 is connected with one end of the capacitor CC2; the other end of the capacitor CC1 is grounded; and the other end of the capacitor CC2 is grounded.

[0033] Preferably, the capacitors CC1 and CC2 and the resistors RC1 and RC2 are connected in series respectively to offset the high-frequency zero point introduced by the main Miller capacitor, eliminate the phase margin loss, and make the circuit still equivalent to a two-stage amplification system within the working bandwidth; the RC compensation network formed by the resistors RC1 and CC1 and the resistors RC2 and CC2 cooperates with the Miller compensation capacitor to realize frequency stability optimization.

[0034] Preferably, the common-mode feedback circuit comprises an operational amplifier OPAMP.

[0035] The common-mode feedback circuit comprises ports Vop, f, f' and g.

[0036] The input ports of the operational amplifier OPAMP form the voltage input port Vop, the input ports f and f' of the common-mode feedback circuit; the output port g of the common-mode feedback circuit is formed by the output port of the operational amplifier OPAMP; and the differential signal output ports Vout+ and Vout- of the composite differential amplification circuit are connected with the input ports f and f' of the common-mode feedback circuit respectively, so as to realize common-mode detection of the output signal.

[0037] Preferably, the common-mode feedback circuit transmits the output end signal and the common-mode voltage to the gate of the PMOS tube M7 and the gate of the PMOS tube M8 of the bulk-driven differential input circuit through the operational amplifier, so that the voltages of the two are embedded in VDD / 2; the current mirror load unit of the bulk-driven differential input circuit is adjusted through negative feedback, the output common-mode level is stabilized, and the linearity of the circuit is ensured.

[0038] Compared with the prior art, the technical scheme of the application has the following technical effects:

[0039] The application realizes stable biasing under low-voltage condition through the biasing circuit, the reference current I B is transmitted to the PMOS tube connected with the diode through the current mirror, so as to automatically adjust the gate voltage, thereby maintaining stable biasing characteristics under ultra-low-voltage condition and improving the energy efficiency and consistency of the system.

[0040] The body driving input circuit of the application receives differential input signals through a body terminal, reduces the effective threshold voltage, realizes input amplification in a sub-threshold working zone and generates a differential output current, combines a cross local positive feedback structure to enhance the equivalent transconductance of the input stage, and compared with the traditional body driving, the transconductance can be increased by 2-3 times, and the first stage amplification gain is significantly improved; meanwhile, the current mirror load is used to replace the traditional tail current source structure to ensure the stability of the static working point under low voltage. Two-stage differential common source amplification units are connected after the input stage to realize high gain amplification and provide sufficient driving capability; the AB class bias structure is used at the output end to ensure that the output swing covers the full rail voltage range, and the PMOS gate of the output tube is connected to the intermediate stage input node through feedforward to realize fast response to input changes, thereby improving the transient characteristics.

[0041] The above description is only a summary of the technical solutions of the application. In order to more clearly understand the technical means of the application, the contents of the description can be implemented, and in order to make the above and other purposes, features and advantages of the application more obvious and easy to understand, the following will be described in detail with the preferred embodiments of the application and with the help of the accompanying drawings.

[0042] According to the detailed description of the specific embodiments of the application in the following text combined with the accompanying drawings, those skilled in the art will more clearly understand the above and other purposes, advantages and features of the application. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual proportion.

[0044] According to the description of the drawings in the document and the corresponding technical content, the titles of the drawings are as follows:

[0045] Figure 1 It is a schematic diagram of the ultra-low power body driving four-stage differential operational transconductance amplifier circuit of the application.

[0046] Figure 2 It is a schematic diagram of the small signal model equivalent circuit structure under the differential input signal of the application.

[0047] Figure 3 It is a schematic diagram of the frequency response comparison of the open loop gain and phase margin of the layout of the application.

[0048] Figure 4 It is a schematic diagram of the equivalent input noise spectrum characteristic of the input end of the application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0050] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0051] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0052] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0053] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0054] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0055] Embodiment 1

[0056] This embodiment mainly describes an ultra-low power bulk-driven four-stage differential operational transconductance amplifier, as shown in the figure, which comprises a bias circuit, a bulk-driven differential input circuit, a composite differential amplification circuit, a frequency compensation circuit and a common-mode feedback circuit. Figure 1

[0057] The bulk-driven differential input circuit takes the bulk terminals of PMOS transistors as differential signal input terminals V in + and V in - respectively, and adopts a cross positive feedback structure to improve the equivalent transconductance, and sets differential signal input ports V in +, V in -, input ports a, b and output ports c, c'.

[0058] The composite differential amplification circuit further amplifies the output signal of the bulk-driven differential input circuit through a two-stage differential common-source amplification unit, and the output stage adopts a feed-forward AB class output unit, which is connected to the input terminal of the two-stage differential common-source amplification unit by connecting the gate of the output unit PMOS transistor to the input terminal of the two-stage differential common-source amplification unit, so as to realize rapid response to input changes and rail-to-rail differential output, and sets input ports d, d', e, differential signal output ports V out +, V out -.

[0059] The frequency compensation circuit realizes stable frequency compensation by combining the Miller capacitor connected across the input and output terminals of the composite differential amplification circuit and the RC compensation network connected in parallel at the output terminal of the differential common-source amplification unit.

[0060] The common-mode feedback circuit is used to stabilize the output common-mode level, and sets a voltage input port V op , input ports f, f' and an output port g.

[0061] The bias circuit provides stable bias voltage for each stage of circuit, and sets a common-mode voltage input port V B1 , output ports V B2 , V B3 .

[0062] The input port a of the bulk-driven differential input circuit is connected to the output port V B2 of the bias circuit, the input port b of the bulk-driven differential input circuit is connected to the output port g of the common-mode feedback circuit, the output port c of the bulk-driven differential input circuit is connected to the input port d of the composite differential amplification circuit, and the output port c' of the bulk-driven differential input circuit is connected to the input port d' of the composite differential amplification circuit.

[0063] The input port e of the composite differential amplification circuit is connected to the output port V​B3 Connection, composite differential amplifier circuit differential signal output port V out + and common mode feedback circuit input port f, composite differential amplifier circuit differential signal output port V out - and common mode feedback circuit input port f' connection;

[0064] Bias circuit common mode voltage input port V B1 and common mode feedback circuit voltage input port V op The common mode voltage VDD / 2 is connected to the common mode voltage VDD / 2.

[0065] Further, the bias circuit includes a current source I B , PMOS M B3 , NMOS M B1 , NMOS M B2 ;

[0066] The bias circuit includes port V B1 , V B2 , V B3 ;

[0067] NMOS M B1 and NMOS M B2 form a current mirror; M B3 The gate and drain are connected to realize the diode characteristic;

[0068] The bias circuit provides stable bias at 0.3V ultra-low voltage through body terminal voltage modulation and current mirror replication;

[0069] The drain of NMOS M B1 is connected to the gate of NMOS M B2 and one end of current source I B , forming the port V B3 of the bias circuit; The body terminal of PMOS M B3 serves as the common mode voltage input port V B1 of the bias circuit; The drain of PMOS M B3 is connected to the drain of NMOS M B2 , forming the port V B2 of the bias circuit; The other end of current source I B , the source of PMOS M B3 are connected to the power supply voltage VDD; The sources of NMOS M B1 , M B2 are grounded.

[0070] Further, the body-driven differential input circuit includes a body-driven unit, a cross-local positive feedback unit and a current mirror load unit;

[0071] The body-driven differential input circuit comprises a port V in + and V in -, a, b, c and c';

[0072] The body-driven unit comprises PMOS transistors M1 and M2, the body terminal of M1 constitutes a positive input terminal V in +, and the body terminal of M2 constitutes a negative input terminal V in -; the gates of M1 and M2 are connected to a bias port a, and the sources are connected to VDD;

[0073] The cross local positive feedback unit comprises NMOS transistors M X1 and M X2 , the gate of M X1 is connected to the drain of M2, and the drain is connected to the drain of M1; the gate of M X2 is connected to the drain of M1, and the drain is connected to the drain of M2; the sources of M X1 and M X2 are connected to ground; and the two are cross-connected to form a local positive feedback, which improves the equivalent transconductance of the input stage;

[0074] The current mirror load unit comprises NMOS transistors M3, M4, M5 and M6, and PMOS transistors M7 and M8; the gates of M5 and M6 are connected to the gates of M3 and M4 respectively to form a current mirror copy, and the gate-drain of M3 and M4 is short-circuited; the gates of M7 and M8 are connected to form a bias port b, and the sources are connected to VDD; the drain of M5 is connected to the drain of M7 to form an output terminal c, and the drain of M6 is connected to the drain of M8 to form an output terminal c'; the drain of M1 is connected to the drain and gate of M3, and the drain of M2 is connected to the drain and gate of M4, so that M3 and M4 form a diode load; and the sources of M3, M4, M5 and M6 are connected to ground.

[0075] Further, the composite differential amplification circuit comprises a two-stage differential common-source amplification unit and a feed-forward AB class output unit;

[0076] The two-stage differential common-source amplification unit comprises PMOS transistors M9, M 10 , M 13 , M 14 , NMOS transistors M 11 , M 12 , M 15 , M 16 , which further amplify the output signal of the body-driven differential input circuit in a cascading manner;

[0077] The feedforward AB class output unit comprises a PMOS transistor M 17 , a PMOS transistor M 18 , an NMOS transistor M 19 , an NMOS transistor M 20 , a capacitor C L1 , a capacitor C L2 ; a gate of the PMOS transistor M 17 , a PMOS transistor M 18 is connected to the input node of the two-stage differential common-source amplification unit in a feedforward manner, so that the output stage can quickly respond to the input voltage change when the input changes;

[0078] The composite differential amplification circuit comprises ports d, d', e, V out +, V out -;

[0079] The input port d of the composite differential amplification circuit is composed of the gate of the PMOS transistor M9 and the gate of the PMOS transistor M 17 ; the drain of the PMOS transistor M9, the drain of the NMOS transistor M 11 , and the gate of the PMOS transistor M 13 are connected; the drain of the PMOS transistor M 13 , the drain of the NMOS transistor M 15 , and the gate of the NMOS transistor M 19 are connected; the input port e of the composite differential amplification circuit is composed of the gate of the NMOS transistor M 11 , the gate of the NMOS transistor M 12 , the gate of the NMOS transistor M 15 , and the gate of the NMOS transistor M 16 ; the output port V out + of the composite differential amplification circuit is composed of the drain of the PMOS transistor M 17 , the drain of the NMOS transistor M 19 , and one end of the capacitor C L1 ; the sources of the NMOS transistors M 11 , M 15 , and M 19 are grounded; the other end of the capacitor C L1 is grounded; the sources of the PMOS transistors M9, M 13 , and M 17 are connected to the power supply voltage VDD;

[0080] The input port d' of the composite differential amplification circuit is composed of the gate of the PMOS transistor M 10 and the gate of the PMOS transistor M 18 ; the drain of the PMOS transistor M 10 , the drain of the NMOS transistor M 12 , and the gate of the PMOS transistor M14 Gate connection; PMOS transistor M 14 drain of NMOS transistor M 16 The drain of the NMOS transistor M 20 The gate connection; the output port V of the composite differential amplifier circuit. out -By PMOS transistor M 18 drain of NMOS transistor M 20 The drain and capacitor C L2 One end is connected to form a structure; NMOS transistor M 12 M 16 M 20 The sources of capacitor C are all grounded; L2 The other end is grounded; PMOS transistor M 10 M 14 M 18 The source terminals are all connected to the power supply voltage VDD.

[0081] Furthermore, the frequency compensation circuit includes capacitor C. C1 C C2 C C3 C C4 resistance R C1 R C2 ;

[0082] Capacitor C C3 C C4 The Miller compensation capacitor disperses the poles of the amplifier, making the output pole of the first stage the dominant pole, avoiding the phase change caused by superposition with other poles, thus reserving sufficient phase margin for circuit stability.

[0083] Capacitor C C1 C C2 resistance R C1 R C2 They are connected in series to cancel the high-frequency zeros introduced by the main Miller capacitor, eliminate phase margin loss, and make the circuit equivalent to a two-stage amplification system within the operating bandwidth.

[0084] Compensation capacitor C C3 Connected across the input terminal d and the output terminal V of the composite differential amplifier circuit out Between +; compensation capacitor C C4 Connected across the input terminal d' and the output terminal V of the composite differential amplifier circuit out Between -; resistance R C1 One end is connected to the NMOS transistor M 15 Drain connection; resistor R C2 One end is connected to the NMOS transistor M 16 Drain connection; resistor R C1 The other end is connected to capacitor C C1One end is connected; resistor R C2 The other end is connected to capacitor C C2 One end is connected; capacitor C C1 The other end of capacitor C is grounded; C2 The other end is grounded;

[0085] Furthermore, the common-mode feedback circuit includes an operational amplifier (OPAMP).

[0086] The common-mode feedback circuit transmits the output signal and common-mode voltage to the gates of PMOS transistor M7 and PMOS transistor M8 in the body drive differential input circuit through the operational amplifier, so that their voltages are embedded at VDD / 2.

[0087] The common-mode feedback circuit includes port V op f, f', g;

[0088] The input ports of the operational amplifier (OPAMP) respectively form the voltage input ports V of the common-mode feedback circuit. op The input ports are f and f'; the output port g of the common-mode feedback circuit is formed by the output port of the operational amplifier OPAMP.

[0089] This embodiment employs a bias circuit where the reference current is transmitted via a current mirror to the diode-connected PMOS transistor to automatically adjust the gate voltage, thereby ensuring stable bias under a 0.3V supply. The body drive input circuit receives the differential signal at the body terminal and introduces a cross-positive feedback structure to enhance the equivalent transconductance and improve the first-stage gain; a current mirror load replaces the tail current source structure to ensure static stability under low voltage. Two stages of differential common-source amplifier units are connected after the input stage to achieve high-gain amplification, providing driving force for the output stage; the output terminal uses an AB-class bias structure to achieve rail-to-rail output swing, and the gate of the PMOS output transistor is fed forward to the intermediate stage input node, enabling the output stage to respond quickly to input changes. The circuit uses a Miller compensation network and an RC series compensation unit to coordinately adjust the dominant pole position, cancel parasitic zeros and suppress high-frequency oscillations, improving phase margin and frequency stability. The common-mode feedback circuit stabilizes the output common-mode level and ensures linearity.

[0090] Based on Embodiment 1, this embodiment describes in detail the frequency compensation technology analysis of an ultra-low power body-driven four-stage differential operational transconductance amplifier according to this application, specifically as follows:

[0091] according to Figure 2 The small-signal model equivalent circuit under differential input signals, after derivation, yields the following formula for the system's loop transfer function:

[0092]

[0093] Among them, the system low-frequency gain Dominant pole frequency Determined by the following formula: In the formula, The transconductance of the i-th amplification unit, This is the equivalent output resistance of this stage. For interstage compensation capacitors, adjust The location of the dominant pole can be controlled while maintaining gain, thereby maintaining a balance between bandwidth and stability. The other coefficients in the system transfer function are as follows:

[0094] , , , .

[0095] In the formula, It is an interstage series capacitor. For the damping resistor connected in series with it; For load capacitance, , These are the output parasitic capacitances for the second and third stages, respectively.

[0096] As shown in the loop transfer function, the fourth-order amplifier can achieve significantly high gain characteristics. However, the impact of the additional poles on stability must be considered. Since a1 and b1 are approximately equivalent, the corresponding zeros and poles cancel each other out. After Miller compensation, we have approximately GBW = Gm1 / Cc2, and the poles in term b4 are much larger than GBW, so they can be ignored. Therefore, after the above zero-pole compensation, a simplified function expression can be obtained as follows:

[0097]

[0098] From the above formula, we can see that, except Besides the pole, there are two other poles affected by b2 and b3. Considering b2, b3, and... Differences in expressions, through adjustment and The two poles resulting from this can potentially be controlled outside the GBW range, a hypothesis verified by subsequent simulations. Therefore, the phase margin of the operational transconductance amplifier can be approximated as:

[0099]

[0100] Through coordinated design , , and transconductance parameters at all levels The adjustable relative distribution of zeros and additional poles ensures a stable phase response across a wide frequency range, guaranteeing stable operation of the four-stage transconductance amplifier.

[0101] This embodiment details the relationship between the frequency compensation unit and the zeros and poles of the circuit frequency, guiding the design of Miller capacitors and series RC circuits. It solves the stability problem caused by the inherent multiple poles of the four-stage operational transconductance amplifier, realizes pole separation of the four-stage operational transconductance amplifier and cancels zeros and suppresses parasitic poles, ensuring the stability of the four-stage structure. Moreover, no additional power consumption is introduced due to compensation, achieving multi-objective optimization of high gain, good stability, wide load range and low power consumption.

[0102] Example 2

[0103] This embodiment details the specific implementation technology and effects of an ultra-low power body-driven four-stage differential operational transconductance amplifier. Specifically, the bias circuit uses a diode-connected PMOS for self-biasing; the input stage adopts a body-driven differential structure, receiving differential signals through the body terminal to achieve efficient amplification and output differential current under ultra-low voltage conditions; at the same time, cross-local positive feedback is introduced to enhance the equivalent transconductance and improve the first-stage gain, and a current mirror load is used to replace the tail current source structure to ensure static stability under low voltage.

[0104] Two differential common-source structures are connected after the input stage to improve the overall gain and driving capability. The output adopts Class AB bias to achieve rail-to-rail output swing, and the output PMOS gate is fed forward to the intermediate stage input node to enhance transient response speed. The circuit uses a Miller compensation network to control the position of the dominant pole, and an RC series circuit is introduced in the output stage to cancel extra poles and suppress high-frequency oscillations. At the same time, a common-mode feedback circuit is added to maintain the stability of the output common-mode level, thereby ensuring the linearity of the amplifier.

[0105] The ultra-low power body-driven four-stage differential operational transconductance amplifier circuit of this invention is designed using 180nm CMOS process, with a power supply voltage of 0.3V and a power consumption of only 57.2 nW, achieving rail-to-rail output dynamic range.

[0106] like Figure 1 As shown, the key circuit parameters are shown in Table 1:

[0107] Table 1 Key Circuit Parameters

[0108]

[0109] The following are the relevant simulation results: Figure 3 As shown, the present invention is illustrated in the case of load capacitor. At 100 pF, the simulated open-loop gain and phase margin frequency response of the operational transconductance amplifier are shown in pre-layout and post-layout configurations. The results show that the DC gain, phase margin (PM), and gain-bandwidth product (GBW) are 128.6 dB, 64.3°, and 15.6 kHz, respectively.Figure 4 The equivalent input noise spectrum characteristics of the input terminal of this invention are shown in the figure; the results show that the input reference noise density is approximately 4.3 µV / kHz at 1 kHz. This indicates that the operational transconductance amplifier maintains a low noise level even under ultra-low power conditions. Furthermore, simulation results show that the present invention achieves a common-mode rejection ratio of 123.7 dB.

[0110] Table 2. Performance Comparison of the Invention with Existing Technologies

[0111]

[0112] Existing technology discloses an improved Miller operational transconductance amplifier based on a body-driven differential pair combined with a DC level shifter unit. This structure achieves rail-to-rail input / output characteristics under ultra-low voltage by operating in the weak inversion region. However, this scheme only employs a two-stage amplification architecture, limiting the transconductance of the input stage. Furthermore, the level shifter unit is sensitive to bias conditions, and the frequency compensation method is relatively simple, resulting in limited phase margin and poor dynamic response performance. In contrast, this invention uses body driving to achieve an ultra-low voltage supply of 0.3V under ultra-low voltage conditions and efficiently amplifies and outputs differential current. A fourth-order amplification circuit is then added to improve the DC gain. At the same time, a frequency compensation unit and output feedforward technology are added to achieve frequency zero-pole separation and cancellation, as well as rail-to-rail output dynamic range. A common-mode feedback circuit is also used to ensure the linearity of the amplifier.

[0113] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. An ultra-low power body driven quad differential operational transconductance amplifier characterized by, The bias circuit, the bulk drive differential input circuit, the composite differential amplification circuit, the frequency compensation circuit and the common-mode feedback circuit are provided. The bias circuit provides stable bias voltage for each stage of circuit, sets a common-mode voltage input port VB1, and outputs ports VB2 and VB3. The common-mode voltage input port VB1 of the bias circuit and the voltage input port Vop of the common-mode feedback circuit are connected to the common-mode voltage VDD / 2. The bulk drive differential input circuit takes the bulk of the PMOS tube as the differential signal input ends Vin+ and Vin-, adopts the cross positive feedback structure to improve the equivalent transconductance, sets differential signal input ports Vin+, Vin-, input ports a and b, and output ports c and c'. The composite differential amplification circuit further amplifies the output signal of the bulk drive differential input circuit through two-stage differential common-source amplification units, adopts a feed-forward AB class output unit in the output stage, connects the gate of the output unit PMOS tube to the input end of the two-stage differential common-source amplification unit to realize rapid response to input changes and rail-to-rail differential output, and sets input ports d, d' and e, and differential signal output ports Vout+ and Vout-. The frequency compensation circuit realizes stable frequency compensation by combining the Miller capacitor connected across the input and output of the composite differential amplification circuit and the RC compensation network connected in parallel at the output end of the differential common-source amplification unit. The common-mode feedback circuit is used for stabilizing the output common-mode level, sets a voltage input port Vop, input ports f and f', and an output port g. The input port a of the bulk drive differential input circuit is connected to the output port VB2 of the bias circuit, the input port b of the bulk drive differential input circuit is connected to the output port g of the common-mode feedback circuit, the output port c of the bulk drive differential input circuit is connected to the input port d of the composite differential amplification circuit, and the output port c' of the bulk drive differential input circuit is connected to the input port d' of the composite differential amplification circuit. The input port e of the composite differential amplification circuit is connected to the output port VB3 of the bias circuit, the differential signal output port Vout+ of the composite differential amplification circuit is connected to the input port f of the common-mode feedback circuit, and the differential signal output port Vout- of the composite differential amplification circuit is connected to the input port f' of the common-mode feedback circuit.

2. The ultra-low power body-driven four-stage differential operational transconductance amplifier according to claim 1, characterized in that The bias circuit comprises a current source IB, a PMOS tube MB3, an NMOS tube MB1 and an NMOS tube MB2. The bias circuit comprises ports VB1, VB2 and VB3. The NMOS tube MB1 and the NMOS tube MB2 constitute a current mirror, and the gate and the drain of the MB3 are connected to realize diode characteristics. The bias circuit provides stable bias at 0.3V ultra-low voltage through bulk voltage modulation and current mirror replication. The drain and the gate of the NMOS tube MB1 are short-circuited and then connected to the gate of the NMOS tube MB2 and one end of the current source IB, forming a port VB3 of a bias circuit; the bulk of the PMOS tube MB3 is used as a common-mode voltage input port VB1 of the bias circuit; the drain and the gate of the PMOS tube MB3 are short-circuited and then connected to the drain of the NMOS tube MB2, forming a port VB2 of the bias circuit; the other end of the current source IB and the source of the PMOS tube MB3 are both connected to a power supply voltage VDD; the sources of the NMOS tubes MB1 and MB2 are both grounded.

3. The ultra-low power body driven four-stage differential operational transconductance amplifier according to claim 1, wherein, The bulk-driven differential input circuit comprises a bulk-driven unit, a cross local positive feedback unit and a current mirror load unit; The bulk-driven differential input circuit comprises ports Vin+, Vin-, a, b, c, c'; The bulk-driven unit comprises PMOS tubes M1 and M2, the bulk of the M1 is used as a positive input end Vin+, and the bulk of the M2 is used as a negative input end Vin-; the gates of the PMOS tubes M1 and M2 are commonly connected to a bias port a, and the sources thereof are connected to VDD; The PMOS tubes M7 and M8 are connected to the gates of the NMOS tubes M5 and M6, respectively, to form a current mirror replication, and the gates and the drains of the NMOS tubes M3 and M4 are short-circuited.

4. The ultra-low power body driven four-stage differential operational transconductance amplifier according to claim 3, characterized in that, The cross local positive feedback unit comprises NMOS tubes MX1 and MX2, the gate of the MX1 is connected to the drain of the M2, and the drain thereof is connected to the drain of the M1; the gate of the MX2 is connected to the drain of the M1, and the drain thereof is connected to the drain of the M2; the sources of the MX1 and MX2 are grounded; the two are cross-connected to form a local positive feedback and improve the equivalent transconductance of an input stage; the gates of the NMOS tubes M5 and M6 are connected to the gates of the M3 and M4, respectively, to form a current mirror replication, and the gates and the drains of the NMOS tubes M3 and M4 are short-circuited.

5. The ultra-low power body driven four-stage differential operational transconductance amplifier of claim 1, wherein, The composite differential amplification circuit comprises a two-stage differential common-source amplification unit and a feed-forward AB class output unit; The composite differential amplification circuit comprises ports d, d', e, Vout+ and Vout-; The two-stage differential common-source amplification unit comprises PMOS tubes M9, M10, M13 and M14, and NMOS tubes M11, M12, M15 and M16; the output signal of the bulk-driven differential input circuit is further amplified through a cascade mode; The input port d of the composite differential amplification circuit is composed of the connection of the gate of the PMOS M9 and the gate of the PMOS M17; the drain of the PMOS M9, the drain of the NMOS M11 and the gate of the PMOS M13 are connected; the drain of the PMOS M13, the drain of the NMOS M15 and the gate of the NMOS M19 are connected; the input port e of the composite differential amplification circuit is composed of the connection of the gate of the NMOS M11, the gate of the NMOS M12, the gate of the NMOS M15 and the gate of the NMOS M16; the sources of the NMOS M11, M15 and M19 are grounded; the sources of the PMOS M9, M13 and M17 are connected to the power supply voltage VDD.

6. The ultra-low power body-driven four-stage differential operational transconductance amplifier according to claim 5, characterized by The feedforward AB class output unit includes the PMOS M17, the PMOS M18, the NMOS M19, the NMOS M20, the capacitor CL1 and the capacitor CL2; the gates of the PMOS M17 and the PMOS M18 are connected to the input node of the two-stage differential common-source amplification unit in a feedforward manner, so that the output stage can quickly respond to the input voltage change when the input changes; The input port d' of the composite differential amplification circuit is composed of the connection of the gate of the PMOS M10 and the gate of the PMOS M18; the drain of the PMOS M10, the drain of the NMOS M12 and the gate of the PMOS M14 are connected; the drain of the PMOS M14, the drain of the NMOS M16 and the gate of the NMOS M20 are connected; the output port Vout+ of the composite differential amplification circuit is composed of the connection of the drain of the PMOS M17, the drain of the NMOS M19 and one end of the capacitor CL1; the other end of the capacitor CL1 is grounded; the output port Vout- of the composite differential amplification circuit is composed of the connection of the drain of the PMOS M18, the drain of the NMOS M20 and one end of the capacitor CL2; the sources of the NMOS M12, M16 and M20 are grounded; the other end of the capacitor CL2 is grounded; the sources of the PMOS M10, M14 and M18 are connected to the power supply voltage VDD.

7. The ultra-low power body driven four-stage differential operational transconductance amplifier of claim 1, wherein, The frequency compensation circuit includes the capacitors CC1, CC2, CC3 and CC4, and the resistors RC1 and RC2; The capacitors CC3 and CC4 are Miller compensation capacitors, which disperse the poles of the amplifier, make the output pole of the first stage the dominant pole, avoid the superposition with other poles to cause phase mutation, and thus reserve sufficient phase margin for the circuit stability; The compensation capacitor CC3 is connected between the input end d of the composite differential amplification circuit and the output end Vout+; the compensation capacitor CC4 is connected between the input end d' of the composite differential amplification circuit and the output end Vout-; one end of the resistor RC1 is connected with the drain of the NMOS transistor M15; one end of the resistor RC2 is connected with the drain of the NMOS transistor M16; the other end of the resistor RC1 is connected with one end of the capacitor CC1; the other end of the resistor RC2 is connected with one end of the capacitor CC2; the other end of the capacitor CC1 is grounded; and the other end of the capacitor CC2 is grounded.

8. The ultra-low power body driven four-stage differential operational transconductance amplifier according to claim 7, characterized by The capacitors CC1 and CC2 and the resistors RC1 and RC2 are connected in series respectively to offset the high-frequency zero point introduced by the main Miller capacitor, eliminate the phase margin loss, and make the circuit still equivalent to a two-stage amplification system within the working bandwidth; the RC compensation network composed of the resistors RC1 and CC1 and the resistors RC2 and CC2 cooperates with the Miller compensation capacitor to realize frequency stability optimization.

9. The ultra-low power body driven four-stage differential operational transconductance amplifier of claim 1, wherein, The common-mode feedback circuit comprises an operational amplifier OPAMP; The common-mode feedback circuit comprises ports Vop, f, f' and g; The input ports of the operational amplifier OPAMP constitute the voltage input port Vop, the input ports f and f' of the common-mode feedback circuit; the output port g of the common-mode feedback circuit is constituted by the output port of the operational amplifier OPAMP; and the differential signal output ports Vout+ and Vout- of the composite differential amplification circuit are connected with the input ports f and f' of the common-mode feedback circuit respectively, so as to realize common-mode detection of the output signal.

10. The ultra-low power body-driven four-stage differential operational transconductance amplifier according to claim 9, characterized by The common-mode feedback circuit transmits the output end signal and the common-mode voltage to the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8 of the bulk-driven differential input circuit through the operational amplifier, so that the voltages of the two are embedded in VDD / 2; the working state of the current mirror load unit of the bulk-driven differential input circuit is adjusted through negative feedback, the output common-mode level is stabilized, and the circuit output linearity is ensured.

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