Voltage comparator circuit, chip and electronic device

Abstract

The invention discloses a voltage comparator circuit, a chip and electronic equipment, and the voltage comparator circuit comprises a differential comparison circuit which is used for receiving an input voltage signal and a reference voltage signal, and outputting a differential signal based on the input voltage signal and the reference voltage signal; the output buffer circuit is connected with the differential comparison circuit and is used for outputting an output voltage signal of the voltage comparator circuit based on the differential signal; the hysteresis control circuit is connected with the output buffer circuit and the differential comparison circuit and is used for outputting an adjusting signal based on the output voltage signal so as to adjust the threshold voltage of the differential comparison circuit; and the clamping circuit is connected with the differential comparison circuit and is used for protecting the differential comparison circuit so as to prevent the differential comparison circuit from overvoltage breakdown. The voltage comparator circuit can bear dynamic high-voltage impact.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, more particularly to a voltage comparator circuit, a chip and an electronic device. BACKGROUND

[0002] In an integrated circuit system such as a power management chip, it is often necessary to monitor the voltage conditions of nodes inside and outside the chip in real time, and to make power regulation, current limiting protection, open circuit protection, short circuit protection and other operations to ensure accurate power output and system stability and reliability. Most power management chip systems need to withstand high voltage (such as 24V, 45V, etc.), and often need to be designed separately for low voltage and high voltage domains. For the voltage monitoring system of a high voltage chip, there is a large voltage range and voltage swing, and high reliability is required for the high voltage comparator. The current voltage comparator circuit can only withstand steady-state high voltage, and when the voltage values of the input voltage and the reference voltage change rapidly, the high voltage is easily coupled to the low voltage node through the source-drain capacitance / gate-drain capacitance of the transistor, thereby causing the risk of overvoltage breakdown. SUMMARY

[0003] The present application is proposed to solve the above problems. According to an aspect of the present application, a voltage comparator circuit is provided, which comprises: a differential comparison circuit configured to receive an input voltage signal and a reference voltage signal, and output a differential signal based on the input voltage signal and the reference voltage signal; an output buffer circuit connected with the differential comparison circuit, configured to output an output voltage signal of the voltage comparator circuit based on the differential signal; a hysteresis control circuit connected with the output buffer circuit and the differential comparison circuit, configured to output an adjustment signal based on the output voltage signal to adjust a threshold voltage of the differential comparison circuit; and a clamping circuit connected with the differential comparison circuit, configured to protect the differential comparison circuit from overvoltage breakdown.

[0004] In an embodiment of the present application, the differential comparison circuit comprises a first common-gate PMOS pair and a second common-gate NMOS pair, and the clamping circuit comprises a first clamping circuit and a second clamping circuit, wherein: the first clamping circuit is a low voltage region clamping circuit, and the low voltage region clamping circuit is connected with the second common-gate NMOS pair; and the second clamping circuit is a high voltage region clamping circuit, and the high voltage region clamping circuit is connected with the first common-gate PMOS pair.

[0005] In an embodiment of the present application, the voltage comparator circuit further comprises a one-way conduction circuit, wherein: the one-way conduction circuit is connected with the differential comparison circuit, and the differential comparison circuit receives the input voltage signal and the reference voltage signal via the one-way conduction circuit.

[0006] In the embodiments of the present application, the first common-gate PMOS pair includes a first PMOS transistor and a second PMOS transistor, and the unidirectional conduction circuit includes a first unidirectional conduction circuit and a second unidirectional conduction circuit, wherein: an input end of the first unidirectional conduction circuit is connected to the input voltage signal, and an output end of the first unidirectional conduction circuit is connected to the first PMOS transistor; an input end of the second unidirectional conduction circuit is connected to the reference voltage signal, and an output end of the second unidirectional conduction circuit is connected to the second PMOS transistor.

[0007] In the embodiments of the present application, the unidirectional conduction circuit includes a dynamic threshold MOS transistor.

[0008] In the embodiments of the present application, the dynamic threshold MOS transistor includes a third PMOS transistor, wherein: a drain of the third PMOS transistor is connected to the input voltage signal or the reference voltage signal; a source of the third PMOS transistor is connected to a source of a PMOS transistor included in the first common-gate PMOS pair; and a gate of the third PMOS transistor is short-circuited with the source and a substrate.

[0009] In the embodiments of the present application, the unidirectional conduction circuit has a leakage prevention function.

[0010] In the embodiments of the present application, the unidirectional conduction circuit further includes a fourth PMOS transistor to realize the leakage prevention function, wherein: a gate of the fourth PMOS transistor is connected to a gate of the third PMOS transistor; a source of the fourth PMOS transistor is connected to a source of the third PMOS transistor; and a drain of the fourth PMOS transistor is connected to a source of a PMOS transistor included in the first common-gate PMOS pair.

[0011] According to another aspect of the present application, a chip is also provided, which includes the voltage comparator circuit described above.

[0012] According to still another aspect of the present application, an electronic device is also provided, which includes the chip described above.

[0013] The voltage comparator circuit, the chip and the electronic device according to the embodiments of the present application increase a clamping circuit relative to a conventional high-voltage voltage comparator, which is connected with a differential comparison circuit, can provide a discharge channel when a voltage of an input voltage signal and a reference voltage signal suddenly rises, prevent overvoltage breakdown of the differential comparison circuit, and protect an output buffer circuit and a hysteresis control circuit; in addition, the clamping circuit can also provide a current path when a voltage difference between the input voltage signal and the reference voltage signal is too large, thereby balancing a source voltage of a MOS pair included in the differential comparison circuit, and preventing breakdown risk thereof. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description thereof taken in conjunction with the accompanying drawings in which: like reference numerals in the accompanying drawings refer to identical or like components and will not be described again. The accompanying drawings which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0015] Figure 1 A schematic block diagram of a voltage monitoring system is shown.

[0016] Figure 2 A system block diagram of a voltage monitoring system of a high voltage chip is shown.

[0017] Figure 3 An exemplary circuit diagram of a voltage comparator based on a common gate amplifier is shown.

[0018] Figure 4 An exemplary circuit diagram of a high voltage voltage comparator is shown.

[0019] Figure 5 An exemplary structure block diagram of a voltage comparator circuit according to embodiments of the present application is shown.

[0020] Figure 6 An exemplary diagram of a DTMOS transistor in a voltage comparator circuit according to embodiments of the present application is shown.

[0021] Figure 7 And Figure 8 An exemplary diagram of a DTMOS transistor in a voltage comparator circuit according to embodiments of the present application is shown. Figure 6 An equivalent parasitic circuit diagram of the structure shown.

[0022] Figure 9 An exemplary diagram of an anti-leakage DTMOS transistor in a voltage comparator circuit according to embodiments of the present application is shown.

[0023] Figure 10 An exemplary diagram of an anti-leakage DTMOS transistor in a voltage comparator circuit according to embodiments of the present application is shown. Figure 9 An equivalent parasitic circuit diagram of the structure shown.

[0024] Figure 11 An exemplary circuit diagram of a voltage comparator circuit according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the present application more obvious, the following will describe the example embodiments according to the present application in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the protection scope of the present application.

[0026] In integrated circuit systems such as power management chips, it is often necessary to monitor the voltage conditions of nodes inside and outside the chip in real time, and to make power regulation, current limiting protection, open circuit protection, short circuit protection and other operations to ensure accurate power output and system stability and reliability. Figure 1 A schematic block diagram of a voltage monitoring system is shown. As Figure 1 shown, the comparator compares the relative relationship between the output stage voltage and the reference source voltage, and sends the overvoltage / undervoltage signal to the main controller. After processing and calculation, the main controller operates the output stage to ensure that the chip operates within a controllable range. At the CMOS level (e.g. 1.8 / 3.3 / 5V), the system design has considerable maturity.

[0027] Most power management chip systems need to withstand high voltage (e.g. 24V, 45V, etc.), and often need to be designed separately for low voltage and high voltage domains. Figure 2 A system block diagram of a voltage monitoring system for a high voltage chip is shown. As Figure 2 shown, the controller is often placed in the low voltage domain to ensure lower power consumption and better matching, and the output stage and driver often operate at higher voltages. For the supporting voltage monitoring circuit, such as the high voltage reference source and the high voltage comparator, it is also often necessary to withstand high voltage. The high voltage comparator, as the core component of the high voltage monitoring circuit, directly determines the performance of the entire system. The high voltage domain often accompanies a large voltage range and voltage swing, and higher requirements are put forward for the reliability of the high voltage comparator.

[0028] For circuits with high voltage, the reference point of the comparator is usually high voltage, and the sampling point is a wide range of voltage input. The common source amplifier is limited by the gate-source voltage tolerance, and if the full input range is to be covered, the simplest way is to convert the sampling voltage into the low voltage domain through resistance division. However, in the process of integrated circuit manufacturing, the actual deviation of the resistance is large, making the sampling result not accurate enough. The common gate amplifier has a source input and a high voltage tolerant drain-source, and can cover the full input range, so the common gate input scheme is often used in practical applications. Figure 3 An exemplary circuit diagram of a voltage comparator based on a common gate amplifier is shown. As Figure 3As shown, its input end is Vin, and the reference end is Vref. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs or MOS tubes) M3 and M4 are used as a common-gate input pair. When the input voltage is unbalanced, the gate-source voltage difference of M3 and M4 is different, and the inverse type coefficients of the two MOSFETs are different, resulting in inconsistent saturation currents of the two MOSFETs, thereby generating a high / low level at the middle node of transistors M2 and M4. After being amplified by the buffer Buf, the level is converted into a digital level Vout and connected to the main controller.

[0029] When Vin and Vref are close, the output result may oscillate due to the limited system noise tolerance. To avoid such problems, a hysteresis module (Hys) controlled by the output signal Vout is often added, as shown in Figure 3 to artificially pull the comparison threshold, ensuring that the system is in a monostable state.

[0030] Figure 3 The circuit shown can work about 1-2V above the voltage withstanding of MOSFET. For higher voltage requirements, a drain extended MOS (DEMOS) or a lateral double-diffused MOS (LDMOS) that can withstand high voltage needs to be introduced.

[0031] High-voltage MOSFETs (such as DEMOS and LDMOS) can withstand higher voltages at the drain end due to the introduction of drift region widening and other technologies, while the gate end and the source end often maintain the characteristics of complementary metal-oxide-semiconductor (CMOS), thereby maintaining a good balance point in terms of voltage withstanding and speed.

[0032] Figure 4 An exemplary circuit diagram of a high-voltage comparator using DEMOS / LDMOS is shown in Figure 4 As shown, M3 and M4 have been replaced by high-voltage PMOS, and a pair of high-voltage NMOS (M5 and M6) has been inserted to prevent the Hys module and the Buf module using standard CMOS devices from being high-voltage punctured.

[0033] However, Figure 4The circuit shown still has the following drawbacks: First, it can only withstand steady-state high voltage. When the voltage of Vin or Vref changes rapidly, the high voltage can easily couple to the low-voltage node through the source-drain capacitance / gate-drain capacitance of the MOSFET. This can easily lead to gate breakdown of M4, M5, and M6, and threaten the underlying M1, M2, Hys, and Buf modules. Second, it is prone to reverse current, leading to voltage domain chaining and latch-up effects. When the voltage of Vin or Vref is lower than the low-voltage rail, the substrate diodes of M3~M6 may become forward biased, easily resulting in a large current from the low-voltage rail to Vin or Vref. This can cause undesirable functional failures, leakage, or even circuit burnout. Third, its input differential voltage is limited. M3 is in diode connection mode, and when the voltage difference between Vin and Vref is greater than the gate-source breakdown voltage, the gate oxide of M4 is prone to breakdown, severely limiting the input voltage differential range of this circuit.

[0034] To solve at least one of the above-mentioned technical problems, the technical solution of this application is proposed, as described below.

[0035] Figure 5 A schematic block diagram of a voltage comparator circuit 1 according to an embodiment of this application is shown. Figure 5 As shown, the voltage comparator circuit 1 may include a differential comparator circuit 11, an output buffer circuit 12, a hysteresis control circuit 13, and a clamping circuit 14. The differential comparator circuit 11 receives an input voltage signal and a reference voltage signal, and outputs a differential signal based on the input and reference voltage signals. The output buffer circuit 12 is connected to the differential comparator circuit 11 and outputs the output voltage signal of the voltage comparator circuit 1 based on the differential signal. The hysteresis control circuit 13 is connected to both the output buffer circuit 12 and the differential comparator circuit 11 and outputs an adjustment signal based on the output voltage signal to adjust the threshold voltage of the differential comparator circuit 11. The clamping circuit 14 is connected to the differential comparator circuit 11 and protects the differential comparator circuit 11 from overvoltage breakdown.

[0036] In the embodiments of this application, the voltage comparator circuit 1, compared to a conventional high-voltage comparator, adds a clamping circuit 14, which is connected to the differential comparator circuit 11. This clamping circuit provides a discharge path when the input voltage signal and the reference voltage signal suddenly rise, preventing overvoltage breakdown of the differential comparator circuit 11 and protecting the output buffer circuit 12 and the hysteresis control circuit 13. Furthermore, the clamping circuit 14 also provides a current path when the voltage difference between the input voltage signal and the reference voltage signal is too large, thereby balancing the source voltage of the MOS pair included in the differential comparator circuit 11 and preventing its breakdown risk.

[0037] In the embodiment of the present application, the differential comparison circuit 11 comprises a first common-gate PMOS pair and a second common-gate NMOS pair, and the clamping circuit 14 comprises a first clamping circuit 14 and a second clamping circuit 14, wherein: the first clamping circuit 14 is a low-voltage region clamping circuit 14 connected with the second common-gate NMOS pair; and the second clamping circuit 14 is a high-voltage region clamping circuit 14 connected with the first common-gate PMOS pair.

[0038] In this embodiment, the first common-gate NMOS pair can be protected by the first clamping circuit 14. Specifically, when the high-voltage end voltage suddenly rises, the source end of the first common-gate NMOS pair can be affected by coupling and appear high voltage. At this time, the body diode of the first clamping circuit 14 can provide a discharge channel to the bias voltage (i.e. the gate voltage of the first common-gate NMOS pair), thereby protecting the first common-gate NMOS pair and protecting the hysteresis control circuit 13 and the output buffer circuit 12. In addition, the first common-gate PMOS pair can also be protected by the second clamping circuit 14. Specifically, when the voltage difference between the input voltage signal and the output voltage signal is too large, the gate oxide (i.e. the silicon dioxide insulating layer between the gate and the channel) of the first common-gate PMOS pair can be damaged. The second clamping circuit 14 can provide a current path from top to bottom or from bottom to top, thereby balancing the source end voltage of the first common-gate PMOS pair and preventing the gate oxide of the first common-gate PMOS pair from being damaged. Exemplarily, the second clamping circuit 14 can be composed of two groups of diode-connected PMOS, which can provide a current path from top to bottom by the channel or a current path from bottom to top by the substrate diode, and can be equivalent to two groups of bidirectional diodes.

[0039] In the embodiment of the present application, the voltage comparator circuit 1 can further comprise a unidirectional conduction circuit, wherein: the unidirectional conduction circuit is connected with the differential comparison circuit 11, and the differential comparison circuit 11 receives the input voltage signal and the reference voltage signal via the unidirectional conduction circuit.

[0040] In this embodiment, by using a unidirectional conduction circuit at the input terminal, in conjunction with the aforementioned high-voltage clamping circuit 14, circuit breakdown and voltage domain crosstalk problems can be further prevented. This is because: in a voltage comparator, the input terminal (input voltage / reference voltage) typically belongs to the external input voltage domain, while the differential comparator circuit 11 belongs to the internal core voltage domain, and the voltage ranges of these two domains are often different; the core characteristic of the unidirectional conduction circuit is forward conduction and reverse cutoff; when the input voltage exceeds the internal voltage domain range, the unidirectional conduction circuit will enter the cutoff state, preventing abnormal voltage from being applied to the differential comparator circuit 11 and avoiding gate oxide breakdown due to overvoltage; if a momentary spike voltage occurs at the input terminal, the unidirectional conduction circuit can work with the clamping circuit 14 to lock the PMOS gate voltage of the differential comparator circuit 11 within a safe withstand voltage range, preventing physical damage to the device. In addition, the unidirectional cutoff characteristic of the unidirectional conduction circuit will block the reverse transmission between the two voltage domains, that is, only allow the input signal to be transmitted in the normal direction (such as from the external input voltage domain to the internal voltage domain), while preventing the voltage of the internal voltage domain from reverse to the external input voltage domain, or the abnormal voltage of the external input voltage domain from entering the internal voltage domain, thereby achieving isolation between the two voltage domains and eliminating the crosstalk problem.

[0041] In the embodiments of this application, the aforementioned first common-gate PMOS pair may include a first PMOS transistor and a second PMOS transistor, and the unidirectional conduction circuit may include a first unidirectional conduction circuit and a second unidirectional conduction circuit, wherein: the input terminal of the first unidirectional conduction circuit is connected to the input voltage signal, and the output terminal of the first unidirectional conduction circuit is connected to the first PMOS transistor; the input terminal of the second unidirectional conduction circuit is connected to the reference voltage signal, and the output terminal of the second unidirectional conduction circuit is connected to the second PMOS transistor. Since the differential comparator circuit 11 includes the first common-gate PMOS pair, that is, it includes two PMOS transistors, the unidirectional conduction circuit is also divided into two paths—the first unidirectional conduction circuit and the second unidirectional conduction circuit, thereby preventing the breakdown of the two transistor circuits and eliminating voltage domain crosstalk problems respectively.

[0042] The unidirectional conduction circuit can be constructed in various ways. Bipolar junction devices (BJD), CMOS devices, and power DMOS devices (BCD) generally do not allow for forward biasing of diodes, and transistors are often used instead. High-voltage transistors are not provided in some processes, and with base-emitter forward bias, carriers are easily injected into the substrate, leading to leakage and affecting the normal function of the circuit. Therefore, in the embodiments of this application, the unidirectional conduction circuit may include a dynamic threshold MOS transistor (DTMOS), which uses Dynamic Threshold MOS (DTMOS) technology to construct an equivalent high-performance diode to achieve the unidirectional conduction circuit. The DTMOS structure is compatible with mixed processes such as BCD, and can be integrated on the same chip as CMOS, power DMOS, and other devices without additional process steps, saving chip area and reducing costs. It is particularly suitable for power management chips and other circuits requiring mixed digital, analog, and power integration. Moreover, DTMOS has extremely low forward conduction loss, higher reverse isolation, no reverse recovery time, faster switching speed, adaptive threshold, and stronger robustness.

[0043] For example, the dynamic threshold MOS transistor may include a third PMOS transistor, wherein: the drain of the third PMOS transistor is connected to the input voltage signal or the reference voltage signal; the source of the third PMOS transistor is connected to the source of the PMOS transistor included in the first common gate PMOS pair; and the gate, source, and substrate of the third PMOS transistor are shorted. Figure 6 An example diagram of a DTMOS transistor is shown. In this example, the high-voltage PMOS transistor MA serves as the third PMOS transistor mentioned above, with its gate, source, and body terminals shorted together to form a diode with the drain terminal to the source terminal. Figure 7 The diagram illustrates a DTMOS structure with a parasitic transistor, QAp, which provides a top-down current path and blocks bottom-up current. Furthermore, due to the source-drain reciprocity of MOSFETs, the drain can be considered the actual source of the MA. The lower the gate voltage, the more the MA tends to conduct; and the lower the body (back gate) voltage, the lower the absolute value of the MA's threshold voltage, also tending towards conduction. Therefore, by shorting the gate, source, and body, when the drain voltage is higher than the source voltage, the MA easily forms a conduction channel, providing a lower on-state voltage drop and conduction loss than QAp.

[0044] However, DTMOS substrate transistors also have the problem of substrate leakage, such as... Figure 8 As shown, when the transistor is forward biased, current is also injected into the substrate. At high temperatures, the threshold voltage drop of the MOSFET is often weaker than that of the transistor, causing most of the current to flow through the transistor, and circuit distortion and failure due to substrate leakage. Based on this, the unidirectional conduction circuit provided in this application can be a unidirectional conduction circuit with leakage protection function.

[0045] For example, the unidirectional conduction circuit further includes a fourth PMOS transistor to achieve leakage protection, wherein: the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor; the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor; and the drain of the fourth PMOS transistor is connected to the source of the PMOS transistor included in the first common-gate PMOS pair. Figure 9 An example diagram of a leakage-protected DTMOS transistor is shown. (Example diagram follows.) Figure 9 As shown, a standard breakdown voltage PMOS MB is inserted into the gate-source connection of the DTMOS. When current flows through the MA, the MB forms a voltage drop approximately equal to its threshold voltage, further reducing the gate voltage of the MA and making it easier for the MA's channel to form. This structure can transfer the voltage drop of the MA to the MB, preventing the parasitic transistor QAp of the MA from becoming forward biased, thereby completely eliminating distortion and failure caused by substrate leakage at high temperatures. Figure 10 for Figure 9 The diagram shows the equivalent parasitic circuit of the DTMOS transistor for leakage protection.

[0046] The voltage comparator circuit 1 according to an embodiment of this application has been described in detail above. Based on the above description, the voltage comparator circuit according to an embodiment of this application can provide a discharge path when the voltage of the input voltage signal and the reference voltage signal suddenly rises, preventing overvoltage breakdown of the differential comparator circuit and protecting the output buffer circuit and hysteresis control circuit. In addition, the clamping circuit can also provide a current path when the voltage difference between the input voltage signal and the reference voltage signal is too large, thereby balancing the source terminal voltage of the MOS pair included in the differential comparator circuit and preventing its breakdown risk. Therefore, the voltage comparator circuit according to an embodiment of this application can withstand dynamic high voltage surges. Furthermore, the voltage comparator circuit according to an embodiment of this application can block the current path from the low voltage domain to the high voltage domain by connecting a unidirectional conduction circuit in series at the input terminal, preventing voltage domain crosstalk. In addition, the voltage comparator circuit according to an embodiment of this application uses DTMOS technology to solve the substrate leakage problem of traditional diodes and transistors. Furthermore, the voltage comparator circuit according to an embodiment of this application uses anti-leakage DTMOS technology to solve the potential substrate leakage problem of DTMOS at high temperatures.

[0047] Figure 11 An exemplary circuit diagram of a voltage comparator circuit according to an embodiment of this application is shown. Figure 11As shown, the voltage comparator circuit includes a differential comparator circuit composed of a common-gate PMOS pair M3 and M4 and a common-gate NMOS pair M5 and M6, a buffer Buf (i.e., the output buffer circuit mentioned above), a hysteresis control circuit composed of a hysteresis circuit Hys and transistors M1 and M2, and clamping circuits Clamp1 (equivalent to the first clamping circuit mentioned above) and Clamp2 (equivalent to the second clamping circuit mentioned above). Furthermore, the circuit may also include a unidirectional conduction circuit Deq. Vin is the input voltage signal, Vref is the reference voltage signal, and Vout is the output voltage signal. Its working principle is as follows: When the high-voltage terminal voltage suddenly rises, the source terminals of M5 and M6 may be affected by coupling, resulting in high voltage. At this time, the body diode of the clamping circuit can provide a discharge path to the bias voltage V_C, protecting the gate oxide of M_5 and M_6 and the Hys and Buf modules. When the voltage difference between Vin and Vref is too large, it may break down the gate oxide of M4. Clmap2 can be composed of two sets of diode-connected PMOS. The diode-connected PMOS can provide a current path from top to bottom through the channel, or a current path from bottom to top through the substrate diode, which can be equivalent to two sets of bidirectional diodes, thereby balancing the source terminal voltages of M3 and M4 and preventing the gate oxide of M4 from being broken down. Furthermore, a unidirectional conduction circuit Deq is connected in series at the input terminal, which, together with the high-voltage region clamping circuit Clmap2 mentioned above, can further prevent circuit breakdown and eliminate voltage domain crosstalk problems, as mentioned above. This unidirectional conduction circuit can be composed of other equivalent circuits of diodes, transistors and MOSFETs, as shown in (a) and (b) in the figure (previously combined with Figures 6 to 10 Its structure will not be described here.

[0048] Therefore, this voltage comparator circuit can withstand dynamic high-voltage surges through clamping circuits in the low-voltage and high-voltage regions. It also blocks the current path from the low-voltage region to the high-voltage region by connecting a unidirectional conduction circuit in series at the input, preventing voltage domain crosstalk. Furthermore, it uses a DTMOS diode to protect the internal circuitry of the high-voltage comparator while preventing substrate leakage problems associated with traditional diodes and transistors. Finally, it inserts a standard voltage-rated PMOS into the DTMOS, further enhancing the channel formation capability of the DTMOS and completely eliminating the risk of leakage from the parasitic transistor at high temperatures.

[0049] According to another aspect of this application, a chip is also provided, which includes the voltage comparator circuit described above according to the embodiments of this application.

[0050] According to another aspect of this application, an electronic device is also provided, which includes the aforementioned chip.

[0051] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0052] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0053] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0054] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0055] Similarly, it should be understood that, for the purpose of simplification and aiding understanding of one or more aspects of this application, various features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, the approach of this application should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with fewer features than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0056] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0057] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0058] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules in the article analysis device according to embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0059] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0060] The above are merely specific embodiments or descriptions of specific embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A voltage comparator circuit, characterized by, The voltage comparator circuit comprises: a differential comparison circuit configured to receive an input voltage signal and a reference voltage signal, and output a differential signal based on the input voltage signal and the reference voltage signal; an output buffer circuit connected to the differential comparison circuit, and configured to output an output voltage signal of the voltage comparator circuit based on the differential signal; a hysteresis control circuit connected to the output buffer circuit and the differential comparison circuit, and configured to output an adjustment signal based on the output voltage signal to adjust a threshold voltage of the differential comparison circuit; a clamping circuit connected to the differential comparison circuit, and configured to protect the differential comparison circuit from over-voltage breakdown.

2. The voltage comparator circuit of claim 1, wherein, The differential comparison circuit comprises a first common-gate PMOS pair and a second common-gate NMOS pair, and the clamping circuit comprises a first clamping circuit and a second clamping circuit, wherein: the first clamping circuit is a low-voltage region clamping circuit connected to the second common-gate NMOS pair; the second clamping circuit is a high-voltage region clamping circuit connected to the first common-gate PMOS pair.

3. The voltage comparator circuit of claim 1 or 2, characterized in that, The voltage comparator circuit further comprises a unidirectional conduction circuit, wherein: the unidirectional conduction circuit is connected to the differential comparison circuit, and the differential comparison circuit receives the input voltage signal and the reference voltage signal via the unidirectional conduction circuit.

4. The voltage comparator circuit of claim 3, wherein, The first common-gate PMOS pair comprises a first PMOS transistor and a second PMOS transistor, and the unidirectional conduction circuit comprises a first unidirectional conduction circuit and a second unidirectional conduction circuit, wherein: an input end of the first unidirectional conduction circuit is connected to the input voltage signal, and an output end of the first unidirectional conduction circuit is connected to the first PMOS transistor; an input end of the second unidirectional conduction circuit is connected to the reference voltage signal, and an output end of the second unidirectional conduction circuit is connected to the second PMOS transistor.

5. The voltage comparator circuit of claim 3, wherein, The unidirectional conduction circuit comprises a dynamic threshold MOS transistor.

6. The voltage comparator circuit of claim 5, wherein, The dynamic threshold MOS transistor comprises a third PMOS transistor, wherein: a drain of the third PMOS transistor is connected to the input voltage signal or the reference voltage signal; a source of the third PMOS transistor is connected to a source of a PMOS transistor included in the first common-gate PMOS pair; a gate of the third PMOS transistor is short-circuited with the source and a substrate.

7. The voltage comparator circuit of claim 6, wherein, The unidirectional conduction circuit has an anti-leakage function.

8. The voltage comparator circuit of claim 7, wherein, The unidirectional conduction circuit further comprises a fourth PMOS transistor to realize the anti-leakage function, wherein: a gate of the fourth PMOS transistor is connected to a gate of the third PMOS transistor; a source of the fourth PMOS transistor is connected to a source of the third PMOS transistor; a drain of the fourth PMOS transistor is connected to a source of a PMOS transistor included in the first common-gate PMOS pair.

9. A chip, characterized by The chip comprises the voltage comparator circuit of any one of claims 1-8.

10. An electronic device, comprising: The electronic device comprises the chip of claim 9.

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