Eye diagram data synchronization circuit and method, serial-to-parallel converter receiving end

Abstract

The application discloses an eye diagram data synchronization circuit and method and a serial-parallel converter receiving end, and belongs to the technical field of high-speed serial data communication; the circuit comprises: a calibration signal generation module for generating a phase calibration signal according to a phase difference between a data sampling signal and an offset sampling signal; two registers for respectively outputting the offset sampling signal and pre / post offset sampling signals; wherein the pre / post offset sampling signals are obtained by outputting the offset sampling signal in advance / delaying half a bit period; and a selection output module for selecting the offset sampling signal or the pre / post offset sampling signals as a synchronized offset sampling signal output according to the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period. The application has wide application range, high synchronization precision and good dynamic performance.

Description

Technical Field

[0001] This invention belongs to the field of high-speed serial data communication technology, specifically relating to an eye diagram data synchronization circuit and method, and a serial-to-parallel converter receiver. Background Technology

[0002] With the rapid development of technologies such as data centers, high-performance computing, and 5G communications, the requirements for inter-chip data transmission rates are increasing daily. Serializers / deserializers (SerDes), as core technologies for achieving high-speed interconnects, have seen their data transmission rates advance to 112Gbps or even higher. At such high rates, signal integrity faces significant challenges, including severe inter-symbol interference, clock jitter, and channel loss.

[0003] To overcome these challenges and ensure extremely low bit error rates (BER), modern SerDes receivers typically employ a system architecture combining decision feedback equalization based on the data sampler and adaptive equalization based on the offset sampler. This significantly reduces the requirements for circuit operating speed, thereby achieving superior performance, lower power consumption, and higher reliability in high-speed scenarios. BER detection is a critical function in evaluating the performance of such systems and for online monitoring. Traditional BER detection methods compare the data recovered by the data sampler with known or expected data patterns. However, this method has an inherent problem: it can only detect whether the data sampler itself is faulty, but cannot effectively assess the performance degradation of the equalization system caused by phase inaccuracies in the offset sampler.

[0004] If the sampling phase of the offset sampler is not precisely aligned with the edge of the data eye diagram, then the adaptive equalizer adjustment based on its output will be suboptimal, or even erroneous. This will lead to a deterioration in the overall equalization effect at the receiver, and the actual system performance (such as the system-level bit error rate) will be far worse than the bit error rate measured based on the data sampler, resulting in a misjudgment of performance.

[0005] Therefore, the currently popular fixed delay line calibration method can be used to calibrate the offset sampler. This method, during the chip design phase, attempts to establish a fixed delay difference between the clock paths of the data sampler and the offset sampler through analog circuit design or layout matching. Upon chip power-up, a simple calibration sequence (such as scanning a fixed delay code) is used to roughly set the phase relationship between the two. However, this method cannot adapt to changes in process technology, voltage, and temperature, lacks dynamism, and has limited accuracy. Summary of the Invention

[0006] This invention provides an eye diagram data synchronization circuit and method, and a serial-to-parallel converter receiver, which can solve the above-mentioned technical problems.

[0007] In a first aspect, an eye diagram data synchronization circuit provided by an embodiment of the present invention includes: a calibration signal generation module, a first register, a second register, and a selection output module;

[0008] The calibration signal generation module is used to generate a phase calibration signal based on the phase difference between the data sampling signal and the offset sampling signal, wherein the phase calibration signal is used to indicate the relationship between the phase difference and half a bit period of the offset sampling signal;

[0009] Of the first register and the second register, one is used to output the offset sampling signal, and the other is used to advance / delay the offset sampling signal by half a bit period to obtain the pre-offset / post-offset sampling signal;

[0010] The selection output module is used to select either the offset sampling signal or the pre / post offset sampling signal as the synchronized offset sampling signal output according to the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period;

[0011] The first and second input terminals of the selection output module are connected to the output terminals of the first and second registers, respectively, and the signal input terminal is connected to the output terminal of the calibration signal generation module.

[0012] In a second aspect, embodiments of the present invention provide an eye diagram data synchronization method, which is applied to the eye diagram data synchronization circuit described in the first aspect above, and the method includes:

[0013] A phase calibration signal is generated based on the phase difference between the data sampling signal and the offset sampling signal, wherein the phase calibration signal is used to indicate the relationship between the phase difference and half a bit period of the offset sampling signal;

[0014] Based on the phase calibration signal, an offset sampling signal or a pre- / post-offset offset sampling signal is selected as the output offset sampling signal after synchronization, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; wherein, the pre- / post-offset offset sampling signal is obtained by outputting the offset sampling signal half a bit period earlier / later.

[0015] Thirdly, embodiments of the present invention provide a serial-to-parallel converter receiver, including: a joint equalization module, a data sampler, an offset sampler, an eye diagram data synchronization circuit as described in the first aspect, an XNOR gate, and an error counter;

[0016] The joint equalization module is used to equalize the input signal to obtain an equalized signal. The data sampler is used to sample the equalized signal at the center of the eye diagram to obtain a data sampled signal. The offset sampler is used to sample the equalized signal at the offset center position of the eye diagram to obtain an offset sampled signal. The eye diagram data synchronization circuit is used to synchronize the offset sampled signal to obtain a synchronized offset sampled signal. The XOR gate is used to perform an XOR operation on the synchronized offset sampled signal and the data sampled signal. The error counter is used to count errors based on the XOR operation result to calculate the bit error rate.

[0017] The beneficial effects of this invention compared to existing technologies are as follows: By processing the offset sampling signal in advance / delay, this invention can ensure that the phase error between the synchronized offset sampling signal and the data sampling signal is less than one bit period, thereby ensuring that both output data of the same bit period, reducing subsequent bit error rate calculation errors, improving signal reception quality, and achieving true and reliable system bit error rate monitoring. Furthermore, the phase calibration signal continuously indicates the specific relationship between the real-time phase difference and half a bit period between the data sampling signal and the offset sampling signal. This information triggers the selection output module to dynamically switch between two signal versions with a fixed half-bit period phase difference. When environmental factors cause phase drift, this switching mechanism can instantly adjust the phase of the offset sampling signal forward or backward by a minimum step, actively and continuously pulling it back to the same bit period as the data sampling signal. This closed-loop adjustment process based on real-time feedback allows the circuit to automatically track and compensate for the effects of process, voltage, and temperature changes, significantly enhancing the dynamic adaptability of synchronization and achieving finer phase control through the adjustment of the minimum quantization step, thus achieving higher precision data synchronization under varying operating conditions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a SerDes receiver;

[0019] Figure 2 This is a schematic diagram of a standard data eye diagram;

[0020] Figure 3 This is a schematic diagram illustrating a scenario for calculating the bit error rate.

[0021] Figure 4 This is a schematic diagram of a scenario where a SerDes receiver performs serial-to-parallel conversion via a data sampler;

[0022] Figure 5 This is a schematic diagram of a scenario where a SerDes receiver performs serial-to-parallel conversion using an offset sampler;

[0023] Figure 6 This is a schematic diagram of another scenario where a SerDes receiver performs serial-to-parallel conversion using an offset sampler;

[0024] Figure 7 This is a schematic diagram of a standard sampling data.

[0025] Figure 8 This is a schematic diagram of sampled data with an offset.

[0026] Figure 9 This is a schematic diagram of a low-quality data eye diagram;

[0027] Figure 10 This is a schematic diagram of an eye diagram data synchronization circuit provided in an embodiment of the present invention;

[0028] Figure 11 This is a schematic diagram of the specific structure of a calibration signal generation module provided in an embodiment of the present invention;

[0029] Figure 12 A schematic diagram of the output signals of each module inside the eye diagram data synchronization circuit when the phase difference is less than half a sampling interval, provided in an embodiment of the present invention;

[0030] Figure 13 A schematic diagram of the output signals of each module inside the eye diagram data synchronization circuit when the phase difference is greater than half a sampling interval, provided in an embodiment of the present invention;

[0031] Figure 14 This is a partial structural schematic diagram of an eye diagram data synchronization circuit provided in an embodiment of the present invention;

[0032] Figure 15 This is a schematic diagram of the structure of a serial-to-parallel converter receiver provided in an embodiment of the present invention.

[0033] Figure label:

[0034] 1: Calibration generation module; 11: Automatic calibration module; 2: Output selection module; R1: First register; R2: Second register; R3: Third register; INV1: First inverter; INV2: Second inverter; INV3: Third inverter; INV4: Fourth inverter; MUX1: First data selector; MUX2: Second data selector; XOR: Exclusive OR gate; TG: Transmission gate; C: Capacitor; NAND: NAND gate; 10: Joint equalization module; 20: Data sampler; 30: Offset sampler; 40: Eye diagram data synchronization circuit; 50: Error counter; XNOR: XNOR gate. Detailed Implementation

[0035] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0036] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0037] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0038] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0039] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0041] Figure 1 The diagram shown is a schematic of a SerDes receiver.

[0042] In one example, see Figure 1 Traditional SerDes receivers typically include a Continuous-Time Linear Equalizer (CTLE), a Decision Feedback Equalizer (DFE), a data sampler, an offset sampler, an XNOR gate, and an error counter. When receiving a signal, the SerDes receiver needs to selectively activate its internal equalization (CTLE+DFE) to process the high-speed serial signal, ensuring that the effective signal is amplified while noise is suppressed, ultimately recovering the correct data. This achieves the goal of obtaining data at the sampling position as shown in the image. Figure 2 The image shown depicts an open eye.

[0043] For example, see Figure 1 Data samplers are typically located on the main data path; see [link / reference]. Figure 2 The sampling clock (i.e., the data clock signal) phase is locked at the center of the data eye diagram, i.e., the optimal sampling time, to sample and recover data with the best signal-to-noise ratio. The offset sampler is usually located in the adaptive control loop, and its sampling clock (i.e., the offset clock signal) phase is usually set at the edge of the data eye diagram, such as near the zero crossover point, or in extreme cases, the entire eye diagram. It is used to monitor the voltage difference of the signal to drive the coefficient adaptive algorithm of equalizers such as DFE and CTLE, thereby optimizing the opening of the data eye diagram.

[0044] Specifically, each point of the offset sampled signal will have a horizontal and a vertical offset relative to the optimal sampling time (i.e., the sampling time of the data sampled signal). See also Figure 3 In (a), the error counter is typically composed of an XOR gate and a NAND gate. See also Figure 3 In (b) of the calculation, when calculating the bit error rate, by setting an appropriate step size, the offset sampling signal and the data sampling signal are compared one after another. If the two are inconsistent, for example, when the signal at the dotted line is received, the error counter is incremented (i.e., count + 1). The bit error rate can be calculated by dividing the final error count by the number of transmitted bits.

[0045] Figure 4 The diagram shown illustrates a scenario where a SerDes receiver performs serial-to-parallel conversion via a data sampler.

[0046] As an example, see Figure 4DIV1_CLK is the data clock signal. The data clock signal, through a Clock and Data Recovery (CDR) circuit, ensures the data sampler is always sampling in the data center. Thus, the data sampler can sample the even-numbered columns of the input serial data on the rising edge of DIV1_CLK and the odd-numbered columns on the falling edge, converting the serial data into two parallel data streams with a certain phase difference. Then, on the rising edge of the DIV1_CLK signal delayed by one cycle, the data sampler can simultaneously sample the odd and even columns from these two parallel data streams, aligning them. Subsequently, on the rising edge of the DIVI_CLK signal delayed by two cycles, the data sampler samples the two parallel data streams delayed by one cycle from the aligned two parallel data streams. Finally, on the rising edge of the frequency-divided data clock signal DIV2_CLK, the data sampler can simultaneously sample four parallel data streams from the aligned two parallel data streams and the two parallel data streams delayed by one cycle, completing the serial-to-parallel data conversion.

[0047] For example, see Figure 4 The data sampler can sample even-numbered data columns D0, D2, D4, and D6 from the serial data on the rising edge of DIV1_CLK, and odd-numbered data columns D1, D3, D5, and D7 on the falling edge. Then, on several rising edges of the DIV1_CLK signal delayed by one cycle, it samples D0, D1, D2, D3, D4, D5, D6, and D7 sequentially and simultaneously to align the even-numbered and odd-numbered data columns. Subsequently, on several rising edges of the DIV1_CLK signal delayed by two cycles, it samples... Figure 4 The data in data columns 1 and 2 are delayed by one cycle. Finally, four parallel data streams are sampled simultaneously from data columns 1 and 2, and the delayed data columns 1 and 2. For example, at the first rising edge of DIV2_CLK, D2 and D3 can be sampled from data columns 1 and 2 respectively, and D0 and D1 can be sampled from the delayed data columns 1 and 2 respectively.

[0048] For example, see Figure 4 After the signal is divided, the frequency becomes half of the original frequency, and the period is doubled.

[0049] As another example, see Figure 5 and Figure 6 The sampling process of the offset sampler is similar to that of the data sampler, except that its sampled data (data represented by the symbol E) will be offset within ±0.5 bit periods relative to the data sampler.

[0050] For example, see Figure 5The offset clock signal DIV1_CLK_O (i.e., the sampling clock signal of the offset sampler) is offset by -0.5 bit cycles (UI) relative to the data clock signal, and the sampled data is also offset by -0.5 bit cycles relative to the data sampler. See also Figure 6 The offset clock signal DIV1_CLK_O is offset by 0.5 bit cycles relative to the data clock signal, and the sampled data is also offset by 0.5 bit cycles relative to the data sampler.

[0051] Specifically, if the offset sampler does not shift, the error counter will receive the following: Figure 7 The two sets of parallel and relatively independent data shown will result in the following if an offset occurs: Figure 8 The example shown is two sets of data with a certain phase difference, such as signal 1 and signal 3, or signal 1 and signal 4. (See also...) Figure 9 If sampling is always fixed at the rising or falling edge of the offset clock signal after frequency division, the "eye" in the signal's eye diagram will be half open and half closed, affecting subsequent bit error rate calculations and data reception quality, especially in high-speed SerDes using 12nm FinFET technology. Therefore, precisely controlling the sampling clock phase of the offset sampler through digital filtering circuits to ensure that it samples data from the same period as the data sampler is an effective and reliable means of achieving accurate and reliable system bit error rate monitoring.

[0052] In view of this, the present invention provides an eye diagram data synchronization circuit that, based on the phase difference between the offset and the data clock signals, selects to directly output an offset sampling signal or selects to output a pre- or post-offset offset sampling signal that is advanced / delayed by half a bit period to participate in subsequent bit error rate calculation. By processing the advance / delay of the offset sampling signal, the phase error between the synchronized offset sampling signal and the data sampling signal can be made less than one bit period, thereby ensuring that both always output data of the same bit period, reducing the calculation error of the subsequent bit error rate, improving the signal reception quality, and realizing true and reliable system bit error rate monitoring.

[0053] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0054] Example 1

[0055] Figure 10 The diagram shown is a structural schematic of an eye diagram data synchronization circuit provided in an embodiment of the present invention. As an example and not a limitation, the circuit may include a calibration generation module 1, a first register R1, a second register R2, and a selection output module 2.

[0056] For example, calibration generation module 1 can generate a phase calibration signal based on the phase difference between the data sampling signal and the offset sampling signal. One of the first register R1 and the second register R2 is used to output the offset sampling signal, and the other is used to advance / delay the offset sampling signal (Offset DATA) by half a bit period to obtain the pre-set / post-set offset sampling signal. The selection output module 2 is used to select the offset sampling signal or the pre-set / post-set offset sampling signal as the synchronized offset sampling signal output, so that the synchronized offset sampling signal is in the same bit period as the data sampling signal.

[0057] Specifically, the first, second, and third input terminals of calibration generation module 1 can respectively input the frequency-divided data clock signal (DIV2_CLK), the frequency-divided offset clock signal (DIV2_CLK_O), and the calibration enable signal (USE EYESCANPHASE Calibration), and the output terminal is connected to the signal input terminal of selection output module 2. The signal input terminals of the first register R1 and the second register R2 both input the offset sampling signal, and the clock input terminals respectively input the mutually inverted first clock signal (DIV2_CLK_O_N) and second clock signal (DIV2_CLK_O_P), and the output terminals are respectively connected to the first and second input terminals of selection input module 2.

[0058] For example, the first and second clock signals are signals with the same frequency and shape as the divided data / offset clock signal.

[0059] In one example, if the data clock signal after frequency division (e.g.) Figure 4 DIV2_CLK) and offset clock signal (e.g. Figure 5 , 6 Phase difference of DIV2_CLK_O That is, the data sampling signal (e.g.) Figure 8 Signal 1) and offset sampling signal (e.g.) Figure 8 If the absolute value of the phase difference between the middle signals (2 / 3 / 4) is less than half a bit period, the offset sampling signal and the data sampling signal will output data of the same bit period at this time. Therefore, the offset sampling signal can be directly output as the synchronized offset sampling signal.

[0060] If the phase difference If the absolute value is greater than or equal to half a bit period, the offset sampling signal will be ahead / delayed by more than one bit period compared to the data sampling signal. In this case, the preceding / following offset sampling signal can be used as the synchronized offset sampling signal output. If the phase difference... If the offset sampling signal is greater than one and a half cycles, the offset sampling signal after the last synchronization can be used as the reset offset sampling signal. The phase difference between its clock signal and the data clock signal can be calculated. The above steps are repeated, and the offset sampling signal is output half a bit cycle earlier or later again, until the phase difference between the data sampling signal and the offset sampling signal is less than half a bit cycle.

[0061] For example, generally, the maximum phase difference between the data clock signal and the offset clock signal is ±0.5 bit cycles, such as ±90°. Then, one bit cycle of the offset / data sampling signal can occupy 90° of phase, and the maximum phase difference between the two can be ±45° (i.e. ±0.5 bit cycles of the offset / data sampling signal).

[0062] This invention, through advance / delay processing of the offset sampling signal, ensures that the phase error between the synchronized offset sampling signal and the data sampling signal is less than one bit period. This guarantees that both signals always output data within the same bit period, reducing subsequent bit error rate calculation errors, improving signal reception quality, and achieving true and reliable system bit error rate monitoring. Furthermore, the phase calibration signal continuously indicates the real-time phase difference between the data sampling signal and the offset sampling signal relative to half a bit period. This information triggers the selection output module to dynamically switch between two signal versions with a fixed half-bit period phase difference. When environmental factors cause phase drift, this switching mechanism instantly adjusts the phase of the offset sampling signal forward or backward by a minimum step, actively and continuously pulling it back to the same bit period as the data sampling signal. This closed-loop adjustment process based on real-time feedback allows the circuit to automatically track and compensate for the effects of process, voltage, and temperature variations. This not only significantly enhances the dynamic adaptability of synchronization but also achieves finer phase control through the adjustment of the minimum quantization step, thus stably achieving higher precision data synchronization under varying operating conditions.

[0063] Example 2

[0064] In some embodiments, the phase relationship between the output signals of the two registers can be determined first based on the effective sampling edges of the first and second registers, and then the register for outputting the offset sampling signal can be determined based on the phase difference between the data sampling signal and the offset sampling signal.

[0065] Generally, the data / offset sampler samples on the rising edge of the divided data / offset clock signal.

[0066] In one possible implementation, if both the first register R1 and the second register R2 are sampled on the rising edge of the clock signal, the signal output by the first register R1 is half a bit ahead of the signal output by the second register R2. In this case, the register for the output offset sampling signal can be set according to the sign of the phase difference.

[0067] In one example, if the phase difference between the data sampling signal and the offset sampling signal is positive, it means that the output of the offset sampling signal is later than the data sampling signal. In this case, the second register R2 can be set to output the offset sampling signal, and the first register R1 can be set to advance the offset sampling signal by half a bit period, thus outputting the pre-offset sampling signal.

[0068] In another example, if the phase difference between the data sampling signal and the offset sampling signal is negative, it means that the offset sampling signal precedes the data sampling signal. In this case, the first register R1 can be set to output the offset sampling signal, and the second register R2 can be set to delay the offset sampling signal by half a bit period, thus outputting the later offset sampling signal.

[0069] In another possible implementation, if both the first register R1 and the second register R2 are sampled on the falling edge of the clock signal, the signal output by the first register R1 is delayed by half a bit period compared to the signal output by the second register R2. In this case, the register for the output offset sampling signal can be set according to the sign of the phase difference.

[0070] In one example, if the phase difference between the data sampling signal and the offset sampling signal is positive, it means that the output of the offset sampling signal is later than the data sampling signal. In this case, the first register R1 can be set to output the offset sampling signal, and the second register R2 can be set to advance the offset sampling signal by half a bit period, thus outputting the pre-offset sampling signal.

[0071] In another example, if the phase difference between the data sampling signal and the offset sampling signal is negative, it means that the offset sampling signal precedes the data sampling signal. In this case, the second register R2 can be set to output the offset sampling signal, and the first register R1 can be set to delay the offset sampling signal by half a bit period, thus outputting the later offset sampling signal.

[0072] Example 3

[0073] Figure 11 The diagram shown illustrates a specific structure of a calibration signal generation module according to an embodiment of the present invention. As an example and not a limitation, the calibration generation module 1 may include an automatic calibration module 11, a first inverter INV1, a first data selector MUX1, and a second inverter INV2.

[0074] In some embodiments, the automatic calibration module 11 can calculate the phase difference between the data sampling signal and the offset sampling signal using the divided data clock signal and the divided offset clock signal, and determine whether the absolute value of the phase difference is greater than half a bit period to generate a first phase calibration signal. The first inverter INV1 can invert a preset phase difference indication signal to obtain a second phase calibration signal. The first data selector MUX1 can select the first / second phase calibration signal according to the calibration mode selection signal, and the second inverter INV2 can invert the signal selected by the first data selector MUX1 to obtain the phase calibration signal.

[0075] For example, the first, second, and third input terminals of the automatic calibration module 11 can be used as the first, second, and third input terminals of the calibration signal generation module 1, respectively, to input the frequency-divided data clock signal, the frequency-divided offset clock signal, and the calibration enable signal. The output terminal of the automatic calibration module 11 can be connected to the I1 input terminal of the first data selection MUX1, and the I0 input terminal of the first data selection MUX1 can be connected to the output terminal of the first inverter INV1, to input the inverted phase difference indication signal (i.e., the second phase calibration signal). The signal input terminal inputs the calibration mode selection signal, and the output terminal is connected to the input terminal of the second inverter INV2. The output terminal of the second inverter INV2 serves as the output terminal of the calibration signal generation module 1.

[0076] For example, the calibration enable signal is used to indicate whether the offset sampling signal is synchronized. Specifically, if the calibration enable signal is high, the eye diagram data synchronization circuit starts working to synchronize the offset sampling signal; if the calibration enable signal is low, the eye diagram data synchronization circuit does not work.

[0077] For example, the phase difference indicator signal can indicate whether the absolute value of the phase difference between the data sampling signal and the offset sampling signal is greater than half a bit period. For instance, if the phase difference between the two is greater than or equal to half a bit period, the phase difference indicator signal can be low; if the phase difference between the two is less than half a bit period, the phase difference indicator signal can be high.

[0078] Optionally, the phase difference indication signal can be manually set by the user.

[0079] In one possible implementation, the first data selection MUX1 can determine whether to start the automatic calibration mode or the manual calibration mode based on the calibration mode selection signal.

[0080] For example, if the calibration mode selection signal is high, i.e. S1=1, the automatic calibration mode can be started, and the first data selection MUX1 selects the first phase calibration signal output by the automatic calibration module 11; if the calibration mode selection signal is low, i.e. S1=0, the manual calibration mode can be started, and the first data selection MUX1 selects the second phase calibration signal output by the first inverter INV1.

[0081] In one example, see Figure 11 The automatic calibration module 11 may include an XOR gate, a TG gate, a capacitor C, a NAND gate, a third inverter INV3, and a third register R3.

[0082] For example, the XOR gate can extract the proportion of times when the data sampling signal and the offset sampling signal are inconsistent within a bit period through logical operations, thus obtaining the phase difference signal. The low-pass filter circuit composed of the transmission gate TG and the capacitor C can filter the phase difference signal, obtain the absolute value of the phase difference and compare it with the size of half a bit period, and then pass the comparison result to the first data selector MUX1 through the NAND gate, the third inverter INV3, and the third register R3.

[0083] Specifically, see Figure 11 The first to third inputs of the XOR gate can be used as the first to third inputs of the automatic calibration module 11, respectively. The output is connected to the input of the transmission gate TG. The output of the transmission gate TG and the first input of the NAND gate are both connected to one end of a capacitor C, with the other end of C grounded. The second input of the NAND gate receives the calibration enable signal, and its output is connected to the input of the third inverter INV3. The output of the third inverter INV3 serves as the output of the automatic calibration module 11.

[0084] As an example, setting the calibration enable signal high initiates the eye diagram data synchronization circuitry. If one bit cycle occupies 90° of phase, see [link to documentation]. Figure 11 and see Figure 12 When the phase difference between the data sampling signal and the offset sampling signal is within 45°, the high-level component of the phase difference signal O1 is less than the low-level component within one cycle. Therefore, after low-pass filtering, O2 is at a low level. Since the calibration enable signal remains at a high level, O3 is at a high level, and the inverted O4 is at a low level. The third register R3 transmits the low level at O4 to I1 (i.e., the I1 input of the first data selector). At this time, the user selects the automatic calibration mode, setting S1=1, and the second inverter INV2 inverts the low level to a high level and transmits it to the selection output module 2. The selection output module 2 selects the second register R2 to output the offset sampling signal.

[0085] As another example, similarly, setting the calibration enable signal high enables the eye diagram data synchronization circuitry to operate. If one bit cycle occupies 90° of phase, see [link to documentation]. Figure 11 and see Figure 13 When the phase difference between the data sampling signal and the offset sampling signal is greater than 45°, the high-level component of the phase difference signal O1 is greater than the low-level component within one cycle. Therefore, after low-pass filtering, O2 is at a high level. Since the calibration enable signal remains at a high level, O3 is at a low level, and the inverted O4 is at a high level. The third register R3 transmits the high level at O4 to I1 (i.e., the I1 input of the first data selector). At this time, the user selects the automatic calibration mode, sets S1=1, and the second inverter INV2 inverts the high level to a low level and transmits it to the selection output module 2. The selection output module selects the first register R1 to output the pre- / post-offset sampling signal.

[0086] Example 4

[0087] Figure 14 The diagram shown is a partial structural schematic of an eye diagram data synchronization circuit provided in an embodiment of the present invention. See also, as an example and not a limitation. Figure 14 The output module 2 may include a second data selector MUX2 and a fourth inverter INV4.

[0088] For example, the second data selector MUX2 can select either the offset sampling signal or the pre / post offset sampling signal based on the phase calibration signal, and the fourth inverter INV4 outputs the selected offset sampling signal or the pre / post offset sampling signal after inverting it.

[0089] Specifically, the I0 input of the second data selection MUX2 is used as the first input of the selection output module 2, the I1 input is used as the second input of the selection output module 2, and the output is connected to the input of the fourth inverter INV4. The output of the fourth inverter INV4 is used as the output of the selection output module 2.

[0090] Example 5

[0091] In some embodiments, the present invention also provides an eye diagram data synchronization method, which can be applied to the above-described eye diagram data synchronization device. The method may include:

[0092] S1, generate a phase calibration signal based on the phase difference between the data sampling signal and the offset sampling signal, wherein the phase calibration signal is used to indicate the relationship between the phase difference and half a bit period of the offset sampling signal.

[0093] S2 selects either the offset sampling signal or the pre- / post-offset offset sampling signal as the synchronized offset sampling signal output based on the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; wherein, the pre- / post-offset offset sampling signal is obtained by advancing / delaying the offset sampling signal by half a bit period.

[0094] This invention, through advance / delay processing of the offset sampling signal, ensures that the phase error between the synchronized offset sampling signal and the data sampling signal is less than one bit period. This ensures that both signals always output data within the same bit period, reducing subsequent bit error rate calculation errors, improving signal reception quality, and achieving true and reliable system bit error rate monitoring. Furthermore, the phase calibration signal continuously indicates the real-time phase difference between the data sampling signal and the offset sampling signal relative to half a bit period. This information triggers the selection output module to dynamically switch between two signal versions with a fixed half-bit period phase difference. When environmental factors cause phase drift, this switching mechanism instantly adjusts the phase of the offset sampling signal forward or backward by a minimum step, actively and continuously pulling it back to the same bit period as the data sampling signal. This closed-loop adjustment process based on real-time feedback allows the circuit to automatically track and compensate for the effects of process, voltage, and temperature variations. This not only significantly enhances the dynamic adaptability of synchronization but also achieves finer phase control through the adjustment of the minimum quantization step, thereby stably achieving higher precision data synchronization under varying operating conditions.

[0095] Example 6

[0096] Figure 15 The diagram shown is a schematic representation of a serial-to-parallel converter receiver according to an embodiment of the present invention. As an example and not a limitation, the serial-to-parallel converter receiver may include a joint equalization module 10, a data sampler 20, an offset sampler 30, an eye diagram data synchronization circuit 40, an XNOR gate, and an error counter 50.

[0097] For example, the joint equalization module 10 can perform equalization processing on the input signal to obtain an equalized signal, the data sampler 20 samples the equalized signal at the center of the eye diagram to obtain a data sampled signal, the offset sampler 30 samples the equalized signal at the offset center of the eye diagram to obtain an offset sampled signal, the eye diagram data synchronization circuit 40 can perform synchronization processing on the offset sampled signal to obtain a synchronized offset sampled signal, the XNOR gate can perform an XNOR operation on the synchronized offset sampled signal and the data sampled signal, and finally the error counter 50 can count errors based on the XNOR operation result to calculate the bit error rate.

[0098] Optionally, the joint equalization module 10 can be composed of CTLE and DFE.

[0099] Optionally, the eye diagram data synchronization circuit 40 can be the eye diagram data synchronization circuit in embodiments 1-4 above.

[0100] This invention, through advance / delay processing of the offset sampling signal, ensures that the phase error between the synchronized offset sampling signal and the data sampling signal is less than one bit period. This guarantees that both signals always output data within the same bit period, reducing subsequent bit error rate calculation errors, improving signal reception quality, and achieving true and reliable system bit error rate monitoring. Furthermore, the phase calibration signal continuously indicates the real-time phase difference between the data sampling signal and the offset sampling signal relative to half a bit period. This information triggers the selection output module to dynamically switch between two signal versions with a fixed half-bit period phase difference. When environmental factors cause phase drift, this switching mechanism instantly adjusts the phase of the offset sampling signal forward or backward by a minimum step, actively and continuously pulling it back to the same bit period as the data sampling signal. This closed-loop adjustment process based on real-time feedback allows the circuit to automatically track and compensate for the effects of process, voltage, and temperature variations. This not only significantly enhances the dynamic adaptability of synchronization but also achieves finer phase control through the adjustment of the minimum quantization step, thus stably achieving higher precision data synchronization under varying operating conditions.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Claims

1. An eye diagram data synchronization circuit, characterized in that, include: Calibration signal generation module, first register, second register, output selection module; The calibration signal generation module is used to generate a phase calibration signal based on the phase difference between the data sampling signal and the offset sampling signal, wherein the phase calibration signal is used to indicate the relationship between the phase difference and half a bit period of the offset sampling signal; Of the first register and the second register, one is used to output the offset sampling signal, and the other is used to advance / delay the offset sampling signal by half a bit period to obtain the pre-offset / post-offset sampling signal; The selection output module is used to select either the offset sampling signal or the pre / post offset sampling signal as the synchronized offset sampling signal output according to the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; The first and second input terminals of the selection output module are connected to the output terminals of the first and second registers, respectively, and the signal input terminal of the selection output module is connected to the output terminal of the calibration signal generation module.

2. The eye diagram data synchronization circuit according to claim 1, characterized in that, The calibration signal generation module includes: an automatic calibration module, a first inverter, a first data selector, and a second inverter; The automatic calibration module is used to automatically generate a first phase calibration signal based on the phase difference; The first inverter is used to invert the preset phase difference indication signal to obtain the second phase calibration signal; The first data selector is used to select the first phase calibration signal / second phase calibration signal according to the calibration mode selection signal, and the second inverter is used to invert the selected first phase calibration signal / second phase calibration signal and output it as the phase calibration signal. The output of the automatic calibration module is connected to the I1 input of the first data selector, the I0 input of the first data selector is connected to the output of the first inverter, the signal input of the first data selector receives the calibration mode selection signal, and the output of the first data selector is connected to the input of the second inverter.

3. The eye diagram data synchronization circuit according to claim 2, characterized in that, The automatic calibration module includes an XOR gate, a transmission gate, a capacitor, a NAND gate, a third inverter, and a third register; The first to third input terminals of the XOR gate serve as the first to third input terminals of the automatic calibration module, respectively, and are sequentially input with the frequency-divided data clock signal, the frequency-divided offset clock signal, and the calibration enable signal. The output terminal is connected to the input terminal of the transmission gate. The output terminal of the transmission gate and the first input terminal of the NAND gate are both connected to one end of the capacitor, and the other end of the capacitor is grounded. The calibration enable signal is input to the second input terminal of the NAND gate, and the output terminal is connected to the input terminal of the third inverter. The output of the third inverter is connected to the data input of the third register; The output of the third register serves as the output of the automatic calibration module.

4. The eye diagram data synchronization circuit according to claim 2, characterized in that, The offset sampling signal is input to the data input terminals of the first and second registers, and the first and second clock signals, which are inversely related, are input to the clock input terminals. The first and second clock signals are in the same frequency and shape as the offset clock signal after frequency division. The offset clock signal is the sampling clock signal of the offset sampler.

5. The eye diagram data synchronization circuit according to claim 4, characterized in that, The register used to output the offset sampling signal is determined based on the sign of the phase difference and the effective sampling edges of the first and second registers.

6. The eye diagram data synchronization circuit according to claim 5, characterized in that, If both the first and second registers have rising edges as valid sampling edges, then the second register is used to output the offset sampling signal when the phase difference is positive, and the first register is used to output the offset sampling signal when the phase difference is negative. If the effective sampling edges of the first and second registers are both falling edges, then when the phase difference is positive, the first register is used to output the offset sampling signal, and when the phase difference is negative, the second register is used to output the offset sampling signal.

7. The eye diagram data synchronization circuit according to claim 1, characterized in that, The selection output module includes a second data selector and a fourth inverter; The second data selector is used to select either the offset sampling signal or the pre / post offset sampling signal according to the phase calibration signal, and the fourth inverter is used to invert the selected offset sampling signal or the pre / post offset sampling signal and output it.

8. The eye diagram data synchronization circuit according to claim 1, characterized in that, If the absolute value of the phase difference is greater than or equal to half a bit period, the selection output module selects the pre- / post-offset sampling signal; if the absolute value of the phase difference is less than half a bit period, the selection output module selects the offset sampling signal.

9. A method for synchronizing eye diagram data, characterized in that, The method is applied to the eye diagram data synchronization circuit according to any one of claims 1-8, and the method includes: A phase calibration signal is generated based on the phase difference between the data sampling signal and the offset sampling signal, wherein the phase calibration signal is used to indicate the relationship between the phase difference and half a bit period of the offset sampling signal; Based on the phase calibration signal, an offset sampling signal or a pre- / post-offset offset sampling signal is selected as the output offset sampling signal after synchronization, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period; wherein, the pre- / post-offset offset sampling signal is obtained by outputting the offset sampling signal half a bit period earlier / later.

10. A serial-to-parallel converter receiver, characterized in that, include: Joint equalization module, data sampler, offset sampler, eye diagram data synchronization circuit as described in any one of claims 1-8, XNOR gate, error counter; The joint equalization module is used to equalize the input signal to obtain an equalized signal. The data sampler is used to sample the equalized signal at the center of the eye diagram to obtain a data sampled signal. The offset sampler is used to sample the equalized signal at the offset center position of the eye diagram to obtain an offset sampled signal. The eye diagram data synchronization circuit is used to synchronize the offset sampled signal to obtain a synchronized offset sampled signal. The XOR gate is used to perform an XOR operation on the synchronized offset sampled signal and the data sampled signal. The error counter is used to count errors based on the XOR operation result to calculate the bit error rate.

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