Channel circuit of navigation and short message integrated processing board card

Abstract

The application provides a channel circuit of a navigation and short message integrated processing board, which comprises a first low noise amplifier module, a double-channel navigation module, a second low noise amplifier module, a third surface acoustic filter, a third low noise amplifier module, a fourth surface acoustic filter, a first radio frequency transceiver integrated module, a second radio frequency transceiver integrated module, a clock module, a first power supply module and a second power supply module; the double-channel navigation module comprises a two-way splitter, a first surface acoustic filter, a second surface acoustic filter and a double-channel navigation radio frequency chip. The application realizes the reception and down-conversion of BD2 B1 frequency points and GPS L1 double-frequency satellite signals, the transmission of short message area and global signals, integrates a radio frequency filter, a low noise amplifier, a double-channel navigation module and a DC / DC module, and realizes the integrated design of each module in a small volume; the problem of the radio frequency circuit design of the integrated processing board card for receiving navigation signals and transmitting short message signals at the same time is solved.

Description

Technical Field

[0001] This invention relates to the field of electrical components technology, and specifically to a channel circuit for a navigation and short message integrated processing board. Background Technology

[0002] With the rapid development of aerospace technology, the development of microsatellites has become a crucial area of ​​aerospace research. As microsatellites are increasingly used in navigation, higher demands are being placed on the size and functionality of navigation receivers, leading to the development of various miniaturized navigation receiver boards. Due to size limitations, traditional navigation receivers and short message processors are typically two separate units, occupying a large volume and weight in the overall satellite layout, increasing satellite costs. Furthermore, microsatellites face strict limitations in size, weight, and energy consumption, and the unique space environment places even higher demands on the reliability and stability of the receivers.

[0003] Therefore, a small-sized, high-performance, highly reliable, multi-functional navigation and short message integrated device is needed to achieve precise orbit determination and short message transmission for microsatellites. Summary of the Invention

[0004] This invention addresses the issues of reliability, size, and multifunctionality of integrated navigation and short message systems in micro-satellite environments. It provides a channel circuit for an integrated navigation and short message processing board that supports simultaneous reception of satellite positioning and navigation signals and enables short message transmission. This board is small in size, highly reliable, and lightweight, making it particularly suitable for applications in micro-satellite environments and meeting the technical requirements of high-reliability, small-volume satellite systems.

[0005] This invention provides a channel circuit for a navigation and short message integrated processing board, including a first low-noise amplifier module and a dual-channel navigation module connected together; a second low-noise amplifier module and a third surface acoustic wave filter connected together; a third low-noise amplifier module and a fourth surface acoustic wave filter connected together; a first radio frequency transceiver module connected to the output terminals of both the third and fourth surface acoustic wave filters; a second radio frequency transceiver module that converts baseband signals to radio frequency signals and transmits them; a clock module connected to the dual-channel navigation module, the first radio frequency transceiver module, and the second radio frequency transceiver module and providing clock signals; a first power supply module that supplies power to the first low-noise amplifier module, the dual-channel navigation module, and the clock module; and a second power supply module that supplies power to the second low-noise amplifier module, the third low-noise amplifier module, the first radio frequency transceiver module, and the second radio frequency transceiver module.

[0006] The dual-channel navigation module includes a splitter connected to the output of the first low-noise amplifier module, a first surface acoustic wave filter and a second surface acoustic wave filter connected to the two outputs of the splitter respectively, and a dual-channel navigation radio frequency chip connected to the outputs of both the first and second surface acoustic wave filters.

[0007] After being amplified by the first low-noise amplifier module, the radio frequency signal enters the splitter through the DC blocking capacitor. The splitter divides the radio frequency input signal into two paths. The first path signal is suppressed by the first surface acoustic wave filter to obtain the suppressed first in-band GPS signal. The second path signal is filtered by the second surface acoustic wave filter to obtain the first in-band BDS signal. When the clock module sends the clock signal, the dual-channel navigation radio frequency chip filters, amplifies with controllable gain, and down-converts the first in-band GPS signal and the first in-band BDS signal, and outputs the first differential intermediate frequency GPS signal and the first differential intermediate frequency Beidou signal to the outside as the first output signal of the channel circuit of the navigation and short message integrated processing board.

[0008] When the clock module sends a clock signal, the first RF transceiver module filters the GPS and BeiDou signals, which have been amplified by the second and third low-noise amplifier modules and filtered by the third and fourth surface acoustic wave filters, respectively. It then performs controlled gain amplification, down-conversion, and outputs the signal to the short message processing module.

[0009] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board described in this invention, the two-splitter operates at a frequency range of 1200MHz to 2000MHz with an isolation impedance of 20dB; the center frequency of the first surface acoustic wave filter is 1575 MHz with a bandwidth of 8 MHz, and the frequency of the GPS signal within the first band is the L1 frequency; the center frequency of the second surface acoustic wave filter is 1561MHz with a bandwidth of 15 MHz, and the frequency of the BDS signal within the first band is the B1 frequency.

[0010] The first low-noise amplifier module, the dual-channel navigation module, the second low-noise amplifier module, the third surface acoustic wave filter, the third low-noise amplifier module, the fourth surface acoustic wave filter, the first RF transceiver module, the second RF transceiver module, the clock module, the first power supply module, and the second power supply module are all connected on a single printed circuit board.

[0011] The channel circuit of the navigation and short message integrated processing board described in this invention, as a preferred embodiment, controls the high-frequency radio frequency signal traces on the printed circuit board to have a 50Ω impedance, so that the clock module traces are located on a separate intermediate signal layer of the printed circuit board, and uses a metal shield to isolate the radio frequency part from the digital circuit, so that the circuit noise figure of the navigation and short message integrated processing board is less than 3 and the in-band fluctuation of the output signal is less than 1dB.

[0012] The third and fourth surface acoustic filters filter, after filtering, controlling gain amplification and down-conversion of the suppressed B2b and S frequency signals, outputs them to the short message information processing module.

[0013] In the first RF transceiver module, the intermediate frequency output pins of the RF chip are multiplexed, allowing for switching between analog signals and 4-bit digital signals.

[0014] The second RF transceiver module inputs LVTTL or CMOS level BPSK signals through the 54-pin INTX input. The transmit channel integrates a low-pass filter, BPSK modulator, variable gain amplifier and RF amplifier to transmit RDSS and global short message L-band inbound signals.

[0015] The clock module includes a temperature-controlled crystal oscillator with an initial accuracy of ≤ at the reference temperature. Allen's variance ≤ Output power ≥9dBm.

[0016] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board described in this invention, the SPI port signal of the dual-channel navigation RF chip is connected to the I / O of the baseband chip. The SPI port signal includes the LE signal, the DATA signal, and the CLK signal.

[0017] The dual-channel navigation RF chip has 56 configuration registers. Registers 0-19 control channel 1, with registers 11-12 controlling the local oscillator signal of channel 1 of the dual-channel navigation module; registers 20-39 control channel 2 of the dual-channel navigation module, with registers 31-32 controlling the local oscillator signal of channel 2 of the dual-channel navigation module; registers 40-49 control the sampling clock of the dual-channel navigation RF chip; and registers 50-55 control the reference unit module of the dual-channel navigation RF chip.

[0018] Registers 11~12 control the local oscillator frequency of channel 1 of the dual-channel navigation module through two control words, P1[7:0] and S1[6:0]. The intermediate frequency output frequency is 3.92MHz, the local oscillator frequency of channel 1 of the dual-channel navigation module is 1571.5MHz, the local oscillator signal PLL operating frequency is 3143MHz, the frequency division ratio is 3143, P1[7:0] is 0X62, and S1[6:0] is 0X17.

[0019] Registers 31~32 control the local oscillator frequency of channel 2 of the dual-channel navigation module through two control words, P2[7:0] and S2[6:0]. The intermediate frequency output frequency is 4MHz, the local oscillator frequency is 1557MHz, the local oscillator signal operating frequency is 3114MHz, the frequency division ratio is 3114, P2[7:0] is 0X61, and S2[6:0] is 0X14.

[0020] Registers 7 and 27 control the output intermediate frequency (IF) point and bandwidth of the dual-channel navigation module. By setting various IF filter operating mode control words, the dual-channel navigation module can achieve different IF frequency ranges. When the IF filter operating mode control word is 11, the output IF frequency range is 16MHz IF and 20MHz bandwidth. When the IF filter operating mode control word is 10, the output IF frequency range is 16MHz IF and 10MHz bandwidth. When the IF filter operating mode control word is 01, the output IF frequency range is 4MHz IF and 4MHz bandwidth.

[0021] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board described in this invention, pins 1, 2, 3, 4, 8, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 47, 48, 49, 50, 63, and 64 of the dual-channel navigation RF chip are grounded; power supply pins 5, 7, 9, 10, 12, 30, 39, and 51 are connected to +3.3V; and power supply pins 20, 22, 23, 24, 25, 37, 38, 46, 56, 57, 58, 59, and 61 are connected to +1V. 0.8V voltage, pins 19, 28, 29, 35, 44, 52, 53, and 62 are unused; pin 6 inputs BeiDou RF signal, pin 11 inputs GPS RF signal, output pins 26, 27, 54, and 55 output the first differential intermediate frequency GPS signal, and output pins 52, 53, 54, and 55 output the first differential intermediate frequency BeiDou signal; loop filter pin 21 connects one end of capacitor C155 and one end of capacitor C156, the other end of capacitor C156 is connected to ground through resistor R162, and the other end of capacitor C155 is grounded. The loop filter pin 60 connects to one end of capacitor C82 and one end of capacitor C83. The other end of capacitor C82 is grounded through resistor R147, and the other end of capacitor C83 is grounded. Configuration pin 40 connects to the external chip select signal RF1_CS through resistor R158. Configuration pin 41 connects to the external data signal RF1_MOSI through resistor R157. Configuration pin 42 connects to the external clock signals RF1, SPI, and CLK through resistor R155. Configuration pin 43 outputs data through resistor R156. Signal RF1_MISO; Clock input pin 45 is connected to one end of capacitor C107. The other end of capacitor C107 is connected to one end of resistors R153 and R154. The other end of resistor R153 is grounded, and the other end of resistor R154 is connected to the input 62MHz clock signal. AD sampling clock input pin 35 is connected to one end of capacitor C131. The other end of capacitor C131 is connected to resistors R159 and R160. The other end of resistor R160 is grounded, and the other end of resistor R159 is connected to the input 62MHz clock signal.

[0022] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board of the present invention, the first power supply module includes voltage regulator N1, voltage regulator N2 and voltage regulator N3.

[0023] The IN and SHDN pins of voltage regulator N1 are connected to one end of capacitor C157 and the +5.4V input voltage, with the other end of capacitor C157 connected to ground. The OUT and ADJ pins of voltage regulator N1 are connected to resistors R170 and R177. The ADJ pin of voltage regulator N1 is connected to resistor R181, with one end of resistor R181 connected to resistor R177 and the other end grounded. The OUT pin of voltage regulator N1 is connected to capacitors C162 and C163 in parallel and the +5V output voltage, with the other ends of capacitors C162 and C163 connected to ground.

[0024] The IN and SHDN pins of voltage regulator N2 are connected to one end of capacitor C159 and the +5.4V input voltage, while the other end of capacitor C159 is grounded. The OUT and ADJ pins of voltage regulator N2 are connected to resistor R174. The ADJ pin of voltage regulator N2 is connected to resistors R178 and R182, with one end of resistor R182 connected to resistor R178 and the other end grounded. The OUT pin of voltage regulator N2 is connected to capacitors C158 and C164 in parallel and the +3.3V output voltage, with the other ends of capacitors C158 and C164 connected to ground.

[0025] The IN and SHDN pins of voltage regulator N3 are connected to one end of capacitor C161 and the +5.4V voltage, while the other end of capacitor C161 is grounded. The OUT and ADJ pins of voltage regulator N3 are connected to resistor R175. The ADJ pin of voltage regulator N3 is connected to resistors R179 and R183, with R179 and R175 connected in series, and the other end of resistor R183 is grounded. The OUT pin of voltage regulator N3 is connected to capacitors C160 and C165 in parallel and the +1.8V output voltage, with the other ends of capacitors C160 and C165 connected to ground.

[0026] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board of the present invention, the second power supply module includes a voltage regulator N4 and a voltage regulator N5.

[0027] The IN and SHDN pins of voltage regulator N4 are connected to one end of capacitor C345 and the +5.4V voltage, and the other end of capacitor C345 is connected to ground; the OUT and ADJ pins of voltage regulator N4 are connected to resistors R370 and R371; the ADJ pin of voltage regulator N4 is connected to resistor R372, with one end of resistor R372 connected to resistor R371 and the other end grounded; the OUT pin of voltage regulator N4 is connected to capacitors C341 and C346 in parallel and the +5V output voltage, with the other ends of capacitors C341 and C346 connected to ground.

[0028] The IN and SHDN pins of voltage regulator N5 are connected to one end of capacitor C359 and the +5.4V voltage, while the other end of capacitor C359 is grounded. The OUT and ADJ pins of voltage regulator N5 are connected to resistor R391. The ADJ pin of voltage regulator N5 is connected to resistors R392 and R393 in series. Resistor R392 is connected in series with resistor R391, and the other end of resistor R393 is grounded. The OUT pin of voltage regulator N5 is connected to capacitors C358 and C360 in parallel and the +3.3V output voltage. The other ends of capacitors C358 and C360 are connected together and then grounded.

[0029] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board of the present invention, the first low-noise amplifier module includes a low-noise module A1, an inductor L35, an inductor L39, a capacitor C310, and a capacitor C311.

[0030] The input pin of the low-noise module A1 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L35 and inductor L39. The other end of inductor L35 and inductor L39 is connected to one end of capacitor C310 and capacitor C311 and +5V. The other end of capacitor C310 and capacitor C311 is grounded.

[0031] The first surface acoustic wave filter includes a surface acoustic wave filter Z1, capacitor C134, capacitor C135, and inductor L12;

[0032] Pin 5 IN of the surface acoustic wave (SAW) filter Z1 is connected to the GPS radio frequency signal. Pin 2 OUT of the SAW filter Z1 is connected to one end of capacitor C134. The other end of capacitor C134 is connected to one end of inductor L12 and capacitor C135. The other ends of inductor L12 and capacitor C135 are grounded.

[0033] The second surface acoustic wave filter includes surface acoustic wave filter Z2, capacitor C99, capacitor C100, and inductor L10;

[0034] Pin 5 (IN) of the surface acoustic wave (SAW) filter Z2 is connected to the BeiDou radio frequency signal. Pin 2 (OUT) of the SAW filter Z2 is connected to one end of capacitor C99. The other end of capacitor C99 is connected to one end of inductor L10 and capacitor C100. The other ends of inductor L10 and capacitor C100 are grounded.

[0035] In a preferred embodiment of the channel circuit of the navigation and short message integrated processing board of the present invention, the second low-noise amplifier module includes a low-noise module A2, an inductor L11, an inductor L13, a capacitor C136, and a capacitor C137.

[0036] The input pin of the low-noise module A2 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L11 and inductor L13. The other end of inductor L11 and inductor L13 is connected to one end of capacitor C136 and capacitor C137 and +5V. The other end of capacitor C136 and capacitor C137 is grounded.

[0037] The third low-noise amplifier module includes low-noise module A3, inductor L36, inductor L38, capacitor C138, and capacitor C139;

[0038] The input pin of the low-noise module A3 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L36 and inductor L38. The other end of inductor L36 and inductor L38 is connected to one end of capacitor C138 and capacitor C139 and +5V. The other end of capacitor C138 and capacitor C139 is grounded.

[0039] The third surface acoustic wave filter includes surface acoustic wave filter Z4, capacitor C323 and inductor L37;

[0040] Pin 2 (IN) of the surface acoustic wave (SAW) filter Z4 is connected to the B2b frequency radio frequency signal, and pin 5 (OUT) of the SAW filter Z4 is connected to one end of capacitor C23. The other end of capacitor C23 is connected to inductor L37, and the other end of inductor L37 outputs the radio frequency signal.

[0041] The third surface acoustic wave filter includes surface acoustic wave filter Z5, capacitor C309 and inductor L34;

[0042] Pin 2 (IN) of the surface acoustic wave (SAW) filter Z5 is connected to the S-frequency radio frequency (RF) signal. Pin 5 (OUT) of the SAW filter Z5 is connected to one end of capacitor C309. The other end of capacitor C309 is connected to inductor L34, and the other end of inductor L34 outputs the RF signal.

[0043] The channel circuit of the navigation and short message integrated processing board of the present invention, as a preferred embodiment, includes a first radio frequency transceiver integrated module comprising a radio frequency transceiver integrated radio frequency chip D29, capacitors C325, C326, C333, C290, C295, C297, resistors R364, R367, R339, R344, R345, and R346;

[0044] The power supply pins 1, 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 57, 61, and 68 of the RF transceiver chip D29 are connected to +3.3V. The enable pins 3, 10, and 13 are also connected to +3.3V. Pins 4, 5, 8, 25, 29, 48, 49, 50, 55, 59, 60, 62, and 69 are grounded. Pins 15, 16, 17, 20, 21, 22, 30, 31, 32, 33, and 58 are left unused.

[0045] The D29 RF transceiver chip has pin 6 for inputting S-frequency RF signals, pin 15 for inputting B2b RF signals, pins 39, 40, 41, and 42 for outputting B2b digital intermediate frequency signals, and pins 30, 31, 32, and 33 for outputting S-frequency digital intermediate frequency signals. The clock input pin 63 is connected to the 62MHz clock signal output by the clock module.

[0046] The CP-RX1 pin 19 of the D29 RF transceiver chip is connected to one end of capacitor C326 and resistor R364. The other end of capacitor C326 is grounded, and the other end of resistor R364 is grounded through capacitor C325. The CP-RX3 pin 56 is connected to one end of capacitor C295 and resistor R347. The other end of capacitor C295 is grounded, and the other end of resistor R347 is grounded through capacitor C290. The SPI_CS_N pin 64 is connected to the external input chip select signal through resistor R339. The SPI_CLK pin 65 is connected to the external input SPI clock signal through resistor R344. The SPI_MOSI pin 64 is connected to the external input data signal through resistor R345. The SPI_MISO pin 64 outputs a data signal to the external device through resistor R339.

[0047] The second RF transceiver module includes an RF transceiver chip D30, capacitors C371, C373, C291, C302, and C336, resistors R341, R438, R439, R440, R441, R342, and R435, an inductor L32, and a filter Z3.

[0048] The power supply pins 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 52, 57, 61, and 68 of the RF transceiver chip D30 are connected to +3.3V, the enable pin 4 is connected to +3.3V, pins 1, 3, 5, 10, 13, 16, 55, 62, and 69 are grounded, and pins 2, 6, 8, 11, 15, 17, 19, 20, 21, 22, 26, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 56, and 58 are left unused.

[0049] The CP-TX pin 50 of the D30 RF transceiver chip is connected to one end of capacitor C373 and resistor R441. The other end of capacitor C373 is grounded, and the other end of resistor R441 is grounded through capacitor C371. The IN-TX pin 54 is connected to one end of resistor R342. The other end of resistor R342 is connected to the signal IF_RD_OUT and resistor R435. The other end of resistor R435 is grounded. The OUT-TX pin 5 is connected to one end of capacitor C302. The other end of capacitor C302 is connected to signal capacitor C291 and... The filter Z2 is connected to pin 5 of the filter Z3 via inductor L32, and the other end of capacitor C291 is grounded. Pin 2 of the filter Z2 outputs a short message to transmit an RF signal. Pin 64 of SPI_CS_N is connected to the external input chip select signal via resistor R341, pin 65 of SPI_CLK is connected to the external input SPI clock signal via resistor R438, pin 64 of SPI_MOSI is connected to the external input data signal via resistor R439, and pin 64 of SPI_MISO outputs a data signal to the external device via resistor R440.

[0050] Both the D29 and D30 RF transceiver chips integrate a low-noise amplifier, mixer, filter, variable gain amplifier, analog-to-digital converter, automatic gain control circuit, BPSK modulator, RF amplifier, frequency synthesizer, clock sampling circuit, low-voltage linear power supply and three-bus control circuit, and can simultaneously complete navigation signal reception and short message transmission.

[0051] The clock module includes crystal oscillator G2, capacitors C277, C278, C280, C281, C282, C275, and C276, resistors R333, R335, R330, R336, R337, R133, R334, R434, R144, inductors L30 and L31;

[0052] The power supply pin 1 of crystal oscillator G2 is connected to one end of parallel capacitors C277 and C280, parallel capacitors C278 and C281, and parallel inductors L30 and L31. The other ends of capacitors C280 and C281 are grounded, and the other ends of inductors L30 and L31 are connected to +5V. Pin 4 of crystal oscillator G2 is grounded. The Vc and Vref pins of crystal oscillator G2 are connected through resistor R333, and the Vc pin is connected to ground through resistor R335 and capacitor C282. The output pin 5 of crystal oscillator G2 is connected to one end of capacitor C275, and the other end of capacitor C275... One end of resistor R330 and one end of resistor R336 are connected to the ground. The other end of resistor R336 is connected to ground through resistor R337 and is also connected to one end of capacitor C276. The other end of capacitor C276 is connected to resistor R133 and outputs the reference clock of the dual-channel navigation module, connected to resistor R144 and outputs the AD sampling clock of the dual-channel navigation module, connected to resistor R334 and outputs the reference clock of the first RF transceiver module, and connected to resistor R434 and outputs the reference clock of the second RF transceiver module.

[0053] The present invention has the following advantages:

[0054] (1) The present invention realizes that while the navigation radio frequency signal and short message signal transmission are processed independently, they are concentrated on a single processing board, which reduces costs. It has the characteristics of low cost, small size and full functionality, which meets the current needs of small satellites that need to be able to transmit short messages while providing navigation and positioning.

[0055] (2) This invention realizes navigation signal processing at 1.5GHz frequency under Beidou and GPS navigation systems, and has achieved reception of short message at 1.2GHz and 2.4GHz frequency. Through the frequency design of the first surface acoustic filter and the second surface acoustic filter in the dual-channel navigation module, this design is also applicable to receiving navigation signals at other multiple frequency points.

[0056] (3) The present invention realizes the radio frequency part of the short message processor, and uses two radio frequency transceiver modules to complete the functions of receiving and sending short messages. It has good isolation and ensures the reliability of the channel circuit.

[0057] (4) This invention realizes the requirement of the clock module to provide clock for both the navigation part and the short message part at the same time, reducing the board area and reducing the cost. The clock amplitude has been verified to meet the usage requirements. Attached Figure Description

[0058] Figure 1 A schematic diagram of the overall design of the channel circuit of a navigation and short message integrated processing board;

[0059] Figure 2aSchematic diagram of voltage regulator N1 for the first power supply module of a navigation and short message integrated processing board;

[0060] Figure 2b A schematic diagram of the voltage regulator N2 of the first power supply module of the channel circuit of a navigation and short message integrated processing board;

[0061] Figure 2c Schematic diagram of voltage regulator N3 for the first power supply module of a navigation and short message integrated processing board;

[0062] Figure 3 A schematic diagram of a dual-channel navigation module circuit for a navigation and short message integrated processing board.

[0063] Figure 4 The schematic diagram of the dual-channel navigation RF chip circuit in the channel circuit of a navigation and short message integrated processing board is shown.

[0064] Figure 5a A schematic diagram of the voltage regulator for the second power supply module of a navigation and short message integrated processing board.

[0065] Figure 5b The channel circuit of a navigation and short message integrated processing board

[0066] Figure 6 The schematic diagrams of the internal circuitry of the first and second RF transceiver modules of a navigation and short message integrated processing board are shown.

[0067] Figure 7 A schematic diagram of the first radio frequency transceiver module circuit of a navigation and short message integrated processing board.

[0068] Figure 8 A schematic diagram of the second radio frequency transceiver module circuit of a navigation and short message integrated processing board.

[0069] Figure 9 This is a schematic diagram of the clock module circuit for a navigation and short message integrated processing board. Detailed Implementation

[0070] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0071] like Figure 1As shown, a channel circuit of a navigation and short message integrated processing board includes: a first power supply module, a second power supply module, a first low noise amplifier module, a second low noise amplifier module, a third low noise amplifier module, a first surface acoustic wave filter, a second surface acoustic wave filter, a third surface acoustic wave filter, a fourth surface acoustic wave filter, a dual-channel navigation module, a first radio frequency transceiver integrated module, a second radio frequency transceiver integrated module, and a clock module.

[0072] The first power supply module supplies power to the clock module, the first low-noise amplifier module, and the dual-channel navigation module; the second power supply module supplies power to the clock module, the second low-noise amplifier module, the third low-noise amplifier module, the first RF transceiver module, and the second RF transceiver module; the clock module provides clock signals to the dual-channel navigation module, the first RF transceiver module, and the second RF transceiver module.

[0073] The external navigation RF input signal is fed into an RF filter, filtered, and then amplified by a low-noise amplifier to obtain a narrowband signal, which is then fed into a matching network. The matching network receives the narrowband signal, attenuates and performs impedance matching on it to obtain the signal to be split, which is then sent to a splitter. The splitter divides the signal to be split into two paths, resulting in a GPS signal and a BeiDou signal, respectively. The splitter sends the GPS signal and the BeiDou signal to a surface acoustic wave filter for out-of-band suppression, resulting in a suppressed first-band in-band GPS signal and a first-band in-band BeiDou signal, which are then sent to the navigation module of the dual-channel navigation module. When the clock module sends the first clock signal, the first navigation module filters, amplifies with controllable gain, and down-converts the suppressed first-band in-band GPS signal and the suppressed first-band in-band BeiDou signal, respectively, and outputs a first differential intermediate frequency GPS signal and a first differential intermediate frequency BeiDou signal, which are then sent to the outside as the first output signal of the channel circuit of the navigation and short message integrated processing unit board. The differential signal refers to the fact that the dual-channel navigation module internally converts the analog signal into a differential digital signal for output.

[0074] The S-band signal and the BeiDou B2 signal enter the RF filter, are filtered, and then amplified by the low-noise amplifier to obtain a narrowband signal, which is then sent to the matching network. The matching network receives the narrowband signal, attenuates it, and performs impedance matching. The S-band signal and the BeiDou B2 signal are then sent to the first RF transceiver module after out-of-band suppression by the surface acoustic wave (SAW) filter. When the clock module sends a clock signal, the first RF transceiver module filters, amplifies with controllable gain, and down-converts the suppressed signal to output an intermediate frequency (IF) signal as the second output signal of the navigation and short message integrated processing board. At the same time, the externally transmitted quasi-IF signal is sent to the second RF transceiver module, where it undergoes DA conversion, low-pass filtering, signal modulation, and controllable gain amplification before being output as a short message RF signal.

[0075] The first in-band composite signal includes L1 and B1I frequency points;

[0076] The second radio frequency signal includes the S frequency point, and the third radio frequency signal includes the B2 frequency point;

[0077] The first power supply module includes voltage regulators N1, N2, and N3; capacitors C157, C162, C163, C159, C158, C164, C161, C160, and C165; and resistors R170, R177, R181, R174, R178, R182, R175, R179, and R183.

[0078] The voltage regulator N1 uses the LT1963AES8 chip from LINEAR Corporation. The IN and SHDN pins of the LT1963AES8 chip are connected to one end of capacitor C157 and the +5.4V voltage, with the other end of capacitor C157 connected to ground. The OUT and ADJ pins of the LT1963AES8 chip are connected to resistors R170 and R177. The ADJ pin of the LT1963AES8 chip is connected to resistor R181, with the other end of resistor R181 connected to ground. The OUT pin of the LT1963AES8 chip is connected to capacitors C162 and C163 and the +5V output voltage.

[0079] The voltage regulator N2 uses the LT1963AES8 chip from LINEAR Corporation. The IN and SHDN pins of the LT1963AES8 chip are connected to one end of capacitor C159 and the +5.4V voltage, with the other end of capacitor C159 connected to ground. The OUT and ADJ pins of the LT1963AES8 chip are connected to resistor R174; the ADJ pin of the LT1963AES8 chip is connected to resistors R178 and R182, with the other end of resistor R182 connected to ground; the OUT pin of the LT1963AES8 chip is connected to capacitors C158 and C164 and the +3.3V output voltage.

[0080] The voltage regulator N3 uses the LT1963AES8 chip from LINEAR Corporation. The IN and SHDN pins of the LT1963AES8 chip are connected to one end of capacitor C161 and the +5.4V voltage, with the other end of capacitor C161 connected to ground. The OUT and ADJ pins of the LT1963AES8 chip are connected to resistor R175. The ADJ pin of the LT1963AES8 chip is connected to resistors R179 and R183, with the other end of resistor R183 connected to ground. The OUT pin of the LT1963AES8 chip is connected to capacitors C160 and C165 and the +1.8V output voltage.

[0081] The first low-noise amplifier module includes a low-noise module A1, inductor L35, inductor L39, capacitor C310, and capacitor C311.

[0082] The low-noise module A1 uses a navigation low-noise amplifier module developed by the Beijing Telemetry Technology Research Institute. The input pin of the low-noise module A1 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L35 and inductor L39. The other end of inductor L35 and inductor L39 is connected to one end of capacitor C310 and capacitor C311 and +5V. The other end of capacitor C310 and capacitor C311 is grounded.

[0083] The first surface acoustic wave filter includes a surface acoustic wave filter Z1, capacitor C134, capacitor C135, and inductor L12.

[0084] The surface acoustic wave (SAW) filter Z1 uses the SBPF6S3050 manufactured by Beijing Aerospace Microelectronics Technology Co., Ltd. Pin 5 IN of the SAW filter Z1 is connected to the GPS radio frequency signal, and pin 2 OUT of the SAW filter Z1 is connected to one end of capacitor C134. The other end of capacitor C134 is connected to one end of inductor L12 and capacitor C135. The other ends of inductor L12 and capacitor C135 are grounded.

[0085] The second surface acoustic wave filter includes surface acoustic wave filter Z2, capacitor C99, capacitor C100, and inductor L10.

[0086] The surface acoustic wave (SAW) filter Z2 uses SBPF6S3016 manufactured by Beijing Aerospace Microelectronics Technology Co., Ltd. Pin 5 IN of the SAW filter Z2 is connected to the Beidou radio frequency signal, and pin 2 OUT of the SAW filter Z2 is connected to one end of capacitor C99. The other end of capacitor C99 is connected to one end of inductor L10 and capacitor C100. The other ends of inductor L10 and capacitor C100 are grounded.

[0087] The dual-channel navigation module includes a navigation RF chip D11, capacitors C82, C83, C107, C155, C156, C131, and resistors R147, R162, R153, R154, R155, R156, R157, R158, R159, and R160.

[0088] The navigation RF chip D11 uses the AB3212MFB chip developed by the 704 Institute of the Ninth Academy of Aerospace Science and Technology. Pins 1, 2, 3, 4, 8, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 47, 48, 49, 50, 63, and 64 of the navigation RF chip D11 are grounded; pins 5, 7, 9, 10, 12, 30, 39, and 51 of the navigation RF chip D11 are connected to +3.3V, and pins 20, 22, 23, 24, 25, 37, 38, 46, 56, 57, 58, 59, and 61 of the navigation RF chip D11 are connected to +1.8V. Pins 19, 28, 29, 35, 44, 52, 53, and 62 of the navigation RF chip D11 are unused; pin 6 of the navigation RF chip D11 inputs the BeiDou RF signal, pin 11 of the navigation RF chip D11 inputs the GPS RF signal, pins 26, 27, 54, and 55 of the navigation RF chip D11 output the first differential intermediate frequency GPS signal, and pins 52, 53, 54, and 55 of the navigation RF chip D11 output the first differential intermediate frequency BeiDou signal; pin 21 of the loop filter of the navigation RF chip D11 is connected to one end of capacitor C155 and one end of capacitor C156, and the other end of capacitor C156 is connected to ground through resistor R162. The other end of pin 55 is grounded; pin 60 of the loop filter of navigation RF chip D11 is connected to one end of capacitor C82 and one end of capacitor C83, the other end of capacitor C82 is connected to ground through resistor R147, and the other end of capacitor C83 is grounded; pin 40 of navigation RF chip D11 is connected to the external input chip select signal RF1_CS through resistor R158; pin 41 of navigation RF chip D3 is connected to the external input data signal RF1_MOSI through resistor R157; pin 42 of navigation RF chip D11 is connected to the external input clock signal RF1_SPI_CLK through resistor R155; navigation RF chip D... Pin 43 of the D11 configuration chip outputs the data signal RF1_MISO through resistor R156; pin 45 of the navigation RF chip D11 is connected to one end of capacitor C107, the other end of capacitor C107 is connected to one end of resistors R153 and R154, the other end of resistor R153 is grounded, and the other end of resistor R154 is connected to the input 62MHz clock signal; pin 35 of the navigation RF chip D11's AD sampling clock input is connected to one end of capacitor C131, the other end of capacitor C131 is connected to resistors R159 and R160, the other end of resistor R160 is grounded, and the other end of resistor R159 is connected to the input 62MHz clock signal.

[0089] like Figure 5a , 5bAs shown, the second power supply module includes voltage regulators N4 and N5, capacitors C341, C345, C346, C358, C359, and C360, and resistors R370, R371, R372, R391, R392, and R393.

[0090] The voltage regulator N4 uses the LT1963AES8 chip from LINEAR Corporation (USA). The IN and SHDN pins of the LT1963AES8 chip are connected to one end of capacitor C345 and the +5.4V voltage, with the other end of capacitor C345 connected to ground. The OUT and ADJ pins of the LT1963AES8 chip are connected to resistors R370 and R371; the ADJ pin of the LT1963AES8 chip is connected to resistor R372, with the other end of resistor R372 connected to ground; the OUT pin of the LT1963AES8 chip is connected to capacitors C341 and C346 and the external +5V output.

[0091] The voltage regulator N5 uses the LT1963AES8 chip from LINEAR Corporation (USA). The IN and SHDN pins of the LT1963AES8 chip are connected to one end of capacitor C359 and the +5.4V voltage, with the other end of capacitor C359 connected to ground. The OUT and ADJ pins of the LT1963AES8 chip are connected to resistor R391; the ADJ pin of the LT1963AES8 chip is connected to resistors R392 and R393, with the other end of resistor R393 connected to ground; the OUT pin of the LT1963AES8 chip is connected to capacitors C358 and C360 and the external +3.3V output.

[0092] The second low-noise amplifier module includes a low-noise module A2, inductors L11 and L13, and capacitors C136 and C137.

[0093] The low-noise module A2 uses a navigation low-noise amplifier module developed by the Beijing Telemetry Technology Research Institute. The input pin of the low-noise module A2 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L11 and inductor L13. The other end of inductor L11 and inductor L13 is connected to one end of capacitor C136 and capacitor C137 and +5V. The other end of capacitor C136 and capacitor C137 is grounded.

[0094] The third low-noise amplifier module includes low-noise module A3, inductors L36 and L38, and capacitors C138 and C139.

[0095] The low-noise module A3 uses a navigation low-noise amplifier module developed by the Beijing Telemetry Technology Research Institute. The input pin of the low-noise module A3 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L36 and inductor L38. The other end of inductor L36 and inductor L38 is connected to one end of capacitor C138 and capacitor C139 and +5V. The other end of capacitor C138 and capacitor C139 is grounded.

[0096] The third surface acoustic wave filter includes surface acoustic wave filter Z4, capacitor C323, and inductor L37;

[0097] The surface acoustic wave (SAW) filter Z4 uses the TA0582A manufactured by Jiashuo Company. Pin 2 IN of the SAW filter Z4 is connected to the B2b frequency radio frequency signal, and pin 5 OUT of the SAW filter Z4 is connected to one end of capacitor C23. The other end of capacitor C23 is connected to inductor L37, and the other end of inductor L37 outputs the radio frequency signal.

[0098] The third surface acoustic wave filter includes surface acoustic wave filter Z5, capacitor C309, and inductor L34;

[0099] The surface acoustic wave (SAW) filter Z5 uses the TA0582A manufactured by Jiashuo Company. Pin 2 IN of the SAW filter Z5 is connected to the S-frequency radio frequency signal, and pin 5 OUT of the SAW filter Z5 is connected to one end of capacitor C309. The other end of capacitor C309 is connected to inductor L34, and the other end of inductor L34 outputs the radio frequency signal.

[0100] The first RF transceiver module includes an RF transceiver chip D29, capacitors C325, C326, C333, C290, C295, C297, and resistors R364, R367, R339, R344, R345, and R346.

[0101] The RF transceiver chip D29 uses the XND2233MQQ chip developed by Chongqing Southwest Integrated Circuit Design Co., Ltd. The power supply pins 1, 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 57, 61, and 68 of the RF transceiver chip D29 are connected to +3.3V. The enable pins 3, 10, and 13 of the RF transceiver chip D29 are connected to +3.3V. Pins 4, 5, 8, 25, 29, 48, 49, 50, 55, 59, 60, 62, and 69 of the RF transceiver chip D29 are grounded. Pins 15, 16, 17, 20, 21, 22, 30, 31, 32, 33, and 58 of the navigation RF chip D29 are left unused.

[0102] The D29 RF transceiver chip receives the S-frequency RF signal at pin 6, and the D5 RF transceiver chip receives the B2b RF signal at pin 15. The D29 RF transceiver chip outputs the B2b digital intermediate frequency signal at pins 39, 40, 41, and 42, and the S-frequency digital intermediate frequency signal at pins 30, 31, 32, and 33. The D29 RF transceiver chip's clock input pin 63 connects to the 62MHz clock signal output from the clock module.

[0103] Pin 19 of the RF transceiver chip D29 is connected to one end of capacitor C326 and resistor R364. The other end of capacitor C326 is grounded, and the other end of resistor R364 is grounded through capacitor C325. Pin 56 of the RF transceiver chip D29 is connected to one end of capacitor C295 and resistor R347. The other end of capacitor C295 is grounded, and the other end of resistor R347 is grounded through capacitor C290. Pin 64 of the RF transceiver chip D29 is connected to the external chip select signal through resistor R339. Pin 65 of the RF transceiver chip D29 is connected to the external SPI clock signal through resistor R344. Pin 64 of the RF transceiver chip D29 is connected to the external data signal through resistor R345. Pin 64 of the RF transceiver chip D29 outputs a data signal to the external device through resistor R339.

[0104] The first RF transceiver module includes an RF transceiver chip D30, capacitors C371, C373, C291, C302, C336, resistors R341, R438, R439, R440, R441, R342, R435, inductor L32, and filter Z3.

[0105] The D30 RF transceiver chip uses the XND2233MQQ chip developed by Chongqing Southwest Integrated Circuit Design Co., Ltd. The power supply pins 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 52, 57, 61, and 68 of the D30 RF transceiver chip are connected to +3.3V. The enable pin 4 of the D30 RF transceiver chip is connected to +... With a voltage of 3.3V, pins 1, 3, 5, 10, 13, 16, 55, 62, and 69 of the RF transceiver chip D29 are grounded, while pins 2, 6, 8, 11, 15, 17, 19, 20, 21, 22, 26, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 56, and 58 of the navigation RF chip D29 are left unused.

[0106] The CP-TX pin 50 of the RF transceiver chip D30 is connected to one end of capacitor C373 and resistor R441. The other end of capacitor C373 is grounded, and the other end of resistor R441 is grounded through capacitor C371. The IN-TX pin 54 of the RF transceiver chip D30 is connected to one end of resistor R342. The other end of resistor R342 is connected to the signal IF_RD_OUT and resistor R435. The other end of resistor R435 is grounded. The OUT-TX pin 5 of the RF transceiver chip D30 is connected to one end of capacitor C302. The other end of capacitor C302 is connected to signal capacitor C291 and then to filter Z through inductor L32. Pin 5 of RF transceiver chip 3 is grounded at the other end of capacitor C291. Pin 2 of filter Z2 outputs short message RF signals. Pin 64 of RF transceiver chip D30 is connected to the external input chip select signal through resistor R341. Pin 65 of RF transceiver chip D30 is connected to the external input SPI clock signal through resistor R438. Pin 64 of RF transceiver chip D30 is connected to the external input data signal through resistor R439. Pin 64 of RF transceiver chip D30 outputs data signals to the external system through resistor R440.

[0107] like Figure 9 As shown, the clock module includes crystal oscillator G2, capacitors C277, C278, C280, C281, C282, C275, C276, resistors R333, R335, R330, R336, R337, R133, R334, R434, R144, and inductors L30 and L31.

[0108] Crystal oscillator G2 is a ZD255-1-17N-0211-62M00000 temperature-controlled crystal oscillator from Wuhan Haichuang Company. Pin 1 of crystal oscillator G2 is connected to capacitors C277 and C280 to ground, capacitors C278 and C281 to ground, and one end of inductors L30 and L31. The other end of inductors L30 and L31 is connected to +5V. Pin 4 of crystal oscillator G2 is grounded. The Vc and Vref pins of crystal oscillator G2 are connected through resistor R333. The Vc pin... Connected to ground via resistor R335 and capacitor C282; pin 5 of crystal oscillator G2 is connected to one end of capacitor C275, the other end of capacitor C275 is connected to one end of resistors R330 and R336, the other end of resistor R336 is connected to ground, the other end of resistor R330 is connected to ground via resistor R337 and also connected to one end of capacitor C276, the other end of capacitor C276 is connected to resistor R133 to output the reference clock of the dual-channel navigation module. Connected to R144, it outputs the AD sampling clock of the dual-channel navigation module; connected to R334, it outputs the reference clock of the first RF transceiver module; connected to R434, it outputs the reference clock of the second RF transceiver module.

[0109] The basic idea of ​​this invention is as follows: This invention relates to a channel circuit for a navigation and short message integrated processor, suitable for receiving passive navigation antenna signals and transmitting short message signals. It requires an integrated power supply module, low-noise module, matching network, surface acoustic wave filter, dual-channel navigation module, RF transceiver module, clock module, and other modules onto a single board. This invention achieves the reception and down-conversion of BD2 B1 frequency and GPS L1 dual-frequency satellite signals, as well as the transmission of short message regional and global signals. It integrates an RF filter, low-noise amplifier, dual-channel navigation module, and DC / DC module, achieving an integrated design of all modules within a small size. It solves the RF circuit design problem of a miniaturized integrated processor board that simultaneously receives navigation signals and transmits short message signals. Ultimately, the channel link gain and noise figure achieve ideal results, meeting the miniaturization design requirements of the channel circuit.

[0110] The dual-channel navigation module includes a two-way splitter and two surface acoustic wave filters, enabling the processing of GPS and BDS navigation signals, including 1.5 GHz. The schematic design is attached. Figure 3 As shown, the radio frequency (RF) signal is amplified by the first low-noise amplifier module and then enters the splitter via a DC blocking capacitor. Considering the commonly used frequency points, the number of frequency points, and the board size, the RF input signal is split into two paths after entering the splitter. The first path signal is passed through the first surface acoustic wave (SAW) filter for out-of-band suppression to obtain the suppressed in-band GPS signal. The second path signal is passed through the second SAW filter to obtain the in-band BDS signal.

[0111] The two-way splitter uses the SP-2G1+ chip from MINI Corporation (USA), with a frequency range of 1200MHz~2000MHz and an isolation impedance of 20dB. The first surface acoustic wave (SAW) filter is the SBPF6S3050 manufactured by Beijing Aerospace Microelectronics Technology Co., Ltd., with a center frequency of 1575 MHz and a bandwidth of 8 MHz, capable of covering the L1 frequency point; the second SAW filter is the SBPF6S3016 manufactured by Beijing Aerospace Microelectronics Technology Co., Ltd., with a center frequency of 1561MHz and a bandwidth of 15 MHz, capable of covering the B1 frequency point. The correspondence between the frequency bands of each SAW filter and the navigation signal frequency points is shown in Table 1.

[0112] Table 1. Correspondence between surface acoustic wave filter frequency bands and navigation signal frequency points

[0113]

[0114] The first power supply module supplies power to the clock module, the first low-noise amplifier module, and the dual-channel navigation module. The schematic design of the LT1963AES8 voltage regulators N1, N2, and N3 in the first power supply module is attached. Figure 2a , 2b As shown in Figure 2c, the input terminals Vin and SHDN of the LT1963AES8 chip are connected to a 5V voltage via capacitors, and multiple capacitors are used for filtering to reduce noise interference. The output terminal Vout undergoes the same treatment. The output Vadj of the LT1963AES8 chip is adjusted to 1.21V. By adjusting the resistance between Vout, ADJ, and ground, the required voltage is output. The power module has high output voltage accuracy (1%), low noise, and a maximum load current of 1.5A, optimizing the circuit's noise figure and meeting the requirements of navigation channel circuits.

[0115] The navigation radio frequency chip in the dual-channel navigation module uses the AB3212MFB chip developed by the 704 Institute of the Ninth Academy of Aerospace Science and Technology. The circuit schematic of the chip is shown below. Figure 4 As shown. When the clock module sends a clock signal, the dual-channel navigation module filters, amplifies with controllable gain, and down-converts the suppressed first-band GPS signal and the suppressed first-band Beidou signal. Then, it outputs the first differential intermediate frequency GPS signal and the first differential intermediate frequency Beidou signal, which are sent to the outside as the first output signal of the channel circuit of the navigation and short message integrated processing board. The chip has a wide controllable gain range (the gain controllable range is 45~87dB) and can output intermediate frequency signals with better in-band flatness (in-band ripple is less than 1dB).

[0116] As can be seen from the above embodiments, the dual-channel navigation module of the present invention performs filtering, controllable gain amplification, and down-conversion processing on the suppressed first-band GPS signal and the suppressed first-band Beidou signal, respectively. Channel 1 of the dual-channel navigation module receives the suppressed first-band GPS signal, and channel 2 of the dual-channel navigation module receives the suppressed first-band Beidou signal. It supports simultaneous reception of Beidou and GPS signals, has high reliability and light weight, and is particularly suitable for applications in micro-satellite environments, meeting the technical requirements of high reliability and small size satellite systems.

[0117] The chip block diagram of the navigation RF chip Ab3212MFB is attached. Figure 3 As shown in the attached diagram, the design schematic is as follows. Figure 4 As shown. The REFIN pin of the chip is the clock input reference, provided by the clock module. It requires low phase noise and high stability to ensure the quality of the output signal. The SPI port signals (including LE, DATA, and CLK) of the navigation RF chip Ab3212MFB are connected to the I / O of the baseband chip. The navigation RF chip Ab3212MFB has 56 configuration registers (0-55). Registers 0-19 control channel 1, with registers 11-12 controlling the local oscillator signal of channel 1 in the dual-channel navigation module; registers 20-39 control channel 2 in the dual-channel navigation module, with registers 31-32 controlling the local oscillator signal of channel 2; registers 40-49 control the sampling clock of the dual-channel navigation module; and registers 50-55 control the reference unit module of the navigation RF chip.

[0118] Registers 11-12 control the local oscillator frequency of channel 1 of the dual-channel navigation module through two control words, P1[7:0] and S1[6:0]. In this invention, channel 1 of the dual-channel navigation module receives the L1 (the navigation signal of the GPS L1 signal) frequency. The intermediate frequency output frequency is 3.92MHz, the local oscillator frequency is 1575.42-3.92=1571.5MHz, and the local oscillator signal PLL working frequency is 2*1571.5=3143MHz. Therefore, the frequency division ratio N is 3143. According to the formula, the frequency division ratio N=(p+1)*32-(s+1)-1, where p is the decimal value of P1[7:0] and s is the decimal value of S1[6:0]. We can get p=98 and s=23. Converting them to hexadecimal, P1[7:0] is 0X62 and S1[6:0] is 0X17. In this invention, channel 2 of the dual-channel navigation module receives the B1 (BeiDou II Phase I B1 signal) frequency. Registers 31-32 control the local oscillator frequency of channel 2 of the dual-channel navigation module through two control words, P2[7:0] and S2[6:0]. The intermediate frequency output frequency is 4MHz, the local oscillator frequency is 1561-4=1557MHz, and the local oscillator signal operating frequency is 2*1557=3114MHz. Therefore, the frequency division ratio N is 3114. According to the formula, the frequency division ratio N=(p+1)*32-(s+1)-1, where p is the decimal value of P2[7:0] and s is the decimal value of S2[6:0]. We can get p=97 and s=20. Converting them to hexadecimal, P2[7:0] is 0X61 and S2[6:0] is 0X14. That is: the operating frequency of the local oscillator signal LO1 of channel 1 of the dual-channel navigation module is set to 3143 MHz; the operating frequency of the local oscillator signal LO2 of channel 2 of the dual-channel navigation module is set to 3114 MHz;

[0119] Meanwhile, depending on different system requirements, this invention can be used to set various different output signal frequencies. Registers 7 and 27 control the output intermediate frequency point and bandwidth. Specific parameters are shown in Table 2.

[0120] Table 2 shows the intermediate frequency points and bandwidths of the control outputs of registers 7 and 27.

[0121]

[0122] As can be seen from Table 2, the design method in this invention can be used for different output intermediate frequency points and different bandwidths, thus expanding the application range of miniaturized passive navigation channel circuits.

[0123] The second power supply module supplies power to the clock module, the second low-noise amplifier module, the third low-noise amplifier module, the first RF transceiver module, and the second RF transceiver module. The schematic design of the voltage regulators N4 and N5 in the second power supply module, which use the LT1963AES8, is attached. Figure 5a As shown, the input terminals Vin and SHDN of the LT1963AES8 chip are connected to a 5V voltage via capacitors, and multiple capacitors are used for filtering to reduce noise interference. The output terminal Vout undergoes the same treatment. The output Vadj of the LT1963AES8 chip is adjusted to 1.21V. By adjusting the resistance between Vout, ADJ, and ground, the required voltage is output. The power module has high output voltage accuracy (1%), low noise, and a maximum load current of 1.5A, optimizing the circuit's noise figure and meeting the requirements of navigation channel circuits.

[0124] The internal schematic diagram of the XND2233MQQ RF chip used in the RF transceiver module is shown below. Figure 6 As shown.

[0125] The schematic design of the XND2233MQQ RF chip selected for the first RF transceiver module is as follows: Figure 7 As shown, when the clock module sends a clock signal, the first RF transceiver module amplifies the signal after it has passed through the second and third low-noise amplifier modules. The third and fourth surface acoustic wave filters then filter and amplify the suppressed B2b and S-frequency signals, and down-convert the signal before outputting it to the short message processing module. At the same time, the intermediate frequency output pins of the RF chip XND2233MQQ are multiplexed to enable switching between analog signal and 4-bit digital signal output. The specific register settings are shown in Table 3.

[0126] Table 3 Analog-to-Digital Switching of RF Chip Intermediate Frequency Output Pins

[0127]

[0128] The schematic design of the XND2233MQQ RF chip selected for the second RF transceiver module is as follows: Figure 8 The second RF transceiver module mainly uses the chip's transmit channel, which inputs LVTTL or CMOS level BPSK signals through pin 54 INTX. The transmit channel integrates a low-pass filter, BPSK modulator, variable gain amplifier, and RF amplifier, realizing the function of converting baseband signals to RF signals. It can be used to transmit RDSS and global short message L-band incoming signals.

[0129] The clock module uses the ZD255-1-17N-0211-62M00000 temperature-controlled crystal oscillator manufactured by Wuhan Haichuang Company. The ZD255-1-17N-0211-62M00000 has a steady-state power consumption of ≤1.2W (@25℃) and an initial accuracy of ≤ [missing value] at the reference temperature. Allen's variance ≤ Output power ≥ 9dBm. The clock signal requirements of the RF chip are comprehensively considered.

[0130] Based on the above considerations, such as Figure 1 As shown, the present invention provides a channel circuit for a navigation and short message integrated processing board, comprising: a first power supply module, a second power supply module, a first low-noise amplifier module, a second low-noise amplifier module, a third low-noise amplifier module, a first surface acoustic wave filter, a second surface acoustic wave filter, a third surface acoustic wave filter, a fourth surface acoustic wave filter, a dual-channel navigation module, a first radio frequency transceiver integrated module, a second radio frequency transceiver integrated module, and a clock module.

[0131] This invention achieves a surface acoustic wave (SAW) filter design with low insertion loss and wide passband performance. The selected SAW filter features low in-band insertion loss, wide passband, and high out-of-band rejection, ensuring signal quality while receiving multiple frequency points. Through the integrated design of multiple modules, including a power supply module and a clock module, along with reasonable inter-module connections, optimized circuit design, and PCB layout, the board achieves independent processing of navigation signal quantity and short message signal transmission within a small size. This significantly reduces costs while maintaining performance, resulting in a low-cost, small-size, and high-signal-quality board suitable for microsatellite applications.

[0132] This invention achieves a radio frequency circuit design with low insertion loss and wide passband performance. In this design, the splitter uses the SP-2G1+ chip from MINI Corporation, with a frequency range of 1.2GHz to 2GHz and an isolation impedance of 20dB. The surface acoustic wave (SAW) filters use the TA series filters from Jiashuo and the SBPF series filters from Beijing Aerospace Microelectronics Technology Co., Ltd., which have low in-band insertion loss, wide passband, and high out-of-band rejection capability, ensuring signal quality while receiving multiple frequency points.

[0133] This invention realizes the design of a dual-channel navigation module with a large range and small step size variable gain control. It adopts a low-noise amplifier of 40dB and the controllable gain range of the dual-channel navigation module is 45~87dB, and the link gain can be adjusted according to the requirements.

[0134] This invention realizes the design of an integrated radio frequency transceiver module circuit, using the XND2233 integrated radio frequency transceiver chip. This chip integrates a low-noise amplifier, mixer, filter, variable gain amplifier, analog-to-digital converter, automatic gain control circuit, BPSK modulator, radio frequency amplifier, frequency synthesizer, clock sampling circuit, low-voltage linear power supply and three-bus control circuit, which can simultaneously complete the functional requirements of navigation signal reception and short message transmission.

[0135] This invention achieves a channel circuit with good system noise figure (circuit noise figure less than 3) and in-band flatness (in-band ripple of output signal less than 1dB), mainly by adopting the following measures:

[0136] (1) Control the impedance of the high-frequency radio frequency signal traces on the printed circuit board to 50Ω;

[0137] (2) The clock module traces are located on a separate intermediate signal layer of the printed circuit board, free from interference from other signals;

[0138] (3) Use a metal shield to fully isolate the radio frequency part from the digital circuit.

[0139] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A channel circuit for a navigation and short message integrated processing board, characterized in that: The system includes a first low-noise amplifier module and a dual-channel navigation module connected together; a second low-noise amplifier module and a third surface acoustic wave filter connected together; a third low-noise amplifier module and a fourth surface acoustic wave filter connected together; a first radio frequency transceiver module connected to the output terminals of both the third and fourth surface acoustic wave filters; a second radio frequency transceiver module that converts baseband signals to radio frequency signals and transmits them; a clock module connected to the dual-channel navigation module, the first radio frequency transceiver module, and the second radio frequency transceiver module and providing clock signals; a first power supply module that supplies power to the first low-noise amplifier module, the dual-channel navigation module, and the clock module; and a second power supply module that supplies power to the second low-noise amplifier module, the third low-noise amplifier module, the first radio frequency transceiver module, and the second radio frequency transceiver module. The dual-channel navigation module includes a splitter connected to the output of the first low-noise amplifier module, a first surface acoustic wave filter and a second surface acoustic wave filter connected to the two outputs of the splitter respectively, and a dual-channel navigation radio frequency chip connected to the outputs of both the first and second surface acoustic wave filters. After being amplified by the first low-noise amplifier module, the radio frequency signal enters the splitter through the DC blocking capacitor. The splitter divides the radio frequency input signal into two paths. The first path signal is suppressed by the first surface acoustic wave filter to obtain the suppressed first in-band GPS signal. The second path signal is filtered by the second surface acoustic wave filter to obtain the first in-band BDS signal. When the clock module sends a clock signal, the dual-channel navigation radio frequency chip filters, amplifies with controllable gain, and down-converts the first in-band GPS signal and the first in-band BDS signal, and outputs the first differential intermediate frequency GPS signal and the first differential intermediate frequency Beidou signal to the outside as the first output signal of the channel circuit of the navigation and short message integrated processing board. When the clock module sends a clock signal, the first radio frequency transceiver module filters, controls the gain amplification, and down-converts the GPS signal and Beidou signal, which have been amplified by the second low-noise amplifier module and the third low-noise amplifier module and filtered by the third surface acoustic wave filter and the fourth surface acoustic wave filter, respectively, and outputs them to the short message information processing module.

2. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The two-way splitter operates in a frequency range of 1200MHz to 2000MHz and has an isolation impedance of 20dB; the center frequency of the first surface acoustic wave filter is 1575 MHz and the bandwidth is 8 MHz, with the frequency of the first in-band GPS signal being L1; the center frequency of the second surface acoustic wave filter is 1561MHz and the bandwidth is 15 MHz, with the frequency of the first in-band BDS signal being B1. The first low-noise amplifier module, the dual-channel navigation module, the second low-noise amplifier module, the third surface acoustic wave filter, the third low-noise amplifier module, the fourth surface acoustic wave filter, the first RF transceiver module, the second RF transceiver module, the clock module, the first power supply module, and the second power supply module are all connected to a single printed circuit board.

3. The channel circuit of the navigation and short message integrated processing board according to claim 2, characterized in that: By controlling the 50Ω impedance of the high-frequency radio frequency signal traces on the printed circuit board, the clock module traces are located on a separate intermediate signal layer of the printed circuit board, and a metal shield is used to isolate the radio frequency part from the digital circuit, so that the circuit noise figure of the navigation and short message integrated processing board is less than 3 and the in-band fluctuation of the output signal is less than 1dB. The third and fourth surface acoustic filters filter the suppressed B2b and S frequency signals, amplify them with controllable gain and down-convert them, and then output them to the short message information processing module. In the first RF transceiver module, the intermediate frequency output pins of the RF chip are multiplexed, allowing for switching between analog signals and 4-bit digital signals. The second RF transceiver module inputs an LVTTL or CMOS level BPSK signal through the INTX pin 54. The transmit channel integrates a low-pass filter, a BPSK modulator, a variable gain amplifier, and an RF amplifier to transmit RDSS and global short message L-band inbound signals. The clock module includes a temperature-controlled crystal oscillator with an initial accuracy of ≤ at the reference temperature. Allen's variance ≤ Output power ≥9dBm.

4. The channel circuit of the navigation and short message integrated processing board according to claim 2, characterized in that: The SPI port signal of the dual-channel navigation RF chip is connected to the I / O of the baseband chip. The SPI port signal includes the LE signal, the DATA signal, and the CLK signal. The dual-channel navigation RF chip has 56 configuration registers. Registers 0-19 control channel 1, with registers 11-12 controlling the local oscillator signal of channel 1 of the dual-channel navigation module; registers 20-39 control channel 2 of the dual-channel navigation module, with registers 31-32 controlling the local oscillator signal of channel 2 of the dual-channel navigation module; registers 40-49 control the sampling clock of the dual-channel navigation RF chip; and registers 50-55 control the reference unit module of the dual-channel navigation RF chip. Registers 11~12 control the local oscillator frequency of channel 1 of the dual-channel navigation module through two control words, P1[7:0] and S1[6:0]. The intermediate frequency output frequency is 3.92MHz, the local oscillator frequency of channel 1 of the dual-channel navigation module is 1571.5MHz, the local oscillator signal PLL operating frequency is 3143MHz, the frequency division ratio is 3143, P1[7:0] is 0X62, and S1[6:0] is 0X17. Registers 31~32 control the local oscillator frequency of channel 2 of the dual-channel navigation module through two control words, P2[7:0] and S2[6:0]. The intermediate frequency output frequency is 4MHz, the local oscillator frequency is 1557MHz, the local oscillator signal operating frequency is 3114MHz, the frequency division ratio is 3114, P2[7:0] is 0X61, and S2[6:0] is 0X14. Registers 7 and 27 control the output intermediate frequency (IF) point and bandwidth of the dual-channel navigation module. By setting various IF filter operating mode control words, the dual-channel navigation module can achieve different IF frequency ranges. When the IF filter operating mode control word is 11, the output IF frequency range is 16MHz IF and 20MHz bandwidth. When the IF filter operating mode control word is 10, the output IF frequency range is 16MHz IF and 10MHz bandwidth. When the IF filter operating mode control word is 01, the output IF frequency range is 4MHz IF and 4MHz bandwidth.

5. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The dual-channel navigation RF chip has pins 1, 2, 3, 4, 8, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 47, 48, 49, 50, 63, and 64 grounded; power supply pins 5, 7, 9, 10, 12, 30, 39, and 51 connected to +3.3V; and power supply pins 20, 22, 23, 24, 25, 37, 38, 46, 56, 57, 58, 59, and 61 connected to +1V. 0.8V voltage, pins 19, 28, 29, 35, 44, 52, 53, and 62 are unused; pin 6 inputs BeiDou RF signal, pin 11 inputs GPS RF signal, output pins 26, 27, 54, and 55 output the first differential intermediate frequency GPS signal, and output pins 52, 53, 54, and 55 output the first differential intermediate frequency BeiDou signal; loop filter pin 21 connects one end of capacitor C155 and one end of capacitor C156, and capacitor C156... The other end is connected to ground via resistor R162, and the other end of capacitor C155 is grounded; loop filter pin 60 is connected to one end of capacitor C82 and one end of capacitor C83, the other end of capacitor C82 is grounded via resistor R147, and the other end of capacitor C83 is grounded; configuration pin 40 is connected to the external input chip select signal RF1_CS via resistor R158, configuration pin 41 is connected to the external input data signal RF1_MOSI via resistor R157, configuration pin 42 is connected to the external input clock signals RF1, SPI, and CLK via resistor R155, and configuration pin 43 outputs the data signal RF1_MISO via resistor R156; clock input pin 45 is connected to one end of capacitor C107, the other end of capacitor C107 is connected to one end of resistors R153 and R154, the other end of resistor R153 is grounded, and the other end of resistor R154 is connected to the input 62MHz clock signal; The AD sampling clock input pin 35 is connected to one end of capacitor C131. The other end of capacitor C131 is connected to resistors R159 and R160. The other end of resistor R160 is grounded, and the other end of resistor R159 is connected to the input 62MHz clock signal.

6. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The first power supply module includes voltage regulator N1, voltage regulator N2 and voltage regulator N3; The IN and SHDN pins of voltage regulator N1 are connected to one end of capacitor C157 and the +5.4V input voltage, with the other end of capacitor C157 connected to ground; the OUT and ADJ pins of voltage regulator N1 are connected to resistors R170 and R177; the ADJ pin of voltage regulator N1 is connected to resistor R181, with one end of resistor R181 connected to resistor R177 and the other end grounded; the OUT pin of voltage regulator N1 is connected to capacitors C162 and C163 in parallel and the +5V output voltage, with the other ends of capacitors C162 and C163 connected to ground. The IN and SHDN pins of voltage regulator N2 are connected to one end of capacitor C159 and the +5.4V input voltage, while the other end of capacitor C159 is grounded. The OUT and ADJ pins of voltage regulator N2 are connected to resistor R174. The ADJ pin of voltage regulator N2 is connected to resistors R178 and R182, with one end of resistor R182 connected to resistor R178 and the other end grounded. The OUT pin of voltage regulator N2 is connected to capacitors C158 and C164 in parallel and the +3.3V output voltage, with the other ends of capacitors C158 and C164 connected to ground. The IN and SHDN pins of voltage regulator N3 are connected to one end of capacitor C161 and the +5.4V voltage, while the other end of capacitor C161 is grounded. The OUT and ADJ pins of voltage regulator N3 are connected to resistor R175. The ADJ pin of voltage regulator N3 is connected to resistors R179 and R183, with R179 and R175 connected in series, and the other end of resistor R183 is grounded. The OUT pin of voltage regulator N3 is connected to capacitors C160 and C165 in parallel and the +1.8V output voltage, with the other ends of capacitors C160 and C165 connected to ground.

7. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The second power supply module includes voltage regulator N4 and voltage regulator N5; The IN and SHDN pins of voltage regulator N4 are connected to one end of capacitor C345 and the +5.4V voltage, and the other end of capacitor C345 is connected to ground; the OUT and ADJ pins of voltage regulator N4 are connected to resistors R370 and R371; the ADJ pin of voltage regulator N4 is connected to resistor R372, with one end of resistor R372 connected to resistor R371 and the other end grounded; the OUT pin of voltage regulator N4 is connected to capacitors C341 and C346 in parallel and the +5V output voltage, with the other ends of capacitors C341 and C346 connected to ground. The IN and SHDN pins of voltage regulator N5 are connected to one end of capacitor C359 and the +5.4V voltage, while the other end of capacitor C359 is grounded. The OUT and ADJ pins of voltage regulator N5 are connected to resistor R391. The ADJ pin of voltage regulator N5 is connected to resistors R392 and R393 in series. Resistor R392 is connected in series with resistor R391, and the other end of resistor R393 is grounded. The OUT pin of voltage regulator N5 is connected to capacitors C358 and C360 in parallel and the +3.3V output voltage. The other ends of capacitors C358 and C360 are connected together and then grounded.

8. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The first low-noise amplifier module includes a low-noise module A1, inductor L35, inductor L39, capacitor C310, and capacitor C311; The input pin of the low-noise module A1 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L35 and inductor L39. The other end of inductor L35 and inductor L39 is connected to one end of capacitor C310 and capacitor C311 and +5V. The other end of capacitor C310 and capacitor C311 is grounded. The first surface acoustic wave filter includes a surface acoustic wave filter Z1, a capacitor C134, a capacitor C135, and an inductor L12; Pin 5 IN of the surface acoustic wave (SAW) filter Z1 is connected to the GPS radio frequency signal. Pin 2 OUT of the SAW filter Z1 is connected to one end of capacitor C134. The other end of capacitor C134 is connected to one end of inductor L12 and capacitor C135. The other ends of inductor L12 and capacitor C135 are grounded. The second surface acoustic wave filter includes a surface acoustic wave filter Z2, a capacitor C99, a capacitor C100, and an inductor L10; Pin 5 (IN) of the surface acoustic wave (SAW) filter Z2 is connected to the BeiDou radio frequency signal. Pin 2 (OUT) of the SAW filter Z2 is connected to one end of capacitor C99. The other end of capacitor C99 is connected to one end of inductor L10 and capacitor C100. The other ends of inductor L10 and capacitor C100 are grounded.

9. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The second low-noise amplifier module includes a low-noise module A2, an inductor L11, an inductor L13, a capacitor C136, and a capacitor C137; The input pin of the low-noise module A2 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L11 and inductor L13. The other end of inductor L11 and inductor L13 is connected to one end of capacitor C136 and capacitor C137 and +5V. The other end of capacitor C136 and capacitor C137 is grounded. The third low-noise amplifier module includes a low-noise module A3, inductor L36, inductor L38, capacitor C138, and capacitor C139. The input pin of the low-noise module A3 is connected to an external radio frequency signal, and the output pin is connected to one end of inductor L36 and inductor L38. The other end of inductor L36 and inductor L38 is connected to one end of capacitor C138 and capacitor C139 and +5V. The other end of capacitor C138 and capacitor C139 is grounded. The third surface acoustic wave filter includes a surface acoustic wave filter Z4, a capacitor C323 and an inductor L37; Pin 2 (IN) of the surface acoustic wave (SAW) filter Z4 is connected to the B2b frequency radio frequency signal, and pin 5 (OUT) of the SAW filter Z4 is connected to one end of capacitor C23. The other end of capacitor C23 is connected to inductor L37, and the other end of inductor L37 outputs the radio frequency signal. The third surface acoustic wave filter includes a surface acoustic wave filter Z5, a capacitor C309, and an inductor L34; Pin 2 (IN) of the surface acoustic wave (SAW) filter Z5 is connected to the S-frequency radio frequency (RF) signal. Pin 5 (OUT) of the SAW filter Z5 is connected to one end of capacitor C309. The other end of capacitor C309 is connected to inductor L34, and the other end of inductor L34 outputs the RF signal.

10. The channel circuit of the navigation and short message integrated processing board according to claim 1, characterized in that: The first radio frequency transceiver module includes a radio frequency transceiver chip D29, capacitors C325, C326, C333, C290, C295, C297, resistors R364, R367, R339, R344, R345, and R346. The power supply pins 1, 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 57, 61, and 68 of the RF transceiver chip D29 are connected to +3.3V. The enable pins 3, 10, and 13 are also connected to +3.3V. Pins 4, 5, 8, 25, 29, 48, 49, 50, 55, 59, 60, 62, and 69 are grounded. Pins 15, 16, 17, 20, 21, 22, 30, 31, 32, 33, and 58 are left unused. The D29 RF transceiver chip has pin 6 for inputting S-frequency RF signals, pin 15 for inputting B2b RF signals, pins 39, 40, 41, and 42 for outputting B2b digital intermediate frequency signals, and pins 30, 31, 32, and 33 for outputting S-frequency digital intermediate frequency signals. The clock input pin 63 is connected to the 62MHz clock signal output by the clock module. The CP-RX1 pin 19 of the D29 RF transceiver chip is connected to one end of capacitor C326 and resistor R364. The other end of capacitor C326 is grounded, and the other end of resistor R364 is grounded through capacitor C325. The CP-RX3 pin 56 is connected to one end of capacitor C295 and resistor R347. The other end of capacitor C295 is grounded, and the other end of resistor R347 is grounded through capacitor C290. The SPI_CS_N pin 64 is connected to the external input chip select signal through resistor R339. The SPI_CLK pin 65 is connected to the external input SPI clock signal through resistor R344. The SPI_MOSI pin 64 is connected to the external input data signal through resistor R345. The SPI_MISO pin 64 outputs a data signal to the external device through resistor R339. The second RF transceiver module includes an RF transceiver chip D30, capacitors C371, C373, C291, C302, and C336, resistors R341, R438, R439, R440, R441, R342, and R435, an inductor L32, and a filter Z3. The power supply pins 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 52, 57, 61, and 68 of the RF transceiver chip D30 are connected to +3.3V, the enable pin 4 is connected to +3.3V, pins 1, 3, 5, 10, 13, 16, 55, 62, and 69 are grounded, and pins 2, 6, 8, 11, 15, 17, 19, 20, 21, 22, 26, 30, 31, 32, 33, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 56, and 58 are left unused. The CP-TX pin 50 of the D30 RF transceiver chip is connected to one end of capacitor C373 and resistor R441. The other end of capacitor C373 is grounded, and the other end of resistor R441 is grounded through capacitor C371. The IN-TX pin 54 is connected to one end of resistor R342. The other end of resistor R342 is connected to the signal IF_RD_OUT and resistor R435. The other end of resistor R435 is grounded. The OUT-TX pin 5 is connected to one end of capacitor C302. The other end of capacitor C302 is connected to signal capacitor C291 and... The filter Z2 is connected to pin 5 of the filter Z3 via inductor L32, and the other end of capacitor C291 is grounded. Pin 2 of the filter Z2 outputs a short message to transmit an RF signal. Pin 64 of SPI_CS_N is connected to the external input chip select signal via resistor R341, pin 65 of SPI_CLK is connected to the external input SPI clock signal via resistor R438, pin 64 of SPI_MOSI is connected to the external input data signal via resistor R439, and pin 64 of SPI_MISO outputs a data signal to the external device via resistor R440. Both the D29 and D30 RF transceiver chips integrate a low-noise amplifier, mixer, filter, variable gain amplifier, analog-to-digital converter, automatic gain control circuit, BPSK modulator, RF amplifier, frequency synthesizer, clock sampling circuit, low-voltage linear power supply and three-bus control circuit, and can simultaneously complete navigation signal reception and short message transmission. The clock module includes a crystal oscillator G2, capacitors C277, C278, C280, C281, C282, C275, and C276, resistors R333, R335, R330, R336, R337, R133, R334, R434, and R144, and inductors L30 and L31. The power supply pin 1 of crystal oscillator G2 is connected to one end of parallel capacitors C277 and C280, parallel capacitors C278 and C281, and parallel inductors L30 and L31. The other ends of capacitors C280 and C281 are grounded, and the other ends of inductors L30 and L31 are connected to +5V. Pin 4 of crystal oscillator G2 is grounded. The Vc and Vref pins of crystal oscillator G2 are connected through resistor R333, and the Vc pin is connected to ground through resistor R335 and capacitor C282. The output pin 5 of crystal oscillator G2 is connected to one end of capacitor C275, and the other end of capacitor C275... One end of resistor R330 and one end of resistor R336 are connected to the ground. The other end of resistor R336 is connected to ground through resistor R337 and is also connected to one end of capacitor C276. The other end of capacitor C276 is connected to resistor R133 and outputs the reference clock of the dual-channel navigation module, connected to resistor R144 and outputs the AD sampling clock of the dual-channel navigation module, connected to resistor R334 and outputs the reference clock of the first RF transceiver module, and connected to resistor R434 and outputs the reference clock of the second RF transceiver module.

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