Decision feedback equalizer, method, controller and communication equipment

Abstract

The invention discloses a decision feedback equalizer, a method, a controller and communication equipment, the decision feedback equalizer comprises a summator and the controller, and the summator comprises a plurality of amplification circuits and a plurality of equalization circuits; the front gates of the FD-SOI type first pair of differential MOS transistors included in each amplification circuit are used for receiving a differential input signal of a current bit, and the back gates are used for grounding; the front gates of the second pair of FD-SOI type differential MOS transistors included in each equalization circuit are used for receiving a differential input signal of a current bit, and the back gates of the second pair of FD-SOI type differential MOS transistors included in each equalization circuit are used for receiving a differential feedback signal of a front mark bit; the controller controls the input number of the equalization circuits, controls the magnitude of the equalization current, and controls the input number of the amplification circuits according to the input number of the equalization circuits, so as to obtain the equalized differential output signal of the current bit, thereby improving the input stability of the equalization circuits and the amplification circuits, and avoiding the adjustment of a common mode compensation circuit. Therefore, the stability of the output common-mode voltage can be improved, and the circuit complexity is reduced.

Description

Technical Field

[0001] This application relates to the field of power control technology, specifically to a decision feedback equalizer, method, controller, and communication device. Background Technology

[0002] In the field of communications, signal integrity is a core prerequisite for achieving high-speed and reliable transmission. However, as signal rates increase, channel attenuation grows exponentially, necessitating equalizers for channel compensation. Decision Feedback Equalizers (DFEs) are commonly used for this purpose. A DFE consists of a summer and a decision unit, which work in a closed-loop coordinated manner. The decision unit generates a feedback signal for the preceding bit and feeds it to the summer. Based on this feedback signal, the summer superimposes a signal onto the current bit to cancel out interference and outputs the equalized signal for the current bit.

[0003] Because DFEs require sufficient bandwidth to support full-rate signal transmission and need to ensure signal linearity, they often employ high-bandwidth, high-linearity, but high-power current-mode logic (CML) paired with passive load resistors to improve linearity and bandwidth.

[0004] Taking a 1-tap DFE as an example, the summer in the DFE requires two pairs of CML differential transistors: one pair receives the current bit signal, and the other pair receives the pre-index bit signal. Since the DFE tap current varies with the channel, it causes variations in the summer's output common-mode voltage. An excessively low output common-mode voltage reduces the positive gain and affects the summer's linearity, while an excessively high output common-mode voltage reduces the effective transconductance of the decision circuit. Therefore, a common-mode compensation circuit is needed to replicate the DFE tap current to the summer using a current mirror to improve the stability of the output common-mode voltage.

[0005] However, the common-mode compensation circuit increases circuit complexity and area, and suffers from problems such as large current replication error; transistor operating region offset, resulting in reduced current mirror accuracy and affecting the stability of output common-mode voltage; insufficient dynamic response of the current mirror, which can easily cause timing errors and affect the sampling accuracy of the decision circuit.

[0006] Similarly, the decision unit in the DFE also requires two pairs of differential transistors: one pair to receive the equalized current bit signal and the other pair to receive the reference voltage, which increases the circuit complexity. Summary of the Invention

[0007] In view of this, this application provides a decision feedback equalizer, method, controller, and communication device, which improves the stability of the output common-mode voltage while reducing circuit complexity and circuit area.

[0008] To solve the above problems, the technical solution provided in this application is as follows:

[0009] This application provides a decision feedback equalizer, comprising: a summer and a controller; the summer includes a first resistor, a second resistor, multiple amplifier circuits, and multiple equalization circuits; the multiple amplifier circuits are connected in parallel; the multiple equalization circuits are connected in parallel; a first terminal of the first resistor is connected to a negative differential output ON node, and a first terminal of the second resistor is connected to a positive differential output OP node; the second terminals of both the first and second resistors are connected to a power supply; each amplifier circuit includes a first pair of differential MOSFETs of type fully depleted silicon-on-insulator (FD-SOI); the front gate of the first pair of differential MOSFETs is used to receive the differential input signal of the current bit; the back gate of the first pair of differential MOSFETs is used to ground; each The first terminal of each amplifier circuit is connected to the ON node and the OP node through the first terminal of the first pair of differential MOSFETs; each equalization circuit includes a second pair of FD-SOI type differential MOSFETs; the front gate of the second pair of differential MOSFETs is used to receive the differential input signal of the current bit; the back gate of the second pair of differential MOSFETs is used to receive the differential feedback signal of the previous bit; the first terminal of each equalization circuit is connected to the ON node and the OP node through the first terminal of the second pair of differential MOSFETs; the controller controls the magnitude of the equalization current by controlling the number of equalization circuits in operation, and controls the number of amplifier circuits in operation according to the number of equalization circuits in operation.

[0010] In one possible implementation, each of the amplifier circuits further includes: a first pair of differential tail current transistors and a first switch; the second terminal of the first pair of differential MOS transistors is grounded through the first pair of differential tail current transistors, and the gate of the first pair of differential tail current transistors is connected to a bias current source through the first switch; the controller controls the activation of each of the amplifier circuits by controlling the closing of the first switch.

[0011] In one possible implementation, each of the amplifier circuits further includes: a first adjustable resistor; the first adjustable resistor is connected in parallel between the second terminals of the first pair of differential MOS transistors.

[0012] In one possible implementation, each of the equalization circuits further includes: a second pair of differential tail current transistors and a second switch; the second terminal of the second pair of differential MOS transistors is grounded through the second pair of differential tail current transistors, and the gate of the second pair of differential tail current transistors is connected to a bias current source through the second switch; the controller controls the activation of each of the equalization circuits by controlling the closing of the second switch.

[0013] One possible implementation is that each of the equalization circuits further includes: a second adjustable resistor; the second adjustable resistor is connected in parallel between the second terminals of the second pair of differential MOSFETs.

[0014] In one possible implementation, the sum of the number of inputs to the equalization circuit and the number of inputs to the amplification circuit remains constant, and the total current input to the first resistor and the second resistor remains constant.

[0015] In one possible implementation, the equalizer further includes: a decision unit; the decision unit includes a first-stage circuit and a second-stage circuit, the first-stage circuit including at least a third pair of FD-SOI type differential MOSFETs; the second-stage circuit is used to isolate the first-stage circuit and the load capacitor; the front gate of the third pair of differential MOSFETs is used to receive the equalized differential signal; the back gate of the third pair of differential MOSFETs is used to receive a reference voltage; the first-stage circuit is used to output the differential feedback signal with the front bit to the back gate of the second pair of differential MOSFETs via the second-stage circuit, based on the comparison result between the reference voltage and the equalized differential signal.

[0016] This application also provides a communication device including any of the decision feedback equalizers described above.

[0017] This application also provides a method for a decision feedback equalizer, comprising: receiving the differential input signal of the current bit using the front gate of a first pair of FD-SOI type differential MOS transistors in an amplifier circuit; receiving the differential input signal of the current bit using the front gate of a second pair of FD-SOI type differential MOS transistors in an equalization circuit; receiving the differential feedback signal of the previous bit output by a decision unit using the back gate of the second pair of differential MOS transistors; a summer including the amplifier circuit and the equalization circuit; controlling the magnitude of the equalization current by controlling the number of equalization circuits in operation, and controlling the number of amplifier circuits in operation according to the number of equalization circuits in operation; the output signals of the first pair of differential MOS transistors and the output signal of the equalization circuit are superimposed, and then converted by a first resistor and a second resistor to obtain the equalized differential signal of the current bit.

[0018] This application also provides a controller for the decision feedback equalizer method described above.

[0019] The decision feedback equalizer provided in this application includes a summer and a controller. The summer includes a first resistor, a second resistor, multiple amplifier circuits, and multiple equalization circuits. Each amplifier circuit includes an FD-SOI type first pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current position, and whose back gate is used to ground. Each equalization circuit includes an FD-SOI type second pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current position, and whose back gate is used to receive the differential feedback signal of the previous position. The controller controls the number of equalization circuits in operation and the magnitude of the equalization current. Based on the number of equalization circuits in operation, the controller controls the number of amplifier circuits in operation. The output signals of the first pair of differential MOSFETs in the operating amplifier circuit and the output signals of the operating equalization circuit are superimposed at the ON and OP nodes, and then converted by the first and second resistors to obtain the equalized differential signal of the current position. This improves the stability of the operation of the equalization circuit and the amplifier circuit, thereby improving the stability of the output common-mode voltage without the need for common-mode compensation circuit adjustment, solving the problems caused by the common-mode compensation circuit, and reducing the circuit complexity. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a summer for an existing DFE (Digital Equivalent Function).

[0021] Figure 2 This is a schematic diagram of a conventional DFE decision mechanism;

[0022] Figure 3 A schematic diagram of a decision feedback equalizer provided in an embodiment of this application;

[0023] Figure 4 A schematic diagram of yet another decision feedback equalizer provided in the embodiments of this application;

[0024] Figure 5 A schematic diagram of another decision feedback equalizer provided in the embodiments of this application;

[0025] Figure 6 A schematic diagram of another decision feedback equalizer provided in the embodiments of this application;

[0026] Figure 7 A flowchart illustrating a decision feedback equalizer method provided in an embodiment of this application. Detailed Implementation

[0027] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] In the field of communications, during signal transmission, channel attenuation increases exponentially with the increase of signal rate. To improve signal integrity, decision feedback equalizers (DFEs) are often used for channel compensation. The following section, with accompanying figures, provides a detailed introduction to existing DFEs.

[0029] The transistors in the summer and decision circuit of existing DFEs are all bulk silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). Bulk silicon MOSFETs have a small voltage variation range at the substrate and low threshold voltage control gain. Therefore, the summer in existing DFEs requires two pairs of differential transistors: one pair to receive the current bit signal and the other pair to receive the preceding bit signal. The decision circuit in existing DFEs also requires two pairs of differential transistors: one pair to receive the equalized current bit signal and the other pair to receive the reference voltage.

[0030] See Figure 1 The figure shows a schematic diagram of a conventional DFE summer.

[0031] The existing DFE summer, including amplifier circuit A1, common-mode compensation circuit A2, tap circuit A3 and bias current source Ibias, can superimpose the differential input signal of the current bit and the differential feedback signal of the previous bit to cancel inter-symbol interference.

[0032] Amplifier circuit A1 includes a first load resistor RL1, a second load resistor RL2, and a tail current source I. D And the first pair of differential transistors M1 and M2. The first terminal of the first load resistor RL1 is connected to the negative differential output ON node, and the first terminal of the second load resistor RL2 is connected to the positive differential output OP node; the second terminals of the first load resistor RL1 and the second terminal of the second load resistor RL2 are both connected to the power supply VDD; the gates of the first pair of differential transistors M1 and M2 receive the differential input signals Ip and In of the current bit, respectively; the first terminals of the first pair of differential transistors M1 and M2 are connected to the ON node and the OP node, respectively; the second terminals of the first pair of differential transistors M1 and M2 are connected to the tail current source I. D .

[0033] Tap circuit A3 includes a second pair of differential transistors M3 and M4, and a tail current array. The gates of the second pair of differential transistors M3 and M4 respectively receive the differential feedback signal D of the pre-index bit output by the decision circuit. n and D p The differential feedback signal D of the pre-index bit n and D pIt is a rail-to-rail digital signal; the first terminals of the second pair of differential transistors M3 and M4 are connected to the ON node and the OP node respectively, and the second terminals of the second pair of differential transistors M3 and M4 are connected to the first terminal of the tail current array, and the second terminal of the tail current array is connected to the bias current source Ibias. The tail current array consists of n tail current units T, and the tap current is adjusted by controlling the conduction and cutoff of each tail current unit T.

[0034] The output signals of the first pair of differential transistors M1 and M2 are superimposed on the ON and OP nodes along with the output signal of the tap circuit A3 to cancel inter-symbol interference. However, the tap current of the DFE varies with the channel, and the output common-mode voltage of the ON and OP nodes also varies with the tap current, leading to variations in the output common-mode voltage. An excessively low output common-mode voltage reduces the positive gain and affects the linearity of the summer, while an excessively high output common-mode voltage reduces the effective transconductance of the decision circuit. Therefore, the prior art employs a common-mode compensation circuit A2 to improve the stability of the summer's output common-mode voltage.

[0035] The common-mode compensation circuit A2 includes transistors M5 through M12, which together form a common-source, common-gate current mirror. The common-mode compensation circuit A2 replicates half of the tap current through the current mirror and injects it into the ON and OP nodes, ensuring that the output common-mode voltage remains constant regardless of the tap current magnitude.

[0036] However, the common-mode compensation circuit A2 increases circuit complexity and area, and has problems such as large current replication error; transistor operating region offset, resulting in reduced current mirror image accuracy and affecting the stability of output common-mode voltage; insufficient dynamic response of current mirror, which can easily cause timing errors and affect the sampling accuracy of decision unit.

[0037] See Figure 2 The figure shows a schematic diagram of a conventional DFE decision mechanism.

[0038] The existing DFE decision unit includes two pairs of differential transistors, one pair of which is used to receive the equalized differential signal V from the summer output. n and V p Another pair is used to receive reference voltages Vrefp and Vrefn, and to make a decision on the equalized differential signal based on the reference voltages Vrefp and Vrefn. However, this decision-maker requires two pairs of differential transistors, which increases the circuit complexity.

[0039] Therefore, embodiments of this application provide a decision feedback equalizer that can improve the stability of the output common-mode voltage and reduce circuit complexity. The decision feedback equalizer provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0040] The embodiments of this application do not specifically limit the application scenarios of the decision feedback equalizer. The decision feedback equalizer can be applied in any communication or data transmission scenario that requires channel compensation, such as optical communication scenarios.

[0041] See Figure 3 The figure is a schematic diagram of a decision feedback equalizer provided in an embodiment of this application.

[0042] The decision feedback equalizer provided in this application includes a summer 10 and a controller 20.

[0043] The summer 10 includes a first resistor R1, a second resistor R2, multiple amplifier circuits 100, and multiple equalizer circuits 200. The multiple amplifier circuits 100 are connected in parallel, and the multiple equalizer circuits 200 are connected in parallel. The first terminal of the first resistor R1 is connected to the negative differential output ON node, and the first terminal of the second resistor R2 is connected to the positive differential output OP node. The second terminals of both the first resistor R1 and the second terminal of the second resistor R2 are connected to the power supply.

[0044] The decision feedback equalizer provided in this application uses a fully depleted silicon-on-insulator (FD-SOI) type MOSFET. The FD-SOI type MOSFET has dual control terminals, a front gate and a back gate, supports back gate regulation capability, and has high threshold voltage regulation gain.

[0045] Each amplifier circuit 100 includes a first pair of FD-SOI type differential MOSFETs FM1; the front gate of the first pair of differential MOSFETs FM1 is used to receive the differential input signals Ip and In of the current bit; the back gate of the first pair of differential MOSFETs FM1 is used to ground VSS; the first terminal of each amplifier circuit 100 is connected to the ON node and the OP node through the first terminal of the first pair of differential MOSFETs FM1.

[0046] Each equalization circuit 200 includes a second pair of FD-SOI type differential MOSFETs FM2; the front gate of the second pair of differential MOSFETs FM2 is used to receive the differential input signals Ip and In of the current bit; the back gate of the second pair of differential MOSFETs FM2 is used to receive the differential feedback signal D of the previous bit. n and D p The first terminal of each equalization circuit 200 is connected to the ON node and the OP node through the first terminal of the second pair of differential MOSFETs FM2.

[0047] The controller 20 controls the number of equalization circuits 200 in operation, thereby controlling the magnitude of the equalization current. Based on the number of equalization circuits 200 in operation, the controller controls the number of amplifier circuits 100 in operation. This causes the output signals of the first pair of differential MOSFETs FM1 in the amplifier circuit 100 and the output signals of the equalization circuits 200 in operation to converge at the ON and OP nodes, and then undergo current-to-voltage signal conversion via the first resistor R1 and the second resistor R2 to obtain the equalized differential signal for the current position. Because the number of equalization circuits 200 in operation is correlated with the number of amplifier circuits 100 in operation, the stability of the operation of both equalization circuits 200 and amplifier circuits 100 is improved, thus enhancing the stability of the output common-mode voltage.

[0048] In one possible implementation, the controller 20 can control the number of inputs to the equalization circuit 200 through an adaptive equalization loop based on the Symbol-by-Symbol Least Mean Squares (SS-LMS) algorithm.

[0049] The decision feedback equalizer provided in this application includes a summer and a controller. The summer includes a first resistor, a second resistor, multiple amplifier circuits, and multiple equalization circuits. Each amplifier circuit includes an FD-SOI type first pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current position, and whose back gate is used to ground. Each equalization circuit includes an FD-SOI type second pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current position, and whose back gate is used to receive the differential feedback signal of the previous position. The controller controls the number of equalization circuits in operation and the magnitude of the equalization current. Based on the number of equalization circuits in operation, the controller controls the number of amplifier circuits in operation. The output signals of the first pair of differential MOSFETs in the operating amplifier circuit and the output signals of the operating equalization circuit are superimposed at the ON and OP nodes, and then converted by the first and second resistors to obtain the equalized differential signal of the current position. This improves the stability of the operation of the equalization circuit and the amplifier circuit, thereby improving the stability of the output common-mode voltage without the need for common-mode compensation circuit adjustment, solving the problems caused by the common-mode compensation circuit, and reducing the circuit complexity.

[0050] See also Figure 3 In one possible implementation, in the decision feedback equalizer provided in this application embodiment, the sum of the number of inputs of the equalization circuit 200 and the number of inputs of the amplifier circuit 100 remains unchanged, so that the total current of the input first resistor R1 and the second resistor R2 remains almost unchanged, thereby improving the stability of the output common-mode voltage.

[0051] See also Figure 3One possible implementation is the decision feedback equalizer provided in this application embodiment, where the differential feedback signal D of the pre-index bit... n and D p It can be represented as ,in, For the tap coefficients of equalization circuit 200, It is related to the number of equalization circuits 200 that are put into operation.

[0052] See Figure 4 This figure is a schematic diagram of another decision feedback equalizer provided in the embodiments of this application.

[0053] The decision feedback equalizer provided in this application embodiment further includes a first pair of differential tail current transistors and a first switch S1 in each amplifier circuit 100. The second terminal of the first pair of differential MOSFETs FM1 is grounded through the first pair of differential tail current transistors, and the gate of the first pair of differential tail current transistors is connected to the bias current source Ibias through the first switch S1. The controller 20 controls the activation of each amplifier circuit 100 by controlling the closing of the first switch S1.

[0054] The embodiments of this application do not specifically limit the type of the first pair of differential tail current transistors, and may include, for example, bulk silicon MOS transistors.

[0055] In one possible implementation, each amplifier circuit 100 further includes a first adjustable resistor Rh1, which is connected in parallel between the second terminals of the first pair of differential MOSFETs FM1. The first adjustable resistor Rh1 can be used to adjust the gain of the amplifier circuit 100, improve the linearity of the amplifier circuit 100, and enhance the common-mode interference immunity of the amplifier circuit 100.

[0056] The decision feedback equalizer provided in this application embodiment further includes a second pair of differential tail current transistors and a second switch S2 in each equalization circuit 200. The second terminal of the second pair of differential MOSFETs FM2 is grounded through the second pair of differential tail current transistors, and the gate of the second pair of differential tail current transistors is connected to the bias current source Ibias through the second switch S2. The controller 20 controls the activation of each equalization circuit 200 by controlling the closing of the second switch S2 to adjust the equalization intensity.

[0057] In one possible implementation, each equalization circuit 200 further includes a second adjustable resistor Rh2, which is connected in parallel between the second terminals of the second pair of differential MOSFETs FM2. The second adjustable resistor Rh2 can be used to adjust the gain of the equalization circuit 200, improve the linearity of the equalization circuit 200, and enhance the common-mode interference immunity of the amplifier circuit 100.

[0058] See Figure 5This figure is a schematic diagram of another decision feedback equalizer provided in an embodiment of this application.

[0059] The decision feedback equalizer provided in this application embodiment also includes a decision unit 30.

[0060] The decision unit 30 includes a first-stage circuit 301 and a second-stage circuit 302. The first-stage circuit 301 includes at least a third pair of FD-SOI type differential MOSFETs FM3. The second-stage circuit 302 is used to isolate the first-stage circuit 301 and the load capacitor CL.

[0061] The front gate of the third pair of differential MOSFETs FM3 is used to receive the equalized differential signal V. p and V n The back gate of the third pair of differential MOSFETs FM3 is used to receive the reference voltages Vrefn and Vrefp.

[0062] The first-stage circuit 301 is used to determine the reference voltages Vrefn and Vrefp and the equalized differential signal V. p and V n The comparison result, after passing through the second-stage circuit 302, outputs a differential feedback signal D with the preceding index. n and D p Give the back gate of the second pair of differential MOSFETs FM2 in the summer.

[0063] The total gain of the decision unit 30 is the product of the gain of the first-stage circuit 301 and the gain of the second-stage circuit 302.

[0064] The decision feedback equalizer provided in this application includes a decision unit, which includes a first-stage circuit and a second-stage circuit. The first-stage circuit includes at least a third pair of FD-SOI type differential MOSFETs. The second-stage circuit is used to isolate the first-stage circuit and the load capacitor. The front gate of the third pair of differential MOSFETs is used to receive the equalized differential signal. The back gate of the third pair of differential MOSFETs is used to receive a reference voltage. The first-stage circuit is used to output a differential feedback signal with a front bit to the back gate of the second pair of differential MOSFETs based on the comparison result between the reference voltage and the equalized differential signal, through the second-stage circuit, thereby reducing circuit complexity and circuit area.

[0065] One possible implementation is that, in the decision feedback equalizer provided in this application embodiment, the tap coefficient of the equalization circuit 200... It is also related to the total gain of the decision unit 30, i.e. It is related to the number of inputs to the equalization circuit 200 and the total gain of the decision unit 30.

[0066] See Figure 6 This figure is a schematic diagram of another decision feedback equalizer provided in an embodiment of this application.

[0067] Figure 6 This is one possible implementation of the decision controller 30. The first-stage circuit 301 also includes first-stage silicon MOSFETs D1 to D9, and the second-stage circuit 302 includes tenth-stage silicon MOSFETs D10 to D17 and a tail capacitor CT. The connection relationship of the first-stage silicon MOSFETs D1 to D17 is not described here. The first-stage circuit 301 provides a large-swing input to the second-stage circuit 302. In one possible implementation, the smaller the load on the first-stage circuit 301, the smaller the output delay. The working principle of the decision controller 30 is described below.

[0068] CLK and CLKB are complementary clocks. For example, when CLK is high, CLKB is low, which is used to trigger the tail capacitor CT array reset and decision action of the decision unit 30.

[0069] During the reset phase, when the clock signal is low, the output nodes MN and MP of the first-stage circuit 301, the intermediate nodes N and P of the first-stage circuit 301, and the output node D of the second-stage circuit 302 are all reset. n and D p It is charged to the power supply voltage.

[0070] During the amplification stage, when the rising edge of the clock signal arrives, the equalized differential signal V... p and V n This causes the MN node and the MP node to discharge at different rates. During this stage, D... n Nodes and D p The nodes discharge simultaneously to turn off the sixteenth and seventeenth silicon MOSFETs D16 and D17. When the voltage at node MN is less than or equal to the voltage threshold, the third and thirteenth silicon MOSFETs D3 and D13 turn on, and the first-stage circuit 301 enters the regeneration phase. The second-stage circuit 302 further amplifies the input signal, and the thirteenth silicon MOSFET D13 turns on D... p The node is charged to turn on the sixteenth body silicon MOSFET D16.

[0071] During the regeneration phase, when D p When the node is charged enough to turn on the sixteenth-cell silicon MOSFET D16, the cross-coupled pair of the sixteenth-cell silicon MOSFET D16 and the seventeenth-cell silicon MOSFET D17 begins to operate, and the second-stage circuit 302 enters the regeneration phase. p The node is further charged to the supply voltage, while D n The node is pulled down to ground by the sixteenth silicon MOSFET D16.

[0072] Among them, the differential output swing, i.e., D n Nodes and D pThe voltage difference between nodes is determined by the charge redistribution between the load capacitor CL and the tail capacitor CT. The larger the capacitance of the tail capacitor CT array, the smaller the differential output swing, i.e., D... n Nodes and D p The smaller the voltage difference between nodes, the smaller the tap current, and the weaker the balance strength of the summer.

[0073] Based on the decision feedback equalizer described above, this application embodiment also provides a communication device, which includes the decision feedback equalizer described above.

[0074] The embodiments of this application do not specifically limit the type of communication device. For example, it may include optical communication devices and electrical interconnection devices.

[0075] The communication device provided in this application includes a decision feedback equalizer, which includes a summer and a controller. The summer includes a first resistor, a second resistor, multiple amplifier circuits, and multiple equalization circuits. Each amplifier circuit includes an FD-SOI type first pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current bit, and whose back gate is used to ground. Each equalization circuit includes an FD-SOI type second pair of differential MOSFETs whose front gate is used to receive the differential input signal of the current bit, and whose back gate is used to receive the differential feedback signal of the previous bit. The controller controls the number of equalization circuits in operation and the magnitude of the equalization current. Based on the number of equalization circuits in operation, the controller controls the number of amplifier circuits in operation. The output signals of the first pair of differential MOSFETs in the operating amplifier circuit and the output signals of the operating equalization circuit are superimposed at the ON and OP nodes, and then converted by the first and second resistors to obtain the equalized differential signal of the current bit. This improves the stability of the operation of the equalization circuit and the amplifier circuit, thereby improving the stability of the output common-mode voltage without the need for common-mode compensation circuit adjustment, thus improving the stability of the communication device and reducing circuit complexity.

[0076] The communication device provided in this application includes a decision feedback equalizer, which includes a decision unit, a first-stage circuit, and a second-stage circuit. The first-stage circuit includes at least a third pair of FD-SOI type differential MOSFETs. The second-stage circuit is used to isolate the first-stage circuit and the load capacitor. The front gate of the third pair of differential MOSFETs is used to receive the equalized differential signal. The back gate of the third pair of differential MOSFETs is used to receive a reference voltage. The first-stage circuit is used to output a differential feedback signal with a front bit to the back gate of the second pair of differential MOSFETs based on the comparison result between the reference voltage and the equalized differential signal, via the second-stage circuit, thereby reducing circuit complexity and circuit area.

[0077] Based on the decision feedback equalizer and communication device described above, this application embodiment also provides a method for using a decision feedback equalizer.

[0078] See Figure 7 The figure is a flowchart of a decision feedback equalizer method provided in an embodiment of this application.

[0079] The method for a decision feedback equalizer provided in this application includes:

[0080] S701: The differential input signal of the current bit is received by the front gate of the first pair of differential MOS transistors of the FD-SOI type in the amplifier circuit.

[0081] S702: The differential input signal of the current bit is received by the front gate of the second pair of differential MOS transistors of the FD-SOI type in the equalization circuit, and the differential feedback signal of the previous bit output by the decision unit is received by the back gate of the second pair of differential MOS transistors. The summer includes an amplifier circuit and an equalization circuit.

[0082] S703: By controlling the number of equalization circuits connected, the magnitude of the equalization current is controlled, and the number of amplifier circuits connected is controlled according to the number of equalization circuits connected.

[0083] S704: The output signals of the first pair of differential MOSFETs and the output signal of the equalization circuit are superimposed, and then converted by the first resistor and the second resistor to obtain the equalized differential signal of the current position.

[0084] The embodiments in this application do not specifically limit the execution order of S701 to S703, and can be set according to the actual application needs. For example, S701 and S702 can be executed simultaneously.

[0085] The decision feedback equalizer method provided in this application embodiment can utilize the front gate of the first pair of FD-SOI type differential MOSFETs in the amplifier circuit to receive the differential input signal of the current position, utilize the front gate of the second pair of FD-SOI type differential MOSFETs in the equalization circuit to receive the differential input signal of the current position, and utilize the back gate of the second pair of differential MOSFETs to receive the differential feedback signal of the previous position. By controlling the number of equalization circuits in operation, the magnitude of the equalization current is controlled, and the number of amplifier circuits in operation is controlled according to the number of equalization circuits in operation. After the output signal of the first pair of differential MOSFETs in the amplifier circuit in operation and the output signal of the equalization circuit in operation are superimposed, the equalized differential signal of the current position is obtained after conversion by the first resistor and the second resistor. This can improve the stability of the operation of the equalization circuit and the amplifier circuit, thereby improving the stability of the output common-mode voltage without the need for adjustment of the common-mode compensation circuit, improving the stability of the communication equipment, and reducing the circuit complexity.

[0086] Based on the decision feedback equalizer, communication device, and decision feedback equalizer method described above, embodiments of this application also provide a controller.

[0087] The controller provided in this application embodiment is used for the decision feedback equalizer method described above.

[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A decision feedback equalizer characterized by, The application relates to a summing device and a controller. The summing device comprises a first resistor, a second resistor, a plurality of amplification circuits and a plurality of equalization circuits. The plurality of amplification circuits are connected in parallel. The plurality of equalization circuits are connected in parallel. A first end of the first resistor is connected to a negative differential output ON node, and a first end of the second resistor is connected to a positive differential output OP node. A second end of the first resistor and a second end of the second resistor are both connected to a power supply. Each of the amplification circuits comprises a first pair of differential MOS transistors in a fully depleted silicon-on-insulator (FD-SOI) type. A front gate of the first pair of differential MOS transistors is used for receiving a differential input signal of a current bit. A back gate of the first pair of differential MOS transistors is used for grounding.

2. The equalizer of claim 1, wherein, A first end of each of the amplification circuits is connected to the ON node and the OP node through a first end of the first pair of differential MOS transistors. Each of the equalization circuits comprises a second pair of differential MOS transistors in the FD-SOI type. A front gate of the second pair of differential MOS transistors is used for receiving the differential input signal of the current bit.

3. The equalizer of claim 2, wherein, A back gate of the second pair of differential MOS transistors is used for receiving a differential feedback signal of a previous bit.

4. The equalizer of claim 1, wherein, A first end of each of the equalization circuits is connected to the ON node and the OP node through a first end of the second pair of differential MOS transistors. The controller controls the size of the equalization current by controlling the number of the equalization circuits to be turned on, and controls the number of the amplification circuits to be turned on according to the number of the equalization circuits to be turned on. Each of the amplification circuits further comprises a first pair of differential tail current transistors and a first switch.

5. The equalizer of claim 4, wherein, A second end of the first pair of differential MOS transistors is grounded through the first pair of differential tail current transistors, and a gate of the first pair of differential tail current transistors is connected to a bias current source through the first switch.

6. The equalizer according to any one of claims 1 to 5, characterized in that The controller controls the number of the amplification circuits to be turned on by controlling the closing of the first switch.

7. The equalizer according to any one of claims 1 to 5, characterized in that Each of the amplification circuits further comprises a first adjustable resistor. The first adjustable resistor is connected in parallel between second ends of the first pair of differential MOS transistors. Each of the equalization circuits further comprises a second pair of differential tail current transistors and a second switch. A second end of the second pair of differential MOS transistors is grounded through the second pair of differential tail current transistors, and a gate of the second pair of differential tail current transistors is connected to a bias current source through the second switch. The controller controls the number of the equalization circuits to be turned on by controlling the closing of the second switch. Each of the equalization circuits further comprises a second adjustable resistor. The second adjustable resistor is connected in parallel between second ends of the second pair of differential MOS transistors. The number of the equalization circuits to be turned on and the number of the amplification circuits to be turned on are kept constant, and the total current input to the first resistor and the second resistor is kept constant. The equalizer further comprises a decision device. The decision device comprises a first-stage circuit and a second-stage circuit. The first-stage circuit comprises at least a third pair of differential MOS transistors in the FD-SOI type. The second-stage circuit is used for isolating the first-stage circuit and a load capacitor. A front gate of the third pair of differential MOS transistors is used for receiving an equalized differential signal. A back gate of the third pair of differential MOS transistors is used for receiving a reference voltage. The first-stage circuit outputs a differential feedback signal of the previous flag bit to the back gate of the second pair of differential MOS transistors through the second-stage circuit according to a comparison result of the reference voltage and the equalized differential signal.

8. A communication device, characterized by The decision feedback equalizer comprises the first-stage circuit.

9. A method of a decision feedback equalizer characterized by, The decision feedback equalizer comprises: The front gate of the first pair of differential MOS transistors in the amplification circuit receives a differential input signal of a current bit; The front gate of the second pair of differential MOS transistors in the equalization circuit receives the differential input signal of the current bit, and the back gate of the second pair of differential MOS transistors receives a differential feedback signal of a previous flag bit output by the decision device; The summer comprises the amplification circuit and the equalization circuit; The number of the equalization current is controlled by controlling the number of the equalization circuit, and the number of the amplification circuit is controlled according to the number of the equalization circuit; The output signal of the first pair of differential MOS transistors and the output signal of the equalization circuit are superimposed, converted through the first resistor and the second resistor, and equalized differential signals of the current bit are obtained.

10. A controller characterized by comprising: The method for executing the decision feedback equalizer of claim 9.

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