A receiving circuit of a four-order pulse amplitude modulation signal and a high-speed communication chip

Abstract

The application discloses a kind of fourth-order pulse amplitude modulation signal receiving circuit and high-speed communication chip.Fourth-order pulse amplitude modulation signal receiving circuit includes: equalization module, level shift and limiting amplifier module, clock data recovery module, sampling module and decoding module;Clock data recovery module is connected with level shift and limiting amplifier module, clock data recovery module is used to recover sampling clock according to the second output signal input and send to sampling module;Sampling module is connected with clock data recovery module, and sampling module is used to use sampling clock respectively to first output signal, second output signal and third output signal are synchronously sampled, and output thermometer code;Decoding module is connected with sampling module, and decoding module is used to decode processing to thermometer code, and is converted into two-way non-return-to-zero code signal after output.This application can reduce circuit complexity, with the advantage of simple structure, can realize excellent performance.

Description

Technical Field

[0001] This invention relates to the field of high-speed communication technology, and in particular to a receiving circuit for a fourth-order pulse amplitude modulation signal and a high-speed communication chip. Background Technology

[0002] In recent years, the Internet and digital integrated circuits have experienced rapid development, with transmission signal frequencies continuously increasing. However, data transmission rates between local area networks (LANs) and wide area networks (WANs), between backplanes, and between chip I / O interfaces remain relatively low, increasingly becoming a performance bottleneck for digital communication systems. With the continuous evolution of the Internet and the significant improvement in the processing speed of digital integrated circuits—especially CPUs—this relatively low-speed data transmission capability between chips, between backplanes, and even between LANs is becoming increasingly prominent as a key weakness restricting the overall throughput of digital communication systems.

[0003] Therefore, when signal rates reach 50Gbps and above, traditional non-return-to-zero (NRZ) modulation methods face severe technical challenges in communication applications. In this high-speed scenario, channel attenuation is significantly amplified, making effective compensation through conventional equalization techniques difficult. Furthermore, employing complex equalization techniques leads to increased power consumption and higher chip area costs.

[0004] To address the technical challenges of high-speed signal transmission mentioned above, the 400GbE (400 Gigabit Ethernet) working group proposed using multi-level modulation techniques for signal transmission, with fourth-order pulse amplitude modulation (PAM4) being a typical example. Compared to traditional non-return-to-zero (NRZ) signals, PAM4 signals have only half the power spectral density bandwidth of NRZ signals, achieving twice the data transmission capacity at the same symbol rate.

[0005] Figure 1 This is a schematic diagram of a PAM4 signal receiving circuit, for reference. Figure 2This structure offers significant advantages: the digital information quantized by the analog-to-digital converter (ADC) exhibits high stability and is easy to store. Furthermore, thanks to feed-forward equalization (FFE) and decision-feedback equalization (DFE) techniques, inter-symbol interference can be eliminated relatively efficiently, thereby effectively reducing the design complexity of FFE and DFE.

[0006] Figure 2 This is a schematic diagram of a PAM4 receiver circuit based on level shifting. (Refer to...) Figure 2 Compared to ADC-based receiver architectures, this novel circuit structure exhibits significant advantages: its circuit design is simpler, eliminating the need for highly complex and demanding high-performance ADCs, and it also eliminates the power-intensive DSP module, thus significantly reducing overall system power consumption. Furthermore, its equalizer section can directly utilize the traditional Continuous Time Linear Equalizer (CTLE) structure for NRZ signals, further simplifying the circuit design. A key feature of this structure is the reduction in data rate through the introduction of a tap, effectively lowering the operating frequency of the clock and data recovery circuit (CDR), thereby reducing the performance requirements for the CDR circuit. However, this also complicates the CDR circuit structure, requiring multiple phase detectors to process four input signals simultaneously, and necessitating the design of an additional phase generation module to generate four different clock phases.

[0007] The high-frequency circuit of the PAM4 receiver based on ADC still faces the following key technical bottlenecks:

[0008] 1) Impact of quantization noise: Compared with the traditional DFE structure, ADC quantization error will lead to signal quality degradation. Especially when the quantization accuracy is insufficient, the DFE tap coefficients may be submerged by quantization noise, which directly affects the reliability of system signal reception.

[0009] 2) High-speed ADC design challenges: In ultra-high-speed (e.g., 50Gbps+) application scenarios, achieving high-precision ADC design faces severe circuit design challenges, including but not limited to linearity optimization, noise suppression and power consumption control.

[0010] 3) Digital Signal Processing (DSP) overhead: Introducing a DSP module will significantly increase system power consumption (up to several watts) and chip area (by about 30%-50%), leading to an increase in overall cost. This has become a core obstacle restricting the large-scale commercial use of this architecture.

[0011] The PAM4 receiver circuit based on level shifting still faces the following technical challenges:

[0012] 1) Increased complexity of CDR circuit: Due to the frequency division of the data rate, the circuit structure of CDR becomes more complex, requiring additional logic control to achieve synchronization of multi-phase clocks and data recovery.

[0013] 2) Multi-phase clock generation challenge: The receiving circuit not only needs to deploy multiple phase detectors to process four input signals simultaneously, but also needs to design a dedicated phase generation module to generate four clock signals with different phases, which significantly increases the design difficulty and power consumption of the clock circuit. Summary of the Invention

[0014] This invention provides a receiving circuit for fourth-order pulse amplitude modulation signals and a high-speed communication chip, which reduces circuit complexity, has the advantage of simple structure, and can achieve excellent performance.

[0015] According to one aspect of the present invention, a receiving circuit for a fourth-order pulse amplitude modulation signal is provided. The receiving circuit for a fourth-order pulse amplitude modulation signal includes: an equalization module, a level shifting and limiting amplification module, a clock data recovery module, a sampling module, and a decoding module.

[0016] The equalization module is connected to the level shifting and limiting amplification module. The equalization module is used to perform equalization processing on the input fourth-order pulse amplitude modulation signal to eliminate inter-symbol interference, and then send it to the level shifting and limiting amplification module.

[0017] The level shifting and limiting amplification module is connected between the equalization module and the sampling module. The level shifting and limiting amplification module is used to shift and amplify the signal after equalization, and separate it into a first output signal, a second output signal and a third output signal corresponding to different levels, and then send them to the clock data recovery module and the sampling module.

[0018] The clock data recovery module is connected to the level shifting and limiting amplification module. The clock data recovery module is used to recover the sampling clock based on the input second output signal and send it to the sampling module.

[0019] The sampling module is connected to the clock data recovery module. The sampling module is used to synchronously sample the first output signal, the second output signal and the third output signal using the sampling clock, and output the corresponding thermometer code.

[0020] The decoding module is connected to the sampling module. The decoding module is used to decode the thermometer code and convert it into two non-return-to-zero code signals before outputting them.

[0021] Optionally, the level shifting and limiting amplification module includes: a level shifting module and a limiting amplification module;

[0022] The level shifting module is connected to the equalization module. The level shifting module is used to level shift and amplify the equalized fourth-order pulse amplitude modulation signal and send it to the limiting amplification module.

[0023] The amplitude limiting and amplification module is connected to the level shifting module and the sampling module. The amplitude limiting and amplification module is used to perform level shifting and amplification on the equalization-processed fourth-order pulse amplitude modulation signal, and separate it into a first output signal, a second output signal and a third output signal corresponding to different levels, and then send them to the clock data recovery module and the sampling module.

[0024] Optionally, the clock data recovery module includes: a phase detector, a V / I converter, a low-pass filter, and a voltage-controlled oscillator;

[0025] The phase detector is connected to the V / I converter and the voltage-controlled oscillator. The phase detector is used to compare the input second output signal and the recovery clock signal generated by the voltage-controlled oscillator to generate and output UP or DN pulse signals.

[0026] The V / I converter is connected to the low-pass filter, and the low-pass filter is connected to the voltage-controlled oscillator. The V / I converter is used to convert the analog control voltage output by the low-pass filter into a proportional control current signal.

[0027] The low-pass filter is used to filter out high-frequency noise and ripple in the UP or DN pulse signal and generate a smooth analog control voltage.

[0028] The voltage-controlled oscillator is used to generate a recovery clock signal with a variable frequency according to the control current signal.

[0029] Optionally, the phase detector is a nonlinear full-rate Bang-Bang phase detector.

[0030] Optionally, the phase detector includes: a first master-slave D flip-flop, a second master-slave D flip-flop, a third master-slave D flip-flop, a fourth master-slave D flip-flop, a first XOR gate, and a second XOR gate;

[0031] The clock input of the first master-slave D flip-flop is connected to the sampling clock, the data input of the first master-slave D flip-flop is connected to the second output signal, and the first master-slave D flip-flop is used to output the first sampling signal;

[0032] The clock input of the second master-slave D flip-flop is connected to the sampling clock, the data input of the first master-slave D flip-flop is connected to the second output signal, the data input of the second master-slave D flip-flop is connected to the output of the first master-slave D flip-flop, and the second master-slave D flip-flop is used to output the second sampling signal;

[0033] The clock input of the third master-slave D flip-flop is connected to the sampling clock, the data input of the third master-slave D flip-flop is connected to the first sampling signal, and the third master-slave D flip-flop is used to output the third sampling signal.

[0034] The first XOR gate is connected to the first master-slave D flip-flop and the second master-slave D flip-flop. The first XOR gate is used to generate a hysteresis indication signal based on the first sampling signal and the second sampling signal input to the input terminal and output it through the output terminal.

[0035] The second XOR gate is connected to the third master-slave D flip-flop and the second master-slave D flip-flop. The second XOR gate is used to generate a lead indication signal based on the second sampling signal and the third sampling signal input to the input terminal and output it through the output terminal.

[0036] Optionally, when the lead indication signal is high, the lag indication signal is low;

[0037] Alternatively, when the lead indicator signal is low, the lag indicator signal is high.

[0038] Optionally, the first master-slave D flip-flop, the second master-slave D flip-flop, the third master-slave D flip-flop, and the fourth master-slave D flip-flop are all composed of two latches cascaded together to form a master-slave D flip-flop, and the input clock phases of the two latches are opposite.

[0039] Optionally, the sampling module includes: a fifth master-slave D flip-flop, a sixth master-slave D flip-flop, and a seventh master-slave D flip-flop;

[0040] The fifth master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the sixth master-slave D flip-flop. The fifth master-slave D flip-flop is used to synchronously sample the first output signal using the sampling clock, output the first thermometer code, and send it to the decoding module.

[0041] The sixth master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the seventh master-slave D flip-flop. The sixth master-slave D flip-flop is used to synchronously sample the second output signal using the sampling clock, output the second thermometer code, and send it to the decoding module.

[0042] The seventh master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the clock data recovery module. The seventh master-slave D flip-flop is used to synchronously sample the third output signal using the sampling clock, output the third thermometer code, and send it to the decoding module.

[0043] Optionally, the decoding module is a PAM4 decoder;

[0044] The PAM4 decoder is connected to the fifth master-slave D flip-flop, the sixth master-slave D flip-flop, and the seventh master-slave D flip-flop. The PAM4 decoder is used to decode the received first thermometer code, the second thermometer code, and the third thermometer code, and convert them into two non-return-to-zero code signals before outputting them.

[0045] According to another aspect of the present invention, a high-speed communication chip is provided, the high-speed communication chip including a receiving circuit for a fourth-order pulse amplitude modulation signal as described in any one of the preceding aspects.

[0046] The technical solution of this invention adopts a modular design through an equalization module, a level shifting and limiting amplification module, a clock data recovery module, a sampling module, and a decoding module, forming a clear and reliable PAM4 signal processing path, reducing design complexity and improving the overall reliability of the system. By employing a clock data recovery module and utilizing the intermediate level signal (second output signal) of the PAM4 signal for clock recovery, data correlation jitter can be effectively suppressed, obtaining a high-precision sampling clock and improving performance in high-frequency and noisy environments. By using a scheme combining synchronous sampling and decoding modules, the sampled thermometer code is accurately and quickly converted into two NRZ data streams, achieving reliable conversion from PAM4 signal to NRZ signal. In summary, this invention solves the problems of high complexity and poor performance in existing circuits, can better inherit and utilize the design concept of NRZ signal receiving circuits, has the advantage of simple structure, and can achieve excellent performance after proper design.

[0047] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of a PAM4 signal receiving circuit.

[0050] Figure 2 This is a schematic diagram of a PAM4 receiver circuit based on level shifting;

[0051] Figure 3 This is a schematic diagram of the circuit structure of a fourth-order pulse amplitude modulation signal according to an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the structure of a clock data recovery module according to an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of a phase detector according to an embodiment of the present invention;

[0054] Figure 6 This is a timing diagram of a phase detector clock phase lead provided according to an embodiment of the present invention;

[0055] Figure 7 This is a timing diagram of a phase detector clock phase lag according to an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of a master-slave D flip-flop according to an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] Figure 3 This is a schematic diagram of a circuit for a fourth-order pulse amplitude modulation signal according to an embodiment of the present invention. (Refer to...) Figure 3 The present invention provides a receiving circuit for a fourth-order pulse amplitude modulation signal, which includes: an equalization module 10, a level shifting and limiting amplification module 20, a clock data recovery module 30, a sampling module 40, and a decoding module 50.

[0060] The equalization module 10 is connected to the level shifting and limiting amplification module 20. The equalization module 10 is used to perform equalization processing on the input fourth-order pulse amplitude modulation signal to eliminate inter-symbol interference and send it to the level shifting and limiting amplification module 20.

[0061] The level shifting and limiting amplification module 20 is connected between the equalization module 10 and the sampling module 40. The level shifting and limiting amplification module 20 is used to shift and amplify the signal after equalization, and separate it into a first output signal Vout_A, a second output signal Vout_B and a third output signal Vout_C corresponding to different levels, and then send them to the clock data recovery module 30 and the sampling module 40.

[0062] The clock data recovery module 30 is connected to the level shifting and limiting amplification module 20. The clock data recovery module 30 is used to recover the sampling clock according to the input second output signal and send it to the sampling module 40.

[0063] The sampling module 40 is connected to the clock data recovery module 30. The sampling module 40 is used to synchronously sample the first output signal Vout_A, the second output signal Vout_B and the third output signal Vout_C using a sampling clock, and output the corresponding thermometer code.

[0064] The decoding module 50 is connected to the sampling module 40. The decoding module 50 is used to decode the thermometer code and convert it into two non-return-to-zero code signals before outputting them.

[0065] Specifically, the equalization module 10 can be a continuous time linear equalizer (CTLE). The input PAM4 signal first enters a CTLE. The main function of the CTLE is to perform equalization processing on the PAM4 signal, thereby eliminating inter-symbol interference generated during signal transmission and improving signal quality.

[0066] The signal, after being equalized by equalization module 10, enters level shifting and limiting amplification module 20. In this module, the equalized signal undergoes level shifting and amplification to provide a suitable level range and signal strength for subsequent signal processing. The PAM4 signal has three eye diagrams with smaller level intervals, making it more sensitive to noise, jitter, and inter-symbol interference. The level-shifted and amplified signal then passes through a limiting amplifier, which effectively processes the PAM4 eye diagram, separating the three eyes and outputting them as the first output signal Vout_A, the second output signal Vout_B, and the third output signal Vout_C. The second output signal Vout_B serves as the input signal to the clock data recovery module 30, used for clock extraction and data synchronization recovery. Level shifting and limiting amplification module 20 not only performs necessary gain and DC bias adjustments but also efficiently separates a single PAM4 signal into three binary signals corresponding to three decision thresholds, laying the foundation for subsequent parallel sampling and thermometer code generation.

[0067] The clock data recovery module 30 is used to recover the accurate sampling clock based on the input second output signal Vout_B (which typically corresponds to the intermediate eye diagram and contains rich clock information) and send the sampling clock to the sampling module 40.

[0068] The three master-slave D flip-flops in the sampling module 40 use the clock recovered by the clock data recovery module 30 to resample the first output signal Vout_A, the second output signal Vout_B, and the third output signal Vout_C, thereby obtaining the first thermometer code Va, the second thermometer code Vb, and the third thermometer code Vc. The thermometer code is a special encoding format that can more accurately represent the signal's level state.

[0069] Finally, the three thermometer codes are decoded by the decoding module 50. The decoding module 50 converts the thermometer codes into two final non-return-to-zero (NRZ) signals, realizing the conversion from PAM4 signals to NRZ signals and completing the signal processing flow of the entire receiving circuit.

[0070] In the circuit architecture, the design of the equalization module and the level shifting and limiting amplification module are consistent with the existing level shift-based PAM4 receiving circuit. The specific signal processing flow is as follows: after the PAM4 signal completes the level shifting operation, it is directly input to a decision comparator. The intermediate level decision result (second output signal Vout_B) output by the comparator will be used as the input signal of the clock data recovery module.

[0071] In the sampling stage, the traditional 1:4 tap changer approach was abandoned. The sampling module uses a high-speed D flip-flop for direct sampling to generate temperature codes. Simultaneously, the multi-phase generation module was removed. This optimized design effectively simplifies the overall architecture of the clock data recovery module.

[0072] The technical solution of this invention adopts a modular design through an equalization module, a level shifting and limiting amplification module, a clock data recovery module, a sampling module, and a decoding module, forming a clear and reliable PAM4 signal processing path, reducing design complexity and improving the overall reliability of the system. By employing a clock data recovery module and utilizing the intermediate level signal (second output signal) of the PAM4 signal for clock recovery, data correlation jitter can be effectively suppressed, obtaining a high-precision sampling clock and improving performance in high-frequency and noisy environments. By using a scheme combining synchronous sampling and decoding modules, the sampled thermometer code is accurately and quickly converted into two NRZ data streams, achieving reliable conversion from PAM4 signal to NRZ signal. In summary, this invention solves the problems of high complexity and poor performance in existing circuits, can better inherit and utilize the design concept of NRZ signal receiving circuits, has the advantage of simple structure, and can achieve excellent performance after proper design.

[0073] Continue to refer to Figure 3 Optionally, the level shifting and limiting amplification module 20 includes: a level shifting module 21 and a limiting amplification module 22;

[0074] The level shifting module 21 is connected to the equalization module 10. The level shifting module 21 is used to shift and amplify the fourth-order pulse amplitude modulation signal after equalization and send it to the limiting amplifier module 22.

[0075] The limiting amplification module 22 is connected to the level shifting module 21 and the sampling module 40. The limiting amplification module 22 is used to perform level shifting and amplification on the equalization-processed fourth-order pulse amplitude modulation signal, and separate it into a first output signal Vout_A, a second output signal Vout_B and a third output signal Vout_C corresponding to different levels, and then send them to the clock data recovery module 30 and the sampling module 40.

[0076] Specifically, the level shifting and limiting amplification module 20 includes a level shifting module 21 and a limiting amplification module 22 connected in sequence. The level shifting module 21 adjusts the equalized signal to a common-mode level suitable for subsequent circuit processing and performs preliminary amplification. The limiting amplification module 22 typically contains multiple comparators or limiting amplifiers with different reference voltages, separating the level-shifted and amplified PAM4 signal into three digital signals: a first output signal Vout_A, a second output signal Vout_B, and a third output signal Vout_C.

[0077] Figure 4 This is a schematic diagram of a clock data recovery module according to an embodiment of the present invention, with reference to... Figure 4 Optionally, the clock data recovery module 30 includes: a phase detector 31, a V / I converter 32, a low-pass filter 33, and a voltage-controlled oscillator 34;

[0078] Phase detector 31 is connected to V / I converter 32 and voltage-controlled oscillator 34. Phase detector 31 is used to compare the input second output signal and the recovery clock signal generated by voltage-controlled oscillator to generate and output UP or DN pulse signal.

[0079] The V / I converter 32 is connected to the low-pass filter 33, and the low-pass filter 33 is connected to the voltage-controlled oscillator 34. The V / I converter 32 is used to convert the analog control voltage output by the low-pass filter into a proportional control current signal.

[0080] The low-pass filter 33 is used to filter out high-frequency noise and ripple in the UP or DN pulse signal and generate a smooth analog control voltage.

[0081] The voltage-controlled oscillator 34 is used to generate a recovery clock signal with a variable frequency based on the control current signal.

[0082] Specifically, the core function of phase detector 31 is to compare the timing relationship (phase difference) between the input NRZ data signal (second output signal Vout_B) and the recovery clock. It does not output a continuous phase error voltage, but rather a discrete binary (or ternary) logic signal. Typically, it outputs an UP (or Early) signal, indicating that the phase of the recovery clock leads the data transition edge (requiring a reduction in VCO frequency / clock phase delay). It typically outputs a DN (or Late) signal, indicating that the phase of the recovery clock lags the data transition edge (requiring an increase in VCO frequency / clock phase advance). Sometimes it includes a HOLD or No Change state, indicating that the phases are roughly aligned. Its advantages are simple structure and high speed (suitable for high-speed applications), but it introduces quantization noise (jitter), and the loop gain is related to the input jitter amplitude (non-linear).

[0083] The core function of the V / I converter 32 is to convert the control voltage output from the low-pass filter 33 into a proportional current signal. Operating principle: It receives the analog voltage from the low-pass filter 33 and generates an output current that is linearly (or approximately linearly) related to it. This current is the actual control signal driving the voltage-controlled oscillator (VCO). Necessity: Many VCOs (especially LC oscillators) have current-sensitive control inputs or require a current signal to drive a charge pump or directly control the oscillator core. The V / I converter 32 provides an interface from the voltage domain (low-pass filter output) to the current domain (VCO control).

[0084] The core function of the low-pass filter 33 is to filter out high-frequency noise and ripple in the UP / DN pulse signal output by the phase detector 31, generate a smooth analog control voltage, and set the dynamic characteristics (bandwidth, stability, jitter suppression) of the PLL loop. Working principle: It receives UP and DN pulses from the phase detector 31 (usually via a charge pump structure, but sometimes the charge pump function is implicit in the PD or V / I), integrates and averages these pulses. UP pulses tend to increase the analog control voltage, while DN pulses tend to decrease it. The low-pass filter 33 (usually an RC low-pass filter or a high-order active filter) smooths these pulses, generating a relatively stable DC voltage. Key parameters: loop bandwidth (determines tracking speed and noise suppression capability), damping factor (determines stability).

[0085] The core function of the voltage-controlled oscillator 34 is to generate a variable-frequency recovery clock signal based on the control current (or indirectly through an analog control voltage). The frequency of this recovery clock is directly proportional (or inversely proportional) to the control current. Operating principle: Its oscillation frequency is modulated by the input control current signal (generated by the V / I converter 32 based on the analog control voltage). When the loop is locked, the output frequency of the voltage-controlled oscillator 34 is precisely equal to (or proportional to) the rate of the input data, and its phase is adjusted to optimally sample the input data (typically at the center of the data transition edge). The recovered clock signal output by the voltage-controlled oscillator 34 is used to re-timing and sampling the input data at the receiving end.

[0086] The overall workflow of the clock data recovery module loop can be summarized as follows: Phase detector 31 compares the input data DataIn with the recovery clock signal generated by voltage-controlled oscillator 34, producing UP or DN pulses to indicate the direction of phase error. These UP / DN pulses are integrated and smoothed by low-pass filter 33 to generate an analog control voltage. V / I converter 32 converts the analog control voltage into a control current signal. Voltage-controlled oscillator 34 adjusts the frequency and phase of its output recovery clock signal according to the control current signal. The adjusted recovery clock signal is fed back to phase detector 31, forming a closed-loop control. The loop continues to operate, eventually locking the frequency of the recovery clock signal to the input data rate and adjusting its phase to correctly sample data (eliminating the phase difference detected by phase detector 31).

[0087] Optionally, the phase detector is a nonlinear, full-rate Bang-Bang phase detector.

[0088] Specifically, phase detectors are mainly divided into two categories: linear phase detectors and nonlinear phase detectors. The output pulse width of a linear phase detector is linearly proportional to the phase difference between the two input signals. Specifically, when the phase difference between the input signals is small, the output pulse width decreases accordingly, which may cause the subsequent V / I (voltage-to-current) converter to fail to respond effectively, thus creating a phase detection dead zone. In contrast, the output pulse width of a nonlinear phase detector is fixed and is only used to characterize the relative leading or lagging state of the two signals' phases.

[0089] The clock data recovery module needs to support high-speed input data rates of 20Gb / s and above. Under this condition, the phase detection dead zone problem of linear phase detectors will be significantly aggravated, greatly increasing the difficulty of their implementation. Therefore, a non-linear Bang-Bang phase detector was selected, which is particularly suitable for high-speed, low-power applications.

[0090] Figure 5 This is a schematic diagram of a phase detector according to an embodiment of the present invention, with reference to... Figure 5 Optionally, the phase detector 31 includes: a first master-slave D flip-flop 311, a second master-slave D flip-flop 312, a third master-slave D flip-flop 313, a fourth master-slave D flip-flop 314, a first XOR gate 315, and a second XOR gate 316.

[0091] The clock input of the first master-slave D flip-flop 311 is connected to the sampling clock CLK, the data input of the first master-slave D flip-flop 311 is connected to the second output signal, and the first master-slave D flip-flop 311 is used to output the first sampling signal S1;

[0092] The clock input of the second master-slave D flip-flop 312 is connected to the sampling clock CLK, the data input of the first master-slave D flip-flop 311 is connected to the second output signal, the data input of the second master-slave D flip-flop 312 is connected to the output of the first master-slave D flip-flop 311, and the second master-slave D flip-flop 312 is used to output the second sampling signal S2.

[0093] The clock input of the third master-slave D flip-flop 313 is connected to the sampling clock CLK, the data input of the third master-slave D flip-flop 313 is connected to the first sampling signal S1, and the third master-slave D flip-flop 313 is used to output the third sampling signal S3.

[0094] The first XOR gate 315 is connected to the first master-slave D flip-flop 311 and the second master-slave D flip-flop 312. The first XOR gate 315 is used to generate a hysteresis indication signal Lag based on the first sampling signal S1 and the second sampling signal S2 input to the input terminal and output it through the output terminal.

[0095] The second XOR gate 316 is connected to the third master-slave D flip-flop 313 and the second master-slave D flip-flop 312. The second XOR gate 316 is used to generate a lead indicator signal Lead based on the second sampling signal S2 and the third sampling signal S3 input to the input terminal and output it through the output terminal.

[0096] Specifically, the phase detector comprises four master-slave D flip-flops and two XOR gates, interconnected to generate the hysteresis and lead indication signals through specific sampling and logic operations. The four master-slave D flip-flops trigger simultaneously, performing XOR operations on different sampling points to determine the lead / hysteresis value. The phase detector samples the input data within one clock cycle, obtaining a first sample signal S1, a second sample signal S2, and a third sample signal S3; subsequently, it performs XOR operations on these sampling results to output the phase detection result.

[0097] Figure 6 This is a timing diagram of a phase detector clock phase leading according to an embodiment of the present invention. When the clock phase leads the data phase (e.g.) Figure 6 As shown in the figure, S1⊕S2=0 and S2⊕S3=1 are satisfied. At this time, in the phase detector output signal, the lead indicator signal Lead is high level and the lag indicator signal Lag is low level.

[0098] Figure 7 This is a timing diagram of a phase detector clock phase lag provided by an embodiment of the present invention. Conversely, when the clock phase lags behind the data phase (e.g.) Figure 7As shown in the figure, if S1⊕S2=1 and S2⊕S3=0, then in the phase detector output signal, the lag indicator signal Lag is high and the lead indicator signal Lead is low. If the results of the calculations S1⊕S2 and S2⊕S3 are equal, it indicates that the input data has not changed.

[0099] Four master-slave D flip-flops share the same clock signal CLK, forming two parallel sampling channels. The first sampling signal S1 represents the reference data of the previous clock cycle; the second sampling signal S2 represents the boundary sampling data of the current clock cycle; and the third sampling signal S3 represents the center sampling data of the current clock cycle. These three points form two continuous observation windows: Window A: S1 → S2 (across cycles); Window B: S2 → S3 (within a cycle). The phase relationship can be determined by two XOR operations: S1⊕S2: detecting the data transition at the cross-clock cycle boundary (the change of data from the previous cycle to the current cycle); S2⊕S3: detecting the data transition within a single clock cycle (the change of data within the current cycle).

[0100] Optionally, when the lead indicator signal is high, the lag indicator signal is low;

[0101] Alternatively, when the lead indicator signal is low, the lag indicator signal is high.

[0102] Specifically, the logic states of the lag indicator signal and the lead indicator signal are mutually exclusive. That is, when the lead indicator signal is high, the lag indicator signal is low; conversely, when the lead indicator signal is low, the lag indicator signal is high. This simplifies the design of subsequent loop filtering.

[0103] Figure 8 This is a schematic diagram of a master-slave D flip-flop according to an embodiment of the present invention, with reference to... Figure 8 Optionally, the first master-slave D flip-flop, the second master-slave D flip-flop, the third master-slave D flip-flop, and the fourth master-slave D flip-flop are all composed of two latches cascaded together to form a master-slave D flip-flop, and the input clock phases of the two latches are opposite.

[0104] Specifically, the D flip-flop used in the phase detector is composed of two cascaded latches, such as... Figure 8 As shown, the two latches have opposite input clocks, forming a master-slave D flip-flop. The first to fourth master-slave D flip-flops are all constructed by cascading two latches with opposite input clock phases, which improves the speed and stability of the flip-flops.

[0105] The clock data recovery module continuously adjusts the output clock frequency based on the phase detection result. Finally, when the loop locks, sampling point S2 will fall on the rising edge of the data and oscillate around it until it reaches a dynamically stable state. At this point, sampling point S3 is located exactly at the center of the data bits and can be used to recover the data.

[0106] Continue to refer to Figure 1 Optionally, the sampling module 40 includes: a fifth master-slave D flip-flop 41, a sixth master-slave D flip-flop 42, and a seventh master-slave D flip-flop 43;

[0107] The fifth master-slave D flip-flop 41 is connected to the limiting amplifier module 22, the decoding module 50 and the sixth master-slave D flip-flop 42. The fifth master-slave D flip-flop 41 is used to synchronously sample the first output signal Vout_A using the sampling clock, output the first thermometer code Va and send it to the decoding module 50.

[0108] The sixth master-slave D flip-flop 42 is connected to the limiting amplifier module 22, the decoding module 50 and the seventh master-slave D flip-flop. The sixth master-slave D flip-flop 42 is used to synchronously sample the second output signal Vout_B using the sampling clock, output the second thermometer code Vb and send it to the decoding module 50.

[0109] The seventh master-slave D flip-flop 43 is connected to the limiting amplifier module 22, the decoding module 50 and the clock data recovery module 30. The seventh master-slave D flip-flop 43 is used to synchronously sample the third output signal Vout_C using the sampling clock, output the third thermometer code Vc and send it to the decoding module 50.

[0110] Specifically, the three master-slave D flip-flops in the sampling module 40 use the clock recovered by the clock data recovery module 30 to resample the first output signal Vout_A, the second output signal Vout_B, and the third output signal Vout_C, thereby obtaining the first thermometer code Va, the second thermometer code Vb, and the third thermometer code Vc. In the sampling stage, the traditional 1:4 tap changer method is abandoned, and instead, three high-speed D flip-flops are used for direct synchronous sampling to generate the corresponding thermometer codes.

[0111] Continue to refer to Figure 1 Optionally, the decoding module 50 is a PAM4 decoder;

[0112] The PAM4 decoder is connected to the fifth master-slave D flip-flop 41, the sixth master-slave D flip-flop 42, and the seventh master-slave D flip-flop 43. The PAM4 decoder is used to decode the received first thermometer code Va, second thermometer code Vb, and third thermometer code Vc, and then output them as two non-return-to-zero code signals.

[0113] Specifically, the decoding module 50 is a PAM4 decoder, which receives the first thermometer code Va, the second thermometer code Vb, and the third thermometer code Vc. Through logical operations, it decodes the three thermometer codes into the final two NRZ signals, completing the signal processing flow of the entire receiving circuit.

[0114] According to another aspect of the present invention, a high-speed communication chip is provided, which includes a receiving circuit for a fourth-order pulse amplitude modulation signal provided in any embodiment of the present invention.

[0115] The high-speed communication chip integrates the aforementioned PAM4 signal receiving circuit. This chip can be the core component of a high-speed serializer / deserializer, an Ethernet physical layer chip, or an optical communication transceiver chip, and is suitable for various high-bandwidth application scenarios that require processing PAM4 signals, such as 400G / 800G Ethernet.

[0116] Since the high-speed communication chip includes the receiving circuit for the fourth-order pulse amplitude modulation signal provided in any embodiment of the present invention, the beneficial effects of the high-speed communication chip and the receiving circuit for the fourth-order pulse amplitude modulation signal are the same, and will not be repeated here.

[0117] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A receiving circuit for a fourth-order pulse amplitude modulation signal, characterized in that, include: Equalization module, level shifting and limiting amplification module, clock data recovery module, sampling module, and decoding module; The equalization module is connected to the level shifting and limiting amplification module. The equalization module is used to perform equalization processing on the input fourth-order pulse amplitude modulation signal to eliminate inter-symbol interference, and then send it to the level shifting and limiting amplification module. The level shifting and limiting amplification module is connected between the equalization module and the sampling module. The level shifting and limiting amplification module is used to shift and amplify the signal after equalization, and separate it into a first output signal, a second output signal and a third output signal corresponding to different levels, and then send them to the clock data recovery module and the sampling module. The clock data recovery module is connected to the level shifting and limiting amplification module. The clock data recovery module is used to recover the sampling clock based on the input second output signal and send it to the sampling module. The sampling module is connected to the clock data recovery module. The sampling module is used to synchronously sample the first output signal, the second output signal and the third output signal using the sampling clock, and output the corresponding thermometer code. The decoding module is connected to the sampling module. The decoding module is used to decode the thermometer code and convert it into two non-return-to-zero code signals before outputting them. The clock data recovery module includes: a phase detector, a V / I converter, a low-pass filter, and a voltage-controlled oscillator; The phase detector is connected to the V / I converter and the voltage-controlled oscillator. The phase detector is used to compare the input second output signal and the recovery clock signal generated by the voltage-controlled oscillator to generate and output UP or DN pulse signals. The V / I converter is connected to the low-pass filter, and the low-pass filter is connected to the voltage-controlled oscillator. The V / I converter is used to convert the analog control voltage output by the low-pass filter into a proportional control current signal. The low-pass filter is used to filter out high-frequency noise and ripple in the UP or DN pulse signal and generate a smooth analog control voltage. The voltage-controlled oscillator is used to generate a recovery clock signal with a variable frequency according to the control current signal.

2. The circuit according to claim 1, characterized in that, The level shifting and limiting amplification module includes: a level shifting module and a limiting amplification module; The level shifting module is connected to the equalization module. The level shifting module is used to level shift and amplify the equalized fourth-order pulse amplitude modulation signal and send it to the limiting amplification module. The amplitude limiting and amplification module is connected to the level shifting module and the sampling module. The amplitude limiting and amplification module is used to perform level shifting and amplification on the equalization-processed fourth-order pulse amplitude modulation signal, and separate it into a first output signal, a second output signal and a third output signal corresponding to different levels, and then send them to the clock data recovery module and the sampling module.

3. The circuit according to claim 1, characterized in that, The phase detector is a nonlinear, full-rate Bang-Bang phase detector.

4. The circuit according to claim 1, characterized in that, The phase detector includes: a first master-slave D flip-flop, a second master-slave D flip-flop, a third master-slave D flip-flop, a fourth master-slave D flip-flop, a first XOR gate, and a second XOR gate; The clock input of the first master-slave D flip-flop is connected to the sampling clock, the data input of the first master-slave D flip-flop is connected to the second output signal, and the first master-slave D flip-flop is used to output the first sampling signal; The clock input of the second master-slave D flip-flop is connected to the sampling clock, the data input of the first master-slave D flip-flop is connected to the second output signal, the data input of the second master-slave D flip-flop is connected to the output of the first master-slave D flip-flop, and the second master-slave D flip-flop is used to output the second sampling signal; The clock input of the third master-slave D flip-flop is connected to the sampling clock, the data input of the third master-slave D flip-flop is connected to the first sampling signal, and the third master-slave D flip-flop is used to output the third sampling signal. The first XOR gate is connected to the first master-slave D flip-flop and the second master-slave D flip-flop. The first XOR gate is used to generate a hysteresis indication signal based on the first sampling signal and the second sampling signal input to the input terminal and output it through the output terminal. The second XOR gate is connected to the third master-slave D flip-flop and the second master-slave D flip-flop. The second XOR gate is used to generate a lead indication signal based on the second sampling signal and the third sampling signal input to the input terminal and output it through the output terminal.

5. The circuit according to claim 4, characterized in that, When the lead indicator signal is high, the lag indicator signal is low; Alternatively, when the lead indicator signal is low, the lag indicator signal is high.

6. The circuit according to claim 4, characterized in that, The first master-slave D flip-flop, the second master-slave D flip-flop, the third master-slave D flip-flop, and the fourth master-slave D flip-flop are all composed of two latches cascaded together to form a master-slave D flip-flop, and the input clock phases of the two latches are opposite.

7. The circuit according to claim 2, characterized in that, The sampling module includes: a fifth master-slave D flip-flop, a sixth master-slave D flip-flop, and a seventh master-slave D flip-flop; The fifth master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the sixth master-slave D flip-flop. The fifth master-slave D flip-flop is used to synchronously sample the first output signal using the sampling clock, output the first thermometer code, and send it to the decoding module. The sixth master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the seventh master-slave D flip-flop. The sixth master-slave D flip-flop is used to synchronously sample the second output signal using the sampling clock, output the second thermometer code, and send it to the decoding module. The seventh master-slave D flip-flop is connected to the limiting amplification module, the decoding module, and the clock data recovery module. The seventh master-slave D flip-flop is used to synchronously sample the third output signal using the sampling clock, output the third thermometer code, and send it to the decoding module.

8. The circuit according to claim 7, characterized in that, The decoding module is a PAM4 decoder; The PAM4 decoder is connected to the fifth master-slave D flip-flop, the sixth master-slave D flip-flop, and the seventh master-slave D flip-flop. The PAM4 decoder is used to decode the received first thermometer code, the second thermometer code, and the third thermometer code, and convert them into two non-return-to-zero code signals before outputting them.

9. A high-speed communication chip, characterized in that, The receiving circuit includes a fourth-order pulse amplitude modulation signal as described in any one of claims 1-8.

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