Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, an isolation layer located above the substrate, an epitaxial layer which is located above the substrate and covers the isolation layer, and a deep trench isolation piece which extends downwards in the epitaxial layer and is connected with the isolation layer. Wherein the isolation layer is located in the second region of the semiconductor structure but does not extend to the first region of the semiconductor structure. The semiconductor structure further includes a first element in the first region and a second element in the second region. Furthermore, the substrate can be used as a drain region of the first element. The second element is located in an isolation region defined by the deep trench isolation member and the isolation layer.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of manufacturing the same, and particularly to semiconductor structures and methods of manufacturing the same for integrating different types of semiconductor elements on the same substrate. Background Technology

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated within a given area. It is also exploring the integration of different types of semiconductor components on the same substrate. However, as the requirements for the electrical performance of semiconductor components continue to increase, the complexity of integrating these components also increases.

[0003] Taking laterally diffused metal-oxide-semiconductor (LDMOS) devices as an example, they can meet the requirements of high output power and gate-source breakdown voltage greater than 60 volts, and are mainly used in high-end audio amplifiers and wireless power amplifiers for cellular networks. The drive current of LDMOS devices is planar. Vertical devices, such as vertically diffused metal-oxide-semiconductor (VDMOS) devices, have the characteristic of high voltage resistance and are widely used in power switch devices. The drive current of VDMOS devices flows vertically. Currently, integrating LDMOS and VDMOS devices with different drive current directions on a substrate increases the complexity of the fabrication method, and the electrical performance of each device is easily affected by other different types of devices, making it unable to meet application requirements. Therefore, although existing semiconductor devices, individually, are usually appropriate and sufficient to meet their intended purpose, their integration and fabrication are not entirely satisfactory. Summary of the Invention

[0004] Some embodiments disclosed herein provide a semiconductor structure including a substrate, an isolation layer located above the substrate, an epitaxial layer located above the substrate and covering the isolation layer, and a deep trench isolation member extending downward in the epitaxial layer and connected to the isolation layer. The isolation layer is located in a second region of the semiconductor structure but does not extend into a first region of the semiconductor structure. The semiconductor structure also includes a first element located in the first region and a second element located in the second region. Furthermore, the substrate contains dopant, which can serve as the drain region of the first element. The second element is located in an isolation region defined by the deep trench isolation member and the isolation layer.

[0005] Some embodiments disclosed herein also provide a method for manufacturing a semiconductor structure, including providing a substrate; forming an isolation layer over the substrate, wherein the isolation layer is located in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; forming an epitaxial layer over the substrate and covering the isolation layer; forming a deep trench isolation member extending downward in the epitaxial layer and connected to the isolation layer; forming a first element in the first region, wherein the substrate serves as the drain region of the first element; and forming a second element in the second region, wherein the second element is located in an isolation region defined by the deep trench isolation member and the isolation layer. Attached Figure Description

[0006] Figure 1 This is a simplified cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0007] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages, according to some embodiments of this disclosure.

[0008] Figure 3 The diagram shows a cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, as illustrated in some other embodiments of this disclosure.

[0009] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages, according to some embodiments of this disclosure.

[0010] Figure 5 This is a schematic cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, according to some embodiments of this disclosure.

[0011] Figure 6A , Figure 6B for Figure 5 A magnified view of a portion of the semiconductor structure.

[0012] Symbol Explanation

[0013] 1, 2: Semiconductor structure

[0014] 11: First Component

[0015] 12: Second Component

[0016] 13: Third Component

[0017] 14: Fourth Component

[0018] 100: Base

[0019] 104: Isolation layer

[0020] 1040: Silicon oxide layer

[0021] 114: Deep trench isolation component

[0022] 114L: Lower part

[0023] 1142: First deep trench isolation component

[0024] 1143: Second deep trench isolation component

[0025] 1144: Third deep trench isolation component

[0026] 1200: Epitaxial materials

[0027] 120: Epitaxial layer

[0028] 102: First epitaxial material layer

[0029] 112: Second epitaxial material layer

[0030] 16: Gate structure

[0031] 31L: Liner

[0032] 311: Insulation layer

[0033] 313: Dielectric layer

[0034] 314: Insulation Part

[0035] 31G: Gate

[0036] 312: Bottom gate

[0037] 316: Top gate

[0038] 321, 331, 341: N-type traps

[0039] 330, 340: P-type trap

[0040] 331B, 340B: Matrix region

[0041] 322, 324, 325, 332, 334, 335, 342, 344, 345, 3321, 3322, 3341, 3342, 3421, 3422, 3441, 3442: Heavily doped regions

[0042] 326, 336, 346, 3361, 3362, 3461, 3462: Gate structures

[0043] 100a, 102a, 104a, 112a, 114a, 120a, 900a, 1040a: Top surface

[0044] 104b, 114b, 901b: Bottom surface

[0045] 104S, 900S, 903S: Side surface

[0046] 900: Substrate

[0047] 9001: The remaining portion of the substrate (supply layer)

[0048] 9002: Removal of substrate

[0049] 900': Supply Department

[0050] 901: Weakening Layer

[0051] 9011: Lower Level

[0052] 9012: Upper Level

[0053] 9030: Mask material

[0054] 903: Mask

[0055] d4, d5: Distance

[0056] d6: Spacing

[0057] h0, h1: Thickness

[0058] A1: First Area

[0059] A2: Second Area

[0060] A3: Third Area

[0061] A4: Fourth Area

[0062] D1: First Direction

[0063] D2: Second Direction

[0064] D3: Third direction Detailed Implementation

[0065] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

[0066] Furthermore, spatially related terms such as "below," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the orientation depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0067] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0068] This disclosure provides a semiconductor structure and its manufacturing method. Through the isolation structures proposed in the embodiments, such as the configuration of local isolation layers and deep trench isolation devices, multiple semiconductor elements of different types can be integrated on the same substrate (e.g., a wafer), particularly multiple semiconductor elements with different drive current directions. The locally configured isolation structures in the embodiments allow the semiconductor elements to exhibit good electrical performance. Furthermore, the manufacturing method of the semiconductor structure in the embodiments is simple and does not require expensive manufacturing costs, enabling the integration of different types of semiconductor elements on the same substrate.

[0069] The applications of this embodiment include integrating multiple semiconductor devices with different current directions during operation on a single substrate. These semiconductor devices are, for example, metal-oxide-semiconductor (MOS) devices, including complementary MOS (CMOS), laterally diffused MOS (LDMOS), double-diffused MOS (DMOS), vertically diffused MOS (VDMOS), or other MOS devices. For example, a VDMOS device with a vertical current direction and an LDMOS device, CMOS device, or other semiconductor device with a horizontal current direction can be integrated on the same substrate. However, this disclosure is not limited to the aforementioned devices.

[0070] Figure 1 This is a simplified cross-sectional view of a semiconductor structure 1 at an intermediate manufacturing stage, according to some embodiments of the present disclosure. According to embodiments, multiple semiconductor elements of different types can be integrated on a substrate 100. An isolation region is formed by forming a locally extended isolation layer, such as a silicon-on-insulator (SOI) layer, above the substrate, and forming deep trench isolation members connected to the isolation layer. This provides a placement area for semiconductor elements with horizontally oriented operating currents, while semiconductor elements with vertically oriented operating currents can be placed in areas outside the isolation layer.

[0071] According to an embodiment, at least one semiconductor element with a vertical current direction and at least one semiconductor element with a horizontal current direction are integrated on a substrate 100. This example illustrates the integration of one semiconductor element with a vertical current direction and three semiconductor elements with horizontal current directions.

[0072] like Figure 1 As shown in this example, a first element 11, a second element 12, a third element 13, and a fourth element 14 are respectively disposed in the first region A1, the second region A2, the third region A3, and the fourth region A4 of the semiconductor structure 1 to form the semiconductor structure 1. The first element 11, the second element 12, the third element 13, and the fourth element 14 are laterally separated (e.g., in the first direction D1).

[0073] In this example, the first element 11 is a vertical metal-oxide-semiconductor (MOS) device, such as a VDMOS device, and is described in connection with the VDMOS device using a split trench gate (SGT) structure as the gate structure 16. However, this disclosure is not limited to this; in some other embodiments, the first element 11 may also include a general trench gate structure. The second element 12, the third element 13, and the fourth element 14 are non-vertical MOS devices, such as NMOS devices, LDPMOS devices, and LDNMOS devices, respectively. However, the semiconductor devices that can be integrated in this disclosure are not limited to the above types.

[0074] Furthermore, to clearly illustrate the content of the embodiments, Figure 1 The detailed structure and description of these components are omitted. Configurations of some applicable first elements 11 to fourth elements 14 and related components will be described later (see reference). Figure 5 , Figure 6A , Figure 6B (Exemplary but not limiting descriptions are provided.)

[0075] According to some embodiments, the semiconductor structure 1 further includes an epitaxial layer 120 and an isolation layer 104 located above the substrate 100, with the isolation layer 104 partially extending within the epitaxial layer 120. For example... Figure 1 As shown, the isolation layer 104 is located outside the first region A1. That is, the isolation layer 104 is locally formed above the substrate 100, for example, it may extend continuously in the second region A2, the third region A3, and the fourth region A4 (e.g., along the first direction D1), but not extend to the first region A1. Furthermore, although Figure 1 The cross-section shows an elongated isolation layer 104 extending in the first direction D1, but when viewed from above the substrate 100 (not shown), this partially disposed isolation layer 104 also extends in the second direction D2.

[0076] According to some embodiments, the material of the isolation layer 104 includes a single layer or multiple layers of insulating material, such as silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. Furthermore, the isolation layer 104 may contain suitable dopants or may not contain any dopants. In some non-limiting examples, the isolation layer 104 is a silicon oxide layer.

[0077] In some embodiments, the substrate 100 is a substrate doped with a high concentration of a first conductivity type, such as a silicon wafer. In applications where a vertical metal-oxide-semiconductor device (MOSS) element is used as the first element 11, since the first region A1 does not contain the isolation layer 104, the substrate 100 with the first conductivity type can serve as the drain region of the first element 11, allowing the drive current to flow in the vertical direction (e.g., the third direction D3). In some embodiments, a back-side conductor layer (not shown) is also formed beneath the substrate 100 to contact the bottom surface of the substrate 100, and the back-side conductor layer forms the drain terminal of the first element 11. In some embodiments, the first conductivity type is n-type, so the substrate 100 is, for example, a highly doped n-type substrate. However, this disclosure is not limited to this; in some other embodiments, the first conductivity type can also be p-type, which is the opposite conductivity type.

[0078] In some embodiments, the epitaxial layer 120 has the same conductivity type as the substrate 100. In this example, both the substrate 100 and the epitaxial layer 120 have a first conductivity type, such as (but not limited to) n-type. Furthermore, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 120.

[0079] Furthermore, the epitaxial layer 120 can be a single-layer or multi-layer structure. For example... Figure 1 As shown, in this example, the epitaxial layer 120 includes a first epitaxial material layer 102 and a second epitaxial material layer 112. In some embodiments, a partially disposed isolation layer 104 is located on the first epitaxial material layer 102, for example, on the top surface 102a of the first epitaxial material layer 102, and the isolation layer 104 extends continuously in the second region A2, the third region A3, and the fourth region A4. The second epitaxial material layer 112 is located on the first epitaxial material layer 102 and covers the isolation layer 104. Since the isolation layer 104 in this embodiment is partially disposed, the second epitaxial material layer 112 is in direct contact with the first epitaxial material layer 102 in the first region A1 outside the isolation layer 104.

[0080] Generally, the multilayer epitaxial layer 120 can have its carrying voltage adjusted. The thicker the epitaxial layer 120, the higher its carrying voltage. Furthermore, the structure of the epitaxial layer 120 can be selected according to the actual application of other components and the epitaxial layer 120. For example, when the doping concentration of the substrate 100 is very high, a multilayer epitaxial layer 120 is formed (e.g., including a first epitaxial material layer 102 and a second epitaxial material layer 112). When the doping concentration of the substrate 100 is not too high, a single-layer epitaxial layer 120 can be formed (e.g., without the first epitaxial material layer 102). Therefore, the formation of a single-layer or multilayer epitaxial layer 120 can be determined according to the actual application, and this disclosure does not impose any particular limitation on this.

[0081] According to some embodiments, the semiconductor structure 1 further includes a deep trench isolation member 114 extending downward in the epitaxial layer 120 and connected to the isolation layer 104. The deep trench isolation member 114 extends, for example, from the top surface 120a of the epitaxial layer 120 toward the substrate 100, for example, along a third direction D3.

[0082] In some embodiments, the bottom of the deep trench spacer 114 may not extend beyond the bottom of the isolation layer 104. In some other embodiments, the bottom of the deep trench spacer 114 may extend beyond the bottom of the isolation layer 104. Accordingly, the bottom of the deep trench spacer 114 may be on approximately the same horizontal plane as the bottom of the isolation layer 104, or it may be on a different horizontal plane. This disclosure does not impose many limitations in this regard, and appropriate design and adjustments can be made according to actual processes.

[0083] In some examples, the deep trench spacer 114 may extend through the second epitaxial material layer 112 to the spacer layer 104; for example, the lower portion of the deep trench spacer 114 may be located in or through the spacer layer 104. Figure 1 As shown, the lower part 114L of the deep trench separator 114 extends from the top surface 104a of the separator 104 to the bottom surface 104b of the separator 104.

[0084] It is worth noting that, although Figure 1 The cross-sectional view shows two long strips of deep trench spacers 114 formed in each of the second region A2, the third region A3 and the fourth region A4 (e.g., extending in the third direction D3), but if viewed from above the substrate 100, these deep trench spacers 114 are, for example, a closed ring surrounding the periphery of the subsequently formed elements.

[0085] According to some embodiments, the isolation structure formed by the configuration of the locally formed isolation layer 104 and the deep trench isolation member 114 can define an isolation region, enabling semiconductor elements disposed in the isolation region (e.g., the second element 12 / the third element 13 / the fourth element 14) to achieve good electrical isolation from semiconductor elements outside the isolation region (e.g., the first element 11). In particular, in some examples where the first element 11 is a VDMOS element, the substrate 100, which serves as the drain of the first element 11, is connected to a drain operating voltage, so that even if the first element 11 is operated, the electrical performance of other integrated elements on the substrate 100 (e.g., the second element 12 / the third element 13 / the fourth element 14 in the isolation region) is not affected.

[0086] Furthermore, in some embodiments, the semiconductor structure 1 includes independently disposed deep trench isolation members 114, which, when connected to the isolation layer 104, can define different isolation regions. Specifically, such as Figure 1As shown, semiconductor structure 1 includes a first deep trench isolation member 1142, a second deep trench isolation member 1143, and a third deep trench isolation member 1144 connected to isolation layer 104, and these deep trench isolation members are spaced appropriately apart in the lateral direction (e.g., in the first direction D1). A second element 12 is located in the isolation region defined by the first deep trench isolation member 1142 and isolation layer 104, wherein the first deep trench isolation member 1142, for example, encloses the periphery of the second element 12. A third element 13 is located in the isolation region defined by the second deep trench isolation member 1143 and isolation layer 104, wherein the second deep trench isolation member 1143, for example, encloses the periphery of the third element 13. A fourth element 14 is located in the isolation region defined by the third deep trench isolation member 1144 and isolation layer 104, wherein the third deep trench isolation member 1144, for example, encloses the periphery of the fourth element 14.

[0087] Furthermore, the first deep trench isolator 1142 and the second deep trench isolator 1143 are, for example, separated by a distance d4 in the lateral direction, and the second deep trench isolator 1143 and the third deep trench isolator 1144 are, for example, separated by a distance d5 in the lateral direction. The distances d4 and d5 may be the same or different, and their actual values ​​can be appropriately selected and adjusted according to the component configuration required for the application.

[0088] Furthermore, in the example where a vertically diffused metal-oxide-semiconductor (VDMOS) device is used as the first element 11, the bottom of its gate structure 16 (e.g., a trench gate structure) may be higher or lower than the isolation layer 104, or approximately at the same horizontal level as the isolation layer 104; this disclosure does not impose any particular limitation on this. Generally, the closer the bottom of the gate structure 16 is to the substrate 100 (which has dopants of a first conductivity type, such as n-type) serving as the drain region, the better the electrical performance of the VDMOS device. Therefore, the depth of the gate structure 16 can adjust the vertical current of the VDMOS. However, the bottom surface of the gate structure 16 of the VDMOS device does not contact the substrate 100 serving as the drain region; that is, it must be separated from the substrate 100 by a distance. In addition, in some embodiments where horizontal elements such as N / PMOS or LDMOS are used as the second element 12, the third element 13, and the fourth element 14, in addition to the good electrical isolation between these elements being achieved through the configuration of locally disposed isolation layers 104 and deep trench isolation members 114, the farther the second element 12, the third element 13, and the fourth element 14 are from the substrate 100, the less the influence of the conductive substrate 100 (e.g., an n-type substrate) on the horizontal MOS elements such as the second element 12, the third element 13, and the fourth element 14 can be reduced.

[0089] The following are illustrated with reference to the accompanying drawings, illustrating two methods for forming an isolation structure (including a partial isolation layer 104 and a deep trench isolation member 114) over a substrate according to some embodiments of this disclosure. It should be noted that the details below are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, other known methods may also be applied to fabricate the isolation structures of the embodiments.

[0090] Figures 2A to 2G This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages according to some embodiments of this disclosure. This example is illustrative (not limiting) of the use of smart cut technology and a single epitaxial layer 120.

[0091] Reference Figure 2A According to some embodiments, a substrate 100 and a substrate 900 are provided. The substrate 100 is, for example, a silicon wafer. An oxide layer, such as a silicon-containing oxide layer 1040, is formed on the top surface 100a of the substrate 100. In some examples, the silicon-containing oxide layer 1040, such as silicon dioxide (SiO2), can be isotropically formed on the top surface 100a of the substrate 100 by an oxidation process. In some embodiments, the oxidation process can be thermal oxidation, radical oxidation, or other suitable processes.

[0092] In some embodiments, the substrate 900 is, for example, a donor wafer. The substrate 900 has a weakening layer 901 that defines the location of subsequent stripping portions of the substrate 900. For example, a hydrogen ion implantation layer can be formed within the substrate 900 using hydrogen ion implantation technology.

[0093] Then, refer to Figure 2B According to some embodiments, the silicon oxide layer 1040 on the substrate 100 is bonded to the substrate 900. For example, the bonding can be achieved by low-temperature annealing of the substrate 100 and the substrate 900. After bonding, the silicon oxide layer 1040 is located between the substrate 900 and the substrate 100.

[0094] Furthermore, in some embodiments, after the silicon oxide layer 1040 is bonded to the substrate 900, a portion of the substrate 900, containing hydrogen ions, exists between the weakening layer 901 and the silicon oxide layer 1040, and this portion, for example, has approximately the same thickness. That is, the weakening layer 901 and the silicon oxide layer 1040 are not in direct contact. Figure 2BAs shown, there is a spacing d6 between the bottom surface 901b of the weakening layer 901 and the top surface 1040a of the silicon oxide layer 1040 (in the third direction D3). This spacing d6 remains approximately equal in the first direction D1.

[0095] Then, refer to Figure 2C According to some embodiments, a smart peeling process is performed on the substrate 900 and the base 100, such as a medium-temperature annealing treatment, to peel off a portion of the substrate 900. The smart peeling process can leave a portion of the material from the substrate 900 on top of the base 100.

[0096] Because weakened regions, such as weakened layer 901, can be created in the substrate 900 through hydrogen ion implantation, the smart stripping process will peel off from the weakened layer 901 to remove a portion 9002 of the substrate 900. For example... Figure 2C As shown, the weakening layer 901 is separated into an upper layer 9012 and a lower layer 9011, for example, along the middle portion. The upper layer 9012 is, for example, the bottom surface of the removed portion 9002 of the substrate 900, and the lower layer 9011 is, for example, the top surface of the remaining portion 9001 of the substrate 900.

[0097] After the smart lift-off process, the remaining portion 9001 of the substrate 900 is transferred over the substrate 100, for example, onto and covering the silicon oxide layer 1040. The remaining portion 9001 of the substrate 900 may be referred to as the donor layer 9001 below. In some examples, the substrate 900 is, for example, a silicon-containing substrate, and the donor layer 9001 is, for example, a donor silicon layer.

[0098] Furthermore, in some embodiments, after the stripping step, a thermal process can be selectively applied to the silicon oxide layer 1040 to increase the density of the oxide layer material. In some embodiments, the aforementioned thermal process can be a rapid thermal annealing (RTA) process.

[0099] Then, refer to Figure 2D According to some embodiments, a mask material 9030 is formed over the supply layer 9001. The mask material 9030 is, for example, a single or multiple layers of hard mask material; for simplicity, a single-layer mask material 9030 is illustrated in the figures. The mask material 9030 may contain oxides, such as silicon dioxide (SiO2). In some examples, an oxide hard mask material may be deposited over the supply layer 9001.

[0100] Reference Figure 2EAccording to some embodiments, the location of the isolation layer 104 locally disposed above the substrate 100 can be defined by a suitable photolithography patterning process.

[0101] In some examples, a patterned photoresist (not shown) corresponding to the location of the isolation layer 104 may be formed on the mask material 9030 (e.g., a hard oxide mask material). For example, this patterned photoresist has multiple openings to expose the top surface of the underlying mask material 9030.

[0102] Furthermore, the aforementioned patterned photoresist can be formed into a patterned photoresist with openings through, for example, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes.

[0103] Subsequently, the mask material 9030 is etched according to the patterned photoresist to form a mask (e.g., an oxide hard mask) 903. This mask 903 exposes the top surface of the underlying supply layer 9001.

[0104] After forming mask 903, the patterned photoresist is removed.

[0105] Next, portions of the supply layer 9001 and the silicon oxide layer 1040 are removed according to the pattern of the mask 903. For example, portions of the supply layer 9001 and the silicon oxide layer 1040 not covered by the mask 903 are removed. The remaining portion of the supply layer 9001 forms a donor portion 900', such as a donor silicon portion. The remaining portion of the silicon oxide layer 1040 forms the isolation layer 104 of this embodiment.

[0106] In some embodiments, such as Figure 2E As shown, the side surface 903S of the mask 903, the side surface 900S of the supply section 900', and the side surface 104S of the isolation layer 104 are substantially coplanar.

[0107] After forming the supply section 900' and the isolation layer 104 of the embodiment, the mask 903 can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After removing the mask 903, a cleaning process can be selectively performed to remove residues.

[0108] Reference Figure 2F According to some embodiments, an epitaxial material 1200 is formed above the substrate 100, wherein the epitaxial material 1200 covers the supply portion 900' and the isolation layer 104.

[0109] In some examples, an excessive amount of epitaxial material 1200 is formed over the substrate 100, and the epitaxial material 1200 covers the top surface 900a and side surface 900S of the supply portion 900', and covers the side surface 104S of the isolation layer 104.

[0110] Furthermore, a planarization process can be selectively performed on the epitaxial material 1200 to give it a flat top surface. The planarization process can be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the aforementioned processes. It is worth noting that after the planarization process, the epitaxial material 1200 in this embodiment is still excessively formed on the top surface 900a of the supply section 900'.

[0111] Then, refer to Figure 2G According to some embodiments, a deep trench isolation member 114 is formed in the epitaxial layer 120, wherein the bottom of the deep trench isolation member 114 is connected to the isolation layer 104. The position of the deep trench isolation member 114 can be defined by a suitable photolithographic patterning process.

[0112] In some examples, a mask (not shown) may be formed over the epitaxial material 1200, and this mask may have a plurality of openings corresponding to the locations of the deep trench isolation members 114 to be formed. In some embodiments, the mask may be, for example, a patterned photoresist formed of a photoresist material. In some other embodiments, the mask material may be a hard mask (HM) composed of oxide and nitride layers. In some examples where a patterned photoresist is used as the mask, the photolithographic patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes, to form the openings of the mask.

[0113] Next, a portion of the epitaxial material 1200 is removed according to the opening of the mask to form deep trenches (not shown) connected to the isolation layer 104. The remaining portion of the epitaxial material 120 forms the epitaxial layer 120. Therefore, in this example, these deep trenches expose the epitaxial layer 120, the supply portion 900', and the isolation layer 104 from top to bottom at the sidewalls adjacent to the isolation layer 104. Then, suitable material is filled into these deep trenches, and a portion of the material is removed by a suitable planarization process to form deep trench spacers 114 in the epitaxial layer 120.

[0114] The planarization process described above is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes. According to some embodiments, after the planarization process, the top surface 114a of the deep trench spacer 114 is substantially coplanar with the top surface 120a of the epitaxial layer 120.

[0115] In some embodiments, each deep trench isolator 114 comprises an insulating material. In some embodiments, each deep trench isolator 114 comprises an insulating material (not shown) and a conductive material (not shown), wherein the insulating material covers the sidewalls and bottom of the conductive material. The insulating material includes, for example (but not limited to), silicon oxide, germanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium dioxide alloy, silicon hafnium dioxide, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable materials, or combinations thereof. In some embodiments, the conductive material includes amorphous silicon, polycrystalline silicon, other suitable materials, or combinations thereof. In some examples, the insulating material comprises silicon oxide, and the conductive material comprises polycrystalline silicon.

[0116] Accordingly, after forming the deep trench isolation member 114 connected to the isolation layer 104, the fabrication of the isolation structure of the embodiment is completed.

[0117] Although Figures 2A to 2G The example shown uses a single-layer epitaxial layer 120, but this disclosure is not limited thereto. In some embodiments, the epitaxial layer 120 may also comprise multiple layers of epitaxial material.

[0118] Figure 3 The diagram shows a cross-sectional view of a semiconductor structure at an intermediate manufacturing stage, as illustrated in some other embodiments of this disclosure. Figure 3 Zhongyu Figure 2G Identical or similar parts use the same or similar reference numbers.

[0119] like Figure 3 As shown, the epitaxial layer 120 includes a first epitaxial material layer 102 and a second epitaxial material layer 112, and the partially disposed isolation layer 104 is located on the first epitaxial material layer 102, for example, on the top surface 102a of the first epitaxial material layer 102. Furthermore, Figure 3 In one example, the bottom surface of the deep trench spacer 114 connected to the isolation layer 104 rests, for example, on the top surface 102a of the first epitaxial material layer 102. According to some embodiments, the top surface 114a of the deep trench spacer 114 is substantially coplanar with the top surface 112a of the second epitaxial material layer 112.

[0120] Please refer to the above. Figures 2A to 2G The manufacturing method forms such as Figure 3 The structure shown is different, but... Figure 3An example is that a first epitaxial material layer 102 is first formed on a substrate 100, and then a silicon oxide layer 1040 is formed on the top surface of the first epitaxial material layer 102 (see reference). Figure 2A (and related instructions). Then bond the substrate 100 to the base material 900 containing the weakening layer 901 (see reference). Figure 2B (and related explanations). Then, a smart stripping process is performed to peel off the weakening layer 901 to remove a portion 9002 of the substrate 900. The remaining portion 9001 of the substrate 900 is located on the silicon oxide layer 1040 (see reference). Figure 2C (and related instructions). Next, a mask 903 is formed, and the position of the isolation layer 104 is defined according to the pattern of the mask 903 (see reference). Figure 2D , Figure 2E (and related explanations). Then, an excess of a second epitaxial material layer 112 is formed on the first epitaxial material layer 102, wherein the second epitaxial material layer 112 covers the supply section 900', the isolation layer 104, and the first epitaxial material layer 102, and a deep trench isolation member 114 is formed in the second epitaxial material layer 112 (see reference). Figure 2F , Figure 2G (and related explanations). The inner wall of the deep trench separator 114 contacts, for example, the excess portion of the second epitaxial material layer 112, the supply portion 900', and the separator layer 104 in sequence from top to bottom.

[0121] In this example, such as Figure 3 As shown, the first epitaxial material layer 102 and the second epitaxial material layer 112 can be collectively referred to as epitaxial layer 120. Therefore, the isolation layer 104 is also formed in the epitaxial layer 120, and the first epitaxial material layer 102 is also included between the isolation layer 104 and the substrate 100.

[0122] According to the above manufacturing method, locally extended isolation layers 104 and deep trench isolation members 114 connected to the isolation layers 104 can be formed in some regions of the semiconductor structure to define the placeable region of the semiconductor element with the drive current in the horizontal direction. The regions without isolation layers 104 are used to place semiconductor elements with the drive current in the vertical direction.

[0123] Besides the manufacturing method using the intelligent stripping process described above, semiconductor structures can also be fabricated in other ways, and this disclosure does not impose many limitations on these methods. Another feasible manufacturing method is proposed below.

[0124] Figures 4A to 4G This is a partial cross-sectional schematic diagram of a semiconductor structure at multiple intermediate manufacturing stages, according to some embodiments of this disclosure. Figures 4A to 4G Zhongyu Figures 2A to 2G Identical or similar components are referred to by the same or similar reference numerals. Furthermore, this example is illustrative (but not limiting) of forming a single-layer epitaxial layer 120.

[0125] Reference Figure 4A According to some embodiments, a substrate 100 and a substrate 900 are provided. A silicon oxide layer 1040 is formed on the top surface 100a of the substrate 100.

[0126] about Figure 4A The configuration, materials, and manufacturing method of the substrate 100, silicon oxide layer 1040, and substrate 900 can be referred to the above. Figure 2A The descriptions of the substrate 100, the silicon oxide layer 1040, and the substrate 900 are not repeated here. It is worth noting that the substrate 900 in this example does not have a weakening layer.

[0127] Then, refer to Figure 4B According to some embodiments, the silicon oxide layer 1040 on the substrate 100 is directly bonded to the substrate 900. After bonding, the silicon oxide layer 1040 is located between the substrate 900 and the substrate 100.

[0128] Then, refer to Figure 4C According to some embodiments, a portion of the substrate 900 is removed, leaving a remaining portion 9001 of the substrate 900 on the silicon oxide layer 1040. The remaining portion 9001 of the substrate 900 may also be referred to as the supply layer 9001. In this example, a thinning process can be performed on the substrate 900 to remove a portion of the substrate 900. Such thinning processes include, for example, chemical mechanical polishing, mechanical polishing, etching, other suitable processes, or combinations thereof.

[0129] The stopping point of the aforementioned thinning process determines the position of the top surface of the supply layer 9001. In this example, after the thinning process, the initial thickness h0 of the substrate 900 ( Figure 4B The thickness h1 of the supply layer 9001 is reduced to that of the other layer. Figure 4C Furthermore, the supply layer 9001 has a generally uniform thickness h1.

[0130] Then, refer to Figure 4D According to some embodiments, a mask material 9030 is formed above the supply layer 9001. The mask material 9030 is, for example, a single or multiple layers of rigid mask material. For simplicity of the illustration, Figure 4D The example uses a single-layer mask material 9030. In some examples, the mask material 9030 is, for example, an oxide hard mask material, such as silicon dioxide (SiO2).

[0131] Then, refer to Figure 4E According to some embodiments, the location of the isolation layer 104 locally disposed above the substrate 100 can be defined by a suitable photolithography patterning process.

[0132] In some examples, a patterned photoresist (not shown) corresponding to the location of the isolation layer 104 may be formed on the mask material 9030, the mask material 9030 may be etched according to the patterned photoresist to form the mask 903, the patterned photoresist may be removed, and the supply layer 9001 and the silicon oxide layer 1040 below the mask 903 may be etched to form the supply portion 900' and the isolation layer 104.

[0133] about Figure 4E The configuration, materials, and manufacturing method of the patterned photoresist, mask 903, supply section 900', and isolation layer 104 can be referred to the above. Figure 2E The details regarding the patterned photoresist, mask 903, supply section 900', and isolation layer 104 will not be repeated here.

[0134] Then, refer to Figure 4F According to some embodiments, an epitaxial material 1200 is excessively formed over the substrate 100, wherein the epitaxial material 1200 covers the supply portion 900' and the isolation layer 104.

[0135] about Figure 4F The configuration, materials, and manufacturing method of the epitaxial material 1200 can be referred to the above. Figure 2F The relevant descriptions of the epitaxial material 1200 will not be repeated here.

[0136] Then, refer to Figure 4G According to some embodiments, a deep trench isolation member 114 is formed in the epitaxial layer 120, wherein the bottom of the deep trench isolation member 114 is connected to the isolation layer 104.

[0137] In some examples, the deep trench isolation element 114 can be formed using appropriate photolithographic patterning and deposition processes. For example, a mask with multiple openings is formed over the epitaxial material 1200, portions of the epitaxial material 1200 are removed through these openings to form deep trenches, and suitable material is filled into these deep trenches to form the deep trench isolation element 114. Details of these processes can be found above. Figure 2G The relevant explanations will not be repeated here.

[0138] Furthermore, regarding Figure 4G The configuration, materials, and manufacturing method of the deep trench isolation component 114 can be referred to the above. Figure 2G The relevant descriptions of the deep groove isolation component 114 will not be elaborated here.

[0139] Based on the above, after forming the deep trench isolation member 114 connected to the isolation layer 104, the fabrication of the isolation structure of the embodiment can be completed.

[0140] In some applications, one or more semiconductor elements with horizontally driven currents can be integrated into an isolation region defined by deep trench isolation 114 and isolation layer 104 above a substrate 100, while one or more semiconductor elements with vertically driven currents can be integrated into the region outside isolation layer 104. The following is an example of one semiconductor structure 2 that integrates VDMOS elements, N / P-type MOS elements, P-type LDMOS elements, and N-type LDMOS elements, but the semiconductor elements that can be integrated in this disclosure are not limited to this combination.

[0141] Figure 5 This is a schematic cross-sectional view of a semiconductor structure 2 at an intermediate manufacturing stage, according to some embodiments of this disclosure. Figure 6A , Figure 6B for Figure 5 A magnified view of a portion of semiconductor structure 2. Figure 5 , Figure 6A , Figure 6B and Figure 1 Identical or similar components are referred to by the same or similar reference numbers, and the details of these components in the above embodiments can be found therein, and will not be repeated in this example.

[0142] like Figure 5 As shown, in some embodiments, the semiconductor structure 2 includes a plurality of VDMOS elements disposed in the first region A1 as the first element 11, and in the example, a separated trench gate (SGT) structure is used as the gate structure 16 of the VDMOS elements, but this disclosure is not limited thereto.

[0143] In some embodiments, the semiconductor structure 2 further includes an N / P-type MOS element disposed in the second region A2 as an example of the second element 12; a P-type LDMOS element disposed in the third region A3 as an example of the third element 13; and an N-type LDMOS element disposed in the fourth region A4 as an example of the fourth element 14. According to some embodiments, the isolation layer 104 in the semiconductor structure 2 is locally formed above the substrate 100, for example, extending continuously along the first direction D1 in the second region A2, the third region A3, and the fourth region A4, but the isolation layer 104 does not extend to the first region A1.

[0144] Reference Figure 5 , Figure 6AAccording to some embodiments, in one example where a VDMOS element is used as the first element 11, each first element 11 includes a gate structure 16 and a heavily doped portion (not shown) adjacent to one side of the gate structure 16 and extending downward from the top surface 120a of the epitaxial layer 120. This heavily doped portion can serve as the source region of the first element 11. Furthermore, a substrate 100 (e.g., n-type) is used as the drain region of the first element 11.

[0145] In some embodiments, the heavily doped portion (not shown) of the source region of the first element 11 and the epitaxial layer 120 have the same conductivity type, and the doping concentration of the heavily doped portion is greater than the doping concentration of the epitaxial layer 120.

[0146] In some embodiments, the substrate 100, the epitaxial layer 120 serving as the drain region of the first element 11, and the heavily doped portion serving as the source region have a first conductivity type, such as (but not limited to) n-type. Furthermore, the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 120.

[0147] In some embodiments, the position of the gate structure 16 of the first element 11 can be defined by a suitable photolithographic patterning process. For example, a mask is first formed above the epitaxial layer 120, and a groove (not shown) is formed in the epitaxial layer 120 (e.g., in the second epitaxial material layer 112) through the mask; then an insulating layer 311 and a dielectric layer 313 are formed on the sidewalls of the groove, and a bottom gate 312 and a top gate 316, which are separated by an insulating portion 314, are formed in the groove to form the gate structure 16.

[0148] The insulating layer 311 and dielectric layer 313 together form a liner 31L in the groove, and the bottom gate 312 and top gate 316 together form a gate 31G. This example gate structure 16 includes the liner 31L, the insulating portion 314, and the gate 31G. However, this disclosure is not limited to this example structure.

[0149] According to some examples, the mask described above is a patterned photoresist formed from a photoresist material. In some other embodiments, the mask material may be a hard mask (HM) composed of oxide and nitride layers. In some examples where a patterned photoresist is used as the mask, the photolithographic patterning process described above includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing processes, to form a plurality of openings (not shown) in the mask. These openings expose the top surface 120a of the epitaxial layer 120. In this example, these openings expose the top surface 112a of the second epitaxial material layer 112.

[0150] According to some examples, after the mask is formed, one or more etching processes are performed through the openings in the mask to remove portions of the epitaxial layer 120, thereby forming grooves in the epitaxial layer 120. The etching processes include, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or combinations thereof.

[0151] In some examples, the groove is positioned corresponding to and below the opening of the mask. Therefore, the formed groove is, for example, a successor to and communicates with the opening. In some embodiments, the depth of the groove in the epitaxial layer 120 (e.g., along a third direction D3) may be greater than, less than, or equal to the depth of the deep trench separator 114 in the epitaxial layer 120 (e.g., along a third direction D3). The size, shape, and position of the mask opening and groove depend on the size, shape, and position of the gate structure 16 to be formed in the actual application, and are not limited herein.

[0152] According to some examples, after the aforementioned grooves are formed in the epitaxial layer 120, the mask can be removed by an ashing process, a wet etching process (e.g., acid etching), or other acceptable processes. After mask removal, a cleaning process can be selectively performed to remove residues.

[0153] Subsequently, according to some examples, a shielding insulating layer is formed on the sidewalls of the trench. The shielding insulating layer is, for example, silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or combinations thereof. Furthermore, the shielding insulating layer can be compliantly formed on the sidewalls and bottom surface of the trench, as well as on the top surface 120a of the epitaxial layer 120, by an oxidation process. The oxidation process can be thermal oxidation, radical oxidation, or other suitable processes.

[0154] In some examples, the shielding insulation layer may also be selectively subjected to a thermal process, such as rapid thermal annealing (RTA), to increase the density of the shielding insulation layer.

[0155] According to some examples, a bottom gate 312 is formed in the lower part of the recess, wherein the bottom gate 312 is located on the aforementioned shielding insulating layer. The bottom gate 312 may be a single-layer or multi-layer structure, and is formed, for example, from amorphous silicon, polycrystalline silicon, other suitable conductive materials, or combinations of the foregoing materials.

[0156] In some examples, a gate electrode material (not shown) can be deposited on a shielding insulating layer using a deposition process, and this gate electrode material fills the space in the trench outside the shielding insulating layer. The deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), other suitable processes, or a combination of the foregoing. Furthermore, in some examples, the gate electrode material can be selectively subjected to thermal processing, such as annealing.

[0157] Next, a portion of the gate electrode material is removed to form a structure as shown. Figure 5 , Figure 6A The bottom gate 312 is shown. For example, excess portions of the deposited gate electrode material can be removed by a planarization process, such as removing a portion of the gate electrode material located above the top surface 120a of the epitaxial layer 120. The planarization process is, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes. Subsequently, the portion of the gate electrode material in the recess is etched back to recess the gate electrode material to a specific depth to form the bottom gate 312 in the recess.

[0158] In some examples, the bottom gate 312 may optionally contain a dopant of a second conductivity type, such as a p-type dopant. In some examples, the dopant of the bottom gate 312 may be boron difluoride (BF2) or other suitable dopant. In addition to reducing the gate-drain capacitance (Cgd) to improve the switching characteristics of the semiconductor device, the bottom gate 312 of the separated trench gate structure, having a second conductivity type, can further enhance the effect of reducing the surface electric field (RESURF).

[0159] According to some examples, after the bottom gate 312 is formed, an etching process can be used to remove the upper portion of the shielding insulating layer. The remaining portion of the shielding insulating layer forms an insulating layer 311 located on the sidewalls and bottom surface of the lower part of the recess. The etching process described above can be, for example, dry etching, wet etching, plasma etching, reactive ion etching, other suitable processes, or combinations thereof. Furthermore, the top surface of the insulating layer 311 may be higher than or lower than the top surface of the bottom gate 312, or substantially coplanar with the top surface of the bottom gate 312, and exhibit a slight dishing effect.

[0160] Subsequently, a dielectric layer 313 is formed on the insulating layer 311 and the bottom gate 312 to serve as the gate dielectric layer for the subsequently formed top gate 316.

[0161] In some examples, a dielectric layer 313 may be compliantly deposited using a suitable deposition process to extend from the top surface 120a of the epitaxial layer 120 to the upper part of the trench, and to cover the top surface of the insulating layer 311 and the top surface of the bottom gate 312. This dielectric layer 313 does not completely fill the trench. Furthermore, the aforementioned deposition processes include, for example, PVD, CVD, atomic layer deposition (ALD), other suitable deposition processes, or combinations thereof.

[0162] In some examples, dielectric layer 313 may comprise silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, alumina-hafnium dioxide alloy, silicon dioxide hafnium, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some examples, the material of dielectric layer 313 differs from the material of the underlying insulating layer 311. In other examples, dielectric layer 313 is made of the same material as insulating layer 311.

[0163] Furthermore, according to some examples, during the formation of dielectric layer 313, bottom gate 312 is also oxidized, and a thicker insulating portion 314 is formed above bottom gate 312. Insulating portion 314, for example, contains insulating oxide. After top gate 316 is subsequently formed, this insulating portion 314 is located between bottom gate 312 and top gate 316, and can be used to electrically isolate bottom gate 312 and top gate 316.

[0164] Subsequently, according to some examples, a top gate 316 is formed in the upper part of the groove.

[0165] For example, the gate electrode material can be deposited on the dielectric layer 313 and fill the space above the trench excluding the dielectric layer 313 by a deposition process, including PVD, CVD, other suitable processes, or a combination of the foregoing. A thermal process, such as annealing, can be selectively applied to the gate electrode material. Subsequently, a portion of the gate electrode material is removed, for example, by a planarization process (including CMP, mechanical polishing, etching, other suitable processes, or a combination thereof) to remove excess gate electrode material, thereby forming the top gate 316.

[0166] like Figure 5 , Figure 6A As shown, the top gate 316 is located on the dielectric layer 313 and is separated from the bottom gate 312 below by an insulating portion 314. The top gate 316 can be a single-layer or multi-layer structure.

[0167] In some examples, the top gate 316 is formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some examples, the aforementioned metals may include, but are not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The aforementioned metal nitrides may include, but are not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The aforementioned metal silicides may include, but are not limited to, tungsten silicide (WSi). x The aforementioned conductive metal oxides may include, but are not limited to, ruthenium oxide (RuO2) and indium tin oxide (ITO).

[0168] Furthermore, in some examples, the top gate 316 may optionally contain a dopant having a second conductivity type (e.g., p-type). Furthermore, the materials used to fabricate the top gate 316 and the bottom gate 312 may be the same or different.

[0169] Accordingly, some example gate structures 16 are fabricated, including a liner 31L, an insulating portion 314, and a gate 31G. The liner 31L in the recess includes an insulating layer 311 and a dielectric layer 313, the bottom gate 312 and the top gate 316 are collectively referred to as gate 31G, and the insulating portion 314 is located between the bottom gate 312 and the top gate 316. However, this disclosure is not limited to this example gate structure 16.

[0170] Furthermore, in the example where a VDMOS device is used as the first element 11, the closer the bottom of the gate structure 16 is to the substrate 100 with a dopant of a first conductivity type (e.g., n-type) serving as the drain region, the better the electrical performance of the VDMOS device. According to some examples, the bottom of the gate structure 16 may be close to the bottom surface of the second epitaxial layer 112 (e.g., close to the isolation layer 104 or approximately equal to the depth of the deep trench isolation member 114), or extend into the first epitaxial layer 102, but the gate structure 16 does not directly contact the substrate 100.

[0171] Refer to Figure 5 , Figure 6A According to some embodiments, in one example where a PMOS element is used as the second element 12, an N-type well 321 can be formed in the isolation region defined by the first deep trench isolation member 1142 and the isolation layer 104, and heavily doped portions 322, 324 and 325 can be formed in the N-type well 321. These heavily doped portions 322, 324 and 325 can be spaced appropriately apart from each other.

[0172] In this example, heavily doped portions 322 and 324 can be the source and drain regions of the subsequently formed PMOS device (second element 12), respectively. Heavily doped portion 325 is the base region of the PMOS device. Furthermore, in this example, heavily doped portions 322 and 324 have the same conductivity type, such as (but not limited to) p-type. Heavily doped portion 325 has a different conductivity type than heavily doped portions 322 and 324; heavily doped portion 325 is, for example, (but not limited to) n-type.

[0173] Furthermore, in some embodiments, a gate structure 326 for a PMOS element (second element 12) is formed above the N-type well 321. The gate structure 326 is located on the epitaxial layer 120 and between the heavily doped portion 322 (source region) and the heavily doped portion 324 (drain region). The gate structure 326 includes, for example, a gate dielectric layer (not shown) and a gate electrode located above the gate dielectric layer.

[0174] Furthermore, in this example, a portion of an epitaxial layer 120, such as a portion of a second epitaxial material layer 112, is also included between the N-type well 321 and the underlying isolation layer 104, so as to achieve better electrical isolation between the formed PMOS element (second element 12) and the substrate 100 (e.g., n-type), and reduce the possible impact of the substrate 100 on the PMOS element when the first element 11 is operating.

[0175] Reference Figure 5 , Figure 6BAccording to some embodiments, in one example where a P-type LDMOS element is used as the third element 13, an N-type well 331 and a P-type well 330 can be formed in the isolation region defined by the second deep trench isolation member 1143 and the isolation layer 104. One of the N-type wells 331 is located between the two P-type wells 330, and the bottom surfaces of the N-type well 331 and the P-type well 330 are covered by a portion of the epitaxial layer 120 (e.g., the second epitaxial material layer 112).

[0176] An N-type well 331 and a P-type well 330 can be formed in the epitaxial layer 120 (e.g., in the second epitaxial material layer 112 in this example) by an ion implantation process. The N-type well 331 and the P-type well 330 extend downward from the top surface 120a of the epitaxial layer 120 into the epitaxial layer 120.

[0177] According to some examples, a P-type LDMOS device also includes a heavily doped region 332 (source region), a heavily doped region 334 (drain region), a heavily doped region 335 (base region), and a gate structure 336. The heavily doped regions 332 and 334 have the same second conductivity type, such as p-type. The heavily doped region 335 has a first conductivity type, such as n-type.

[0178] More specifically, such as Figure 6B As shown, the gate structure 336 includes gate structures 3361 and 3362 disposed over the P-type well 330 and the N-type well 331.

[0179] The heavily doped portion 332 (source region) includes a heavily doped portion 3321 adjacent to the gate structure 3361 and a heavily doped portion 3322 adjacent to the gate structure 3362. The heavily doped portions 3321 and 3322 are located in the N-type well 331.

[0180] The heavily doped portion 334 (drain region) includes a heavily doped portion 3341 adjacent to the gate structure 3361 and a heavily doped portion 3342 adjacent to the gate structure 3362. The heavily doped portions 3341 and 3342 are located in two P-type wells 330, respectively.

[0181] The heavily doped portion 335 (base region) is located in the N-type well 331 and is disposed between the two heavily doped portions 3321 and 3322 (source regions).

[0182] Furthermore, according to some examples, an N-body region 331B is also formed in the N-type well 331. Heavily doped portions 335 (base region) and heavily doped portions 3321 and 3322 (source regions) are formed in the N-body region 331B.

[0183] Furthermore, according to some examples, the doping concentration of the N-type well 331 is less than the doping concentration of the heavily doped regions 332 (including 3321 and 3322; source regions) and 334 (including 3341 and 3342; drain regions). The doping concentration of the N-type substrate region 331B is less than the doping concentration of the heavily doped regions 332 and 334.

[0184] Furthermore, in this example, between the N-type well 331 and the P-type well 330 and the underlying isolation layer 104, there is also a portion of the epitaxial layer 120, such as a portion of the second epitaxial material layer 112, so that the formed P-type LDMOS element (third element 13) is farther away from the substrate 100 (e.g., n-type), achieving better electrical isolation and reducing the possible impact of the substrate 100 on the third element 13 when the first element 11 is operating.

[0185] Refer to Figure 5 , Figure 6B According to some embodiments, in one example where an N-type LDMOS element is used as the fourth element 14, a P-type well 340 and an N-type well 341 may be formed in the isolation region defined by the third deep trench isolation member 1144 and the isolation layer 104. The P-type well 340 is located between the two N-type wells 341, and the bottom surfaces of the P-type well 340 and the N-type well 341 are covered by a portion of the epitaxial layer 120 (e.g., the second epitaxial material layer 112).

[0186] An N-type well 341 and a P-type well 340 can be formed in the epitaxial layer 120 (e.g., in the second epitaxial material layer 112 in this example) by an ion implantation process. The N-type well 341 and the P-type well 340 extend downward from the top surface 120a of the epitaxial layer 120 into the epitaxial layer 120.

[0187] According to some examples, an N-type LDMOS device also includes a heavily doped region 342 (source region), a heavily doped region 344 (drain region), a heavily doped region 345 (base region), and a gate structure 346. The heavily doped regions 342 and 344 have the same first conductivity type, such as n-type. The heavily doped region 345 has a second conductivity type, such as p-type.

[0188] More specifically, such as Figure 6B As shown, the gate structure 346 includes gate structures 3461 and 3462 disposed over the N-type well 341 and the P-type well 340.

[0189] The heavily doped portion 342 (source region) includes a heavily doped portion 3421 adjacent to the gate structure 3461 and a heavily doped portion 3422 adjacent to the gate structure 3462. The heavily doped portions 3421 and 3422 are located in the P-type well 340.

[0190] The heavily doped portion 344 (drain region) includes a heavily doped portion 3441 adjacent to the gate structure 3461 and a heavily doped portion 3442 adjacent to the gate structure 3462. The heavily doped portions 3441 and 3442 are located in two N-type wells 341, respectively.

[0191] The heavily doped portion 345 (base region) is located in the P-type well 340 and is disposed between the two heavily doped portions 3421 and 3422 (source regions).

[0192] Furthermore, according to some examples, a p-body region 340B is also formed in the p-type well 340. Heavily doped portions 345 (base region) and heavily doped portions 3421 and 3422 (source regions) are formed in the p-body region 340B.

[0193] Furthermore, according to some examples, the doping concentration of the P-type well 340 is less than the doping concentration of the heavily doped regions 342 (including 3421 and 3422; source regions) and 344 (including 3441 and 3442; drain regions). The doping concentration of the P-type substrate region 340B is less than the doping concentration of the heavily doped regions 342 and 344.

[0194] Furthermore, in this example, a portion of an epitaxial layer 120, such as a portion of a second epitaxial material layer 112, is also included between the N-type well 341 and the P-type well 340 and the underlying isolation layer 104, to achieve better electrical isolation between the formed N-type LDMOS element (fourth element 14) and the substrate 100 (e.g., n-type), reducing the potential impact of the substrate 100 on the fourth element 14 when the first element 11 is operating.

[0195] In the formation of such Figure 5 After the components are assembled, an insulating layer (not shown) can be formed above the epitaxial layer 120, and this insulating layer covers the gate structures 16, 326, 336 and 346. Furthermore, a plurality of contacts (not shown) are formed in the insulating layer, which are the gate structures (16 / 326 / 336 / 346), drain regions (324 / 334 / 344), source regions (322 / 332 / 342) and base regions (325 / 335 / 345) of the respective elements (11 / 12 / 13 / 14).

[0196] In summary, the semiconductor structure and manufacturing method disclosed in some embodiments of this disclosure, with its isolation structure including, for example, a local isolation layer and a deep trench isolation device, can integrate various types of semiconductor devices, particularly those with different current directions, on the same substrate (e.g., a wafer). In the application of these embodiments, vertical semiconductor devices with a vertical current direction, such as VDMOS devices, and non-vertical semiconductor devices with a non-vertical current direction (e.g., horizontal direction), such as N / PMOS and LDMOS, can be integrated. According to some embodiments, a locally extending isolation layer is provided above the substrate, and one or more isolation regions can be defined by the connection between the deep trench isolation device and the isolation layer. Non-vertical semiconductor devices are disposed in the isolation regions, while vertical semiconductor devices are disposed in areas without an isolation layer (i.e., outside the isolation regions). According to some embodiments, the substrate of the semiconductor structure contains a highly doped dopant as the drain region of the vertical semiconductor device. By providing a local isolation layer, the influence of the substrate on the electrical performance of the non-vertical semiconductor device can be reduced, enabling both the integrated vertical and non-vertical semiconductor devices to achieve good electrical performance. Therefore, according to the application of the embodiments disclosed herein, BCD (including bipolar, CMOS and DMOS elements) and VDMOS elements can be integrated on the same wafer to comprehensively solve the design challenges of complex, high-power applications.

[0197] Furthermore, according to the manufacturing methods proposed in some embodiments of this disclosure, a partially extended isolation layer and a semiconductor device integrating different types of semiconductor elements can be fabricated on a substrate through simple processes compatible with existing technologies. Moreover, when integrating different semiconductor elements, similar components can be fabricated together in the same process, saving steps; for example, multiple deep trench isolation elements can be formed in the same process, and wells or heavily doped portions of the same conductivity type can be formed in the same process. Therefore, the processes of these embodiments are simple and do not significantly increase additional manufacturing costs.

[0198] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; an isolation layer over the substrate, wherein the isolation layer is in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; an epitaxial layer over the substrate and covering the isolation layer; a deep trench isolation in the epitaxial layer and connecting with the isolation layer; a first element in the first region, and the substrate as a drain region of the first element; and a second element in the second region, and the second element in an isolation region defined by the deep trench isolation and the isolation layer. A lower portion of the deep trench isolation extends from a top surface of the isolation layer to a bottom surface of the isolation layer.

2. The semiconductor structure of claim 1, wherein, The isolation layer contacts a top surface of the substrate.

3. The semiconductor structure of claim 1, wherein, A bottom surface of the deep trench isolation contacts the top surface of the substrate.

4. The semiconductor structure of claim 3, wherein, The epitaxial layer further comprises:

5. The semiconductor structure of claim 1, wherein, a first epitaxial material layer over the substrate and extending in the first region and the second region of the semiconductor structure, wherein the isolation layer is over the first epitaxial material layer; and a second epitaxial material layer over the first epitaxial material layer and covering the isolation layer, wherein the deep trench isolation extends downward in the second epitaxial material layer and connects with the isolation layer. The isolation layer is directly formed on a top surface of the first epitaxial material layer.

6. The semiconductor structure of claim 5, wherein, A bottom surface of the deep trench isolation contacts a top surface of the first epitaxial material layer.

7. The semiconductor structure of claim 5, wherein the first and second semiconductor layers are formed of a same material. The deep trench isolation penetrates the isolation layer, and a bottom surface of the deep trench isolation is coplanar with a bottom surface of the isolation layer.

8. The semiconductor structure of claim 1, wherein, Driving current of the first element flows from a top surface of the epitaxial layer to the substrate, and driving current of the second element flows along the top surface of the epitaxial layer.

9. The semiconductor structure of claim 1, wherein, The substrate and the epitaxial layer have a same conductivity type, and a doping concentration of the substrate is greater than a doping concentration of the epitaxial layer.

10. The semiconductor structure of claim 1, wherein, The isolation layer continuously extends from the second region to a third region of the semiconductor structure, wherein the second region is between the third region and the first region.

11. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises:

12. The semiconductor structure of claim 11, wherein, a third element in the third region, wherein a current direction of the third element flows along the top surface of the epitaxial layer. The deep trench isolation is a first deep trench isolation disposed in the second region, wherein the second element is in the isolation region defined by the first deep trench isolation and the isolation layer, 13. The semiconductor structure of claim 12, wherein, The semiconductor structure further comprises: a second deep trench isolation disposed in the third region, and the second deep trench isolation and the first deep trench isolation are laterally separated by a distance, wherein the third element is in another isolation region defined by the second deep trench isolation and the isolation layer. The semiconductor structure comprises:

14. A method of manufacturing a semiconductor structure, characterized by, forming an isolation layer over a substrate, wherein the isolation layer is in a second region of the semiconductor structure but does not extend to a first region of the semiconductor structure; forming an epitaxial layer over the substrate and covering the isolation layer; ​ a deep trench isolation structure is formed in the epitaxial layer and extends downward to connect the isolation layer; a first element is formed in the first region, and the substrate serves as a drain region of the first element; and a second element is formed in the second region, and the second element is located in an isolation region defined by the deep trench isolation structure and the isolation layer.

15. The method of manufacturing a semiconductor structure according to claim 14, wherein forming the isolation layer over the substrate includes: providing the substrate; forming a silicon-containing oxide layer over a top surface of the substrate; bonding the silicon-containing oxide layer to a base material, wherein after bonding, the silicon-containing oxide layer is located between the base material and the substrate; removing a portion of the base material, a remaining portion of the base material being a supply layer located over the silicon-containing oxide layer; forming a mask over the supply layer; removing portions of the supply layer and portions of the silicon-containing oxide layer according to the mask, a remaining portion of the supply layer forming a supply portion, and a remaining portion of the silicon-containing oxide layer forming the isolation layer; and removing the mask.

16. The method of manufacturing a semiconductor structure according to claim 15, wherein the base material has a weakened layer therein, wherein after bonding the silicon-containing oxide layer to the base material, there is a vertical spacing between the weakened layer and the silicon-containing oxide layer, the manufacturing method further includes: peeling from the weakened layer to remove the portion of the base material, the remaining portion of the base material being the supply layer remaining over the silicon-containing oxide layer.

17. The method of manufacturing a semiconductor structure according to Claim 15, wherein after bonding the silicon-containing oxide layer to the base material, further including: performing a thinning process on the base material to remove the portion of the base material.

18. The method of manufacturing a semiconductor structure according to Claim 15, wherein after providing the substrate, performing a thermal oxidation process on the substrate to form the silicon-containing oxide layer on the top surface of the substrate.

19. The method of manufacturing a semiconductor structure according to Claim 15, wherein the epitaxial layer is formed in excess over the substrate, and the epitaxial layer covers a top surface and side surfaces of the supply portion and covers side surfaces of the isolation layer.

20. The method of manufacturing a semiconductor structure according to claim 19, wherein, the deep trench isolation structure is formed to extend downward from a top surface of the epitaxial layer to a bottom surface that connects the isolation layer, wherein an inner sidewall of the deep trench isolation structure sequentially contacts, from top to bottom, an excess portion of the epitaxial layer, the supply portion, and the isolation layer.

21. The method of manufacturing a semiconductor structure according to Claim 14, wherein the epitaxial layer further includes: a first epitaxial material layer located on the substrate and extending in the first region and the second region of the semiconductor structure, wherein the isolation layer is located over the first epitaxial material layer; and a second epitaxial material layer located on the first epitaxial material layer and covering the isolation layer, wherein the deep trench isolation structure extends downward in the second epitaxial material layer and connects the isolation layer.

22. The method of manufacturing a semiconductor structure according to claim 21, wherein the isolation layer is formed directly on a top surface of the first epitaxial material layer.

23. The method of manufacturing a semiconductor structure according to claim 22, wherein a bottom surface of the deep trench isolation structure contacts the top surface of the first epitaxial material layer.

24. The method of manufacturing a semiconductor structure according to Claim 14, wherein a driving current of the first element flows in a direction from a top surface of the epitaxial layer toward the substrate, and a driving current of the second element flows in a direction along the top surface of the epitaxial layer.

25. The method of manufacturing a semiconductor structure according to Claim 14, wherein The isolation layer continuously extends from the second region to a third region of the semiconductor structure, wherein the second region is located between the third region and the first region.

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