High-heat-dissipation plate-level packaging structure and manufacturing method thereof

Abstract

The invention discloses a high-heat-dissipation board-level packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging. The packaging structure comprises a metal layer, a chip, a plastic packaging layer, a rewiring layer, a passivation layer and an exposed terminal, the metal layer is patterned to form a metal structure, the chip is mounted on the metal structure, the plastic packaging layer wraps the chip and the metal structure and is provided with a window, the metal layer is arranged in a back-to-back manner, and the packaging structure forms a double-surface symmetrical structure through back-to-back bonding. The manufacturing method is based on the same inventive concept, two process paths are provided, and the core steps include metal structure preparation, chip mounting, plastic packaging, windowing, bearing plate removal, double-sided bonding, rewiring layer and terminal preparation, large plate splitting and cutting and the like. The heat dissipation effect is improved through the back exposed metal layer, warping is controlled through double-face symmetric bonding, the cost is reduced through the plastic packaging layer serving as a passivation layer, the structural strength is enhanced through the embedded metal layer, meanwhile, the production efficiency is improved through double-face operation, and the packaging structure can be widely applied to consumer electronic products, high-speed operation electronic products and professional electronic products.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a high heat dissipation plate level packaging structure and its manufacturing method. Background Technology

[0002] With the increasing demands for functional integration, large storage space, high reliability, and miniaturized packaging in mobile consumer electronics products such as mobile phones, computers, and digital cameras, high-density microelectronic assembly technology has become the mainstream technology direction for the next generation of electronic products. To adapt to this development trend, chips are evolving towards higher density, faster speed, smaller size, and lower cost. Fan-out (FO) packaging structures, as an important type of wafer-level packaging, are widely used in multi-chip packaging, ultra-thin packaging, and 3D system-in-package scenarios due to their advantages of a large number of input / output (I / O) ports and high integration flexibility (enabling multi-chip integration in both vertical and horizontal directions). The emergence of wafer-level fan-out packages (WLFOPs) has greatly increased the number of I / O ports in the package, meeting the development needs of multi-functional chips.

[0003] To further reduce production costs and improve production efficiency, manufacturers have introduced larger-sized panels as carrier boards, launching panel-level fanout package (PLFOP) technology. This technology enables larger-area overall packaging, significantly improving packaging efficiency and reducing costs, and has broad development prospects. For example, a 300x300mm panel... 2 A silicon wafer can produce approximately 600 ICs, while using board-level fan-out packaging technology in a 500x500mm package... 2 Up to 2600 ICs can be packaged on the panel, with a production volume of 300x300mm. 2 This is more than four times faster than wafer packaging, effectively enhancing the product's market competitiveness. Meanwhile, board-level fan-out packaging technology also offers advantages such as design flexibility, excellent electrothermal performance, diverse business models, and wide applicability.

[0004] However, with the continuous improvement of the integration of modern electronic chips and the continuous reduction of package feature size, chip power consumption has increased dramatically, and heat dissipation has become a key challenge in the development of board-level packaging technology. The heat dissipation performance of chip packaging is directly related to the operating performance, reliability, security, and user experience of electronic devices, and is an indispensable core element in new product design and packaging design. In addition, the embedding of products during PLP packaging can easily lead to uncontrollable warpage during the process. Traditional packaging steps are cumbersome, costly, and the packaging structure has insufficient strength, which also restricts the further promotion and application of board-level fan-out packaging technology.

[0005] Therefore, there is an urgent need for a packaging structure and preparation method that can solve the above-mentioned technical problems. Summary of the Invention

[0006] This invention provides a high heat dissipation plate-level packaging structure and its fabrication method, overcoming the problems existing in the prior art. The technical solution is as follows: On the one hand, a high heat dissipation plate level packaging structure is provided, including a metal layer 101, a chip 501, a molding layer 601, a redistribution layer 1001, a passivation layer 1002, and an exposed terminal 1003; The metal layer 101 is initially formed on the carrier plate 102, and after patterning, it forms a metal layer pattern 401. The chip 501 is mounted on the metal layer pattern 401. The molding compound 601 encapsulates the chip 501 and the metal layer pattern 401, and the molding compound 601 has a window 701 corresponding to the chip 501; The metal layer 101 is exposed, and the support plate 102 has been removed. The encapsulation structure forms a double-sided symmetrical structure through back-to-back bonding, and the stress of the upper and lower layers cancels each other out. The redistribution layer 1001, passivation layer 1002 and exposed terminal 1003 are sequentially formed on the surface of the molding layer 601.

[0007] Optionally, the material of the metal layer 101 includes one or more combinations of Cu, Al, Ag, and Au.

[0008] Optionally, the thickness of the metal layer 101 is 50um to 200um.

[0009] Optionally, the size range of the window 701 is 10um~200um, and the offset accuracy is controlled at ±5um.

[0010] Optionally, the back-to-back bonding method includes one of thermal bonding, hybrid bonding, and ionic bonding.

[0011] On the other hand, a method for manufacturing a high heat dissipation plate level package structure is provided, applicable to the aforementioned high heat dissipation plate level package structure, characterized in that it includes: Step S1: A metal layer 101 of 50~200um is formed on the support plate 102; Step S2, cover the metal layer 101 with a photosensitive adhesive film 201; Step S3: Form a photolithographic pattern of the metal layer by exposure and development; Step S4: Form the metal layer pattern 401 by wet etching and remove the photosensitive film 201; Step S5: Mount the chip 501 onto the metal layer pattern 401; Step S6: The chip 501 and the metal layer pattern 401 are encapsulated in the molding layer 601 using a molding process. Step S7: A window 701 is formed on the molding layer 601 corresponding to the chip 501 by laser or dry etching process; Step S8: Remove the support plate 102 on the back of the metal layer pattern 401; Step S9: The two products processed in step 8 are bonded together back to back using a bonding method. Step S10: A redistribution layer 1001, a passivation layer 1002, and an exposed terminal 1003 are sequentially formed on the molding compound 601. Step S11: Separate the two connected large boards by debonding. Step S12: Cut the large board into individual packages.

[0012] Optionally, the chip 501 in step S5 can be mounted using one of the following methods: conductive silver paste mounting, hybrid bonding mounting, or thermal bonding mounting.

[0013] Optionally, the molding layer 601 described in step S6 also serves as the first passivation layer of the encapsulation structure.

[0014] Optionally, the packaging structure can be fabricated using a double-sided substrate encapsulation process.

[0015] Optionally, the metal layer 101 in step S1 can be formed by electroplating or lamination.

[0016] Compared with the prior art, the present invention has the following significant advantages.

[0017] This invention discloses a high-heat-dissipation-plate level packaging structure and its fabrication method. The packaging structure includes a metal layer, a chip, a molding compound, a redistribution layer, a passivation layer, and exposed terminals. The metal layer is patterned to form a metal structure, the chip is mounted on the metal structure, the molding compound wraps the chip and the metal structure and has a window, and the metal layer is exposed on the back. The packaging structure is formed by back-to-back bonding to form a double-sided symmetrical structure. The fabrication method is based on the same inventive concept and provides two process paths. The core steps are metal structure preparation, chip mounting, molding, windowing, carrier board removal, double-sided bonding, redistribution layer and terminal preparation, board splitting and cutting, etc. This application improves heat dissipation by exposing the metal layer, controls warpage by double-sided symmetrical bonding, reduces costs by using the molding compound as a passivation layer, enhances structural strength by embedding the metal layer, and improves production efficiency by using double-sided operation. It can be widely used in consumer, high-speed computing, and professional electronic products. Attached Figure Description

[0018] Figure 1 The schematic diagram of the structure corresponding to process path S1 shows the carrier plate 102 and the metal layer 101 formed thereon by electroplating or lamination. Figure 2 The schematic diagram corresponding to process path S2 shows the photosensitive film 201 covering the metal layer 101; Figure 3 This is a schematic diagram of the structure corresponding to process path S3, showing the photolithographic pattern of the metal layer formed by ultraviolet light exposure and development. Figure 4 The schematic diagram of the structure corresponding to process path S4 shows the metal layer pattern 401 formed by wet etching. Figure 5 The schematic diagram corresponding to process path S5 shows the chip 501 mounted on the metal layer pattern 401. Figure 6 The schematic diagram corresponding to process path S6 shows the molding layer 601 that encapsulates the chip 501 and the metal layer pattern 401. Figure 7 The schematic diagram of the structure corresponding to process path S7 shows the window 701 on the molding layer 601 that corresponds to the chip 501. Figure 8 The diagram below shows the structure corresponding to process path S8, illustrating the structure after removing the support plate 102. Figure 9 The diagram shows the structure corresponding to process path S9, illustrating the double-sheet structure after "back-to-back" bonding. Figure 10 The diagram shows the redistribution layer 1001, passivation layer 1002 and exposed terminal 1003 formed sequentially in process path S10. Figure 11 This is a structural diagram corresponding to process path S11, showing the two large boards after debonding. Figure 12 The diagram shows the structure corresponding to process path S12, illustrating the cut single package. Figure 13 The schematic diagram of the structure corresponding to process path S1 shows the carrier plate 102 and the photosensitive adhesive film 101 formed thereon by coating or pressing. Figure 14 This is a schematic diagram of the structure corresponding to process path S2, showing the metal layer photolithography pattern 201 formed by white light + development; Figure 15 The schematic diagram of the structure corresponding to process path S3 shows the metal line 301 formed by electroplating. Figure 16 The schematic diagram of the structure corresponding to process path S4 shows the metal circuit 301 after the photosensitive film is removed. Figure 17 The schematic diagram corresponding to process path S5 shows the chip 501 mounted on the metal line 301. Figure 18 The schematic diagram of process path S6 shows the molding layer 601 that encapsulates chip 501 and metal lines 301. Figure 19 The schematic diagram of the structure corresponding to process path S7 shows the window 701 on the molding layer 601 that corresponds to the chip 501. Figure 20 The diagram shows the structure after removing the support plate 102, corresponding to process path S8. Figure 21 The diagram shows the structure corresponding to process path S9, illustrating the double-sheet structure after "back-to-back" bonding. Figure 22 The schematic diagram of the structure corresponding to process path S10 shows the redistribution layer 1001, passivation layer 1002 and exposed terminal 1003 formed sequentially. Figure 23 This is a structural diagram corresponding to process path S11, showing the two large boards after debonding. Figure 24 The diagram below shows the structure corresponding to process path S12, illustrating the cut single package. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0020] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0021] Example 1 - Structure correspond Figures 1 to 24 The high heat dissipation plate level package structure includes a metal layer (101), a chip (501), a molding layer 601, a redistribution layer 1001, a passivation layer 1002, and exposed terminals 1003. The specific implementation details are as follows.

[0022] In the interaction between the metal layer and the carrier plate, a metal layer 101 is first formed on the carrier plate 102. After patterning, a metal layer pattern 401 is obtained. Subsequently, the carrier plate 102 is removed through a process, leaving only the metal layer-related structures as the heat dissipation and support core. Figure 1 The diagram shows the initial structure of the support plate 102 and the metal layer 101. Figure 4 The graphical representation of the metal layer pattern 401. Figure 8 This describes the structural state after removing the carrier plate; for another process path, the metal structure is formed by photolithography of a photosensitive film followed by electroplating, such as... Figure 13 The diagram shows the initial structure of the carrier plate 102 and the photosensitive film 101. Figure 15 Metal circuit 301 formed by electroplating, Figure 20 This shows the structural state after the support plate has been removed.

[0023] In chip mounting and encapsulation, chip 501 is precisely mounted onto the metal layer pattern 401 or metal circuit 301. The encapsulation process completely encapsulates chip 501 and the metal structure using a molding layer 601. A window 701 is machined on the molding layer 601 at the position corresponding to chip 501 to provide a channel for subsequent electrical connections. For example... Figure 5 , Figure 17 The structures after chip mounting are completed under different process paths. Figure 6 , Figure 18 This is the state of the package after it has been sealed in plastic. Figure 7 , Figure 19 This is the structure after the 701 window is formed.

[0024] In a double-sided symmetrical structure design, two semi-finished products with the load-bearing plates removed are connected back-to-back via bonding to form a double-sided symmetrical structure. Warpage is controlled by utilizing the principle of stress cancellation between the upper and lower layers. For example... Figure 9 , Figure 21 The image shows a bilayer symmetrical structure bonded under different process paths.

[0025] In the surface structure, a redistribution layer 1001, a passivation layer 1002, and exposed terminals 1003 are sequentially fabricated on the surface of the molding compound 601 to achieve effective output of chip electrical signals. For example... Figure 10 , Figure 22 The image shows a complete package with a surface structure under different process paths.

[0026] The final product is formed by debonding and disassembling the large board, and then cutting it into individual packages, such as... Figure 11 , Figure 23 This is the structure after the large board is disassembled. Figure 12 , Figure 24 This is a single packaged unit after cutting.

[0027] As can be seen, this core structure solves key problems in board-level packaging through the core design of "exposed metal layer + double-sided symmetrical bonding". First, the exposed metal layer replaces the traditional epoxy resin as the heat dissipation medium. The heat source of the chip is conducted to the metal layer through silicon and then quickly diffuses to the environment, which greatly improves the heat dissipation efficiency. Second, the double-sided symmetrical structure offsets the stress between the upper and lower layers, controls the warpage of the board in the process from the structural design level, and provides a guarantee for the stability of subsequent packaging steps.

[0028] Example 2 -- Structure Based on Example 1, continue to correspond Figures 1 to 24 The marking provides further encapsulation structure features, and the specific implementation details are as follows.

[0029] Regarding the selection of metal layer materials, metal layer 101 or metal circuit 301 can be made of one or more combinations of Cu, Al, Ag, and Au. The selection can be flexible based on product cost budget and heat dissipation performance requirements. For example, high-end products can use Ag or Au materials to improve heat dissipation efficiency, while conventional products can use Cu or Al to balance cost and performance.

[0030] Regarding the thickness of the metal layer, the thickness of the metal layer 101 or the metal line 301 is strictly controlled within the range of 50um to 200um. During implementation, it can be adjusted according to the overall thickness requirements of the package and the heat dissipation requirements. For example, a thickness of 150um to 200um can be selected for scenarios with high heat dissipation requirements, and a thickness of 50um to 100um can be selected for scenarios with high requirements for thinness.

[0031] Regarding windowing accuracy control, the size of the 701 window is set to 10um~200um, and the offset accuracy is controlled within ±5um. In practice, the accuracy can be ensured by laser positioning or dry etching positioning technology to avoid poor contact between the subsequent redistribution layer and the chip due to windowing offset. The windowing accuracy control standards are consistent under the two process paths.

[0032] Regarding the choice of bonding method, back-to-back bonding can adopt thermal bonding, hybrid bonding or ionic bonding. The choice should be made according to the production equipment conditions. Thermal bonding is suitable for mass production scenarios, hybrid bonding is suitable for high-precision packaging requirements, and ionic bonding is suitable for scenarios with high requirements for bonding strength. Both process paths can use the above bonding methods.

[0033] Therefore, in this embodiment, the material and thickness design of the metal layer, combined with the exposed structure, significantly improves heat dissipation efficiency compared to traditional packaging, meeting the heat dissipation requirements of high-power chips. The combination of the double-sided symmetrical structure and the appropriate bonding method effectively offsets process stress, greatly reduces the warpage of the large board, and improves production yield. Strict control over the window size and precision ensures the connection stability between the redistribution layer and the chip, reducing signal transmission loss. The diverse selection of materials and bonding methods allows the packaging structure to adapt to the packaging needs of different types of electronic products, resulting in wider compatibility.

[0034] Example 3 - Preparation Method The manufacturing method of this invention is based on the same inventive concept and provides two process implementation paths (hereinafter referred to as "process path one" and "process path two"). The core difference lies only in the initial preparation stage of the metal structure (metal layer / metal circuit). The design ideas, technical principles and technical effects of the other key steps (chip mounting, molding, windowing, bonding, surface structure preparation, etc.) are the same. They all revolve around the core objectives of "high heat dissipation, warpage control, cost reduction and structural strength". Through a unified core design and differentiated process adaptation, it meets the requirements of different production equipment conditions and cost.

[0035] The specific steps and implementation details for process route one are as follows.

[0036] Metal layer fabrication: To achieve a balance between high heat dissipation and structural strength, while also ensuring the thinness of the package, a metal layer 101 with a thickness of 50µm to 200µm is formed on the carrier plate 102 by electroplating or lamination. Electroplating is suitable for high-precision thickness control applications, while lamination is suitable for mass production applications, such as... Figure 1 The image shows the structure after the metal layer has been fabricated.

[0037] Photosensitive film coating: High-temperature resistant photosensitive film 201 is selected and uniformly coated onto the surface of metal layer 101 through lamination, ensuring that the film is free of bubbles and wrinkles, thus guaranteeing the accuracy of subsequent photolithography. Figure 2 As shown.

[0038] Photolithography pattern formation: To ensure clear edges and precise dimensions of the photolithographic pattern, laying the foundation for subsequent metal layer pattern formation, ultraviolet light exposure is used, with exposure energy selectable at 100-150 mJ / cm². 2 Within the specified range, after development, a photomask consistent with the preset metal layer pattern is obtained, such as... Figure 3 As shown.

[0039] Metal layer pattern preparation: Wet etching is performed using a sulfuric acid-hydrogen peroxide etchant system. The etching time can be adjusted according to the metal layer thickness. After etching, the remaining adhesive film is removed using a stripping solution to obtain a clean and well-formed metal layer pattern 401. Figure 4 As shown.

[0040] Chip mounting: Chip 501 is mounted using conductive silver paste, hybrid bonding, or thermal bonding. The mounting method is selected based on the chip's pin type; for example, thermal bonding is used for chips with metal pins, while conductive silver paste is used for chips with non-metal pins. This ensures a stable connection between the chip and the metal layer pattern 401. Figure 5 As shown.

[0041] Molding Process: To ensure the molding layer 601 fully encapsulates the chip and metal structure, while also providing insulation and protection as the first passivation layer, and to reduce packaging steps and costs, epoxy resin molding compound is selected. Molding is performed using a transfer molding process. The molding temperature can be set between 175-185℃, and the pressure can be 10-15MPa. Figure 6 As shown.

[0042] Window Formation: To accurately reserve electrical connection channels and avoid misalignment leading to poor contact, windows 701 are formed on the molding layer 601 using laser etching or dry etching processes. The process is selected according to the window size; small windows (10µm~50µm) can be formed using laser etching, while large windows (50µm~200µm) can be formed using dry etching. Figure 7 As shown.

[0043] Carrier plate removal: Carrier plate 102 is removed by a combination of mechanical peeling and chemical cleaning, ensuring no residue remains on the back of the metal layer and guaranteeing unobstructed heat dissipation channels. Figure 8 As shown.

[0044] Double-sided bonding: To effectively counteract the stress between the upper and lower layers and control the warpage of the large board, two semi-finished products are bonded back-to-back using thermal bonding, hybrid bonding, or ion bonding methods. The bonding temperature and pressure can be adjusted according to the bonding method. For example, thermal bonding can use a temperature of 220-240℃ and a pressure of 8-12MPa to ensure a stable bond. Figure 9 As shown.

[0045] Redundancy layer and terminal fabrication: A copper redundancy layer 1001, a polyimide passivation layer 1002, and tin-lead alloy exposed terminals 1003 are fabricated using a sputtering and electroplating process. These are sequentially formed to achieve the electrical signal output function. Figure 10 As shown.

[0046] Large board separation: To avoid damage to the package structure during separation and ensure product yield, the two large boards are separated by mechanical debonding. The separation force can be controlled within the range of 50-80N. Figure 11 As shown.

[0047] Single package cutting: To ensure a smooth, chip-free cut surface and guarantee the dimensional accuracy of each package, a diamond wheel cutting process is used. The cutting speed can be selected from 100-150mm / s to divide the large board into individual packages, such as... Figure 12 As shown.

[0048] Process route two is another adapted form of the core process of this route. The specific steps and implementation details are as follows.

[0049] Photosensitive film preparation: To ensure a tight bond between the photosensitive film and the substrate, free from bubbles and misalignment, and to guarantee the accuracy of subsequent photolithography, a photosensitive film 101 is formed on the substrate 102 by coating or lamination. The photosensitive film is made of photosensitive adhesive or photosensitive film material. The lamination temperature can be set within the range of 80-100℃, and the pressure can be 3-5 MPa. Figure 13 As shown.

[0050] Photolithography pattern formation: To meet the low-cost mass production requirements of white light exposure while ensuring precise pattern formation, a white light exposure process is adopted, with exposure energy selectable from 80-120 mJ / cm². 2 The area is defined, and after development, a metal layer photolithographic pattern 201 is obtained, as shown below. Figure 14 As shown.

[0051] Metal circuit fabrication: To ensure uniform thickness, good conductivity, and adequate structural strength of the metal circuit, metal circuit 301 is formed by electroplating on the photolithographic pattern using an acidic copper sulfate electroplating solution. The electroplating current density can be controlled within 2-5 A / dm³. 2 The range is adjusted according to the required circuit thickness, such as... Figure 15 As shown.

[0052] Photosensitive adhesive film removal: To thoroughly remove any remaining photosensitive adhesive film without damaging the metal circuit surface, an alkaline stripping solution is used. The stripping temperature can be set at 50-60℃, and the time can be selected as 5-10 minutes. After removal, the surface of the 301 metal circuit is clean and free of residue. Figure 16 As shown.

[0053] Chip mounting: Using the same mounting method as process path one (conductive silver paste, hybrid bonding, or thermal bonding), chip 501 is mounted on metal circuit 301, ensuring a secure connection. Figure 17 As shown.

[0054] Molding process: To achieve integrated encapsulation protection and passivation layer functions, and to reduce packaging steps and lower costs, the same molding compound and process parameter range as in process path one are selected to complete the encapsulation of the chip and metal circuitry. The molding layer 601 also serves as the first passivation layer. Figure 18 As shown.

[0055] Window Formation: To accurately reserve electrical connection channels and ensure the reliability of subsequent rewiring layers and chip connections, the same etching process and precision control standards as process path one are used to form window 701, as shown below. Figure 19 As shown.

[0056] Carrier plate removal: Carrier plate 102 is removed using chemical etching. The etching solution only acts on the carrier plate material and does not damage the metal circuitry or molding compound, ensuring unobstructed heat dissipation channels in the metal layer. Figure 20 As shown.

[0057] Double-sided bonding: To counteract process stress and control board warpage, the same bonding method and process parameter range as in process path one are used to complete back-to-back bonding of the two sheets, ensuring a stable bond. Figure 21 As shown.

[0058] Redundancy layer and terminal fabrication: A chemical plating + electroplating process is used to prepare the redundancy layer 1001, the silicon oxide passivation layer 1002, and the pure tin exposed terminal 1003. Figure 22 As shown.

[0059] Large-plate separation: The dual large-plate system is separated using a chemical debonding method, leaving no adhesive residue in the package after separation. Figure 23 As shown.

[0060] Single-package cutting: To balance cutting efficiency and package edge quality, and ensure precise dimensions of individual products, laser cutting is employed. Cutting speeds can be selected from 200-300 mm / s. Figure 24 As shown.

[0061] Therefore, it can be seen that in the preparation method provided in this application embodiment, both process paths adopt the double-sided operation of substrate packaging. Compared with the traditional single-sided operation, the production efficiency is greatly improved, the output per unit time is increased, and the unit product cost is further reduced. The two paths provide differentiated process options. There are multiple feasible methods for steps such as metal structure formation, photolithography, mounting, and bonding, which can be adapted to different production equipment and cost requirements, thus expanding the scope of process applicability. The molding layer also serves as a passivation layer, reducing packaging steps. Double-sided operation improves efficiency, and mature etching, electroplating and other processes reduce production energy consumption, thereby reducing packaging costs in multiple dimensions. The process parameters of each step (such as metal layer thickness and windowing accuracy) are strictly controlled. Both process paths can produce packaging products that meet the requirements, with high product consistency and stable yield.

[0062] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0063] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. The above descriptions are merely optional embodiments of this application and are not intended to limit the application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A high heat dissipation board level package structure, characterized in that, The package structure comprises a metal layer (101), a chip (501), a plastic sealing layer (601), a rewiring layer (1001), a passivation layer (1002) and exposed terminals (1003); The metal layer (101) is initially formed on a carrier plate (102), and a metal layer pattern (401) is formed after a patterning process. The chip (501) is attached to the metal layer pattern (401); The plastic sealing layer (601) wraps the chip (501) and the metal layer pattern (401), and the plastic sealing layer (601) is provided with a window (701) corresponding to the chip (501); The metal layer (101) is provided on the back of the carrier plate (102) which is removed after processing; The package structure is formed by back-to-back bonding to form a double-sided symmetric structure, and the stress of the upper and lower layers is offset. The rewiring layer (1001), the passivation layer (1002) and the exposed terminals (1003) are sequentially formed on the surface of the plastic sealing layer (601).

2. The high heat dissipation board-level package structure according to claim 1, wherein, The material of the metal layer (101) comprises one or more combinations of Cu, Al, Ag and Au.

3. The high heat dissipation board-level package structure according to claim 1, wherein, The thickness of the metal layer (101) is 50-200um.

4. The high heat dissipation board-level package structure of claim 1, wherein, The size of the window (701) ranges from 10um to 200um, and the offset accuracy is controlled to be ±5um.

5. The high heat dissipation board-level package structure according to claim 1, wherein, The back-to-back bonding method comprises one of thermal bonding, hybrid bonding and ion bonding.

6. A method for manufacturing a high heat dissipating package structure, which is suitable for the high heat dissipating package structure as claimed in any one of claims 1 to 5, wherein The package structure comprises: Step S1: forming a metal layer (101) with a thickness of 50-200um on a carrier plate (102); Step S2: covering a layer of photosensitive adhesive film (201) on the metal layer (101); Step S3: forming a metal layer photoetching pattern by exposure and development; Step S4: forming a metal layer pattern (401) by wet etching, and removing the photosensitive adhesive film (201); Step S5: attaching a chip (501) to the metal layer pattern (401); Step S6: wrapping the chip (501) and the metal layer pattern (401) in a plastic sealing layer (601) by a plastic sealing process; Step S7: forming a window (701) on the plastic sealing layer (601) corresponding to the chip (501) by laser or dry etching process; Step S8: removing the carrier plate (102) on the back of the metal layer pattern (401); Step S9: connecting two products processed in step (8) back-to-back by bonding; Step S10: sequentially forming a rewiring layer (1001), a passivation layer (1002) and exposed terminals (1003) on the plastic sealing layer (601); Step S11: splitting the two connected large plates by debonding; Step S12: cutting the large plate into single packages.

7. The method of claim 6, wherein the method further comprises: The attachment method of the chip (501) in step S5 comprises one of conductive silver paste attachment, hybrid bonding attachment and thermal bonding attachment.

8. The method of claim 6, wherein the method further comprises: The plastic sealing layer (601) in step S6 simultaneously serves as the first passivation layer of the package structure.

9. The method of claim 6, wherein the method further comprises: The preparation of the package structure is completed by a double-sided operation method of the substrate packaging.

10. The method of claim 6, wherein the method further comprises: The formation method of the metal layer (101) in step S1 is electroplating or pressing.

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