Semiconductor device failure analysis method
By selecting input ports in the failure region of semiconductor devices for signal testing and step-by-step dissection, the problem of difficulty in locating the failure location of complex packaging structures in existing technologies is solved, and rapid and accurate failure analysis is achieved.
Patent Information
- Application Number
- CN202511672292.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-03-20
AI Technical Summary
Existing technologies struggle to quickly and accurately locate the failure sites of semiconductor devices with complex packaging structures, especially in flip-chip packages, wafer-level fan-out packages, and multilayer stacked packages.
By selecting the input port of the failure area of the semiconductor device for signal testing, abnormal signal images are obtained. The device is dissected layer by layer until the end of the abnormal signal image coincides with the peak position. The failure location is then accurately located using methods such as grinding, etching, cutting or ion polishing.
It enables rapid and accurate location of failure sites in semiconductor devices, avoiding over- or under-analysis, and improving the efficiency and accuracy of failure analysis.
Smart Images
Figure CN121703612A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and in particular to a method for analyzing the failure of semiconductor devices. Background Technology
[0002] Semiconductor devices can fail due to various reasons during use, even exhibiting anomalies such as open circuits and short circuits. Failure analysis is a crucial method for locating these anomalies. By analyzing the causes of semiconductor device failures, determining the failure mechanisms, and identifying the root causes, it plays a vital role in improving the reliability and quality of semiconductor products.
[0003] However, with the rapid development of chip packaging manufacturing technology, the integration level of chip packaging is gradually increasing, leading to the rapid development of flip-chip packaging, wafer-level fan-out packaging, and multilayer stacked packaging. These semiconductor devices have complex packaging structures and dense interconnections, making it difficult for conventional failure analysis methods, such as hotspot testing and IV testing, to accurately locate the failure sites. This increases the difficulty of failure analysis and hinders the rapid development of the technology. Therefore, there is an urgent need for a failure analysis method that can quickly and accurately identify the specific failure location of semiconductors to solve this problem. Summary of the Invention
[0004] Based on this, the purpose of the present invention is to provide a semiconductor device failure analysis method, which has the advantages of accurately locating the failure position and facilitating rapid analysis.
[0005] A semiconductor device failure analysis method for detecting the physical failure location of a semiconductor device under test includes the following steps: Step S1: Select at least one failure port in the failure region of the semiconductor device under test as an input port, and perform signal testing on the semiconductor device under test through the input port to obtain an abnormal signal image of the semiconductor device under test. Step S2: Compare the abnormal signal image with the feedback signal image of a qualified semiconductor device test to obtain the peak position of the abnormal signal image; Step S3: Starting from the end of the semiconductor device under test away from the input port, the semiconductor device under test is dissected layer by layer, so that the end of the semiconductor device under test away from the input port moves closer to the physical failure location; Step S4 involves dissecting the semiconductor device under test until the end of the abnormal signal image coincides with the peak position of the abnormal signal image, thereby locating the physical failure location of the semiconductor device under test.
[0006] The semiconductor device failure analysis method of the present invention dissects the semiconductor device under test layer by layer from the end away from the input port. By using abnormal signal images, the dissection is stopped when the end of the abnormal signal image coincides with the peak position of the abnormal signal image. This method can precisely control the dissection progress, avoid over-dissection or under-dissection, and thus quickly and accurately locate the specific location of the semiconductor device failure.
[0007] Further, step S4 specifically includes the following steps: during the dissection, observe the abnormal signal image, and observe that the end of the abnormal signal image gradually approaches the peak position of the abnormal signal image; continue the dissection until the end of the abnormal signal image coincides with the peak position of the abnormal signal image, and find the physical failure location of the semiconductor device under test.
[0008] Further, step S2 specifically includes the following steps: comparing the abnormal signal image with the qualified semiconductor device test feedback signal image to find the deviation position between the abnormal signal image and the qualified semiconductor device test feedback signal image; finding the peak value of the abnormal signal image at the deviation position, i.e., the peak position of the abnormal signal image.
[0009] Furthermore, the dissection method includes, but is not limited to, grinding, etching, cutting, ion grinding, and FIB.
[0010] Furthermore, the signal at the input port of the semiconductor device under test is located at the beginning of the abnormal signal image; the signal at the actual physical failure location of the semiconductor device under test is located at the peak position of the abnormal signal image; and the signal at the end of the semiconductor device under test furthest from the input port is located at the end of the abnormal signal image.
[0011] Furthermore, step S1 specifically includes the following steps: Step S11: Identify the failure region and region port of the semiconductor device under test, and select at least one failure port in the failure region as the input port. Step S12 connects the test device to the input port signal, applies a test signal to the input port through the test device, and generates an abnormal feedback signal. Step S13 receives the abnormal feedback signal through the test equipment and processes the abnormal feedback signal to obtain an abnormal signal image of the semiconductor device under test.
[0012] Furthermore, the failure region includes at least one failure port; the failure region includes, but is not limited to, one or more of the following: open circuit region, leakage current increase region, and impedance increase region.
[0013] Furthermore, the failure port includes, but is not limited to, one or more of the following: open circuit test failure port, leakage current increase failure port, and impedance increase failure port.
[0014] Furthermore, the test signal includes, but is not limited to, one or more of current signals, voltage signals, impedance signals, and current density signals; the test equipment includes, but is not limited to, TDR equipment and pulse current equipment.
[0015] Furthermore, the testing equipment also includes an oscilloscope for displaying images of abnormal signals.
[0016] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a semiconductor device failure analysis method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of an inverted solder package according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the step-by-step layer-by-layer dissection of the semiconductor device under test according to an embodiment of the present invention; Figure 4 This is an impedance-time curve showing the difference between the abnormal feedback signal and the test feedback signal of a qualified semiconductor device in an embodiment of the present invention. Detailed Implementation
[0018] When performing failure analysis on failed semiconductor devices, it is necessary to identify the specific location of the failure. In existing technologies, failure locations are typically located and analyzed using testing methods such as hot spot testing and IV testing. Hot spot testing involves energizing the semiconductor device under test and utilizing the time difference between thermal radiation and conduction at the fault point to detect the failure. IV testing measures the current and voltage values under different voltages and currents, plotting the relationship between current and voltage; this test can quickly reveal the electrical failure mode of the device.
[0019] However, as the integration level of chip packaging gradually increases, the ability of existing testing methods such as hot spot testing to locate failure sites is gradually decreasing. Taking hot spot testing as an example, when dealing with semiconductor devices with complex packaging structures and tight interconnect structures, such as flip-chip packages, wafer-level fan-out packages, and multilayer stacked packages, the thermal radiation is blocked by the complex packaging structure, which increases the testing difficulty and makes it difficult to locate the failure site of the semiconductor device.
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] In the description of this invention, it should be noted that the terms "vertical direction," "up," "down," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0022] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to thermally conductive connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0023] Example 1 Please see Figure 1 This invention provides a method for analyzing semiconductor device failures.
[0024] The semiconductor device failure analysis method of this invention is used to locate the failure location of the semiconductor device under test; specifically, it includes the following steps: Step S1: Select at least one failure port in the failure region of the semiconductor device under test as an input port, and perform signal testing on the semiconductor device under test through the input port to obtain the abnormal signal image of the semiconductor device under test.
[0025] Step S2: Compare the abnormal signal image with the feedback signal image of the qualified semiconductor device test to obtain the peak position of the abnormal signal image.
[0026] Step S3: Starting from the end of the semiconductor device under test away from the input port, dissect the semiconductor device under test layer by layer, so that the end of the semiconductor device under test away from the input port moves closer to the physical failure location.
[0027] Step S4: During the dissection, observe the abnormal signal image and observe that the end of the abnormal signal image gradually approaches the peak of the abnormal signal image; continue the dissection until the end of the abnormal signal image coincides with the peak of the abnormal signal image, and find the physical failure location of the semiconductor device under test.
[0028] Further, step S2 specifically includes: comparing the abnormal signal image with the qualified semiconductor device test feedback signal image to find the deviation position between the abnormal signal image and the qualified semiconductor device test feedback signal image; and finding the peak value of the abnormal signal image at the deviation position, i.e., the peak position of the abnormal signal image.
[0029] Furthermore, the signal at the input port of the semiconductor device under test (DUT) is located at the beginning of the abnormal signal image. The signal at the actual physical failure location of the DUT is located at the peak of the abnormal signal image. The signal at the end of the DUT furthest from the input port is located at the end of the abnormal signal image.
[0030] Furthermore, in step S3, when the semiconductor device under test (DUT) is dissected layer by layer from the end furthest from the input port, the length of the DUT changes, with the end furthest from the input port moving closer to it. Since the signal at the input port of the DUT appears as the beginning of the abnormal signal image, and the signal at the end furthest from the input port appears as the end, the layered dissection of the DUT is represented by a "step-by-step truncation" of the abnormal signal image, resulting in a shortened length. Furthermore, in step S3, it can be observed that the end of the abnormal signal image moves closer to the peak value.
[0031] In some embodiments, the dissection method includes, but is not limited to, grinding, etching, cutting, ion milling, and FIB.
[0032] Therefore, in step S4, when the end of the abnormal signal image coincides with the peak position of the abnormal signal image, it indicates that the semiconductor device under test has been gradually dissected layer by layer until the end of the semiconductor device under test away from the input port coincides with the actual physical failure position, so that the physical failure position of the semiconductor device under test is exposed and can be directly observed and further analyzed and studied.
[0033] In some embodiments, the dissection method includes, but is not limited to, grinding, etching, cutting, ion milling, and FIB.
[0034] Furthermore, step S1 specifically includes the following steps: S11: Identify the failure region and region port of the semiconductor device under test, and select at least one failure port in the failure region as the input port.
[0035] In step S11, the failure region includes at least one failure port. In some embodiments, the failure region includes, but is not limited to, one or more of an open-circuit region, a leakage current increase region, and an impedance increase region. Further, the failure port is a semiconductor device test failure port; the failure port includes, but is not limited to, one or more of an open-circuit test failure port, a leakage current increase failure port, and an impedance increase failure port.
[0036] In some embodiments, step S11 further includes identifying the failure mode of the semiconductor device under test.
[0037] Step S12: Connect the test device to the input port signal, apply a test signal to the input port through the test device, and then generate an abnormal feedback signal.
[0038] In some embodiments, the test signal includes, but is not limited to, one or more of current signals, voltage signals, impedance signals, and current density signals; the test equipment includes, but is not limited to, TDR equipment and pulse current equipment.
[0039] Step S13: Receive the abnormal feedback signal through the test equipment, process the abnormal feedback signal, and obtain the abnormal signal image of the semiconductor device under test.
[0040] Furthermore, the abnormal feedback signal is a signal that deviates from the test feedback signal image of the semiconductor device under test and the qualified semiconductor device. In some embodiments, the test equipment also includes an oscilloscope for displaying the abnormal signal image.
[0041] Example 2 Please see Figures 2 to 4 In this embodiment, a flip-chip package is used as the semiconductor device under test, and the semiconductor device failure analysis method of this invention is used to perform failure analysis on the flip-chip package. The flip-chip package includes a chip body 1, a chip UBM lead 2, a substrate 3, and a plurality of BGA solder balls 4. The chip body 1 is connected to the substrate 3 through the chip UBM lead 2, and the BGA solder balls 4 are disposed on the opposite side of the substrate 3 opposite to the chip body 1. The chip body 1 is interconnected with the outside world through the BGA solder balls 4 as ports to realize the chip function.
[0042] Step S11: Confirm the failure mode of the inverted solder package by using an ATE tester or IV curve test, identify the failure area and specific failure port of the inverted solder package, and select at least one failure port in the failure area as input port 4a.
[0043] In this embodiment, the failure mode of the flip-chip package is confirmed by IV testing. By performing IV testing on each port separately and observing the difference between the obtained IV curve and the IV curve of the normal port, the failure mode is confirmed. In this embodiment, the failure mode is the increase of VDD to VSS impedance, and the failure port is the VDD lead-out port.
[0044] Step S12: Connect the test device to the input port 4a signal, apply a test signal to the input port 4a through the test device, and then generate an abnormal feedback signal.
[0045] In this embodiment, the testing equipment is a TDR testing machine 5. The input port 4a is soldered to the TDR testing machine 5 via copper wire, and the soldering method is brazing. The TDR testing machine 5 applies a current signal to the input port 4a, thereby generating an abnormal feedback signal.
[0046] Step S13: The TDR test instrument 5 receives and processes the abnormal feedback signal, thereby obtaining the abnormal signal image of the semiconductor device under test and displaying it on the oscilloscope.
[0047] Step S2: Compare the deviation of the abnormal signal image with the test feedback signal image of the qualified semiconductor device to determine the peak position of the abnormal signal image of the current signal. This position is the corresponding position of the failure position of the increased VDD to VSS impedance of the flip-chip package in the abnormal signal image.
[0048] Please see Figure 4 , Figure 4 Curve 6a represents the abnormal signal image of the abnormal feedback signal, and curve 6b represents the image information of the feedback signal image of the qualified semiconductor device test.
[0049] Step S3: Fix the inverted solder package and grind the inverted solder package layer by layer from the opposite side 4b of the input port 4a, so that the opposite end of the inverted solder package at the input port 4a moves closer to the failure position where the VDD to VSS impedance increases.
[0050] Step S4: During the grinding process, observe the abnormal signal image of the abnormal feedback signal. Observe that the end of the abnormal signal image gradually approaches the peak of the abnormal signal image. Continue grinding until the end of the abnormal signal image of the abnormal feedback signal and the peak of the abnormal signal image coincide. Locate the failure location where the VDD to VSS impedance of the flip-chip package increases.
[0051] Since the peak of the abnormal signal image is the signal at the physical failure location of the semiconductor device under test, when the end of the abnormal signal image coincides with the peak of the abnormal signal image, it indicates that the semiconductor device under test has been gradually dissected layer by layer until the end of the semiconductor device under test that is far from the input port coincides with the actual physical failure location. At this time, the physical failure location is exposed, which is convenient for subsequent analysis and processing.
[0052] The semiconductor device failure analysis method of the present invention can accurately locate the failure location of the semiconductor device by monitoring abnormal signal images through testing equipment and dissecting the failed sample layer by layer to the peak position of the abnormal signal image. The semiconductor device failure analysis method of the present invention effectively shortens the failure analysis time, helps testers quickly locate the failure location of semiconductor devices, and is beneficial for testers to conduct subsequent analysis and improvement of semiconductor device products.
[0053] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and the present invention also intends to include these modifications and variations.
Claims
1. A semiconductor device failure analysis method for detecting the physical failure location of a semiconductor device under test, characterized in that, Includes the following steps: Step S1: Select at least one failure port in the failure region of the semiconductor device under test as an input port, and perform signal testing on the semiconductor device under test through the input port to obtain an abnormal signal image of the semiconductor device under test. Step S2: Compare the abnormal signal image with the feedback signal image of a qualified semiconductor device test to obtain the peak position of the abnormal signal image; Step S3: The semiconductor device under test is dissected layer by layer from the end away from the input port, so that the end away from the input port moves closer to the physical failure location. Step S4 involves dissecting the semiconductor device under test until the end of the abnormal signal image coincides with the peak position of the abnormal signal image, thereby locating the physical failure location of the semiconductor device under test.
2. The semiconductor device failure analysis method according to claim 1, characterized in that, Step S4 specifically includes the following steps: during the dissection process, observe the abnormal signal image and observe that the end of the abnormal signal image gradually approaches the peak position of the abnormal signal image; continue the dissection until the end of the abnormal signal image coincides with the peak position of the abnormal signal image, and find the physical failure location of the semiconductor device under test.
3. The semiconductor device failure analysis method according to claim 1, characterized in that, Step S2 specifically includes the following steps: comparing the abnormal signal image with the qualified semiconductor device test feedback signal image to find the deviation position between the abnormal signal image and the qualified semiconductor device test feedback signal image; finding the peak value of the abnormal signal image at the deviation position, i.e., the peak position of the abnormal signal image.
4. The semiconductor device failure analysis method according to claim 3, characterized in that: The dissection method includes, but is not limited to, grinding, etching, cutting, ion grinding, and FIB (fiber optic osmosis).
5. The semiconductor device failure analysis method according to claim 3, characterized in that: The signal at the input port of the semiconductor device under test is located at the beginning of the abnormal signal image; the signal at the actual physical failure location of the semiconductor device under test is located at the peak position of the abnormal signal image; and the signal at the end of the semiconductor device under test furthest from the input port is located at the end of the abnormal signal image.
6. The semiconductor device failure analysis method according to claim 1, characterized in that, Step S1 specifically includes the following steps: Step S11: Identify the failure region and region port of the semiconductor device under test, and select at least one failure port in the failure region as the input port. Step S12 connects the test device to the input port signal, applies a test signal to the input port through the test device, and generates an abnormal feedback signal. Step S13 receives the abnormal feedback signal through the test equipment and processes the abnormal feedback signal to obtain an abnormal signal image of the semiconductor device under test.
7. The semiconductor device failure analysis method according to claim 6, characterized in that: The failure region includes at least one failure port; the failure region includes, but is not limited to, one or more of the following: open circuit region, leakage current increase region, and impedance increase region.
8. The semiconductor device failure analysis method according to claim 7, characterized in that: The failure port includes, but is not limited to, one or more of the following: open circuit test failure port, leakage current increase failure port, and impedance increase failure port.
9. The semiconductor device failure analysis method according to claim 6, characterized in that: The test signal includes, but is not limited to, one or more of current signals, voltage signals, impedance signals, and current density signals; the test equipment includes, but is not limited to, TDR equipment and pulse current equipment.
10. The semiconductor device failure analysis method according to claim 9, characterized in that: The testing equipment also includes an oscilloscope for displaying images of abnormal signals.