Apparatus, method and system for register renaming

Abstract

Apparatuses, methods, and systems for register renaming are disclosed. A conflict detector circuit is configured to detect a register conflict between the first decoded instruction and the second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to computer architecture. More specifically, the subject matter disclosed herein relates to register renaming for executing mixed instructions with register conflicts. BACKGROUND

[0002] This Background section is intended to provide only a general overview of context and therefore the concepts disclosed in this section should not be construed as an acknowledgment of prior art.

[0003] Advances in data science, artificial intelligence (AI), and machine learning (ML) have led to a revolution in technology across various industries. To accommodate these changes, semiconductor devices and systems have also been developed with new technologies including computing architecture, processor and memory design, network security, and communication interfaces. Among these developments, processor architecture has become increasingly important, especially in applications that require high throughput, low power, and small physical space, such as mobile devices.

[0004] In advanced processor architecture designs, instruction pipeline structures have been widely applied in many processing applications including multi-threading and parallel operations. As the demand for high performance computing increases, the design of efficient processor architecture is increasingly facing many challenges. Issues such as architectural register dependencies, out-of-order and in-order execution, circuit complexity, inefficient compiler techniques, and complexity of communication and interfaces in a multi-processor environment have created many problems in instruction pipeline design. Compilers tend to generate inefficient code when resolving register conflicts without taking advantage of the internal structure of the micro-architecture. Hardware solutions tend to be overly complex, resulting in larger silicon area and are not suitable for high performance computing.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the present disclosure, and therefore it can contain information that does not constitute prior art. SUMMARY

[0006] To overcome these problems, systems and methods for techniques of register renaming in micro-architecture are described herein. The techniques aim to provide an efficient structure for resolving conflicts in register usage. The techniques include a hardware implementation of a circuit that renames registers at runtime when instructions flow through an instruction pipeline in a processing element (PE).

[0007] In an embodiment, a register renaming circuit includes a conflict detector circuit and a mapping circuit. The conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

[0008] In an embodiment, a method includes detecting a register conflict between a first decoded instruction and a second decoded instruction, the register conflict being associated with a first architectural register and a first physical register corresponding to the first architectural register, changing the first architectural register to a second architectural register, and mapping the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

[0009] In an embodiment, a system includes a host processor configured to manage processor operations and memory operations, and a processing element (PE) in a cluster of PEs configured to be managed by the management processor. The PE includes a register renaming circuit including a conflict detector circuit and a mapping circuit. The conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction, the register conflict being associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread.

[0010] Advantages of the invention

[0011] According to embodiments of the present disclosure, there is provided a register renaming for executing mixed instructions with register conflicts with improved performance. BRIEF DESCRIPTION OF DRAWINGS

[0012] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the drawings, wherein:

[0013] Figure 1 is a block diagram illustrating a system according to an embodiment.

[0014] Figure 2 is a diagram illustrating an execution circuit in a PE according to an embodiment.

[0015] Figure 3 FIG. 1 is a diagram illustrating a register renaming circuit according to an embodiment.

[0016] Figure 4 FIG. 2 is a diagram illustrating a mapping circuit according to an embodiment.

[0017] Figure 5 FIG. 3 is a flowchart illustrating a process for register renaming according to an embodiment.

[0018] Figure 6 FIG. 4 is a flowchart illustrating a process of mapping to physical registers according to an embodiment. DETAILED DESCRIPTION

[0019] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood by those skilled in the art that the various aspects of the disclosure can be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0020] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar meanings) throughout this specification (or variations thereof) does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In this regard, the term “exemplary” as used herein means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Moreover, depending on the context, singular terms can include their corresponding plural forms and plural terms can include their corresponding singular forms. Similarly, hyphenated terms (e.g., “two-dimensional”) can occasionally be used in conjunction with corresponding non-hyphenated versions (e.g., “two dimensions”) where the hyphenated form is not intended to be a nominalization. Likewise, the use of a capitalization of a word (e.g., a product name, a computer

[0021] Furthermore, depending on the context, singular terminology can include its corresponding plural forms and plural terminology can include its corresponding singular form. It will be further understood that the various drawings shown and discussed herein are only illustrative and are not drawn to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the various drawings to indicate corresponding or analogous elements, portions, sections, etc.

[0022] The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] As used herein, the terms "first," "second," etc. are used as labels for nouns that they follow and do not necessarily describe a temporal or chronological order, unless explicitly stated otherwise. Moreover, the use of the terms top, bottom, over, under and the like are used for clarity with respect to the figures and are not otherwise intended to restrict the scope of the disclosure to any one or more particular arrangements or relative orientations. Additionally, the use of the terms first, second, etc. to describe a variety of elements or instances do not imply that the elements or instances are in any way prioritized, but rather simply label them in some manner for illustrative purposes. Furthermore, the use of the terms first, second, etc. do not denote or otherwise imply any sort of ordering in terms of importance, timing, chronology, or the like. For example, a first contact is not necessarily made before the second contact. Moreover, the use of the terms first, second, etc. to describe a variety of elements or instances do not imply that the elements or instances are in any way prioritized, but rather simply label them in some manner for illustrative purposes. Furthermore, the use of the terms first, second, etc. do not denote or otherwise imply any sort of ordering in terms of importance, timing, chronology, or the like. For example, a first contact is not necessarily made before the second contact.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] As used herein, the term “module” refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein with respect to the module. For example, software can be embodied in software packages, code, and / or instruction sets or instructions, and the term “hardware” as used in any embodiment described herein can include, for example, components, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware that stores instructions executed by programmable circuitry, individually or in any combination. Modules can be embodied collectively or individually as circuitry that forms part of a larger system, such as, but not limited to, an integrated circuit (IC), a system on-chip (SoC), a component, etc.

[0027] As used herein, the term “solid state” in the context of storage refers to a storage technology that uses integrated circuits rather than moving parts (e.g., spinning disks, platters, read / write heads) to store data. The term “flash memory” refers to a type of non-volatile memory that retains data even when power is removed. It is commonly used in solid state drives (SSDs). There are two types of flash memory: NAND-type flash memory and NOR-type flash memory. NAND flash memory has a high storage density and lower cost per bit, and is suitable for use in SSDs, mobile applications. NOR flash is optimized for random access and is commonly used in applications that require fast code execution.

[0028] As used herein, the term “buffer” in the context of storage refers to a memory device that stores data or information on a temporary basis as part of an operation involving moving data from one location to another. Buffers are typically implemented by static random access memory (RAM) for fast access. Buffers can be organized as standard SRAM or first-in-first-out (FIFO) organization.

[0029] In an embodiment, techniques for register renaming are disclosed. The techniques provide efficiency in a processing instruction pipeline in the microarchitecture of a processing element (PE) in a system using multiple PEs. The techniques provide several advantages, including fast processing of stages in the instruction pipeline, specialized circuitry to perform specific tasks, and independent operation of a compiler, among others. In the instruction pipeline, instructions go through several stages, including decode, register renaming, issuance, execution, and retirement. The register renaming is the stage that follows the instruction decode stage. This stage is performed by a register renaming circuit that includes a conflict detector circuit and a mapping circuit. The conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE). The mapping circuit can include a name changer circuit and a mapping table. The name changer circuit is configured to change the first architectural register to the second architectural register. The mapping table is configured to map the second architectural register to the second physical register. The mapping table stores an architectural identifier that identifies one of the first architectural register or the second architectural register and a physical identifier that identifies the second physical register.

[0030] Figure 1 is a block diagram illustrating a system 100 according to an embodiment. The system 100 can be implemented as one or more system-on-chip (SoC) packages including high-density devices such as three-dimensional (3D) packages. The system 100 includes a host processor 110, an input / output (I / O) controller 140, a network interface card (NIC) 146, a graphics display controller (GDC) 150, a bus 155, a memory controller 160, and a plurality of processing elements 170 k(k = 1,..., N). These components can interface or include other components described further below. System 100 can include more or fewer components than those described above. In addition, one component can be integrated into another component. For example, I / O controller 140, GDC 150, and memory controller 160 can be integrated into one module. The integration can be partial and / or overlapping. For example, GDC 150 can be integrated into host processor 110, I / O controller 140 and memory controller 160 can be integrated into one single controller, etc. System 100 can be an example showing the role of high bandwidth memory (HBM) circuitry in a high compute (HC) platform. Many HC platforms can use several HBM circuits, including stacked dynamic random access memory (DRAM) operating in conjunction with processing units or I / O circuitry. In many cases, the environment of the application adds additional criteria, including low power consumption, reliable signal integrity, fault tolerance, and reliable operation under extreme conditions, including high temperature and cramped spaces. Examples of other applications that would benefit from highly integrated HBM designs include mobile communications (e.g., smartphones, base stations, user equipment), cameras, vehicles, entertainment (e.g., gaming, multimedia, music, movies), technical design (e.g., animation, graphics), medical (e.g., visualization, medical imaging), robotics, drones, automated test equipment, audio processing, speech synthesizers, video and image analysis, vision, automated facial recognition, artificial intelligence (AI) applications, and data centers.

[0031] Host processor 110 is a programmable device that can execute a set of programs or instructions to perform tasks. It can be a general purpose processor, a digital signal processor, a microcontroller, a neural processing unit (NPU), or a specially designed processor such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). It can include a single core or multiple cores. Each core can have multiple threads of execution. Host processor 110 can have simultaneous multi-threading features to further exploit parallelism due to multiple threads across multiple cores. Host processor 110 can include memory management circuitry (MMC) 120 and processing management circuitry (PMC) 130. Host processor 110 can include more or fewer components than those described above. Bus 155 can be any suitable bus connecting host processor 110 to other devices, including multiple PEs 170 k (k = 1,..., N). These components can interface or include other components described further below. System 100 can include more or fewer components than those described above. In addition, one component can be integrated into another component. For example, I / O controller 140, GDC 150, and memory controller 160 can be integrated into one module. The integration can be partial and / or overlapping. For example, GDC 150 can be integrated into host processor 110, I / O controller 140 and memory controller 160 can be integrated into one single controller, etc. System 100 can be an example showing the role of high bandwidth memory (HBM) circuitry in a high compute (HC) platform. Many HC platforms can use several HBM circuits, including stacked dynamic random access memory (DRAM) operating in conjunction with processing units or I / O circuitry. In many cases, the environment of the application adds additional criteria, including low power consumption, reliable signal integrity, fault tolerance, and reliable operation under extreme conditions, including high temperature and cramped spaces. Examples of other applications that would benefit from highly integrated HBM designs include mobile communications (e.g., smartphones, base stations, user equipment), cameras, vehicles, entertainment (e.g., gaming, multimedia, music, movies), technical design (e.g., animation, graphics), medical (e.g., visualization, medical imaging), robotics, drones, automated test equipment, audio processing, speech synthesizers, video and image analysis, vision, automated facial recognition, artificial intelligence (AI) applications, and data centers.

[0032] The I / O controller 140 controls storage 142 and input / output devices 144. The storage 142 can include CD-ROMs, hard disks, and solid-state drives (SSDs). The input devices can include stylus, keyboard, mouse, microphone, and image sensor. The output devices can include audio devices, speakers, scanner, and printer. The network interface card (NIC) 146 provides an interface to a network, e.g., via a wireless medium 148.

[0033] The memory controller 160 can be an extension of the MMC 120. It controls memory devices, such as memory 162, HBM 164, and non-volatile memory (NVM) 166. The memory 162 can include static random access memory (SRAM) and dynamic random access memory (DRAM). The HBM 164 can include a 3-D stack of memory dies to provide high bandwidth, low latency, low power, and high storage capacity. It can also have processing-in-memory (PIM) capability. The NVM 166 can include read-only memory (ROM), flash memory, wide IO NAND, MRAM, and / or other types of memory. The memory 162 can store instructions or programs loaded from the NVM 166 or storage 142 that, when executed by any of the host processor 110 or the PEs 170 k k cause any of the host processor 110 or the PEs 170 k to perform operations as described in various embodiments. It can also store data used in the operations. The NVM 166 can include instructions, programs, constants, or data that are maintained regardless of whether it is powered. The instructions or programs can correspond to the functions described below. In one embodiment, the programs can include a compiler that compiles programs to be executed in one of the PEs 170 k

[0034] The GDC 150 controls the display device 152 and provides graphics operations. It can be integrated inside the host processor 110. It typically has a graphical user interface (GUI) to allow interaction with a user that can send commands or activate functions.

[0035] Additional devices or bus interfaces can be used for interconnection and / or extension. Some examples can include peripheral component interconnect express (PCIe) bus, universal serial bus (USB), etc.

[0036] The host processor 110 and the plurality of processing elements 170 kA tight communication interface is maintained at least via bus 155 and other separate lines. A plurality of PEs 170 k operate under the control and management of host processor 110. Once enabled and started, each of PEs 170 k can execute its own program and access data in its private instruction memory 192 and data memory 194. Host processor 110 can provide an abstraction layer for the entire architecture. In essence, it can hide the complexity of program execution from the user or high-level application. The application program can specify what needs to be done, and host processor 110 will take care of the details of how to perform it by assigning or dispatching tasks to individual PEs.

[0037] Host processor 110 includes memory management circuit (MMC) 120 and processing management circuit (PMC) 130. Each of PEs 170 k (k = 1,..., N) includes LI cache 172 k , configuration (CFG) circuit 174 k , execution circuit 180 k , interrupt circuit 182 k , instruction memory 192 k , data memory 194 k , computation circuit 196 k , and communication interface 198 k . Host processor 110 and PEs 170 k may include more or less components than those described above. In the following, for the sake of clarity, the index k of PE 170 k and its associated elements can be dropped.

[0038] The MMC 120 is configured to operate with or without the memory controller 160 to manage memory operations to at least one of the L2 cache 125, the main memory 134, the LI cache 172, the memory 162, the HBM 164, or the NVM 166 in the PE 170 based on memory accesses of at least one of the PMC 130 and at least one of the PE 170. The memory operations can include at least one of read accesses, write accesses, page table updates, translation lookaside buffer (TLB) updates, cache responses, and access violation responses. The L2 cache 125 can be configured to function as a translation lookaside buffer (TLB) to translate virtual memory to physical memory. The L2 cache 125 is typically implemented by fast memory such as fast SRAM to allow the MMC 120 to quickly retrieve virtual-to-physical page mappings without accessing slower page tables. It can also function as a cache storage to provide fast responses to memory accesses. The MMC 120 can update the page table in the memory 162 or the TLB in the L2 cache 125 when there is a new entry in the table. The MMC 120 can respond to any access violation, such as a non-existent memory address, buffer overflow, null pointer, etc. It can report any violation to a test controller (not shown) for debugging or testing purposes.

[0039] The PMC 130 includes a main execution circuit 132, a main memory 134, and an interrupt controller 136. It is configured to manage at least one processor operation performed by at least one of the PE 170. The processor operation can include at least one of program initiation, program execution, and interrupt delivery. The main execution circuit 132 can be a processing unit or circuit capable of executing programs or instructions stored in the main memory 134. The program can be any suitable program. In one embodiment, the program is a compiler of a program compiled for execution in the PE 170. The main memory 134 is private to the PMC 130. It can be any suitable type of memory such as DRAM, SRAM, magnetoresistive random access memory (MRAM), flash memory, or any combination thereof. The main memory 134 can include a page table to translate virtual pages to physical pages as part of the memory management task done by the MMC 120. The main execution circuit 132 can also access the memory 162, the HBM 164, and the NVM 166 via the memory controller 160. The interrupt controller 136 controls and manages interrupt requests from / to the PE 170 and interrupt servicing. This can include prioritizing the interrupt requests and sending commands or messages to the PE 170.

[0040] Each of the PEs 170 is configured to operate independently or in coordination with other PEs 170 and the host processor 110. Together, they form a multi-processor system that can work in parallel or sequentially based on overall system goals. In each of the PEs 170, the execution circuit 180 is configured as circuitry capable of executing programs, instructions, or commands stored in the instruction memory 192. The execution circuit 180 interfaces or communicates with the instruction memory 192, the data memory 194, the computation circuit 196, the communication interface 198, and the memory controller 160 via the bus 190. Through the memory controller 160, the execution circuit 180 accesses the memory 162, the HBM 164, and the NVM 166. In some embodiments, the execution circuit 180 includes an instruction pipeline that processes instructions from the instruction memory 192. Details of the instruction pipeline will be described in more detail below. Figure 2An instruction pipeline in execution circuit 180 is described. Execution circuit 180 can access data stored in data memory 194. Data memory 194 can be used to store temporary data and data structures, such as a stack or heap for program execution. Instruction memory 192 and data memory 194 are private or local to the associated PE and can be implemented by any suitable memory including DRAM, SRAM, MRAM, flash memory, or any combination thereof. Compute circuit 196 is configured to perform logic and / or compute operations. It can include multiple functional units, tensor units, math units, as well as buffers and interconnects. These compute units can be scheduled by a PE scheduler (not shown). The PE scheduler can be configured by host processor 110. Communication interface 198 provides an interface for communication between PEs and between the associated PE and host processor 110. LI cache 172 provides fast cache memory to execution circuit 180. It can be used to implement a TLB for address translation. It can be connected to L2 cache 125 in host processor 110 for additional cache operations. By allowing the LI cache 172 in each PE to communicate with the L2 cache 125, the PEs can share information between them. Interrupt circuit 182 provides interrupt request and response services between PEs and between the PE and host processor 110 for inter-processor interrupts (IPIs). It generates IPIs to another PE and receives IPI responses from another PE. A PE can preload data or state in memory 162 before requesting an interrupt so that another PE can retrieve the data when servicing the interrupt. It can also generate an interrupt to the main execution circuit 132 through interrupt controller 136 when the PE requests service or reports status. For example, when a PE completes a currently assigned task, it can send an interrupt to the main execution circuit 132. Before sending the interrupt, it can transmit a message, result, data, status, or condition to memory 162 or HBM 164 to allow the main execution circuit 132 to check the message when it responds to the interrupt. This allows an efficient communication protocol between the PE and host processor 110. CFG circuit 174 includes CFG data that configures the PE 170 to perform operations or computations as needed. CFG circuit 174 can also enable or disable the PE under control of host processor 110.

[0041] Figure 2 is a diagram illustrating execution of a PE 170 according to an embodiment. Figure 1 The execution circuit 180 shown. Execution circuit 180 includes instruction buffer 210, instruction pipeline 220, register buffer 260, and register file 270. Execution circuit 180 can include more or fewer components than those described above.

[0042] Instruction buffer 210 stores instructions from instruction memory 192 and queues them for feeding into instruction pipeline 220. It can include small buffers inserted between stages in pipeline 220 to hold instruction flow moving. It can buffer in-order instructions, out-of-order instructions, or predicted branch instructions by corresponding circuitry (not shown).

[0043] Instruction pipeline 220 includes multiple stages to prepare instructions for execution in program flow. Stages in instruction pipeline 220 include a fetch stage 222, a decode stage 226, a register renaming stage 230, an issuance stage 234, an execution stage 238, a memory stage 242, a writeback stage 246, and a retirement stage 250. Pipeline 220 can include more or fewer stages than those described above. Also, not all stages are active for all instructions.

[0044] Fetch stage 222 retrieves instructions from instruction buffer 210 or directly from instruction memory 192. A program counter (not shown) tracks the address of instructions. Fetched instructions are typically held in an instruction register ready to be decoded. Fetch stage 222 can include branch prediction, out-of-order execution, reorder buffers, mispredicted branch handling, and other fetch mechanisms to provide smooth flow of instructions through the pipeline.

[0045] Decode stage 226 involves decoding, interpreting, and translating the binary representation of instructions into parts that can be understood and executed. This includes separating instructions into opcodes and operands and determining what action to perform. The results of decode stage 226 include decoded instructions, which will be further examined to determine if there are conflicts in register usage during execution of the instructions. Decode stage 226 can include branching to microcode corresponding to the instructions.

[0046] Register renaming stage 230 resolves register conflict usage in decoded instructions. It eliminates false data dependencies, especially write-after-write (WAW) and read-after-write (WAR) hazards. Register renaming stage 230 maps logical or architectural register names to physical register names in a processor internal register file. This process is dynamically updated as instructions flow through the pipeline so that no conflicts occur and operands can be read and written correctly. Register renaming stage 230 includes register renaming circuitry 235, which will be described further in Figure 3

[0047] ​The issue or issue stage 234 prepares instructions for execution. It can include selecting and scheduling instructions taking into account factors such as program order and dependency analysis. The issue stage 234 can include allocating resources (e.g., functional units, memory accesses) and retrieving operands. The issue can include in-order and out-of-order schemes.

[0048] The execution stage 238 executes instructions as issued and prepared by the issue stage 234. It uses the compute circuitry 196 (in Figure 1 ) to perform execution that can include arithmetic and logical operations provided by functional units and other operations. It can retrieve operands from the register file 270, compute memory addresses, and evaluate branch predictions. It can obtain operands from the memory stage 242 that accesses the LI cache 172 and the bus 190.

[0049] The memory stage 242 obtains operands from memory or writes data to memory. Examples of instructions that can access memory include loads and stores. If an instruction does not access memory, the memory stage 242 can be bypassed.

[0050] The writeback stage 246 writes results of the execution stage 238 back to the register file 270. It writes data to the register buffer 260, which sends data to the register file 270 when ready. Depending on the instruction, the writeback stage 246 can obtain data to write back directly from the compute circuitry 196 or from the memory stage 242.

[0051] The retirement stage 250 finalizes execution of instructions. It can be combined with the writeback stage 246. It can include handling exceptions, releasing resources, and other housekeeping functions.

[0052] Figure 3 is a diagram showing the register renaming circuit 235 employed in the register renaming stage 230 in Figure 2 is a diagram showing the register renaming circuit 235 employed in the register renaming stage 230 in Figure 3 The process of register renaming is also illustrated with the illustrative examples shown in blocks 310, 315, 320, 356, and 370.

[0053] The register renaming circuit 235 includes a conflict detector circuit 340 and a mapping circuit 350. The register renaming circuit 235 can include more or fewer components than the components described above. For example, the conflict detector circuit 340 and the mapping circuit 350 can be combined in one unit or circuit. In one embodiment, the conflict detector circuit 340 and the mapping circuit 350 are used with a compiler to perform register renaming at compile time. In another embodiment, the conflict detector circuit 340 and the mapping circuit 350 are used to perform register renaming at runtime.

[0054] The conflict detector circuit 340 is configured to detect a register conflict between the first decoded instruction 332 and the second decoded instruction 334. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The first decoded instruction 332 and the second decoded instruction 334 can be part of a microcode sequence in a microarchitecture of the PE 170.

[0055] The block 310 shows three instructions A, B, and C in sequence. The block 315 shows mnemonics for the instruction A, the instruction B, and the instruction C. The instruction A is load %r1, a[i], where %r1 is a reference to an architectural or logical register r1 and a[i] is a reference to element i of an array a[]. The mnemonic for the instruction A is r1 <- a[i], where the arrow <- indicates a load or move operation. Similarly, the instruction B is load %r2, b[i], which represents r2 <- b[i], and the instruction C is mul_add c, d, which represents c <- c*d + c, where * is a multiplication operator and + is an addition operator. The instructions 1 and 2 are referred to as simple instructions because they reference only a single register in the destination. Simple instructions are easy to decode, and the registers are explicitly defined. In contrast, the instruction 3 is referred to as a complex instruction because it involves multiple registers in both the source and the destination. Complex instructions can not explicitly define the registers, and thus they can cause register conflicts.

[0056] After the decode stage 226, the instructions in the block 310 can become the decoded instructions in the block 320. Figure 1 A compiler in the host processor 110 in the system 100 can compile the instructions in the block 310. The block 320 includes the decoded instructions 1, 2, 4, 5, 6, 7, and 8. The instructions 4, 5, 6, 7, and 8 are compiled and decoded instructions from the instruction 3. It can be recognized that there is a register conflict between the instruction 1 and the instruction 6 and between the instruction 2 and the instruction 7. The conflicts exist because for the instruction 1 and the instruction 6, the destination register r1 is used for both instructions, and for the instruction 2 and the instruction 7, the destination register r2 is used for both instructions. The result of the register conflicts is that the previous contents of the registers r1 and r2 are overwritten and destroyed.

[0057] In this example, instruction 1 and instruction 6 are referred to as first decoded instruction 332 and second decoded instruction 334, respectively. Conflict detector circuit 340 receives first decoded instruction 332 and second decoded instruction 334 and determines if there is a register conflict. This can be done by comparing the destination registers in the two instructions. If they are the same and if the contents of the preceding register have not been saved, there is a conflict. If they are different or if they are the same but the contents of the preceding register have been saved, there is no conflict, and if all instructions in the group have been processed, the process can continue to the next pair or to the next stage. Conflicts are searched for in all possible pairs in the group. When there is a conflict, a register renaming operation is performed to resolve the conflict. This can be done by mapping circuit 350. The registers shown in the decoded instructions are referred to as architectural or logical registers. They do not represent the actual physical registers in register file 270 that store the data. First decoded instruction 332 and second decoded instruction 334 are decoded from a single thread in PE 170. In one embodiment, the actual physical registers are grouped into two sets: a primary set 353 and a redundant set 354. Primary set 353 includes the physical registers that are used as primary registers for mapping. Redundant set 354 acts as a backup group and includes physical registers that are redundant and are used when primary registers are used and are not available for mapping during the renaming operation. Initially, all primary registers are available. As the instructions progress, the registers are used, and there are fewer and fewer available primary registers. When there are no available primary registers, redundant registers can be used until a primary register is freed up. Redundant set 354 is hidden from the user to simplify instruction translation or decoding.

[0058] When a conflict occurs, the register renaming renames one of the architectural registers so that it will reference a different physical register. In Figure 3In the example shown, there is a conflict between instruction 1 and instruction 6 involving architectural register r1 (in block 320). At the beginning, architectural register r1 is mapped to first physical register pr1 from the primary set. When the conflict is detected at instruction 6, architectural register r1 is changed or translated to second architectural register r5, which is mapped to second physical register pr5 to avoid overwriting first physical register pr1. In other words, mapping circuit 350 is configured to change first architectural register r1 in instruction 6 to second architectural register r5, which is mapped to second physical register pr5 that is available in primary set 353 and different from first physical register pr1. In this example, five physical registers are used at this time for illustration only, as four architectural registers are mapped to four corresponding physical registers prior to the conflict. When the conflict occurs, assuming that next physical register pr5 from the primary set is available, it will be used to map to r5. Mapping circuit 350 will be described further in Figure 4 Mapping circuit 350. By selecting a different physical register, the contents of the register in the previous decoded instruction are preserved. To this end, mapping circuit 350 includes a mapping table 352 that maps architectural registers to physical registers. Mapping table 352 shows the following mapping:

[0059] r1→pr1

[0060] r2→pr2

[0061] r3→pr3

[0062] r4→pr4

[0063] r5→pr5

[0064] r6→rpr2

[0065] ...

[0066] rN→prN

[0067] The next conflict occurs in instruction 2 and instruction 7, as both use architectural register r2 as a destination register. At instruction 2, architectural register r2 is mapped to physical register pr2. When the conflict is detected at instruction 7, architectural register r2 will be mapped to architectural register r6, so that it can be mapped to another available primary physical register (e.g., pr6), as discussed above for instruction 6. However, assume that no primary physical registers are available, as they are used for other instructions, architectural register r6 will be mapped to a backup or redundant physical register selected from redundant set 354. The redundant set 354 of physical registers can be used as a backup, as primary physical registers are likely to be exhausted, especially when many instructions are pending. The redundant set 354 is hidden from the user, and will be used when no primary physical registers are available for renaming in register file 370. Alternatively, other techniques can be employed to free up physical registers, including temporarily storing the contents in memory, if no physical registers are available. Other techniques can also be used if the redundant set 354 is also exhausted. In this example, assume that redundant physical register rpr2 is available. Architectural register r6 is mapped to redundant physical register rpr2 to illustrate this concept.

[0068] Block 356 illustrates the register renaming process. For instruction 1 and instruction 6 of block 320, architectural register r1, which is mapped to physical register prl in mapping table 352, will be renamed to architectural register r5 in the case of instruction 6, which is mapped to physical register pr5 to become instruction 9. Physical register pr5 is different from physical register prl and is available in primary set 353. With respect to instruction 2 and instruction 6, for instruction 2, architectural register r2 is mapped to physical register pr2. For instruction 7, architectural registers r2 and r1 are renamed to architectural registers r6 and r5, respectively. For illustrative purposes, assume that no physical registers are available in primary set 353 after the register renaming in instruction 6. Architectural register r6 is therefore mapped to a register in redundant set 354. Assume that this redundant register is redundant physical register rpr2 in redundant set 354, which is different from pr2 and is available according to mapping table 352. As a result, the conflict at architectural registers r1 and r2 is resolved.

[0069] Block 370 includes the final sequence of instructions after register renaming. Instruction 6, instruction 7, and instruction 8 are converted to instruction 9, instruction 10, and instruction 11, respectively. All register conflicts have been resolved. The instructions are then forwarded to the issue stage 234.

[0070] Figure 4 is a diagram illustrating a Figure 3The diagram of the mapping circuit 350 is shown. The mapping circuit 350 includes a register name changer 420 and a mapping table 430. The mapping circuit 350 can include more or less components than those described above.

[0071] The register name changer 420 receives the decoded instruction 410 from the conflict detector circuit 340. The decoded instruction 410 includes the first architectural register as described above with respect to block 320 in FIG. 3. The register name changer 420 is a circuit configured to change the first architectural register in the decoded instruction 410 to a second architectural register. This is shown in block 356 in FIG. 4, where the architectural register r1 is changed to the architectural register r5, and the architectural register r2 is changed to the architectural register r6. Figure 3 Figure 3 The register name changer 420 generates an architectural identifier that identifies the register, such as a register number.

[0072] The mapping table 430 is configured to map the second architectural register to a second physical register. It is a fast memory (e.g., SRAM) that contains identifiers of architectural registers and corresponding physical registers, including redundant physical registers, as shown in table 352 in FIG. 3. Since the registers used in the instruction store data temporarily, there is no specific selection criteria other than availability of the registers. Thus, the mapping table 430 can select any register that is available to store the data. As shown in block 354 in FIG. 3, depending on the availability, either the primary set 353 or the redundant set 354 can be used. In some embodiments, the mapping table 430 can be implemented by a lookup table (LUT) or a hash function. The mapping table 430 generates a physical identifier 435 that corresponds to the architectural identifier 425. The physical identifier 435 can then be used to access the register file 270, if needed. The physical identifier 435 is then forwarded to the emission stage 234. Figure 3 Figure 3

[0073] Figure 5 is a flow diagram showing a process 500 for register renaming according to an embodiment.

[0074] ​​​At the start, the process 500 receives decoded instructions from a decoder (block 510). The decoded instructions can include instructions with register conflicts. Next, the process 500 detects a register conflict between a first decoded instruction and a second decoded instruction (block 520). The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE). The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. This can be accomplished by scanning the register fields of the instructions and determining if there are any matches. In addition, the operation can also include checking the state of the register to determine if the register has been saved. The process 500 then determines if there is a register conflict (block 530). If no (no at block 530), the process 500 determines if all of the instructions in the block have been processed (block 535). If no, the process 500 returns to block 520 to continue checking other instructions. Otherwise, if all of the instructions have been processed for renaming, the process 500 is terminated.

[0075] If there is a register conflict (yes at block 530), then the process 500 changes the first architectural register to a second architectural register and maps the second architectural register to a second physical register different from the first physical register (block 540). Next, the process 500 issues the first decoded instruction associated with the first physical register and the second decoded instruction associated with the second physical register to an execution circuit for execution (block 550). This is to advance the instructions to the issue stage. The process 500 is then terminated.

[0076] Figure 6 is a flow diagram illustrating a process 540 of mapping to physical registers according to an embodiment. Figure 5 is a flow diagram illustrating a process 540 of mapping to physical registers according to an embodiment.

[0077] At the start, the process 540 changes a first architectural register to a second architectural register (block 610). This is shown in block 356 in Figure 3 where the architectural registers r1 and r2 are changed to architectural registers r5 and r6, respectively. Next, the process 540 maps the second architectural register to a second physical register (block 620). The mapping is shown in the mapping table 352 in Figure 3 where r5 is mapped to pr5 and r6 is mapped to rpr2. The mapping table 352 stores an architectural identifier identifying one of the first architectural register or the second architectural register and a physical identifier identifying the second physical register. The process 540 is then terminated.

[0078] All or part of the embodiments can be implemented by various means depending on the application based on specific features and functions. These devices can include hardware, software, or firmware, or any combination thereof. Hardware, software, or firmware elements can have several modules coupled to each other. Hardware modules are coupled to another module via mechanical, electrical, optical, electromagnetic, or any physical connection. Software modules are coupled to another module via function, procedure, method, subroutine or subroutine call, jump, linking, parameter, variable and argument passing, function return, etc. Software modules are coupled to another module to receive variables, parameters, parameter values, pointers, etc., and / or generate or pass results, update variables, pointers, etc. Firmware modules are coupled to another module via any combination of the above hardware and software coupling methods. Hardware, software, or firmware modules can be coupled to any one of other hardware, software, or firmware modules. A module can also be a software driver or interface that interacts with an operating system running on a platform. A module can also be a hardware driver for configuring, setting, initializing, sending data to and receiving data from a hardware device. The device can include any combination of hardware, software, and firmware modules.

[0079] Embodiments of the subject matter and operations described in this specification can be implemented in digital electronic circuits, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by or control of the operation of a data processing device. Alternatively or additionally, the program instructions can be encoded on artificially generated propagating signals, such as machine-generated electrical, optical, or electromagnetic signals, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be or is included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. Furthermore, although the computer storage medium is not a propagating signal, it can be a source or destination of computer program instructions encoded in artificially generated propagating signals. The computer storage medium can also be or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Furthermore, the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0080] While the specification can include many specific embodiments, the embodiments should not be construed as limiting the scope of any claims that can be presented. It should be noted that there are many alternatives for implementing the inventive concepts described herein. The embodiments described herein are merely by way of example. It should also be noted that the term "example" as used herein means "serving as an example, instance, or illustration." Any implementation described herein as an "example" is not necessarily to be construed as preferred or advantageous over other implementations. Likewise, the term "implementation" does not necessarily mean that an implementation is necessarily the best implementation, but merely an implementation that serves as an example, instance, or illustration.

[0081] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0082] Accordingly, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, actions recited in the claims can be performed in a different order and still achieve desirable results. Additionally, the process depicted in the accompanying figures can not necessarily require the particular order or chronological sequence illustrated, nor do they necessarily all convey the same result. In certain implementations, multitasking and parallel processing can be advantageous.

[0083] As will be recognized by the skilled person, the innovative concepts described herein can be modified and varied widely. Accordingly, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.

Claims

1. An apparatus for renaming registers, comprising: A collision detector circuit is configured to detect a register collision between a first decoded instruction and a second decoded instruction, the register collision being associated with a first architecture register and a first physical register corresponding to the first architecture register; as well as The mapping circuit is configured to change the first architecture register to a second architecture register and map the second architecture register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in the processing element PE.

2. The apparatus according to claim 1, wherein, The first architecture register and the first physical register are the destinations of the first decoded instruction and the second decoded instruction.

3. The apparatus according to claim 1, in, The first decoded instruction is a simple instruction that references a register that is a register of the first architecture, and the second decoded instruction is a complex instruction that references at least a source register and a destination register that is a register of the second architecture.

4. The apparatus according to claim 1, wherein, The second physical register is selected from the primary set and the redundant set based on availability.

5. The apparatus according to claim 1, wherein, The first decoded instruction associated with the first physical register and the second decoded instruction associated with the second physical register are sent by the instruction transmitter to the execution circuit for execution.

6. The apparatus according to claim 1, wherein, The mapping circuit includes: The name changer circuit is configured to change the first architecture register to the second architecture register; and A mapping table is configured to map the second architecture registers to the second physical registers. The mapping table stores the architecture identifier that identifies one of the first architecture register or the second architecture register, and the physical identifier that identifies the second physical register.

7. The apparatus according to claim 1, wherein, The first decoded instruction and the second decoded instruction are part of a microcode sequence in the microarchitecture of the processing element.

8. The apparatus according to claim 1, wherein, The collision detector circuit and the mapping circuit are used in the compiler to rename registers at compile time.

9. The apparatus according to claim 1, wherein, The collision detector circuit and the mapping circuit are used to rename registers during runtime.

10. The apparatus according to claim 1, wherein, The PE is part of a PE cluster in a high-bandwidth memory (HBM) processing system.

11. A method for renaming a register, comprising: Detect register conflicts between a first decoded instruction and a second decoded instruction, the register conflicts being associated with a first architecture register and a first physical register corresponding to the first architecture register; Change the first architecture register to the second architecture register; and Map the second architecture register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in the processing element PE.

12. The method according to claim 11, wherein, The first architecture register and the first physical register are the destinations of the first decoded instruction and the second decoded instruction.

13. The method according to claim 11, in, The first decoded instruction is a simple instruction that references a register that is a register of the first architecture, and the second decoded instruction is a complex instruction that references at least a source register and a destination register that is a register of the second architecture.

14. The method according to claim 11, wherein, The second physical register is selected from the primary set and the redundant set based on availability.

15. The method of claim 11, further comprising sending the first decoded instruction associated with the first physical register and the second decoded instruction associated with the second physical register to the execution circuit for execution.

16. The method according to claim 11, wherein, The mapping includes: The second architecture register is mapped to the second physical register using a mapping table. The mapping table stores the architecture identifier that identifies one of the first architecture register or the second architecture register, and the physical identifier that identifies the second physical register.

17. The method according to claim 11, wherein, The first decoded instruction and the second decoded instruction are part of a microcode sequence in the microarchitecture of the processing element.

18. The method according to claim 11, wherein, The detection of register conflicts and mappings is performed by the compiler at compile time.

19. The method according to claim 11, wherein, The detection of register conflicts and mappings is performed at runtime.

20. A system for renaming registers, comprising: The host processor is configured to manage processor operations and memory operations; as well as The PEs in the processing element PE cluster are configured to be managed by a management processor, and the PEs include: The register renaming circuit includes: A collision detector circuit is configured to detect register collisions between a first decoded instruction and a second decoded instruction, the register collisions being associated with a first architecture register and a first physical register corresponding to the first architecture register; and The mapping circuit is configured to change the first architecture register to a second architecture register and map the second architecture register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread.

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