Task scheduler structure for dynamic reconfigurable chip

Abstract

The invention discloses a task scheduler structure for a dynamic reconfigurable chip, which is characterized in that in a task control register group, a task sequence number register defines a task sequence number, a task loading / running register defines that a task starts to be loaded or run, and a task description register stores a task feature description information initial address; the task label group records a task state; the scheduling logic module judges whether the task is a new task to be loaded or a loaded task to be run according to the task loading / running register; when the task is a new task, reading data from the external memory according to the information stored in the task description register, and writing the data to the processing unit; and when the task is a loaded task to be operated, sending a task starting command to the processing unit according to the task label group. The method is responsible for chip function configuration, the participation degree of the main controller can be reduced, and when the chip runs the current configuration function, programs and data needed by next function configuration are loaded into the processing unit in parallel.

Description

Technical Field

[0001] This invention relates to a task scheduler structure for dynamically reconfigurable chips, belonging to the field of reconfigurable chip technology. Background Technology

[0002] Dynamically reconfigurable chips have two key characteristics: first, the functional units of the chip are reconfigurable after manufacturing; second, they can map algorithms to the processing units within the chip. Unlike fine-grained reconfigurable processing chips—Field-Programmable Gate Arrays (FPGAs)—dynamically reconfigurable chips, due to their use of coarse-grained ALUs (Arithmetic Logic Units) as processing units and simplified interconnect structures, offer significant advantages over FPGAs in terms of configuration information volume, configuration latency, and chip power consumption. Dynamically reconfigurable chips comprise data and control paths. The data path uses a Processing Unit Array (PEA) to perform calculations on the data; the control path receives and buffers configuration data, handling the configuration of the data path. The process of transmitting configuration data to the data path is called configuration. Traditionally, the control path of dynamically reconfigurable chips typically employs multi-configuration board technology, where each configuration board stores the configuration information required to reconfigure the processing unit's function, allowing for rapid switching of configuration information between configuration boards. With the ever-increasing demands for computational power in high-performance computing (HPC), computing capacity has become a significant bottleneck. When dynamically reconfigurable chips integrating single or multiple physical processors (PEs) (in the tens) are insufficient to meet the needs of HPC, dynamically reconfigurable chips integrating numerous PEs (in the hundreds) have emerged and gradually become an important component of HPC, as they are better suited for processing large-scale, highly parallel programs. Therefore, in applications, dynamically reconfigurable chips are generally used in conjunction with processors. The dynamically reconfigurable chip acts as a high-performance accelerator, while the processor is responsible for configuring and controlling the dynamically reconfigurable chip, acting as a task scheduler, and handling the parts of the program with high serializability and complex flow control.

[0003] The processing unit architecture in dynamically reconfigurable chips is evolving from direct mapping operators of the ALU to simpler processor cores that map to a single thread. This places higher demands on the scheduler within the chip, which is responsible for functional configuration and control. Early dynamically reconfigurable chips, due to their simple functions and clearly defined application algorithms, had insufficient task scheduling requirements; their primary focus was on functional configuration, typically handled by a simple processor. However, modern dynamically reconfigurable chips need to be more universally applicable, and the algorithms used in these applications are rapidly evolving and changing. To adapt to this, a single ALU-structured processing unit can no longer meet the changing application demands. The architecture of processing units is increasingly converging towards simpler processor cores, making the task scheduler within the chip play an increasingly significant role in improving performance.

[0004] Constrained by R&D and production costs, dynamically reconfigurable chips that are only suitable for single-domain algorithms are gradually losing attention. Instead, the trend is towards dynamically reconfigurable chips that integrate a large number of processing units, have streamlined processor cores within each unit, are universally adaptable to applications, and can adapt to rapid algorithmic changes. Because the chip integrates many processing units, for ease of management and control, several processing units are arranged into Processing Unit Arrays (PEAs), making the PEA the basic macrounit within the dynamically reconfigurable chip. Each dynamically reconfigurable chip integrates multiple PEAs. Each processing unit spends a significant amount of time running the software and the required programs and data, which greatly impacts the performance of the dynamically reconfigurable chip. Furthermore, in applications, processing units execute not just one task, but many. These tasks are executed sequentially. Traditionally, only after the preceding task is completed does the loading of programs and data required for the subsequent task begin, and so on. To improve the resource computing efficiency of the processing units and enhance chip performance, it is necessary to begin loading programs and data required for the subsequent task while the preceding task is executing. Traditional dynamic reconfigurable chips typically focus on the rapid switching between several configuration functions in their configuration managers. Modern dynamic reconfigurable chips, however, place greater emphasis on the scheduling of multiple tasks. This presents a new challenge for traditional chips, leading to four significant drawbacks in their schedulers: 1) Traditional dynamic reconfigurable chips lack a task scheduler, relying solely on a configuration manager responsible for configuring different functions; 2) Some modern dynamic reconfigurable chips implement their schedulers using the main controller. However, in practical applications, the main controller often handles highly serial and complex program components. Requiring the main controller to handle task scheduling consumes a significant amount of its runtime, directly reducing overall chip performance; 3) Some schedulers are implemented in software... Currently, by calling hardware primitives through system software, one or more processing units can be combined into a "logical core" to form a set of processing units with different computing capabilities to meet the characteristics of the application and support software definition and hardware reconfiguration. However, this requires software and hardware co-design. The software compilation system needs to support static task partitioning and compilation of hardware primitives. It only implements task partitioning but does not implement dynamic task scheduling. 4) Some scheduler structures borrow the design methods of schedulers in many-core processors. Through thread-level scheduling, thread blocks are evenly distributed to each processing unit. A large number of threads are used to hide long-latency memory access overhead. However, what is hidden here is more data memory access latency. Dynamically reconfigurable chips have program memory access in addition to data memory access. It does not solve all the problems as a whole. Summary of the Invention

[0005] The purpose of this invention is to overcome the aforementioned shortcomings and provide a task scheduler structure for dynamically reconfigurable chips, solving the technical problems of high main controller involvement and inability to achieve dynamic scheduling in existing dynamically reconfigurable chips. The task scheduler of this invention is responsible for chip function configuration, reducing the involvement of the main controller, and while the chip is running the currently configured function, it loads the programs and data required for the next function configuration into the processing unit in parallel.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0007] This invention relates to a task scheduler structure for dynamically reconfigurable chips, particularly for dynamically reconfigurable chips with a large number of integrated processing units and designed for high-performance computing. These chips are characterized by high application performance requirements, long single function configuration time, numerous functions to be configured, and short switching time between different configuration functions. The task scheduler of this invention is responsible for chip function configuration, which can reduce the involvement of the main controller. While the chip is running the current configuration function, it loads the program and data required for the next function configuration into the processing unit in parallel.

[0008] A task scheduler structure for dynamically reconfigurable chips includes: a task control register group, a task tag group, and a scheduling logic module;

[0009] The task control register set is configured by the external host controller. The task control register set includes a task sequence number register, a task load / run register, and a task description register. The task sequence number register defines the task sequence number; the task load / run register defines whether the task has started loading or started running; and the task description register stores the starting address of the task characteristic description information.

[0010] The task tag group contains multiple task tags. Each task tag corresponds one-to-one with a task that has been loaded (i.e. is ready to run) or is ready to be loaded into the dynamically reconfigurable chip. The task tag contains the task number and task status information from the task number register. The task tag is modified accordingly based on the task load / run register and the scheduling logic module’s control over the task.

[0011] The scheduling logic module determines whether a task is a new task to be loaded or a loaded task to be run based on the task load / run register information. When a task is a new task to be loaded, the scheduling logic module reads data from the corresponding external memory based on the information stored in the task description register and writes the read data to the processing unit. When a task is a loaded task to be run, the scheduling logic module issues a task start command to the processing unit participating in the task execution based on the task status information recorded in the task tag group.

[0012] Furthermore, the external main controller writes data into the control register group through the main controller read / write interface;

[0013] The task sequence number register consists of 32 registers, with the lower 15 bits being valid. It defines the sequence number of the task to be loaded or ready to run, with each task represented by a sequence number.

[0014] The task load / run register consists of 32 registers, with the lower 2 bits being valid. When the lowest bit is set to '1', the task load is defined to begin, and when the next lowest bit is set to '1', the task execution is defined to begin.

[0015] Furthermore, the task description register consists of 32 registers;

[0016] The task feature description information is compiled before the dynamically reconfigurable chip runs and becomes part of the program in the external memory of the main controller.

[0017] When loading a task, the scheduling logic module reads in sequence the seven fields of the task feature description information stored in the task description register, starting from the starting address of the task feature description information. The seven fields are: participating PEA definition, participating PE definition, program loading word count, program loading source address, data loading word count, data loading source address, and data loading destination address.

[0018] The first field defines the PEA (Processing Unit Array), with each bit corresponding to a processing unit array. When a bit is '1', it indicates that the corresponding processing unit array will participate in the task's execution. The second field defines the PE (Processing Unit Array), with each bit corresponding to a processing unit within the array. When a bit is '1', it indicates that the corresponding processing unit will participate in the task's execution. The third field specifies the size of the task program loaded into the processing unit. The fourth field specifies the storage address of the task's corresponding program in the main controller's external memory after compilation. When loading a program into the processing unit, the corresponding code of the task program is read sequentially from this address. The fifth field specifies the data size required for the task to be loaded into the processing unit. The sixth field specifies the storage address of the data required for the task to run after compilation by the compiler in the external memory of the main controller. When loading data into the processing unit, data is read out one by one starting from this address. The seventh field specifies the starting address of the data required for the task to run after being read from the external memory of the main controller and written to the local memory of the processing unit. Starting from this address, the write address of the data read from the external memory of the main controller continues to increase sequentially. When the address increases, it increments by 1 in word addressing mode and by 4 in byte addressing mode.

[0019] Furthermore, the task tag group contains a set of task tags. The number of task tags is consistent with the number of storage banks divided into the local storage space of the processing unit. Each task tag is a 32-bit register that records the status of a loaded or running task. The task status includes whether it has been loaded, whether it is running, and the starting bank information of the processing unit program to which the task is loaded.

[0020] Furthermore, the task tag is 32 bits long from the least significant bit to the most significant bit, with the least significant bit being bit 0 and the most significant bit being bit 31. The 32-bit task tag register is divided into 7 bit fields: valid flag field, task sequence number field, start BANK field, reserved field, running flag field, loading flag field, and loaded flag field.

[0021] Furthermore, the valid flag field is bit 31 of the 32-bit register. When this bit is '1', it indicates that the data in the task tag is valid; otherwise, it is invalid. The task sequence number field is bits 16 to 30 of the 32-bit register, a total of 15 bits, which is the task sequence number corresponding to the task tag. The start BANK field is bits 12 to 15 of the 32-bit register, a total of 4 bits, which is the BANK sequence number of the task loaded into the local memory of the processing unit. The reserved field is bits 3 to 11 of the 32-bit register, and these 9 bits are kept at 0. The run flag field is bit 2 of the 32-bit register. When this bit is '1', it indicates that the task corresponding to the task sequence number field in the task tag is running. If the value is '1', it indicates that the task corresponding to the task number field in the task label is not running; the loading flag field is bit 1 of a 32-bit register. When this bit is '1', it indicates that the task corresponding to the task number field in the task label is being loaded, and the program and data are being loaded into the local memory corresponding to the processing unit. Otherwise, it indicates that the task corresponding to the task number field in the task label is not being loaded; the loaded flag field is bit 0 of a 32-bit register. When this bit is '1', it indicates that the task corresponding to the task number field in the task label has completed loading the program and data into the local memory corresponding to the processing unit. Otherwise, it indicates that the task corresponding to the task number field in the task label has not been loaded.

[0022] Furthermore, the scheduling logic module has three external interfaces: a memory read / write interface, a processing unit array data packet send / receive interface, and a task start command interface.

[0023] When a new task is loaded, the scheduling logic module reads data from the external memory of the corresponding main controller through the memory read / write interface according to the information stored in the task description register, and writes the read data to the local memory of the processing unit participating in the task execution through the data packet transceiver interface of the processing unit array.

[0024] For a running, loaded task, the scheduling logic module sends a task start command to the processing unit based on the task status recorded in the task tag group.

[0025] Furthermore, the logical functions of the scheduling logic module include:

[0026] After power-on reset, monitor whether there are any data changes in the task load / run register; if there are changes, execute step S2, otherwise repeat step S1.

[0027] S2 checks whether the least significant bit of the task load / run register is set to '1'. If it is set to '1', proceed to step S3. Otherwise, check whether the second least significant bit of the task load / run register is set to '1'. If it is set to '1', proceed to step S8. Otherwise, return to step S1.

[0028] The S3 task description register stores the starting address of the task feature description information, and the task feature description information is read in sequentially.

[0029] S4 calculates the number of banks required by the corresponding program based on the number of program loading words in the task feature description information; analyzes all tag information in the task tag group; if there are tags with invalid flags, write the information of this task into the tag; if there are no tags with invalid flags, according to the first-in-first-out principle, clear the tag of the earliest recorded task and write the information of this task into it.

[0030] The loading flag field of the S5 task label is set to '1', and the task program loading process is started according to the definition of the number of words loaded and the source address of the program.

[0031] S6 starts the data loading process based on the definitions of the number of words loaded, the source address of the data loading, and the destination address of the data loading.

[0032] S7 updates the task label corresponding to the task, sets the loading flag field to '0', sets the loaded flag field to '1', and executes step S1;

[0033] S8 analyzes all tags in the task tag group and determines whether the task to be run has been loaded. If it has not been loaded, it jumps to step S3; if it has been loaded, it executes step S9.

[0034] S9 sends a task start command to the processing unit participating in the task execution according to the start BANK bit field information in the task label corresponding to the task to be executed.

[0035] S10 updates the task label corresponding to the task, sets the run flag field to '1', and ends the logic judgment;

[0036] S11 checks whether the second lowest bit in the task load / run register is set to '1'. If it is set to '1', then proceed to step S9; otherwise, end the logic check.

[0037] Furthermore, in step S4, the scheduling logic module sets two pointers: one to record the BANK loaded by the current task and the other to record the BANK to be loaded by the next task. The pointer to record the BANK loaded by the current task is reset to 0, and the pointer to record the BANK to be loaded by the next task is the pointer to the BANK loaded by the current task plus the number of BANKs required by the task program.

[0038] In step S4, the information written to the task tag includes: the lower 15 bits of the task sequence number register are written to the task sequence number field of this task tag; the value of the BANK pointer of the currently loaded task is written to the start BANK field of this task tag; and the valid flag field of this task tag is set to '1'.

[0039] Furthermore, in step S5, the task program loading process includes:

[0040] At the beginning, the program reads the source address as the program loading source address, writes the program destination address to the storage module corresponding to the starting BANK bit field in the label, reads the program code from the source address, and writes it into the starting BANK of the processing unit participating in the task. Then the program reads the source address and increments it by 1, and reads the program again according to the new address and writes it into the BANK, until the number of times the program reads and writes reaches the number of words loaded by the program.

[0041] In step S6, the data loading process includes:

[0042] Initially, the data read source address is the data load source address, and the data write destination address is the data load destination address. Data is read from the source address and written to the local memory of each processing unit participating in the task. Then, the data read source address and the data write destination address are incremented by 1, and the data read again according to the new address is written to the local memory of the processing unit until the number of data reads and writes reaches the number of task feature description words loaded.

[0043] Compared with the prior art, the present invention has at least one of the following advantages:

[0044] (1) The task scheduler structure of the present invention is fully implemented in hardware. The task loading efficiency is higher than that of software implementation, which can significantly shorten the task loading time. Moreover, this scheduling is not at the instruction level, but at a more macro-level task level. When scheduling, it is not necessary to pay attention to too many instruction execution details, such as instruction fetching, dispatching and condition judgment, but only to the task status. This simplifies the scheduler design and can adapt to the integration of more processing units.

[0045] (2) In the task scheduler structure of the present invention, the main controller is only responsible for simple settings of the "task control register group". The subsequent program and data loading process does not require the participation of the main controller. In this way, the main controller is responsible for the processing of the program part with high seriality and relatively complex processing, while the dynamically reconfigurable chip is responsible for the loop code program part with high parallelism, large data volume and relatively simple flow control. This achieves the combination of the advantages of different architectures, which can improve chip performance and conform to the development trend of high-performance computing.

[0046] (3) When the current task is running, the present invention can load the program and data required for the subsequent task to run in parallel to the processing unit. Once the current task is finished, the subsequent task can be started immediately, hiding the program and data loading time, shortening the dynamic reconstruction time, and ensuring that the task can switch within 1 to 2 clock cycles at the fastest.

[0047] (4) The present invention can load programs and data for all processing units of multiple processing unit arrays, or load programs and data for specific processing units within a specific processing unit array. That is, it can load only programs or only data, which has great flexibility.

[0048] (5) The task scheduler structure of the present invention supports loading multiple tasks. Each task corresponds to a tag. The tag records the starting BANK information of the task loaded into the processing unit. When a task is to be run, the "scheduling logic module" issues a task start command directly according to the starting BANK information in the tag. When multiple task tags are valid, just like the CACHE commonly used in processors, it supports fast switching of multiple tasks. This fast switching of multiple tasks can significantly improve the adaptability and processing performance of the dynamic reconfigurable chip to applications.

[0049] (6) The task scheduler of the present invention can be used not only in dynamically reconfigurable chips, but also in many-core processors with MIMD (Multiple Instruction Multiple Data) architecture, providing programs and data for the operation of processor cores integrated in many-core processors. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of a task scheduler structure for a dynamically reconfigurable chip according to the present invention;

[0051] Figure 2 This is a schematic diagram illustrating the task feature description format of the present invention;

[0052] Figure 3 This is a schematic diagram of the task tag structure of the present invention;

[0053] Figure 4 This is a flowchart illustrating the logical function of the scheduling logic module of the present invention. Detailed Implementation

[0054] The features and advantages of the present invention will become clearer and more apparent from the following detailed description.

[0055] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0056] The dynamically reconfigurable chip task scheduler structure designed in this invention is a dedicated hardware circuit that supports loading programs and data required by multiple subsequent tasks while the current task is running. The scheduler structure includes a task control register group, a task tag group, and a scheduling logic module. The task control register group is set by the external main controller, specifying the task number to be loaded or run, and the task characteristic description address information. The task tag group records the status of each loaded or running task, including whether it has been loaded, whether it is currently running, and the starting memory address of the task loaded into the processing unit. The scheduling logic module analyzes and determines whether to load a new task or run an already loaded task based on the information input from the task control register group and the task tag group, and updates the tag information in the task tag group in a timely manner. This module can read data from the scheduler's external memory through the memory read / write interface according to the program and data addresses and the number of words loaded specified by the relevant registers in the task control register group, and write the read data to the processing unit's private local program memory and local data memory using the processing unit array data packet transceiver interface. In this task scheduler architecture, the main controller is only responsible for simple settings of the task control register group. The subsequent program and data loading process requires no involvement from the main controller. The main controller primarily handles the more serial and complex program parts, improving chip performance in conjunction with the acceleration effect of the processing unit array. This task scheduler architecture can load the program and data required for subsequent tasks into the processing unit while the current task is running. Once the current task finishes, the subsequent task can be started immediately, hiding the program and data loading time and enabling dynamic reconfiguration of the chip's functions. This task scheduler architecture supports loading multiple tasks, each task corresponding to a tag that records information about the local program storage modules involved in running that task. When running a task, the scheduling logic module issues a task start command directly according to the program storage module information in the task label. The processing unit receives the task start command and can start running the task directly from this program storage module. In this way, the scheduling logic module can quickly issue multiple task start commands to achieve rapid switching between multiple tasks. This task scheduler structure is implemented entirely in hardware, and the task loading efficiency is higher than that of software implementation, which can significantly shorten the task loading time. Moreover, this scheduling is not at the instruction level, but at a more macro-level task level. During scheduling, it is not necessary to pay attention to too many instruction execution details, such as instruction fetching, dispatching, and condition judgment, but only to the task status. This simplifies the scheduler design and can accommodate the integration of a larger number of processing units.

[0057] More specifically, this invention employs dedicated hardware circuitry to implement the task scheduler, whose structure includes a task control register group, a task tag group, and a scheduling logic module. The task control register group includes a task sequence number register, a task load / run register, and a task description register, which are configured by the main controller external to the task scheduler structure. Specifically, the task sequence number register defines the sequence number of the task to be loaded or run; the task load / run register defines whether the task has started loading or running; the task description register stores an address, and the seven addresses starting from this address describe the main characteristics of the task. The data in these seven addresses sequentially define the processing unit array information participating in the task's execution, the processing unit information within each processing unit array participating in the task's execution, the number of program words loaded, the program load source address, the number of data words loaded, the data load source address, and the data load destination address. The program load source address and data load source address refer to the starting addresses of the program and data to be loaded into the local program memory and local data memory of the processing unit, defined within the main controller's storage space; the data load destination address is the starting address of the data loaded into the local data memory of the processing unit, defined within the processing unit's storage space. The "task tag group" consists of 16 task tags. Each task tag records the status of a loaded or running task, including whether it has been loaded, whether it is running, and the starting BANK (memory block) information of the processing unit program to which the task is loaded. To enable the processing unit to write new programs and data during runtime, its local storage space is divided into multiple storage BANKs. Each BANK is implemented using an independent storage module. The local storage space of the processing unit can be divided into 4, 8, or 16 BANKs. Thus, the overall local memory of the processing unit consists of 4, 8, or 16 storage modules. The number of task tags matches the number of BANKs. For each processing unit, each BANK has a fixed storage address range. Processing unit BANKs are numbered to distinguish different BANKs. Therefore, once the BANK number corresponding to the task is recorded in the task tag, the corresponding storage module can be found within the processing unit. The scheduling logic module analyzes and determines whether to load a new task or run an already loaded task based on the information input from the task control register group and the task tag group, and updates the task tag information in the task tag group in a timely manner.When loading a new task, this module can read data from the corresponding external memory through the memory read / write interface according to the program, data address and number of words specified in the "task description register", and write the read data to the local program memory and local data memory inside the processing unit using the processing unit array data packet transceiver interface. When running a loaded task, this module issues a task start command to the processing unit participating in the task execution according to the program start BANK information in the corresponding task label.

[0058] Example:

[0059] The task scheduler structure of this invention is as follows: Figure 1 As shown. Figure 1 The system mainly includes 3 modules and 4 sets of external interfaces. The 3 modules are the task control register group 101, the task tag group 102, and the scheduling logic module 103. The 4 sets of external interfaces are the main controller read / write interface 107, the memory read / write interface 108, the processing unit array data packet transceiver interface 109, and the task start command 110.

[0060] The task control register group 101 is connected to the main controller read / write interface 107 and the scheduling logic module 103. The input is to the main controller read / write interface 107, which is responsible for writing data to each register within the register group. The output is connected to the scheduling logic module 103, where the data information of each register is output. The task control register group 101 contains three control registers: the task sequence number register 104, the task load / run register 105, and the task description register 106.

[0061] Task sequence number register 104 is a 32-bit register with its lower 15 bits being valid. It defines the sequence number of the task to be loaded or ready to run. Each task is represented by a sequence number, so a maximum of 32,768 tasks can be distinguished through task sequence number register 104.

[0062] The task load / run register 105 is a 32-bit register with its lower 2 bits being valid. When the lowest bit is set to '1', the task is defined to start loading, and when the second lowest bit is set to '1', the task is defined to start running.

[0063] Task Description Register 106 is a 32-bit register that stores a 32-bit address. This address is the starting address for storing task characteristic description information. The seven addresses starting from this address sequentially store information such as the processing unit array participating in the task execution, the processing unit information within each processing unit array participating in the task execution, and the program and data to be loaded into the local memory of the processing unit. See [link to specific stored content] for details. Figure 2 The task feature description format shown is 200.

[0064] Task tag group 102, consisting of a set of task tags 111, is connected to scheduling logic module 103. The scheduling logic module is responsible for updating the data in the task tags. Task tag group 102 contains 16 task tags 111. Each task tag records the status of a loaded or running task, including whether it has been loaded, whether it is running, and the starting BANK information of the processing unit program to which the task is loaded. To enable the processing unit to write new programs and data during runtime, its local storage space is divided into multiple storage BANKs. Each BANK uses one storage module, which can be divided into 4 BANKs, 8 BANKs, or 16 BANKs. Thus, the overall local memory of the processing unit consists of 4 storage modules, 8 storage modules, or 16 storage modules. The number of task tags is consistent with the number of BANKs. Currently, task tag group 102 contains 16 task tags 111, indicating that the overall local memory of the processing unit consists of 16 storage modules.

[0065] Task label 111 is a 32-bit register (from least significant bit 0 to most significant bit 31) that records the status of a loaded or running task, including whether it has been loaded, whether it is currently running, and the starting BANK information of the processing unit program to which the task has been loaded. The specific format is as follows: Figure 3 As shown.

[0066] The scheduling logic module 103 is a sequential logic circuit connected to the task control register group 101 and the task tag group 102. This module has three external interfaces, which are also the three external interfaces of the entire task scheduler: a memory read / write interface 108, a processing unit array data packet transceiver interface 109, and a task start command 110. This module is mainly responsible for loading tasks or issuing task execution commands based on the information in the task control register group, and updating the task tag information in the task tag group in a timely manner. For loading a new task, this module can read data from the corresponding main controller's external memory through the memory read / write interface 108 according to the program, data source address, and number of words specified in the task description register, and write the read data to the local memory of the processing unit participating in the task execution using the processing unit array data packet transceiver interface 109. For running an already loaded task, this module issues a task start command 110 to the processing unit according to the starting BANK segment number 303 information in the corresponding task tag. The specific logic judgment process is as follows: Figure 4 As shown.

[0067] The main controller read / write interface 107 is a read / write channel between the main controller outside the task scheduler and the relevant registers inside the task scheduler. The main controller reads and writes to the task control register group 101 through this interface. This interface mainly includes input address lines, data lines, read signals, write signals and output bus ready signals.

[0068] The memory read / write interface 108 is a channel for the scheduling logic module 103 to read task-related programs and data. In order to load the task into the local memory of the processing unit participating in the task execution, the scheduling logic module 103 needs to read the program and data corresponding to the task from the addresses specified by the program loading source address 204 and the data loading source address 206 through the memory read / write interface according to the information specified by the task feature description format 200. The memory read / write interface includes output address lines and read signals, and input data lines and bus ready signals.

[0069] The task start command 110 is a start signal sent by the scheduling logic module 103 to the processing unit participating in the task execution. This task start command is a set of signals output in parallel through 5 signal lines. This set of signals represents a 5-bit binary data from high bit to low bit. The highest bit is the task start valid bit. If this bit is '1', it means that the "task start command" is valid. If this bit is '1', it means that the "task start command" is invalid. The lower 4 signal lines are the "start BANK" information in the "task tag" corresponding to the running task.

[0070] Figure 2 The task feature description format 200 consists of 7 fields, each 32 bits. The data registered in the task description register 106 is the starting storage address of these 7 fields. When loading the task, the scheduling logic module 103 can start from this address and read the 7 fields of the task feature description format sequentially. These 7 fields are: Participating PEA Definition 201, Participating PE Definition 202, Program Load Word Count 203, Program Load Source Address 204, Data Load Word Count 205, Data Load Source Address 206, and Data Load Destination Address 207. These 7 fields need to be compiled directly by the compiler before the dynamically reconfigurable chip runs, becoming part of the program in the external memory of the main controller. Figure 2In the task feature description format, the first field, PE definition 201, corresponds to a processing unit array. Each bit corresponds to a processing unit array. When a bit is '1', it indicates that the processing unit array corresponding to that bit will participate in the task's execution. Since this field is 32 bits, it can correspond to a maximum of 32 processing unit arrays. PE definition 202 is the second field, also corresponding to a processing unit in the array. When a bit is '1', it indicates that the processing unit corresponding to that bit will participate in the task's execution. This field is 32 bits long, so it can correspond to a maximum of 32 processing units, meaning the processing unit array can contain a maximum of 32 processing units. The third field, 203, specifies the size of the task program loaded into the processing unit. The lower 16 bits of this field are valid, indicating that the maximum size of the program loaded into the processing unit is 65536 words. The fourth field, 204, specifies the source address of the program loaded into the main controller after compilation. The external memory address is used to read the code corresponding to the task program one by one, starting from this address when loading the program into the processing unit. The data load word count 205 is the 5th field in the task feature description format, specifying the data size required by the task to be loaded into the processing unit. The lower 16 bits of this field are valid, indicating that the maximum data size loaded into the processing unit is 65536 words. The data load source address 206 is the 6th field in the task feature description format, specifying the storage address of the data required for task execution in the external memory of the main controller after compilation. When loading data into the processing unit, the data is read one by one, starting from this address. The data load destination address 207 is the 7th field in the task feature description format, specifying the starting address of the data required for task execution after it is read from the external memory of the main controller and written to the local memory of the processing unit. Starting from this address, the write address increases sequentially for subsequent data read from the external memory of the main controller. When the address increases, it increments by 1 in word addressing mode and by 4 in byte addressing mode.

[0071] Figure 3 For task tag structure, in Figure 3The task tag register consists of 32 bits from least significant bit to most significant bit, with the least significant bit being bit 0 and the most significant bit being bit 31. The 32-bit task tag register is divided into 7 bit fields: valid flag field 301, task sequence number field 302, start BANK field 303, reserved field 304, running flag field 305, loading flag field 306, and loaded flag field 307. The valid flag field 301 is bit 31 of this 32-bit register. When this bit is '1', it indicates that the data in the task tag is valid; otherwise, it is invalid. The task sequence number field 302 is bits 16 to 30 of this 32-bit register, a total of 15 bits, which is the task sequence number corresponding to this task tag. The start BANK field 303 is bits 12 to 15 of this 32-bit register, a total of 4 bits, which is the BANK sequence number of this task loaded into the processing unit's local memory. If this 4-bit data is the binary number '0001', it means that the task is loaded into the storage module corresponding to BANK_1 in the processing unit's local memory; if this 4-bit data is the binary number '0010', it means that the task is loaded into the storage module corresponding to BANK_2 in the processing unit's local memory. The reserved field 304 is bits 3 to 11 of this 32-bit register, and these 9 bits are kept at 0. Bit 305 is bit 2 of this 32-bit register. When this bit is '1', it indicates that the task corresponding to task number bit 302 in the task label is running; otherwise, it indicates that the task corresponding to task number bit 302 in the task label is not running. Bit 306 is bit 1 of this 32-bit register. When this bit is '1', it indicates that the task corresponding to task number bit 302 in the task label is being loaded, loading the program and data into the local memory corresponding to the processing unit; otherwise, it indicates that the task corresponding to task number bit 302 in the task label is not being loaded. Bit 307 is bit 0 of this 32-bit register. When this bit is '1', it indicates that the task corresponding to task number bit 302 in the task label has completed loading the program and data into the local memory corresponding to the processing unit; otherwise, it indicates that the task corresponding to task number bit 302 in the task label has not been loaded.

[0072] Figure 4 As a timing logic unit, the scheduling logic module 103 is illustrated in its logic function flowchart. The flowchart analyzes the control registers and status flag registers of the task control register group 101 and the task tag group 102. Following the flowchart, logical judgments are performed to determine the completion of task loading and task execution control.

[0073] 41) After power-on reset, monitor whether there is any data change in the task load / run register 105; if there is a change, execute step 42); otherwise, repeat step 41).

[0074] 42) Determine if the least significant bit of the task load / run register 105 is set to '1'. If it is set to '1', proceed to step 43). Otherwise, determine if the next least significant bit of the task load / run register 105 is set to '1'. If it is set to '1', proceed to step 48). Otherwise, return to step 41).

[0075] 43) Based on the starting address of the task feature information specified in the task description address register, read in 7 task feature description words in sequence;

[0076] 44) Based on the number of programs loaded (203) in the task feature description information, calculate the number of banks required by the corresponding program of the task. Set two pointers in the scheduling logic module, one to record the bank loaded by the current task and the other to record the bank to be loaded by the next task. The pointer to record the bank loaded by the current task is reset to 0 after reset. The pointer to record the bank to be loaded by the next task is the pointer to the bank loaded by the current task plus the number of banks required by the task program. Analyze all the tag information in the task tag group 102. If there is a tag with an invalid flag, write the information of this task into the tag. If there is no tag with an invalid flag, according to the first-in-first-out principle, clear the tag of the earliest recorded task and write the information of this task into it. The information written into the task tag includes: the lower 15 bits of the task sequence number register 104 are written into the task sequence number field label 302 of this task tag, the value of the current task loaded bank pointer is written into the starting bank field 303 of this task tag, and the valid flag field 301 of this task tag is set to '1'.

[0077] 45) When the task label is loaded, the loading flag field 306 is set to '1'. Based on the definition of the number of program words loaded 203 and the program loading source address 204 in the task feature descriptor, the task program loading process is started. Initially, the program reads the source address as the program loading source address 204 in the task feature descriptor and writes the program destination address to the storage module corresponding to the starting BANK field 303 in the label. The program code is read from the source address and written to the starting BANK of the processing unit participating in the task. Then, the program reads the source address and increments it by 1 (by word addressing), and reads the program again according to the new address and writes it to the BANK, until the number of times the program reads and writes reaches the number of program words loaded 203 in the task feature descriptor.

[0078] 46) Based on the definitions of data loading word count 205, data loading source address 206, and data loading destination address 207 in the task feature descriptor, the data loading process is initiated. Initially, the data read source address is the task feature descriptor data loading source address 206, and the destination address for writing data to the processing unit is the task feature descriptor data loading destination address 207. Data is read from the source address and written to the local memory of each processing unit participating in the task. Then, the data read source address and the data write destination address are incremented by 1 (by word addressing), and the data read again at the new address is written to the local memory of the processing unit until the number of data reads and writes reaches the task feature descriptor data loading word count 205.

[0079] 47) Update the task label corresponding to the task, set the loading flag field 306 to '0', set the loaded flag field 307 to '1', and execute step 51).

[0080] 48) Analyze all tags in task tag group 102 to determine whether the task to be run has been loaded. If not, jump to step 43). If it has been loaded, execute step 49.

[0081] 49) According to the information in the starting BANK bit field 303 in the task label corresponding to the task to be run, issue a task start command 110 to the processing unit participating in the task run.

[0082] 50) Update the "Task Tag" corresponding to the task, set the run flag field 305 to '1', and end the logic judgment.

[0083] 51) Determine if the second least significant bit in the task load / run register 105 is set to '1'. If it is set to '1', proceed to step 49); otherwise, end the logical judgment.

[0084] In summary, this invention provides a task scheduler structure for dynamically reconfigurable chips. It is a dedicated hardware circuit composed of a task control register group, a task tag group, and a scheduling logic module. It is task-level scheduling, supporting the integration of a larger number of processing units. It supports loading programs and data required by subsequent tasks while the current task is running; it supports loading multiple tasks. When a task needs to be run, the scheduling logic module issues a task start command directly according to the loading start BANK information in the task tag, enabling rapid switching between multiple tasks. It can load tasks for all processing units or for specific processing units; it can load only programs or only data, offering great flexibility. This invention is applicable to dynamically reconfigurable chips, especially those with a large number of integrated processing units (PEs) and designed for high-performance computing. This design can improve task loading efficiency, free up the main controller, shorten dynamic reconfiguration time, and improve the overall performance of dynamically reconfigurable chips.

[0085] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

[0086] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A task scheduler structure for dynamically reconfigurable chips, characterized in that, include: Task control register group (101), task tag group (102), and scheduling logic module (103); The task control register group (101) is set by the external main controller; the task control register group (101) includes a task sequence number register (104), a task load / run register (105), and a task description register (106). The task sequence number register (104) defines the task sequence number; the task load / run register (105) defines whether the task has started loading or started running; the task description register (106) stores the starting address of the task characteristic description information. The task tag group (102) contains multiple task tags. Each task tag corresponds one-to-one with a task that has been loaded or is about to be loaded into the dynamic reconfigurable chip. The task tag contains the task number and task status information from the task number register (104). The task tag makes corresponding changes to the control of the task based on the task load / run register (105) and the scheduling logic module (103). The scheduling logic module (103) determines whether the task is a new task to be loaded or a loaded task to be run based on the information in the task load / run register (105). When the task is a new task to be loaded, the scheduling logic module (103) reads data from the corresponding external memory according to the information stored in the task description register (106) and writes the read data to the processing unit; when the task is a loaded task to be run, the scheduling logic module (103) sends a task start command to the processing unit participating in the task execution according to the task status information recorded in the task tag group (102).

2. The task scheduler structure for a dynamically reconfigurable chip according to claim 1, characterized in that, The external main controller writes data into the control register group (101) through the main controller read / write interface (107); The task sequence number register (104) consists of 32 registers, with the lower 15 bits being valid. It defines the sequence number of the task to be loaded or to be run, with each task represented by a sequence number. The task load / run register (105) consists of 32 registers, with the lower 2 bits being valid. When the lowest bit is set to '1', the task load is defined to begin, and when the next lowest bit is set to '1', the task execution is defined to begin.

3. The task scheduler structure for a dynamically reconfigurable chip according to claim 2, characterized in that, The task description register (106) consists of 32 registers; The task feature description information is compiled before the dynamically reconfigurable chip runs and becomes part of the program in the external memory of the main controller. When loading a task, the scheduling logic module (103) reads in the task description register (106) the starting address of the task feature description information stored therein, and reads in the seven fields of the task feature description information in sequence. The seven fields are PEA definition (201), PE definition (202), number of program loaded words (203), program loaded source address (204), number of data loaded words (205), data loaded source address (206), and data loaded destination address (207). The first field is the PEA definition (201), where each bit corresponds to a processing unit array. When a bit is '1', it indicates that the processing unit array corresponding to that bit will participate in the task's execution. The second field is the PE definition (202), where each bit corresponds to a processing unit in the processing unit array. When a bit is '1', it indicates that the processing unit corresponding to that bit will participate in the task's execution. The third field is the program load word count (203), which specifies the size of the task program loaded into the processing unit. The fourth field is the program load source address (204), which specifies the storage address of the task program in the external memory of the main controller after compilation. When loading the program into the processing unit, the task program is read out one by one starting from this address. The code; the number of words loaded (205) is the 5th field, which specifies the size of the data required by the task to be loaded into the processing unit; the data loading source address (206) is the 6th field, which specifies the storage address of the data required by the task to run after compilation by the compiler in the external memory of the main controller. When loading data into the processing unit, the data is read out one by one starting from this address; the data loading destination address (207) is the 7th field, which specifies the starting address of the data required by the task to run after being read from the external memory of the main controller and written to the local memory of the processing unit. Starting from this address, the data to be read from the external memory of the main controller continues to be written to the address in turn. When the address is increased, it is incremented by 1 in word addressing mode and incremented by 4 in byte addressing mode.

4. The task scheduler structure for a dynamically reconfigurable chip according to claim 3, characterized in that, The task tag group (102) contains a set of task tags (111). The number of task tags (111) is consistent with the number of storage banks divided into the local storage space of the processing unit. Each task tag (111) is a 32-bit register that records the status of a loaded or running task. The task status includes whether it has been loaded, whether it is running, and the starting BANK information of the processing unit program to which the task is loaded.

5. A task scheduler structure for a dynamically reconfigurable chip according to claim 4, characterized in that, The task tag (111) is 32 bits long from the least significant bit to the most significant bit, with the least significant bit being bit 0 and the most significant bit being bit 31. The 32-bit task tag register is divided into 7 bit fields, namely the valid flag field (301), the task sequence number field (302), the start BANK field (303), the reserved field (304), the running flag field (305), the loading flag field (306), and the loaded flag field (307).

6. The task scheduler structure for a dynamically reconfigurable chip according to claim 5, characterized in that, The valid flag field (301) is bit 31 of the 32-bit register. When this bit is '1', it indicates that the data in the task tag is valid; otherwise, it is invalid. The task sequence number field (302) is bits 16 to 30 of the 32-bit register, a total of 15 bits, which is the task sequence number corresponding to the task tag. The start BANK field (303) is bits 12 to 15 of the 32-bit register, a total of 4 bits, which is the BANK sequence number loaded into the local memory of the processing unit. The reserved field (304) is bits 3 to 11 of the 32-bit register, and these 9 bits are kept at 0. The run flag field (305) is bit 2 of the 32-bit register. When this bit is '1', it indicates that the task corresponding to the task sequence number field (302) in the task tag is running; otherwise, it indicates that the task is not running. The task corresponding to the task number field (302) in the task label is not running; the loading flag field (306) is bit 1 of the 32-bit register. When this bit is '1', it indicates that the task corresponding to the task number field (302) in the task label is being loaded, and the program and data are being loaded into the local memory corresponding to the processing unit. Otherwise, it indicates that the task corresponding to the task number field (302) in the task label is not being loaded; the loaded flag field (307) is bit 0 of the 32-bit register. When this bit is '1', it indicates that the task corresponding to the task number field (302) in the task label has completed loading the program and data into the local memory corresponding to the processing unit. Otherwise, it indicates that the task corresponding to the task number field (302) in the task label has not been loaded.

7. The task scheduler structure for a dynamically reconfigurable chip according to claim 1, characterized in that, The scheduling logic module (103) has three external interfaces: a memory read / write interface (108), a processing unit array data packet send / receive interface (109), and a task start command (110). When a new task is loaded, the scheduling logic module (103) reads data from the external memory of the corresponding main controller through the memory read / write interface (108) according to the information stored in the task description register (106), and writes the read data to the local memory of the processing unit participating in the task execution through the data packet transceiver interface (109). For a running and loaded task, the scheduling logic module (103) sends a task start command (110) to the processing unit according to the task status recorded in the task tag group (102).

8. A task scheduler structure for a dynamically reconfigurable chip according to claim 6, characterized in that, The logical functions of the scheduling logic module (103) include: After power-on reset, monitor whether there are any data changes in the task load / run register (105); if there are any changes, execute step S2; otherwise, repeat step S1. S2 determines whether the least significant bit of the task load / run register (105) is set to '1'. If it is set to '1', then proceed to step S3. Otherwise, determine whether the second least significant bit of the task load / run register (105) is set to '1'. If it is set to '1', then proceed to step S8. Otherwise, return to step S1. The S3 task description register (106) stores the starting address of the task feature description information, and the task feature description information is read in sequentially; S4 calculates the number of BANKs required by the program corresponding to the task based on the number of program loading words (203) in the task feature description information; analyzes all tag information in the task tag group (102); if there is an invalid tag, write the information of this task into the tag; if there is no invalid tag, according to the first-in-first-out principle, clear the tag of the earliest recorded task and write the information of this task into it. The loading flag field (306) of the S5 task label is set to '1', and the task program loading process is started according to the definition of the number of words loaded (203) and the source address of the program loading (204). S6 starts the data loading process based on the definitions of the number of words loaded (205), the source address of the data loading (206), and the destination address of the data loading (207); S7 updates the task label corresponding to the task, sets the loading flag field (306) to '0', sets the loaded flag field (307) to '1', and executes step S1; S8 analyzes all tags in the task tag group (102) to determine whether the task to be run has been loaded. If it has not been loaded, it jumps to step S3. If it has been loaded, it executes step S9. S9 sends a task start command to the processing unit participating in the task execution according to the start BANK bit field (303) information in the task label corresponding to the task to be executed; S10 updates the task label corresponding to the task, sets the run flag field (305) to '1', and ends the logic judgment; S11 checks whether the second least significant bit in the task load / run register (105) is set to '1'. If it is set to '1', then step S9 is executed; otherwise, the logic judgment ends.

9. A task scheduler structure for a dynamically reconfigurable chip according to claim 8, characterized in that, In step S4, the scheduling logic module (103) sets two pointers, one to record the BANK loaded by the current task and the other to record the BANK to be loaded by the next task. The pointer to record the BANK loaded by the current task is 0 after being reset, and the pointer to record the BANK to be loaded by the next task is the pointer to the BANK loaded by the current task plus the number of BANKs required by the task program. In step S4, the information written into the task tag includes: the lower 15 bits of the task sequence number register (104) are written into the task sequence number field (302) of this task tag; the value of the BANK pointer of the currently loaded task is written into the start BANK field (303) of this task tag; and the valid flag field (301) of this task tag is set to '1'.

10. A task scheduler structure for a dynamically reconfigurable chip according to claim 8, characterized in that, In step S5, the task program loading process includes: At the beginning, the program reads the source address as the program loading source address (204), writes the program destination address to the storage module corresponding to the starting BANK bit field (303) in the tag, reads the program code from the source address, and writes it into the starting BANK of the processing unit participating in the task. Then the program reads the source address and increments it by 1, and reads the program again according to the new address and writes it into the BANK until the number of times the program reads and writes reaches the number of program loading words (203). In step S6, the data loading process includes: Initially, the data read source address is the data load source address (206), and the data write destination address is the data load destination address (207). Data is read from the source address and written to the local memory of each processing unit participating in the task. Then, the data read source address and the data write destination address are incremented by 1, and the data read again according to the new address is written to the local memory of the processing unit until the number of data reads and writes reaches the number of task feature description words loaded (205).

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