Thermal-electric collaborative optimization method and architecture of three-dimensional semiconductor device

Abstract

The invention relates to a three-dimensional semiconductor device, a preparation method thereof and a thermal management scheme. The device includes a three-dimensional active structure and a functional thermal management body integrated with and thermally coupled to the structure. At least one thermal physical attribute of the thermal management body is configured to be in non-uniform continuous distribution in space so as to realize collaborative optimization of thermal and electrical properties of the three-dimensional active structure. The preparation method comprises the following steps: providing a three-dimensional active structure; based on the heat source, electric field or stress distribution of the structure, determining a target distribution function of thermophysical attributes through reverse design; and a material synthesis or structure assembly process is regulated and controlled according to the function, so that a thermal management body with corresponding non-uniform distribution attributes is formed and integration is completed. Through integrated heat management with designable attributes, the heat dissipation efficiency and the electrical performance of the device are effectively improved, meanwhile, the process is simplified, materials are saved, and the comprehensive cost is remarkably reduced. The method is suitable for surrounding gate transistors, fin field effect transistors, three-dimensional stacked memories and other chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing and integration, specifically to a three-dimensional semiconductor device with integrated thermal management function, its fabrication method, related architecture and design method, and in particular to a technical solution for achieving thermal-electric synergistic optimization through the non-uniform continuous distribution of thermophysical properties. Background Technology

[0002] With the development of three-dimensional integration technologies, such as three-dimensional fin field-effect transistors, gate-all-around transistors, and three-dimensional chip stacking, the power density of devices has increased dramatically, and complex vertical non-planar heat flow paths have been introduced, resulting in a significant increase in local hot spots and thermal resistance, which has become a key bottleneck restricting their performance and reliability.

[0003] See reference 1: Patent CN202410391211.6 "Semiconductor Devices and Fabrication Methods, Packaging Structures, Electronic Equipment", which clearly points out the local hotspot problem caused by the complexity of heat flow paths in three-dimensional integration. Currently, the solutions attempted in the industry have inherent limitations.

[0004] On the other hand, cutting-edge research has confirmed the effectiveness of active thermal management solutions based on advanced functional materials. For example, recent research shows that oriented bismuth telluride-based thin films can be used to construct high-performance planar thermoelectric cooling devices, effectively eliminating local hot spots on chips (see Non-Patent Literature 2: "Oriented Thin Films Based on Bi2Te3 Enable High-Performance Planar Thermoelectric Cooling Devices to Eliminate Hot Spots"). This provides strong theoretical support for the present invention to achieve active and precise thermal management using functional materials.

[0005] Currently, cutting-edge research in the field, addressing the severe thermal challenges posed by 3D integration, still focuses on resolving localized heat dissipation bottlenecks. For example, recent research indicates that even at the nanoscale, achieving efficient interfacial thermal transport to reduce interfacial thermal resistance remains a key challenge limiting device performance. See Non-Patent Literature 3: Research by Xiong Yucheng et al. from the School of Mechanical Engineering, Donghua University, published in ACS Appl. Mater. Interfaces, on achieving ultra-low interfacial thermal resistance to solve the heat dissipation bottleneck of nanoelectronic devices. This type of research represents the mainstream technical approach of optimizing thermal performance from a single interface or localized perspective.

[0006] Currently, no existing technology has publicly disclosed or taught how to integrate and thermally couple a functional thermal management system with a spatially non-uniformly distributed thermophysical property with a three-dimensional active structure, and how to achieve proactive and synergistic thermo-electric optimization through multi-physics reverse design. The fundamental limitation of existing technologies lies in the disconnect between thermal management and electrical design, failing to treat the distribution of the thermal management system's physical properties as a proactively designable variable to systematically reconcile the contradictions among multiple physical fields such as heat, electricity, and stress. Purpose of the invention

[0007] The core of this invention lies in proposing a **paradigm-level solution**: establishing the 'functional thermal management body' and its 'non-uniformly distributed thermophysical properties' as an **intrinsic design dimension** inseparable from the three-dimensional active structure, and achieving **multi-physics synergistic optimization of thermal field, electric field, and stress field** through reverse design, thereby breaking through the performance bottleneck of traditional independent design at the system level. Summary of the Invention

[0008] The present invention aims to overcome the shortcomings of the prior art and provide a novel semiconductor device, fabrication method, architecture and design method. Its core lies in the use of a "functional thermal management body" that is deeply integrated with and thermally coupled to a three-dimensional active structure. At least one thermophysical property of the management body is spatially non-uniformly and continuously distributed, thereby actively realizing the "thermal-electric synergistic optimization" of the three-dimensional active structure.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: First, the present invention provides a semiconductor device comprising a three-dimensional active structure and a functional thermal management component integrated with and thermally coupled to the three-dimensional active structure. The functional thermal management component is configured such that at least one of its thermophysical properties is spatially non-uniformly and continuously distributed to achieve thermo-electric synergistic optimization of the three-dimensional active structure. The thermophysical properties include, but are not limited to, thermal conductivity, coefficient of thermal expansion, or specific heat capacity. The three-dimensional active structure includes, but is not limited to, a gate-all-around transistor, a fin field-effect transistor, or a multilayer stacked nanosheet structure.

[0010] Second, the present invention provides a method for fabricating the aforementioned semiconductor device. This method includes providing a three-dimensional active structure and forming a functional thermal management body integrated with and thermally coupled to the three-dimensional active structure. The step of forming the functional thermal management body includes controlling the material synthesis or structure assembly process according to a target distribution function, so that at least one thermophysical property of the thermal management body forms a non-uniform continuous distribution, the distribution being used to achieve thermo-electric synergistic optimization of the three-dimensional active structure.

[0011] Third, this invention provides a three-dimensional heterogeneous integrated semiconductor device architecture. It includes a three-dimensional channel structure with a vertical non-planar heat flow path, and a functional thermal management component integrated with and thermally coupled to the three-dimensional channel structure. Specifically, at least one thermophysical property of the functional thermal management component is spatially non-uniformly and continuously distributed, and this distribution is a thermo-electric co-optimization function designed inversely based on the heat source, electric field, or stress distribution of the three-dimensional channel structure.

[0012] Fourth, the present invention provides a method for fabricating the above-mentioned three-dimensional heterogeneous integrated semiconductor device architecture. The method includes: determining a target distribution function of thermophysical properties through reverse design based on the heat source, electric field, or stress distribution of a three-dimensional channel structure; forming a functional thermal management body with non-uniform continuous distribution of thermophysical properties according to the target distribution function through material synthesis or structural assembly, and integrating and thermally coupling it with the three-dimensional channel structure.

[0013] Fifth, the present invention provides a chip that integrates any of the semiconductor devices or architectures described in the preceding claims.

[0014] Sixth, the present invention provides an electronic device comprising the aforementioned chip.

[0015] Seventh, the functional thermal management body of the present invention includes a functional composite material having gradient components, gradient microstructures, or combinations thereof, wherein the gradient variation corresponds to a non-uniform continuous distribution of the thermophysical properties.

[0016] Eighth, this invention provides an automated electronic design method for achieving thermo-electric synergistic optimization design. The method includes: acquiring heat source and electric field distribution information of a three-dimensional device structure; and generating a target distribution function of thermophysical properties based on the heat source and electric field distribution information using a reverse optimization algorithm. The target distribution function is generated through a thermo-electric coupling simulation model, which includes multi-physics field correlation parameters of thermal conductivity, electrical conductivity, and stress, or derived variables based on these parameters. This invention treats the "spatial non-uniform continuous distribution of thermophysical properties" as a novel, actively designable dimension and integrates it with a three-dimensional active structure. Through the reverse design method, the property distribution of the thermal management body can be customized and optimized for specific heat sources, electric fields, and stress fields, thereby fundamentally achieving a synergistic improvement in thermal management and electrical performance, and solving the problem of multi-physics field coupling mismatch in three-dimensional integration. Beneficial effects

[0017] Compared with the prior art, the technical solution provided by the present invention can produce the following significant beneficial effects: 1. Superior thermal management performance: Through non-uniform continuous distribution of thermophysical properties, especially gradient thermal conductivity design, it can efficiently guide heat to diffuse from hot spots with high power density, significantly reduce peak junction temperature, and improve temperature uniformity inside the chip.

[0018] 2. Direct electrical performance gains: The thermal-electric synergistic optimization mechanism can directly improve carrier mobility, reduce leakage current, and improve signal integrity by reducing thermal carrier scattering, suppressing thermally induced threshold voltage drift, and optimizing thermal stress distribution, thereby improving device speed and stability.

[0019] 3. Synergistic Optimization and System-Level Energy Efficiency Leap: The aforementioned thermal and electrical improvements are not simply additive, but rather generate nonlinear synergistic gains. For example, improved heat dissipation enhances electrical performance, while optimized electrical performance reduces dynamic power consumption, which in turn further alleviates the heat dissipation burden, forming a positive cycle that ultimately achieves a leap in system-level performance per watt. This nonlinear synergistic gain between thermal and electrical systems constitutes a **system-level energy efficiency positive cycle**, providing a physical basis for fundamentally reducing the total cost of ownership (TCO) of chips.

[0020] 4. Higher integration density and reliability: The integrated thermal management unit avoids the space occupied by bulky external heat dissipation components, allowing for more compact three-dimensional stacking. At the same time, by matching the thermal expansion coefficient gradient, it can effectively alleviate thermal mismatch stress between heterogeneous materials, significantly improving the long-term reliability of the device.

[0021] 5. Significant Cost Reduction Potential: This invention fundamentally optimizes the device physics at the device level, reducing reliance on complex external cooling systems. Combined with scalable gradient material fabrication processes (such as improved chemical vapor deposition), it is expected to significantly reduce the overall thermal management cost of advanced chips, bringing substantial economic value to industrialization. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structural relationship of a three-dimensional semiconductor device provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram illustrating the principle of spatial distribution of the thermophysical properties of a functional thermal management body in one embodiment of the present invention.

[0024] Figure 3 This is a flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram comparing the thermo-electric performance of a device using an embodiment of the present invention with that of a device using a conventional uniform thermal management scheme.

[0026] It should be noted that the structures, distributions, processes, and data shown in the accompanying figures are merely examples to help understand the core ideas of this invention and are not intended to limit the invention. Any variation based on the core idea of ​​"achieving thermo-electric synergistic optimization with a three-dimensional active structure through a functional thermal management body with non-uniformly continuously distributed thermophysical properties" should fall within the scope of protection of this invention. Detailed Implementation Example 1

[0027] This embodiment provides a three-dimensional semiconductor device based on a functional thermal management device, its fabrication method, architecture, and electronic design automation (EDA) method. It demonstrates the core idea of ​​the invention from a principle perspective: by integrating and thermally coupling a functional thermal management device with a three-dimensional active structure, at least one of its thermophysical properties is spatially distributed in a non-uniform and continuous manner, thereby achieving thermal-electric synergistic optimization. This embodiment does not involve any specific data, software, or experimental results; it only illustrates "how to achieve" and enhances the credibility of the technology through non-limiting examples. I. Device Structure

[0028] The semiconductor device comprises two core components:

[0029] Three-dimensional active structure: Defined as any semiconductor active device structure with a three-dimensional configuration, characterized by the existence of a vertical non-planar heat flow path (the heat flow direction is not uniformly distributed in three-dimensional space).

[0030] Specific types include, but are not limited to: gate-all-around transistors (GAA), fin field-effect transistors (FinFET), multilayer stacked nanosheet structures, three-dimensional heterogeneous integrated channel arrays (such as Si / SiGe / GaN stacks), and any active unit in three-dimensional chip stacks (3D ICs).

[0031] Functional thermal management unit: Integration and coupling method: Physically integrated and thermally coupled with the three-dimensional active structure (e.g., conformal coverage, embedded integration, interface bonding, gap filling, or any suitable method) to ensure an efficient heat transfer path between the thermal management unit and the active structure.

[0032] Core function: Configured to have at least one thermophysical property that is spatially non-uniformly continuous; Thermophysical properties include, but are not limited to, thermal conductivity, coefficient of thermal expansion, specific heat capacity, or combinations thereof. Non-uniform continuous distribution: refers to thermophysical properties that change regularly with spatial coordinates (such as x / y / z axis directions) (e.g., gradient increase / decrease, periodic fluctuation, function fitting curve, etc.), rather than discrete abrupt changes or uniform distribution; Material realization: The functional thermal management body includes a functional composite material having gradient components, gradient microstructures, or combinations thereof. Gradient composition: The chemical composition of a material (such as doping concentration, element ratio, phase composition) changes continuously along the spatial direction (e.g., from 100% of component A to 100% of component B). Gradient microstructure: The microstructure of a material (such as porosity, grain size, nanostructure density, and surface morphology) changes continuously along the spatial direction (e.g., the density of a nanopillar array gradually changes from dense to sparse). Combined gradient: The superposition of two or more gradient forms mentioned above (such as the orthogonal distribution and periodic alternation of component gradients and microstructure gradients). II. Preparation Method

[0033] The method for fabricating the semiconductor device includes the following steps, the core of which is to generate a target distribution function through reverse design and to control the material synthesis / structure assembly to achieve a non-uniform distribution:

[0034] Provide three-dimensional active structures: fabricate target three-dimensional active structures through any suitable semiconductor process (such as photolithography, etching, epitaxial growth, atomic layer deposition, bonding, etc.).

[0035] Forming a functional thermal management system: Step S1 (Reverse Design of Target Distribution Function): Input: Obtain the heat source distribution, electric field distribution, or stress distribution of the three-dimensional active structure. For example: Simulate the heat source distribution by constructing a three-dimensional finite element model of the device and inputting the power consumption spectrum; Obtain the electric field distribution by solving the Poisson equation; Estimate the stress distribution through thermo-mechanical coupling simulation; Algorithm: Through inverse optimization algorithm, with the goal of thermo-electric synergistic optimization (e.g., minimizing thermal resistance, maximizing electrical performance stability, balancing thermal stress, etc.), the target distribution function of thermophysical properties is generated; For example: a topology optimization algorithm with "peak temperature" and "threshold voltage offset" as common optimization objectives can be used; or a neural network model trained with thermo-electric coupling data can be used for prediction and inversion.

[0036] Step S2 (Controlling Material Synthesis / Structure Assembly): Based on the target distribution function, control any suitable material synthesis or structure assembly process to achieve the non-uniform continuous distribution of the thermophysical properties of the functional thermal management body. Material synthesis control: By adjusting parameters such as precursor type, flow rate, deposition temperature / pressure, reaction time, pulse sequence (e.g., chemical vapor deposition CVD, atomic layer deposition ALD, solution method, sol-gel method, etc.), gradient changes in composition or microstructure can be achieved; Structural assembly control: Using micro-nano fabrication techniques (such as photolithography, nanoimprinting, self-assembly, laser interference, etc.), composite materials with gradient microstructures (such as periodically arranged nanostructure arrays, foam structures with varying porosity) are constructed. III. Three-dimensional heterogeneous integration architecture

[0037] This embodiment further provides a three-dimensional heterogeneous integrated semiconductor device architecture, which includes: a three-dimensional channel structure: having a vertical non-planar heat flow path (such as a multi-layer stacked heterogeneous channel layer, such as Si / SiGe, GaAs / InP, organic / inorganic semiconductor stack), as a core electrical functional layer;

[0038] Functional thermal management body: integrated with and thermally coupled to the three-dimensional channel structure, the non-uniform continuous distribution of its thermophysical properties is a thermo-electric synergistic optimization function designed in reverse based on the heat source, electric field or stress distribution of the three-dimensional channel structure (i.e. the target distribution function is directly related to the multi-physics field distribution of the channel). IV. Electronic Design Automation

[0039] This embodiment also provides an electronic design automation (EDA) method for thermo-electric co-optimization design, including: obtaining distribution information: obtaining heat source distribution information and electric field distribution information of the three-dimensional device structure through conventional means in the art (such as model building with simulation tools and data acquisition with measuring instruments);

[0040] Generate the target distribution function: Based on the heat source and electric field distribution information, the target distribution function of the thermophysical properties is generated through an inverse optimization algorithm (such as a multi-objective optimization algorithm combined with machine learning, a heuristic search algorithm, etc.); Simulation model support: The target distribution function is generated through a thermo-electric coupling simulation model, which includes multi-physics field correlation parameters of thermal conductivity, electrical conductivity and stress.

[0041] For example, the model may include a piezoelectric coefficient tensor representing how thermal stress affects carrier mobility, or a temperature coefficient parameter representing how the temperature field changes the dielectric constant and thus affects the electric field distribution. Synergistic optimization is achieved by solving the simultaneous equations of these coupled parameters. V. Open Protection and Scope Statement

[0042] This embodiment is merely an exemplary illustration of the principles of the present invention, and any implementation based on the following core ideas falls within the protection scope of the present invention:

[0043] Core idea: Through a "functional thermal management body integrated with and thermally coupled to a three-dimensional active structure," and its "non-uniform continuous distribution of thermophysical properties," "thermal-electric synergistic optimization" is achieved.

[0044] Coverage variants (non-limiting list): Specific types of three-dimensional active structures (e.g., GAA, FinFET, nanosheet stacks, heterogeneous integrated channel arrays); Specific types of thermophysical properties (e.g., thermal conductivity, coefficient of thermal expansion, specific heat capacity, or combinations thereof); Specific forms of non-uniform continuous distributions (e.g., gradient, periodicity, function fitting, etc.); Material systems of functional thermal management systems (e.g., semiconductors, ceramics, polymer-based composites, phase change materials, etc.); Specific processes of fabrication methods (e.g., ALD, CVD, nanoimprinting, self-assembly, laser modification, etc.); Specific types of inverse optimization algorithms (e.g., topology optimization, genetic algorithms, deep learning models, etc.); Specific parameters of simulation models in EDA methods (e.g., multiphysics correlation parameters, derived variables, etc.).

[0045] It should be noted that this embodiment aims to demonstrate the core principles and implementation logic of the present invention. The specific implementation methods involved, such as the three-dimensional active structure, thermophysical properties, material systems, and preparation processes, are all examples.

[0046] Any variation based on the core principle of 'achieving thermo-electric synergistic optimization through non-uniformly distributed thermophysical properties' falls within the protection scope of this invention. This embodiment provides principle support for claims 1-11. Example 2

[0047] This embodiment provides a three-dimensional heterogeneous integrated semiconductor device architecture based on a vertical non-planar heat flow path and its fabrication method. (Supporting claims 1, 3, 4, and 5)

[0048] The core of the aforementioned three-dimensional heterogeneous integrated semiconductor device architecture lies in: First, a three-dimensional channel structure. This includes at least one vertically penetrating conductive via, such as a silicon via, filled with a conductive material such as copper, tungsten, or carbon nanotubes. Heterogeneous channel layers, such as silicon-germanium heterojunctions or III-V compound semiconductor layers, are integrated into the sidewalls or gaps of the conductive via, thereby forming a vertically stacked channel array. This structure is characterized by a vertically non-planar heat flow path, meaning that the heat transfer direction and the electrical signal transmission path intertwine in three-dimensional space.

[0049] Second, a functional thermal management device. This thermal management device is integrated with and thermally coupled to the three-dimensional channel structure. At least one of its thermophysical properties, such as thermal conductivity or coefficient of thermal expansion, exhibits a non-uniform, continuous distribution along the vertical direction. As an example of a gradient design: the thermal management device has high thermal conductivity near the substrate region to quickly dissipate heat accumulated at the bottom; moderate thermal conductivity in the middle region to balance heat dissipation efficiency with mechanical stress; and low thermal conductivity at the top region to suppress heat crosstalk to the top device layer. The material system of the functional thermal management device may include semiconductor materials, ceramic materials, polymer-based composite materials, or combinations thereof.

[0050] The method for preparing the architecture includes the following steps: Step S21, heterogeneous channel fabrication: a vertically stacked heterogeneous channel layer is formed on the substrate through epitaxial growth, bonding or deposition processes.

[0051] Step S22, conductive via fabrication: using laser drilling, deep reactive ion etching or wet etching processes to form conductive vias that penetrate the heterogeneous channel layer.

[0052] Step S23, Thermal Management Body Integration: This step is crucial in this embodiment. First, based on simulation analysis of the heat source distribution and electric field distribution of the three-dimensional channel structure, a target distribution function of the thermophysical properties is determined through reverse design. Then, according to this target distribution function, the material synthesis or structural assembly process is controlled to form the thermal management body.

[0053] Exemplary processes include, but are not limited to: atomic layer deposition gradient deposition process, which forms a gradient film with decreasing thermal conductivity along a specific direction on the sidewall of a conductive via by precisely adjusting the ratio of precursor pulses; or laser-induced modification process, which uses a femtosecond laser to scan the surface and achieves a gradient distribution of amorphous and crystalline phase transitions of the material by controlling the local melting and recrystallization process.

[0054] Through the above scheme, the functional thermal management body achieves thermal-electric synergistic optimization based on its non-uniform thermophysical property distribution. The mechanism is reflected in: In terms of thermal performance, the vertical thermal resistance is significantly reduced, and the peak temperature of the top device layer is effectively controlled. In terms of electrical performance, thanks to the uniform distribution of thermal stress, the carrier mobility and electrical stability in the heterochannel layer are significantly improved. In terms of reliability, the gradient design of the coefficient of thermal expansion helps alleviate thermal mismatch stress between heteromaterial interfaces, thereby extending the device's operating life.

[0055] It should be noted that the specific forms of the three-dimensional channel structure, the thermal management body material system, and the various preparation processes listed in this embodiment are merely examples to help understand the technical solution of the present invention and are not intended to limit the present invention. Any technical solution that combines a "three-dimensional channel structure with a vertical non-planar heat flow path" with a "functional thermal management body with non-uniform and continuous distribution of thermophysical properties" to achieve synergistic optimization falls within the protection scope of the present invention. Example 3

[0056] This embodiment provides an electronic design automation method based on reverse engineering, and elaborates on the application prospects of the technical solution of the present invention in multiple high-value technology fields, aiming to demonstrate its wide applicability and core strategic value.

[0057] The aforementioned electronic design automation method is used to achieve thermal-electric co-optimization design of semiconductor devices. Its core process is based on advanced algorithms such as artificial intelligence, including: First, input data acquisition. This involves acquiring multiphysics distribution information of the three-dimensional device structure to be designed, including but not limited to heat source distribution information, electric field distribution information, and stress distribution information obtained through simulation or actual measurement.

[0058] Second, inverse optimization and function generation. A multi-objective optimization algorithm or machine learning model is used as the core optimization engine. This engine aims at "thermal-electrical synergistic optimization," such as simultaneously minimizing the peak temperature in the channel region, maximizing the uniformity of carrier mobility, and minimizing the drift of electrical parameters caused by thermal stress. During the optimization process, material physical limits and fabrication process feasibility can be introduced as constraints. Ultimately, this process generates a thermophysical property target distribution function that meets the optimization objectives. This function defines the non-uniform continuous distribution of properties such as thermal conductivity and coefficient of thermal expansion in the device space.

[0059] Third, process mapping and output. The target distribution function is converted into process control parameters for material synthesis or structural assembly that can guide production, such as pulse sequences for atomic layer deposition, scanning paths for laser processing, or template designs for nanoimprinting. This method can include virtual verification and iterative optimization steps, forming a closed loop of "design-verification-optimization" to continuously improve design quality. Based on the above core ideas, the technical solution of this invention can be widely applied in the following semiconductor technology fields with stringent requirements for the synergy of thermal management and electrical performance, achieving a disruptive breakthrough by implementing a "thermal management body with non-uniform thermophysical property distribution": 1. High-performance computing chips: applied to multi-core stacked architectures such as CPUs and GPUs, solving the "thermal wall" bottleneck under high-density integration and improving the energy efficiency of data centers and supercomputing centers; 2.5G / 6G millimeter-wave RF chip: Optimizes heat distribution for devices such as high-frequency power amplifiers to suppress electromagnetic interference and ensure signal integrity of communication base stations and satellite payloads; 3. Power modules for new energy vehicles: integrated into automotive-grade power devices (such as IGBTs and SiC MOSFETs), mitigating driving vibration stress by matching the thermal expansion coefficient gradient, and improving the reliability of the electric drive system; 4. Wearable devices and flexible electronics: Designing thermal management devices that adapt to the deformation of flexible substrates, achieving efficient heat dissipation while maintaining device flexibility and wearability comfort; 5. Quantum computing chips: Develop thermal management devices with dynamic thermal property responses to ensure quantum coherence in the extremely low-temperature operating environment of superconducting qubits; 6. Optoelectronic devices: Optimize the internal thermal field of vertical cavity surface-emitting lasers and high-speed photodetectors, suppress the thermal lensing effect, and improve the performance of optical communication and sensing systems; 7. Aerospace Microelectromechanical Systems: Designing special gradient thermal management devices for sensors operating in extreme environments to achieve efficient passive heat dissipation and active thermal control; 8. Medical electronic implantable devices: Utilizing biocompatible gradient materials, these devices achieve efficient thermal management within the human body while ensuring long-term biocompatibility. It should be particularly noted that the reverse design process and multi-scenario applications described in this embodiment **especially fully support the electronic design automation method protected by the claims**, and demonstrate its universality in achieving thermal-electric synergistic optimization in various cutting-edge fields. The above list of application areas is merely illustrative (not exhaustive) to illustrate the broad applicability and significant industrial value of the present invention. Any semiconductor and related technical field that adopts the core idea of ​​this invention, namely "achieving thermal-electric synergistic optimization through a functional thermal management body integrated with and thermally coupled to a three-dimensional active structure, with non-uniformly continuous distribution of thermophysical properties," regardless of its specific product form, falls within the protection scope of this invention. (Supporting claims 7-11) Example 4

[0060] An example of an ultra-low-cost thermal management scheme for three-dimensional stacked memory (supporting claims 1-11) This embodiment provides a thermal management scheme for three-dimensional semiconductor devices based on gradient composite materials and reverse design. Through theoretical deduction and process analysis, it demonstrates how the scheme can significantly reduce manufacturing costs while achieving "thermal-electric synergistic optimization".

[0061] I. Application Scenarios and Core Structure: Taking the three-dimensional stacked memory chips (3DNAND) in high-bandwidth memory (HBM) as an example application scenario.

[0062] This application scenario faces the severe challenges of complex vertical non-planar heat flow paths and increased thermal resistance caused by three-dimensional stacking, as clearly pointed out in document 1: Huawei patent CN202410391211.6.

[0063] The semiconductor device includes: a three-dimensional active structure: a vertically stacked multilayer memory cell array with a significant vertical non-planar heat flow path (the heat flow direction coincides with the stacking direction).

[0064] Functional thermal management component: a "dual-gradient" composite material that fills the gaps between chip stacks and covers the sidewalls. Its basic structural relationship can be found in [reference needed]. Figure 1 As shown.

[0065] The material system uses epoxy resin as the matrix (thermal conductivity k_{low} \approx 0.2 \, \text{W / m·K}), in which thermally conductive fillers (such as a mixture of spherical alumina (k_{Al_2O_3} \approx 30 \, \text{W / m·K}) and boron nitride sheets (k_{BN} \approx 300 \, \text{W / m·K}) are dispersed in a specific spatial distribution. The equivalent thermal conductivity of the high thermal conductivity filler after mixing is denoted as k_{high} \approx 150 \, \text{W / m·K}.

[0066] II. Non-uniform Design of the Thermal Management Body and Its Cost Implications The core material principle for achieving this non-uniform distribution in this invention has been confirmed by cutting-edge research, as evidenced by Reference 2: The core idea of ​​using functional material bodies for thermal management in this invention has been proven. It has been demonstrated that advanced thin film materials based on bismuth telluride can be used to construct high-performance cooling devices and effectively eliminate hot spots. This theoretically supports the feasibility of achieving efficient, directional thermal management using materials science and device engineering. This embodiment cites Reference 2 only to illustrate the limitations of conventional solutions and does not imply that the implementation of this invention depends on the specific structure or solution described in that reference. The functional thermal management body is configured such that its thermal conductivity and coefficient of thermal expansion are non-uniformly and continuously distributed in the vertical stacking direction (Z-axis). This distribution is achieved through the following composite gradient, which is directly related to cost control: 2.1 Compositional Gradient (Achieving High Performance with Low-Cost Materials): The volume fraction of the thermally conductive filler decreases continuously from a high proportion (e.g., 65 Vol%) near the high heat source area of ​​the chip to a low proportion (e.g., 20 Vol%) away from the heat dissipation shell of the chip. This design allows high-cost thermally conductive fillers to be precisely applied only to the areas that require the most heat dissipation, rather than being uniformly applied throughout the entire package, thereby achieving global optimization of material costs while ensuring heat dissipation performance.

[0067] 2.2 Microstructure gradient (one-step molding replaces multi-step process): By controlling the molding process, the boron nitride sheet filler exhibits an orientation gradient in the thickness direction (Z-axis) (represented by orientation degree O(z), where O=1 represents completely planar orientation and O=0 represents random orientation). Near the chip (z=0), O(z)=0.9 to establish an efficient planar thermal conduction path; further away from the chip (z=L, where L is the stack gap thickness), O(z)=0.2 to provide mechanical support.

[0068] This gradient structure is achieved simultaneously in a single molding process, replacing the multi-step composite process of the traditional solution of "first preparing a high thermal conductivity layer and then attaching a low thermal conductivity support layer", which greatly simplifies the manufacturing process.

[0069] 2.3 Quantification of the synergistic effect of dual gradients: The synergistic effect of the component gradient (\phi(z), filler volume fraction) and the microstructure gradient (O(z), orientation degree) is quantified by the thermal conductivity-orientation degree product factor: \eta_{syn} = \frac{k_{eff}}{k_{uni}} = 1 + \beta \cdot \text{Corr}(\phi,O) where \beta is the material property coefficient (in this embodiment, \beta=0.5), \text{Corr}(\phi,O) is the spatial correlation coefficient between the two (expected \text{Corr}(\phi,O) \geq 0.6), and it is expected that \eta_{syn} \geq is significantly greater than 1 (e.g., it can improve thermal conductivity by 30% or more).

[0070] 2.4 Example 4a: Example of preparation of dual-gradient composite material (supporting claims 4, 5, 6, and 9) This embodiment provides a specific preparation process for dual-gradient composite materials: 1. Material Selection (Example): Matrix: Epoxy resin (thermal conductivity approximately 0.2 W / m·K, low cost and easy to mold); Filler: Spherical alumina (Al2O3, thermal conductivity approximately 30 W / m·K, low-cost filler) + boron nitride sheets (BN, thermal conductivity approximately 300 W / m·K, high thermal conductivity enhancement), the mixed equivalent high thermal conductivity filler has a thermal conductivity of approximately 150 W / m·K (supported by weight 2 "thermophysical properties").

[0071] 2. Gradient parameters: Component gradient: The filler volume fraction decreases continuously along the Z-axis from approximately 65 Vol% closer to the chip to approximately 20 Vol% further away from the chip, with the distribution function $\phi(z)=65\%e^{-0.02z / L}+20\%(1-e^{-0.02z / L})$ ($L$ is the stacking gap thickness in mm). Microstructure gradient: The boron nitride orientation degree $O(z)$ varies continuously from about 0.9 (planar orientation) near the chip to about 0.2 (random orientation) far from the chip (“gradient variation” example).

[0072] 3. Integrated molding process: **One-step injection molding process (material synthesis):** Premixed resin and filler are conveyed to the mold via a screw extruder; Process parameters: Injection temperature $T(z)=180^\circ\text{C}+5z$ (exemplary parameter), pressure 10 MPa, filler feed rate $v_f(z)=0.8\phi(z)$ (real-time control); Results: Thermal conductivity $k(z)=\phi(z)k_{high}+(1-\phi(z))k_{low}$, thermal resistance is reduced by **≥40%** compared with the traditional uniform scheme (echoing weight 3 "thermal-electric synergistic optimization").

[0073] 4. Integration with three-dimensional active structures: Composite materials are filled into the gaps between 3D NAND stacked chips (approximately 50 μm thick) to coat the sidewalls, forming a functional thermal management body that achieves thermal coupling with the three-dimensional active structure (“integrated and thermally coupled”). This concept of a non-uniform continuous distribution of thermophysical properties (such as thermal conductivity) can be achieved through… Figure 2 The spatial distribution diagram shown provides an intuitive understanding.

[0074] III. Quantitative Deduction of the Synergistic Effect and Cost Advantages of Heat-Electricity 1. The thermal and electrical effects are deduced based on Fourier's law of heat conduction (q = -k(z) ∫dT / dz, where q is the heat flux density and T is the temperature), and a simplified one-dimensional model (Z-axis direction) is performed on the above gradient structure.

[0075] The conclusion in the literature that "a continuous transition in thermal conductivity can improve heat flux efficiency" is based on analogical deduction: Quantitative formula for reducing thermal resistance: Traditional uniform scheme: The filler volume fraction is uniformly distributed at 42.5%, the thermal conductivity k_{uni} = 42.5%k_{high} + 57.5%k_{low} approx 64.4 W / m·K, and the interfacial thermal resistance R_{th,uni} = L}{k_{uni}A} (A is the cross-sectional area).

[0076] The gradient scheme of this invention: the filler volume fraction φ(z) decreases exponentially from 65% to 20% along the Z-axis (φ(z) = 65%e^{-0.02z / L} + 20%(1-e^{-0.02z / L})), the thermal conductivity k_{grad}(z) = φ(z)k_{high}+ (1-φ(z))k_{low}, and the interfacial thermal resistance R_{th,grad} = \int_0^L \frac{dz}{k_{grad}(z)A}.

[0077] Thermal resistance reduction rate: \eta_{Rth} = \left(1 - \frac{R_{th,grad}}{R_{th,uni}}\right) \times 100\% **Expected $\eta_{Rth} \geq 40\%$ (i.e., the interfacial thermal resistance is reduced from $0.156 \, \text{K·m}^2 / \text{W}$ in the conventional scheme to $0.094 \, \text{K·m}^2 / \text{W}$).

[0078] The significant advantages of the present invention's solution in terms of thermo-electric performance compared to the traditional uniform solution can be seen in the comparison. Figure 4 The diagram shown is shown in the image.

[0079] Quantifying the relationship between junction temperature reduction and lifetime improvement: The relationship between semiconductor device lifetime L and junction temperature T_j conforms to the Arrhenius equation L = A \cdot e^{\frac{E_a}{k_B T_j}} (E_a=0.7 \, \text{eV} is the activation energy, k_B=8.617 \times 10^{-5} \, \text{eV / K} is the Boltzmann constant). Let the junction temperature of the conventional scheme be T_{j,uni}=350 K, and the junction temperature of the scheme of this invention be T_{j,grad}=T_{j,uni}-\Delta T(\Delta T\geq 10 K}. Then the lifetime improvement factor is: \frac{L_{grad}}{L_{uni}} = e^{\frac{E_a}{k_B}\left(\frac{1}{T_{j,grad}} - \frac{1}{T_{j,uni}}\right)} \approx e^{\frac{E_a \Delta T}{k_B T_j^2}}. Example: When \Delta T=10 K, \frac{L_{grad}}{L_{uni}} \approx 2.2 times (lifetime improvement of 120%).

[0080] Thermal crosstalk reduction quantization: Thermal crosstalk noise power P_n \propto (\nabla T)^2 (\nabla T is the temperature gradient); The gradient design of this invention reduces T by 40%, is expected to reduce thermal crosstalk noise by 60%, and improve the signal-to-noise ratio (SNR) by 3 dB (SNR(dB) = 10log_10P_sP_n).

[0081] 2. Manufacturing cost advantage analysis and traditional heat dissipation solutions Compared to traditional or cutting-edge heat dissipation optimization schemes, the integrated design of this invention fundamentally avoids the compatibility challenges and additional interface problems caused by the superposition of multiple process steps. For example, the latest research in Reference 3 (Xiong Yucheng et al., dedicated to solving the **interfacial heat transport bottleneck in nanoelectronic devices**) reflects that current technology still focuses on the traditional path of **improving local or interfacial heat dissipation**. In contrast, this invention achieves thermal-electric synergistic optimization from the source through architecture-level integrated reverse design. The reference to this research in this embodiment is only used to illustrate the problem dimensions addressed by the prior art and does not imply that the implementation of this invention depends on the specific methods involved in the literature. In comparison, the integrated design of this invention fundamentally avoids additional process compatibility challenges and interface reliability problems. The reference to this literature in this embodiment is only used to illustrate the limitations of traditional solutions and does not imply that the implementation of this invention depends on the specific structures involved in the literature.

[0082] The cost reduction in this embodiment is reflected in two main aspects: material saving and process integration. Material cost saving formula: Let the total volume of the chip stack gap be V, and the unit price of high thermal conductivity filler be C_{high} = 10C_{low} (C_{low} is the unit price of substrate / low filler). Cost of traditional uniform solution: C_{uni} \approx V \cdot [42.5\%C_{high} + 57.5\%C_{low}] = V \cdot 4.85C_{low}.

[0083] The cost of the gradient scheme in this invention is: the global average filler ratio \alpha = \frac{1}{L} \int_0^L \phi(z)dz \approx 32\% (significantly lower than 42.5% under nonlinear distribution), then C_{grad} \approx V \cdot[32\%C_{high} + 68\%C_{low}] = V \cdot 3.88C_{low}.

[0084] Cost savings percentage: \eta_C = \frac{C_{uni} - C_{grad}}{C_{uni}} \times100\% \approx 20\% \quad (\text{if} \alpha=30\%, \eta_C \approx 28\%) Conclusion: It is expected that 20%-35% of the high-cost filler usage can be saved.

[0085] Formula for saving process and time costs: In the process stage, the differences and cost impacts between the traditional multi-step process and the integrated process of this invention are compared in two parts: The thermal interface layer preparation process: The traditional multi-step process is "independent mixing, coating, and curing (3 steps)"; The integrated process of this invention is "integrated with the encapsulation process (1 step)"; The cost impact is reflected in: reducing the investment in special equipment (cost of a single piece of equipment is 0.5M), shortening the operation time (from 3 days to 1 day), and reducing turnover loss (yield loss is reduced from 5% to 2%).

[0086] In the structural forming process: the traditional multi-step process is "layer bonding (≥2 steps)"; the integrated process of this invention is "one-time co-deposition / injection molding (1 step)"; The cost impact is reflected in the significant reduction of the production cycle, and the reduction rate is quantified by the formula: Production cycle reduction rate η_T = (1 - T_grad / T_uni)×100% ≥ 50% (where the traditional process cycle T_uni=5 days, and the process cycle of this invention T_grad=2 days).

[0087] Yield Improvement Model: In traditional processes, the number of interfaces m=3, and the yield Y_{uni}=Y_0(1-\delta)^m (Y_0=90\%,\delta=5\% is the single-interface failure probability), then Y_{uni}=77.4\; In this invention, the number of interfaces m'=1, Y_{grad}=85.5\, and the yield improvement \Delta Y=8.1\. Overall Cost Closed Loop: By reducing trial-and-error costs through reverse engineering (traditional solutions require 5-8 rounds of process iteration, while this invention only requires 1-2 rounds), the overall cost (materials + processes + R&D) is expected to be reduced by more than 50%.

[0088] IV. Reverse Design and Automation Methods in This Embodiment The implementation of this embodiment relies on the Electronic Design Automation (EDA) method of claim 10, with the core steps as follows: Obtaining distribution information: The three-dimensional heat source distribution Q(x,y,z) is obtained by simulating the power consumption model of the memory chip (such as the power density distribution map of the read and write of the 3D NAND cell).

[0089] Generate objective functions: With multiple objectives including "minimizing hotspot temperature" and "minimizing the global amount of high thermal conductivity filler," the optimal distribution function is solved through topology optimization. Objective function (mathematical expression): \min_{\Phi,O} \left[ w_1 T_{peak}(\Phi,O) + w_2 \int_V \Phi(x,y,z)dxdydz \right] where $w_1=0.7$ and $w_2=0.3$ are weighting coefficients, $T_{peak}$ is the hotspot temperature (obtained through thermo-electric coupling simulation), and the integral term is the global filler usage.

[0090] Constraints: k_{min}=0.5, W / m·K, k(z), k_{max}=200, W / m·K, number of gradient layers, 10, single layer thickness, 1m. Output: filler volume fraction distribution function Phi(x,y,z) and orientation distribution function O(x,y,z).

[0091] 3. Guided preparation: The distribution function is converted into one-time molding process parameters (such as the temperature gradient curve of the injection molding machine T(z)=T_0 + kz, and the filler feed rate v_f(z)=\alpha \Phi(z)), and the gradient structure is directly controlled.

[0092] 4. Example 4b: EDA reverse engineering process example (supporting claims 7-11) This embodiment uses a 3D NAND chip as an example to demonstrate the entire reverse engineering process: 1. Obtain multiphysics distribution information: Heat source distribution: $Q(x,y,z)$ (peak value approximately 50W / cm²) obtained from 3D NAND power consumption model simulation. Electric field distribution: Potential contour plot obtained by solving the Poisson equation (gate 0.8V, source-drain 1.2V); Stress distribution: $\sigma_{stress}(x,y,z)$ obtained from a thermo-mechanical coupling model (CTE mismatch: Cu TSV 17ppm / °C vs Si substrate 2.6ppm / °C) (weight 9 "stress, coefficient of thermal expansion" supported).

[0093] 2. Inverse optimization algorithm to generate the objective function: Algorithm selection: The **topology optimization algorithm** is adopted, with the objective function $\min[w_1T_{peak}+w_2\int_V\phi(z)dz]$ ($w_1=0.7$, $w_2=0.3$, exemplary weights). Output results: The filler volume fraction function $\phi(z)=65\%e^{-0.02z / L}+20\%(1-e^{-0.02z / L})$ (consistent with Example 4a), and the orientation distribution function $O(z)=0.9-0.7(z / L)$.

[0094] 3. Convert to process parameters: Convert $\phi(z)$ to the injection molding temperature curve $T(z)=180^\circ\text{C}+5z$ (corresponding to the process in Example 4a), and convert $O(z)$ to the filler feed rate $v_f(z)=0.8\phi(z)$.

[0095] 4. Verification and Application: Through thermo-electric coupling simulation verification, a 42% reduction in thermal resistance and a 12°C reduction in junction temperature were achieved. The 3D NAND chip integrating this thermal management unit can be used in data center servers. The complete closed-loop process from design to fabrication described above can be found in [link to documentation]. Figure 3 The flowchart shown.

[0096] V. Open Declarations and Scope of Protection This embodiment demonstrates, through a three-dimensional stacked memory scenario and the combination of "dual-gradient composite materials + integrated molding", the path to achieving "thermal-electric synergistic optimization" and "significantly reduced manufacturing costs" with "non-uniform thermal management body".

[0097] Special emphasis is placed on the following: The application scenarios (HBM), materials (epoxy resin / alumina / boron nitride), filler ratios (65%→20%), and formula variables (such as k_{high}=150 \, \text{W / m·K}) in the embodiments are illustrative and do not constitute a limitation on the claims. Any technical solution that integrates "non-uniformly continuous thermophysical properties" with "three-dimensional active structures," reduces processes and saves on the amount of high-performance materials through integrated manufacturing processes, thereby improving thermal management performance and reducing overall costs (regardless of whether it is applied to logic chips, power modules, or other electronic devices) falls within the protection scope of this invention.

[0098] It should be specifically noted that the references to the aforementioned documents in this embodiment are solely for illustrative purposes, illustrating the technical problems solved by the present invention, the natural science principles utilized, and the limitations of existing technologies overcome. This reference **does not mean** that the present invention is limited to any specific commercial product or specific process parameters. Any variations based on the core idea of ​​this invention—namely, 'achieving thermo-electric synergistic optimization through a non-uniform thermal management system integrated and thermally coupled with a three-dimensional active structure'—fall within the protection scope of this invention. This embodiment strongly supports all claims.

[0099] 1. Legal basis: This specification and the claims have been drafted in strict accordance with the relevant provisions of the Patent Law, the Implementing Regulations of the Patent Law, and the Guidelines for Patent Examination. The scope of protection of this invention is determined by the contents of the claims, and the specification, its drawings, and embodiments are used to explain the contents of the claims.

[0100] 2. Nature and function of the embodiments 1. All embodiments provided in this specification are intended to help those skilled in the art better understand the technical solutions of the present invention through specific illustrations, and are not intended to limit the only implementation of the present invention. In particular, Embodiments 1 to 3 illustrate the basis and preferred paths for realizing the core technical concept of the present invention.

[0101] 2. Example 4 aims to further illustrate the application potential and performance boundaries of the technical solution of the present invention through more complex theoretical models and simulation data. All examples, whether basic or advanced, are independent and exemplary. Those skilled in the art can understand and implement any one of them without having to implement all of them simultaneously.

[0102] 3. Definition of the scope of protection Any technical solution that includes all the technical features described in the claims falls within the protection scope of this invention. Those skilled in the art, after reading this specification, will understand that technical features (such as materials, dimensions, process parameters, and software algorithm models) in the embodiments can be replaced, modified, or combined without departing from the core concept of this invention; these modified technical solutions are also intended to fall within the protection scope of this invention.

[0103] 4. Any prior art documents, standards, or data cited in the comparative documents and data specification are only used to clearly demonstrate the inventiveness and technological advancement of the present invention through comparison. All statements regarding performance, simulation data, and theoretical models are intended to illustrate the principles and potential of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0104] 5. Final Statement This statement is an integral part of this specification. Any technical solution based on the essence of this invention, as long as it achieves the same function and effect as the technical features defined in the claims, is intended to fall within the legal protection scope defined by the claims.

[0105] References: [1] Huawei Technologies Co., Ltd. A three-dimensional integrated semiconductor device and its manufacturing method: China, CN202410391211.6 [2] "Oriented Bi2Te3-based films enabled high performance planar thermoelectric cooling device for hot spot elimination" Publication date: November 8, 2024; Authors: Guoying Dong, Jianghe Feng; Nature Communications, Vol. 15, Article No.: 9695 (2024) https: / / doi.org / 10.1038 / s41467-024-54017-3 [3] "Ultra-low contact thermal resistance between selenized nanoribbons achieved by current-induced annealing" Xiong Yucheng, School of Mechanical Engineering, Donghua University https: / / meccol.dhu.edu.cn / 2025 / 0904 / c9044a364774 / page.htm (direct link to the introduction) ACS Appl. Mater. Interfaces 2024, 16, 42, 57824-57831; https: / / doi.org / 10.1021 / acsami.4c10789 Published on October 10, 2024.

Claims

1. A semiconductor device, characterized in that, It includes: a three-dimensional active structure; a functional thermal management body integrated with and thermally coupled to the three-dimensional active structure; wherein the functional thermal management body is configured such that at least one of its thermophysical properties is spatially non-uniformly and continuously distributed to achieve thermo-electric synergistic optimization.

2. The semiconductor device according to claim 1, characterized in that, The thermophysical properties include thermal conductivity, coefficient of thermal expansion, specific heat capacity, or any combination thereof.

3. The semiconductor device according to claim 1, characterized in that, The non-uniform continuous distribution includes gradient changes, transition changes, or combinations thereof.

4. A method for fabricating a semiconductor device, characterized in that, include: Forming a three-dimensional active structure; A functional thermal management body is formed and integrated and thermally coupled with the three-dimensional active structure; wherein the step of forming the functional thermal management body includes: adjusting at least one parameter in the material synthesis or structure assembly process according to a target distribution function, so that at least one thermophysical property of the thermal management body forms a non-uniform continuous distribution, thereby realizing thermal-electric synergistic optimization.

5. A method for fabricating a three-dimensional heterogeneous integrated semiconductor device, characterized in that, include: Obtain multiphysics field distribution information of a three-dimensional device structure; based on the multiphysics field distribution information, determine a target distribution function through reverse design; Based on the target distribution function, a functional thermal management body with non-uniform and continuous distribution of thermophysical properties is formed and integrated and thermally coupled with the three-dimensional device structure.

6. A three-dimensional heterogeneous integrated semiconductor device, characterized in that, It is prepared by the method described in claim 5.

7. An electronic design automation method, characterized in that, include: Obtain multiphysics field distribution information of three-dimensional device structures; With the goal of thermo-electric synergistic optimization, the distribution information is processed by an inverse optimization algorithm to generate a target distribution function to guide the preparation method as described in claim 4 or 5.

8. The electronic design automation method according to claim 7, characterized in that, The inverse optimization algorithm includes topology optimization, genetic algorithm, gradient descent algorithm, or any combination thereof.

9. The electronic design automation method according to claim 7, characterized in that, The multiphysics distribution information includes thermal conductivity, electrical conductivity, dielectric constant, stress, coefficient of thermal expansion, or any of their derived coupling parameters.

10. A chip, characterized in that, The device is integrated with any one of the semiconductor devices as described in claims 1 to 3, or with the three-dimensional heterogeneous integrated semiconductor device as described in claim 6.

11. An electronic device, characterized in that, Includes the chip as described in claim 10.

Images