Automatic design method and device of cache system, storage medium and electronic equipment

Abstract

The invention provides an automatic design method of a cache system, the cache system is applied to a processor, and the method comprises the following steps: decomposing the cache system into a data supply unit and a cache management unit according to functions; according to prior knowledge, disassembling the data supply unit and the cache management unit into different subunits according to functions; writing a cache simulator to simulate the behavior of each subunit, and collecting first input and output data of each subunit from the cache simulator; and calling a circuit automatic design algorithm, and generating a logic circuit of the cache system according to the first input and output data. The invention further provides an automatic design device of the cache system, a storage medium and electronic equipment. Therefore, the cache system of the processor can be automatically designed by fusing an existing circuit automatic design algorithm and human priori knowledge, so that the performance of the automatically designed processor can be greatly improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology for processors, and more particularly to an automatic design method, apparatus, storage medium, and electronic device for a cache system. Background Technology

[0002] While current mainstream EDA (Electronic Design Automation) toolchains are deeply integrated into the processor development process, their functional positioning remains at the design-aid stage, lacking the ability to independently complete core logic architecture design. Although existing automatic circuit design algorithms have the initial ability to automatically design large-scale gate circuit processors, the performance of the designed processors is significantly lower than the performance of mainstream human designs.

[0003] Processors need to interact with memory systems during operation. Due to the memory wall dilemma faced by current semiconductor technology, there is a significant gap between the processor's computing speed and the memory system's access speed. This results in the processor's computing units not being fully utilized, thus limiting processor performance. Therefore, human-designed processors generally employ cache systems, building a "fast memory" layer on top of "slow memory," thereby creating a large and fast memory. However, existing automated logic design algorithms cannot automatically design cache systems, resulting in automatically designed processors having lower performance than manually designed ones.

[0004] In conclusion, the existing technology obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the Invention

[0005] To address the aforementioned shortcomings, the present invention aims to provide an automatic design method, apparatus, storage medium, and electronic device for a cache system, which can automatically design a processor's cache system, thereby significantly improving the performance of the automatically designed processor.

[0006] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0007] In a first aspect, embodiments of the present invention provide an automatic design method for a cache system, wherein the cache system is applied in a processor, and the method includes:

[0008] The unit decomposition step divides the cache system into a data supply unit and a cache management unit according to their functions.

[0009] The module decomposition step involves, based on prior knowledge, decomposing the data supply unit and the cache management unit into different sub-units according to their functions.

[0010] The cache simulation step involves writing a cache simulator to simulate the behavior of each sub-unit and collecting the first input and output data of each sub-unit from the cache simulator.

[0011] The circuit design steps involve calling an automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

[0012] According to the automatic design method of the caching system of the present invention, the cache simulation step further includes:

[0013] Define the input / output interfaces of each sub-unit;

[0014] Write a periodically accurate cache simulator to simulate the behavior of each subunit;

[0015] Based on the first input data for training, the cache simulator is run to obtain the first output data for training each of the sub-units;

[0016] The first input / output data of each of the sub-units is collected from the cache simulator.

[0017] According to the automatic design method of the cache system of the present invention, the step of running the cache simulator to obtain the first output data for training each of the sub-units based on the first input data for training includes:

[0018] Based on the first input data used for training, the cache simulator is run step by step to obtain the first output data used for training each of the sub-units.

[0019] According to the automatic design method of the cache system of the present invention, the data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookup and / or data return;

[0020] The cache management unit is used to determine the data cached during program runtime.

[0021] According to the automatic design method of the cache system of the present invention, after the circuit design step, the method further includes:

[0022] The cache verification step verifies the consistency between the generated logic circuit and the cache simulator.

[0023] According to the automatic design method of the caching system of the present invention, the cache verification step further includes:

[0024] The hardware description language code of the logic circuit is converted into the corresponding high-level language code to generate the corresponding test model, and the cache simulator is used as the reference model.

[0025] Differential tests are performed on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator.

[0026] According to the automatic design method of the cache system of the present invention, the step of performing differential tests on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator further includes:

[0027] Based on the second input data for verification, the test model is run to obtain the second output data for verification of each sub-unit;

[0028] Based on the second input data for verification, the reference model is run to obtain the third output data for verification of each of the sub-units;

[0029] The consistency between the logic circuit and the cache simulator is verified by analyzing the second output data and the third output data.

[0030] Secondly, embodiments of the present invention provide an automatic design apparatus for a cache system constructed based on any one of the methods described above, wherein the cache system is applied in a processor, and the apparatus includes:

[0031] The cache decomposition module is used to decompose the cache system into a data supply unit and a cache management unit according to their functions.

[0032] The unit decomposition module is used to decompose the data supply unit and the cache management unit into different sub-units according to their functions based on prior knowledge;

[0033] A cache simulation module is used to write a cache simulator to simulate the behavior of each of the sub-units and to collect the first input and output data of each of the sub-units from the cache simulator.

[0034] The circuit design module is used to call the automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

[0035] Thirdly, embodiments of the present invention provide a storage medium for storing a computer program for performing any of the methods described herein.

[0036] Fourthly, embodiments of the present invention provide an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor, when executing the computer program, implements any of the methods described above.

[0037] Therefore, the automatic design technology of the cache system of the present invention includes: decomposing the cache system into a data supply unit and a cache management unit according to function; further decomposing the data supply unit and the cache management unit into different sub-units according to function based on prior knowledge; writing a cache simulator to simulate the behavior of each sub-unit and collecting the first input and output data of each sub-unit from the cache simulator; and calling an existing automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data. Thus, the present invention can integrate existing automatic circuit design algorithms and human prior knowledge to automatically design the cache system of a processor, thereby significantly improving the performance of the automatically designed processor. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the automatic design method for a cache system provided in Embodiment 1 of the present invention;

[0039] Figure 2 This is a flowchart illustrating the automatic design method for a cache system provided in Embodiment 2 of the present invention;

[0040] Figure 3 This is a schematic diagram illustrating the design process of the caching system provided in Embodiment 3 of the present invention;

[0041] Figure 4 This is a schematic diagram of the verification process of the caching system provided in Embodiment 4 of the present invention;

[0042] Figure 5 This is a schematic diagram of the automatic design device for the cache system provided in Embodiment 5 of the present invention;

[0043] Figure 6 This is a schematic diagram of the automatic design device for the cache system provided in Embodiment Six of the present invention;

[0044] Figure 7 This is a schematic diagram of the structure of the electronic device provided in Embodiment 7 of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0047] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0048] The automatic design method of the caching system provided by the present invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0049] In its research on intelligent design of cache systems, this invention discovered that existing automatic circuit design algorithms can only implement instruction set architectures, thus the automatically designed processors do not include a cache system. This invention introduces artificial architectural knowledge into existing automatic circuit design algorithms by manually modeling the cache system design space in a high dimension, thereby automatically designing the logic circuits of the cache system.

[0050] Figure 1 This is a flowchart illustrating the automatic design method for a cache system provided in Embodiment 1 of the present invention. The cache system is applied in a processor, and the method includes:

[0051] Step S101, cache decomposition step, decomposes the cache system into a data supply unit and a cache management unit according to function.

[0052] Preferably, the data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookups, and / or data returns. The data supply unit provides access paths for fast storage and slow storage, returning data from fast storage when a cache hit occurs.

[0053] Preferably, the cache management unit is used to determine the data cached during program runtime, with the aim of improving cache utilization and maximizing the use of the data supply unit (data supply layer) to access fast storage channels.

[0054] Step S102, Unit decomposition step: Based on prior knowledge, the data supply unit and the cache management unit are decomposed into different sub-units according to their functions.

[0055] Step S103, Cache simulation step: Write a cache simulator to simulate the behavior of each sub-unit, and collect the first input and output data of each sub-unit from the cache simulator.

[0056] Preferably, after the sub-units are split, the input and output interfaces of each sub-unit are defined, and a cache simulator with a precise development cycle is used to simulate the behavior of each sub-unit. On specified input data, the output data of the sub-units is obtained by running the cache simulator, and a large amount of input and output data is collected from the cache simulator.

[0057] Step S104, circuit design step: call the existing automatic circuit design algorithm to generate the logic circuit of the buffer system based on the first input and output data.

[0058] This invention addresses the low performance issue of existing automatically designed processors by proposing a method for automatically designing cache systems. This method integrates prior human knowledge with automated circuit design algorithms, introducing an automatically designed cache system onto the foundation of existing automatically designed processors. The cache system is divided into two components: a data supply unit and a cache management unit. Through a periodic, precise cache simulator and automated circuit design algorithms, these components are automatically generated, thereby improving the performance of the automatically designed processor.

[0059] Figure 2 This is a flowchart illustrating the automatic design method for a cache system provided in Embodiment 2 of the present invention. The cache system is applied in a processor, and the method includes:

[0060] Step S201, cache decomposition step, decomposes the cache system into a data supply unit and a cache management unit according to function.

[0061] Preferably, the data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookups, and / or data returns. The data supply unit provides access paths for fast storage and slow storage, returning data from fast storage when a cache hit occurs.

[0062] Preferably, the cache management unit is used to determine the data cached during program runtime, with the aim of improving cache utilization and maximizing the use of the data supply unit's access to fast storage channels.

[0063] Step S202, Unit decomposition step: Based on prior knowledge, the data supply unit and the cache management unit are decomposed into different sub-units according to their functions.

[0064] Step S203, Cache simulation step: Write a cache simulator to simulate the behavior of each sub-unit, and collect the first input and output data of each sub-unit from the cache simulator.

[0065] Preferably, step S203 further includes:

[0066] (31) Define the input and output interfaces of each sub-unit.

[0067] (32) Write a periodically accurate cache simulator to simulate the behavior of each sub-unit.

[0068] (33) Based on the first input data for training, run the cache simulator to obtain the first output data for training each sub-unit. More preferably, this step includes: based on the first input data for training, run the cache simulator step-by-step to obtain the first output data for training each sub-unit. The step-by-step operation refers to the operation mode of allowing the cache simulator to execute one instruction or one clock cycle at a time according to the settings, and then pausing, so that the developer can observe the changes in the system state after the program executes the current step.

[0069] (34) Collect the first input and output data of each subunit from the cache simulator.

[0070] Step S204, circuit design step: call the existing circuit automatic design algorithm based on input and output to generate the logic circuit of the buffer system according to the first input and output data.

[0071] Step S205, cache verification step, verifies the consistency between the generated logic circuit and the cache simulator.

[0072] Preferably, step S205 further includes:

[0073] (51) Convert the hardware description language code of the logic circuit into the corresponding high-level language code, generate the corresponding test model, and use the cache simulator as the reference model.

[0074] (52) Perform differential tests on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator. Better yet, this step further includes:

[0075] Based on the second input data used for verification, the test model is run to obtain the second output data used for verification of each sub-unit;

[0076] Based on the second input data for verification, the reference model is run to obtain the third output data for verification of each sub-unit;

[0077] The consistency between the verification logic circuit and the cache simulator is verified by analyzing the second and third output data.

[0078] The technical solution of Embodiment 2 of the present invention mainly includes the following key points:

[0079] Key point 1: The caching system is automatically designed according to mechanism and strategy. The caching system is divided into a data supply unit and a cache management unit according to function, and these two parts are designed using automatic circuit design algorithms.

[0080] Key point 2: Cache simulators for the data supply unit and cache management unit of the caching system. Based on prior human knowledge, these two units are functionally broken down into different sub-units, and cycle-accurate simulations for each sub-unit are written.

[0081] Key point 3: Export the input and output data of the sub-units from the cache simulator, use the input and output to complete the automatic design, and use the cache simulator to complete the design verification; use the cache simulator to obtain the input and output data during the execution of the cache system, call the existing circuit automatic design algorithm to generate the logic circuit of the cache system, and finally verify the consistency between the logic circuit and the simulator behavior.

[0082] Figure 3 This is a schematic diagram illustrating the design process of the caching system provided in Embodiment 3 of the present invention. Based on the functions that the caching system needs to support in the out-of-order processor, the automatic design of the caching system is decomposed into automatic designs for the data supply unit and the cache management unit. Utilizing prior human knowledge, the data supply unit and the cache management unit are functionally broken down into different sub-units. After the sub-units are decomposed, the input / output interfaces of each sub-unit are defined, and a cache simulator with a precise development cycle is used to simulate the behavior of each sub-unit. On specified input data, the output data of the sub-unit is obtained by single-stepping through the cache simulator. By collecting a large amount of input / output data and calling existing automatic circuit design algorithms based on input / output, the logic circuit of the caching system is finally obtained.

[0083] Figure 4 This is a schematic diagram of the verification process of the cache system provided in Embodiment 4 of the present invention. The design flow of the present invention needs to ensure the consistency between the automatically generated sub-unit circuits and the cache simulator. The automatically designed sub-unit RTL (Register Transfer Level) is used to obtain high-level language code (RTL) using tools such as Verilator. RTL is a hardware description language code that replaces the corresponding sub-unit in the pre-written cache simulator as a test model; the pre-written cache simulator serves as a reference model. Differential tests are performed on the two models to verify the consistency between the circuit and the cache simulator sub-unit by sub-unit.

[0084] It should be noted that the automatic design method for the cache system provided in this embodiment of the invention can be executed by an electronic device, an apparatus, or a control module within that apparatus for executing the method. This embodiment of the invention uses an apparatus executing the method as an example to illustrate the automatic design apparatus for the cache system provided in this embodiment of the invention.

[0085] Figure 5 This is a schematic diagram of the structure of the automatic design device for a cache system provided in Embodiment 5 of the present invention. The cache system is applied in a processor. The automatic design device 100 for the cache system includes a cache decomposition module 10, a unit disassembly module 20, a cache simulation module 30, and a circuit design module 40, wherein:

[0086] The cache decomposition module 10 is used to decompose the cache system into a data supply unit and a cache management unit according to their functions.

[0087] Preferably, the data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookups, and / or data returns. The cache management unit is used to determine the data cached during program runtime.

[0088] The unit decomposition module 20 is used to decompose the data supply unit and the cache management unit into different sub-units according to their functions based on prior knowledge.

[0089] The cache simulation module 30 is used to write a cache simulator to simulate the behavior of each sub-unit and to collect the first input and output data of each sub-unit from the cache simulator.

[0090] The circuit design module 40 is used to call the automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

[0091] Figure 6 This is a schematic diagram of the structure of the automatic design device for a cache system provided in Embodiment 6 of the present invention. The cache system is applied in a processor. The automatic design device 100 for the cache system includes a cache decomposition module 10, a unit disassembly module 20, a cache simulation module 30, a circuit design module 40, and a cache verification module 50, wherein:

[0092] The cache decomposition module 10 is used to decompose the cache system into a data supply unit and a cache management unit according to their functions.

[0093] Preferably, the data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookups, and / or data returns. The cache management unit is used to determine the data cached during program runtime.

[0094] The unit decomposition module 20 is used to decompose the data supply unit and the cache management unit into different sub-units according to their functions based on prior knowledge.

[0095] The cache simulation module 30 is used to write a cache simulator to simulate the behavior of each sub-unit and to collect the first input and output data of each sub-unit from the cache simulator.

[0096] Preferably, the cache simulation module 30 further includes:

[0097] Define submodule 31 to define the input and output interfaces of each subunit.

[0098] Write submodule 32 to write a periodically accurate cache simulator to simulate the behavior of each subunit.

[0099] The simulation submodule 33 is used to run the cache simulator to obtain the first output data for training each subunit based on the first input data for training. More preferably, it runs the cache simulator step-by-step to obtain the first output data for training each subunit based on the first input data for training.

[0100] The acquisition submodule 34 is used to acquire the first input and output data of each subunit from the cache simulator.

[0101] The circuit design module 40 is used to call the automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

[0102] The cache verification module 50 is used to verify the consistency between the generated logic circuit and the cache simulator.

[0103] Preferably, the cache verification module 50 further includes:

[0104] The model generation submodule 51 is used to convert the hardware description language code of the logic circuit into the corresponding high-level language code, generate the corresponding test model, and use the cache simulator as the reference model.

[0105] The model testing submodule 52 is used to perform differential testing on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator. Specifically, it includes: running the test model based on the second input data for verification to obtain the second output data for verification of each sub-unit; running the reference model based on the second input data for verification to obtain the third output data for verification of each sub-unit; and verifying the consistency between the logic circuit and the cache simulator by analyzing the second and third output data.

[0106] The automatic design device for the caching system provided in this embodiment of the invention can achieve Figures 1-4The various processes implemented in the embodiment of the automatic design method for the caching system shown will not be described again here to avoid repetition.

[0107] The automatic design apparatus for a cache system provided in this embodiment of the invention includes: a cache decomposition module 10, used to decompose the cache system into a data supply unit and a cache management unit according to function; a unit decomposition module 20, used to decompose the data supply unit and the cache management unit into different sub-units according to function based on prior knowledge; a cache simulation module 30, used to write a cache simulator to simulate the behavior of each sub-unit and collect the first input and output data of each sub-unit from the cache simulator; and a circuit design module 40, used to call an automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data. Therefore, this invention can integrate existing automatic circuit design algorithms and human prior knowledge to automatically design the cache system of a processor, thereby significantly improving the performance of the automatically designed processor.

[0108] The present invention also provides a storage medium for storing, for example, Figures 1-4 A computer program for the automatic design method of any of the aforementioned caching systems. For example, computer program instructions, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operation of the computer, achieving the same technical effect; to avoid repetition, these will not be elaborated further here. The program instructions for invoking the methods of the present invention may be stored in a fixed or removable storage medium, and / or transmitted via data streams in broadcast or other signal carrying media, and / or stored in the storage medium of a computer device operating according to the program instructions.

[0109] According to one embodiment of the present invention, the present invention also provides such a Figure 7The illustrated electronic device 400 may optionally include a storage medium 200 for storing computer programs and a processor 300 for executing the computer programs. When the computer program is executed by the processor 300, it implements any of the aforementioned automatic design methods for a caching system, triggering the electronic device 400 to execute methods and / or technical solutions based on the foregoing embodiments, achieving the same technical effects. To avoid repetition, these methods will not be elaborated upon here. It should be noted that the electronic devices in this embodiment include mobile electronic devices and non-mobile electronic devices. For example, mobile electronic devices may be mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, wearable devices, super mobile personal computers, netbooks, or personal digital assistants, etc., while non-mobile electronic devices may be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This embodiment does not specifically limit the scope of the invention.

[0110] It should be noted that the present invention can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of the present invention can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present invention (including associated data structures) can be stored in a computer-readable recording medium, such as RAM memory, a magnetic or optical drive, a floppy disk, or similar devices. Furthermore, some steps or functions of the present invention can be implemented in hardware, for example, as circuitry that works with a processor to perform the various steps or functions.

[0111] This invention can be implemented on a computer as a computer-based method, or in dedicated hardware, or a combination of both. Executable code or portions thereof for the method according to the invention can be stored on a computer program product. Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Optionally, the computer program product includes non-transitory program code components stored on a computer-readable medium so as to execute the method according to the invention when the program product is executed on a computer.

[0112] In an optional embodiment, the computer program includes computer program code components adapted to perform all the steps of the method according to the invention when the computer program is run on a computer. Optionally, the computer program is embodied on a computer-readable medium.

[0113] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0114] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. An automatic design method for a caching system, characterized in that, The cache system is applied in the processor, and the method includes: The unit decomposition step divides the cache system into a data supply unit and a cache management unit according to their functions. The module decomposition step involves, based on prior knowledge, decomposing the data supply unit and the cache management unit into different sub-units according to their functions. The cache simulation step involves writing a cache simulator to simulate the behavior of each sub-unit and collecting the first input and output data of each sub-unit from the cache simulator. The circuit design steps involve calling an automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

2. The automatic design method for a caching system according to claim 1, characterized in that, The cache simulation step further includes: Define the input / output interfaces of each sub-unit; Write a periodically accurate cache simulator to simulate the behavior of each subunit; Based on the first input data for training, the cache simulator is run to obtain the first output data for training each of the sub-units; The first input / output data of each of the sub-units is collected from the cache simulator.

3. The automatic design method for a caching system according to claim 2, characterized in that, The step of running the cache simulator to obtain the first output data for training each sub-unit based on the first input data used for training includes: Based on the first input data used for training, the cache simulator is run step by step to obtain the first output data used for training each of the sub-units.

4. The automatic design method for a caching system according to claim 1, characterized in that, The data supply unit establishes a data path between the processor and the memory for receiving memory access requests, cache lookups, and / or data returns. The cache management unit is used to determine the data cached during program runtime.

5. The automatic design method for a caching system according to claim 1, characterized in that, The circuit design steps are followed by: The cache verification step verifies the consistency between the generated logic circuit and the cache simulator.

6. The automatic design method for a caching system according to claim 5, characterized in that, The cache verification step further includes: The hardware description language code of the logic circuit is converted into the corresponding high-level language code to generate the corresponding test model, and the cache simulator is used as the reference model. Differential tests are performed on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator.

7. The automatic design method for a caching system according to claim 6, characterized in that, The step of performing differential tests on the test model and the reference model to verify the consistency between the logic circuit and the cache simulator further includes: Based on the second input data for verification, the test model is run to obtain the second output data for verification of each sub-unit; Based on the second input data for verification, the reference model is run to obtain the third output data for verification of each of the sub-units; The consistency between the logic circuit and the cache simulator is verified by analyzing the second output data and the third output data.

8. An automatic design apparatus for a cache system constructed based on the method of any one of claims 1 to 7, characterized in that, The cache system is applied in the processor, and the device includes: The cache decomposition module is used to decompose the cache system into a data supply unit and a cache management unit according to their functions. The unit decomposition module is used to decompose the data supply unit and the cache management unit into different sub-units according to their functions based on prior knowledge; A cache simulation module is used to write a cache simulator to simulate the behavior of each of the sub-units and to collect the first input and output data of each of the sub-units from the cache simulator. The circuit design module is used to call the automatic circuit design algorithm to generate the logic circuit of the cache system based on the first input and output data.

9. A storage medium, characterized in that, Used to store a computer program for performing the method according to any one of claims 1 to 7.

10. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 7.

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