Data read-write circuit, ferroelectric memory and data read-write method

Abstract

The invention relates to a data read-write circuit, a ferroelectric memory and a data read-write method, and the data read-write circuit comprises a flying capacitor auxiliary switch which is used for carrying out the non-DC offset sampling of an input signal, and obtaining an output signal; the comparison module comprises a comparison unit, a calibration unit and an elimination unit, the comparison unit is used for receiving the output signal and carrying out integration level processing and positive feedback level processing on the output signal to obtain a processed signal, and the calibration unit is used for calibrating the processed signal based on a preset calibration period to obtain a calibrated signal; and the elimination unit is used for eliminating the influence of threshold voltage mismatch on the calibrated signal to obtain a final output signal. Therefore, the problems of high resistance state and speed limitation of a ferroelectric memory transmission gate switch and insufficient power consumption and precision of a sensitive amplifier in related technologies are solved, the switching speed of the ferroelectric memory is improved, the static or dynamic power consumption of the ferroelectric memory is remarkably reduced, and the precision is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a data read-write circuit, a ferroelectric memory and a data read-write method. BACKGROUND

[0002] Currently, there are two major power consumption and performance bottleneck problems in the ferroelectric memory (FeRAM): (1) High resistance state and speed limitation of switch structure: In traditional FeRAM, the digital signal switch mostly adopts the transmission gate (TG) structure. When the switch is off, the output end presents a high resistance state rather than an ideal zero potential, resulting in signal residue and noise sensitivity problems. In addition, the conduction speed of the transmission gate switch is limited by the metal-oxide-semiconductor (MOS) tube channel resistance, which is difficult to meet the high-speed storage demand, especially in the application scenario of frequent reading and writing, the performance is limited. (2) Insufficient power consumption and precision of sensitive amplifier: The sensitive amplifier of FeRAM adopts the traditional strongarm comparator structure, which has a high number of mos tube stacking layers and is not suitable for low-voltage scenarios. The power consumption of the doubletail structure is higher than that of the traditional strongarm comparator structure at the same performance. The comparator offset and threshold voltage (Threshold Voltage, vth) drift caused by process deviation will reduce the data reading precision and affect the reliability of the memory.

[0003] In view of the problems of the FeRAM, the related art mainly improves from the aspects of transmission gate switch and strongarm comparator. In the aspect of transmission gate switch, in the traditional FeRAM, the transmission gate is composed of a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS) and an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) in parallel, and is turned on and turned off through complementary control signals. The complementary control signals can be a clock signal (CLK) and a clock bar signal (CLKB). The advantage is that the structure is simple, but the following defects exist: (1) the output end is in a high impedance state when turned off, which is easy to be interfered by adjacent signal lines, resulting in charge residue and rising of the bit error rate; (2) the on-resistance is large, typically hundreds of ohms, resulting in signal transmission delay and difficulty in meeting the high-speed storage requirement. Secondly, in the aspect of strongarm comparator, the existing sensitive amplifier mainly adopts the classic strongarm structure, which realizes high-speed comparison through the cross-coupled differential pair and the tail current source, and lacks an effective offset calibration mechanism. A process deviation of ±10 mV will significantly reduce the data reading accuracy.

[0004] In addition, the related art has the following defects: (1) the high impedance state problem and the speed bottleneck caused by the insufficient transmission gate switch. The high impedance state problem mainly reflects that if the output end is not forced to be pulled down to the ground potential when turned off, the residual charge may cause logic errors, and a reset circuit needs to be additionally designed, increasing the system complexity. The speed bottleneck mainly reflects that the on-resistance and the parasitic capacitance form a resistor-capacitor delay (RC), and the performance significantly decreases in the high-speed read-write scene. (2) The high required power voltage and the limited accuracy problem caused by the insufficient traditional strongarm comparator. The high required power voltage mainly reflects that the high required power voltage: the multi-layer tube stack makes it difficult to reduce the power voltage, thereby causing high power consumption. The multi-layer stack limits the input range. The kickback noise is large. The limited accuracy mainly reflects that the offset voltage and the threshold voltage drift lack compensation mechanisms, resulting in rising of the misjudgment rate, especially in high-temperature or low-voltage environments. SUMMARY

[0005] The application provides a data read-write circuit, a ferroelectric memory and a data read-write method to solve the problems of high resistance state and speed limitation of a ferroelectric memory transmission gate switch, insufficient power consumption and precision of a sensitive amplifier in the prior art, and improve the switching speed of the ferroelectric memory while significantly reducing its static or dynamic power consumption and improving its precision.

[0006] The first aspect of the application provides a data read-write circuit, comprising: The ferroelectric capacitor auxiliary switch is configured to sample the input signal without DC offset to obtain an output signal. The comparison module comprises a comparison unit, a calibration unit and an elimination unit, wherein The comparison unit is configured to receive the output signal and perform integral stage processing and positive feedback stage processing on the output signal to obtain a processed signal, the calibration unit is configured to calibrate the processed signal based on a preset calibration period to obtain a calibrated signal, and the elimination unit is configured to eliminate the influence of threshold voltage mismatch on the calibrated signal to obtain a final output signal.

[0007] Optionally, in some embodiments, the ferroelectric capacitor auxiliary switch comprises: The first NOT gate is connected to the signal input node and configured to receive the input signal; The first switch is connected to the output end of the first NOT gate, and the first end of the first switch is connected to the first power supply access node; The second switch is connected to the output end of the first NOT gate, the first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to the ground node; The second NOT gate is connected to the connection node between the first end of the first switch and the second end of the first switch; The third switch is connected to the output end of the second NOT gate, and the first end of the third switch is connected to the first power supply access node; The third NOT gate and the fourth switch are connected to the output end of the third NOT gate, the first end of the fourth switch is connected to the second end of the third switch, and the second end of the fourth switch is connected to the signal output node; The fifth switch is connected to the signal output node, and the second end of the fifth switch is connected to the ground node; The sixth switch is connected to the signal output node, and the second end of the sixth switch is connected to the ground node; The flying capacitor module is connected with the second power access node at a first end, connected with the third power access node at a second end, connected with the input end of the second NOT gate at a third end, connected with the input end of the third NOT gate at a fourth end, connected with the control end of the fifth switch at a fifth end, and connected with the control end of the sixth switch at a sixth end.

[0008] Optionally, in some embodiments, the flying capacitor module comprises: a fourth NOT gate, the input end of the fourth NOT gate being connected with the second power access node; a fifth NOT gate, the input end of the fifth NOT gate being connected with the third power access node; a first flying capacitor switch unit, the first end of the first flying capacitor switch unit being connected with the output end of the fourth NOT gate, the second end of the first flying capacitor switch unit being connected with the output end of the fifth NOT gate, the third end of the first flying capacitor switch unit being connected with the input end of the second NOT gate, and the fourth end of the first flying capacitor switch unit being connected with the control end of the fifth switch; a second flying capacitor switch unit, the first end of the second flying capacitor switch unit being connected with the output end of the fourth NOT gate, the second end of the second flying capacitor switch unit being connected with the output end of the fifth NOT gate, the third end of the second flying capacitor switch unit being connected with the input end of the third NOT gate, and the fourth end of the second flying capacitor switch unit being connected with the control end of the sixth switch.

[0009] Optionally, in some embodiments, the first flying capacitor switch unit comprises: a seventh switch, one end of the seventh switch being connected with the output end of the fourth NOT gate; an eighth switch, one end of the eighth switch being connected with the other end of the seventh switch, and the other end of the eighth switch being connected with the input end of the second NOT gate; a ninth switch, one end of the ninth switch being connected with the output end of the fifth NOT gate; a tenth switch, one end of the tenth switch being connected with the other end of the ninth switch, and the other end of the tenth switch being connected with the control end of the eleventh switch; a first capacitor, one end of the first capacitor being connected with the connection node between the seventh switch and the eighth switch, and the other end of the first capacitor being connected with the connection node between the ninth switch and the tenth switch.

[0010] Optionally, in some embodiments, the second flying capacitor switch unit comprises: an eleventh switch, one end of the eleventh switch being connected with the output end of the fourth NOT gate; a twelfth switch, one end of the twelfth switch being connected with the other end of the eleventh switch, and the other end of the twelfth switch being connected with the input end of the third NOT gate. The thirteenth switch, one end of which is connected to the output of the fifth NOT gate; The fourteenth switch, one end of which is connected to the other end of the thirteenth switch, and the other end of which is connected to the control terminal of the twelfth switch; The second capacitor has one end connected to the connection node between the eleventh and twelfth switches, and the other end connected to the connection node between the thirteenth and fourteenth switches.

[0011] Optionally, in some embodiments, the comparison unit is an improved doubletail comparator, which includes a subthreshold biased integral stage and a cross-coupled positive feedback stage.

[0012] Optionally, in some embodiments, the calibration unit is specifically used to short-circuit the input terminal of the comparison unit to the common-mode voltage based on a preset calibration cycle, and execute a preset successive approximation front-end calibration strategy to generate digital codewords for offsetting random offsets, so as to convert the processed signal into a calibrated signal according to the digital codewords.

[0013] Optionally, in some embodiments, the elimination unit is specifically used to preset the gate-source voltage of the differential input pair of the comparison unit to the corresponding threshold voltage during the circuit initialization phase, so as to eliminate the influence of threshold voltage mismatch on the calibrated signal and obtain the final output signal.

[0014] A second aspect of this application provides a ferroelectric memory, including the data read / write circuit described in the first aspect embodiment.

[0015] A third aspect of this application provides a data read / write method, which employs the data read / write circuit described in the first aspect embodiment, and includes the following steps: The output signal is obtained by sampling the input signal without DC offset using a flying capacitor-assisted switch. The comparison unit of the comparison module receives the output signal, performs integral-level processing and positive feedback-level processing on the output signal to obtain the processed signal, and the calibration unit of the comparison module calibrates the processed signal based on a preset calibration period to obtain the calibrated signal. The elimination unit of the comparison module eliminates the influence of threshold voltage mismatch on the calibrated signal to obtain the final output signal.

[0016] Therefore, the input signal can be sampled without DC offset by the flying capacitor auxiliary switch to obtain an output signal; the output signal is received by a comparison unit in the comparison module, and the output signal is subjected to integral stage processing and positive feedback stage processing to obtain a processed signal; the processed signal is calibrated by a calibration unit in the comparison module based on a preset calibration period to obtain a calibrated signal, and the influence of threshold voltage mismatch on the calibrated signal is eliminated by an elimination unit in the comparison module to obtain a final output signal. Therefore, the problems of high resistance state and speed limitation of the ferroelectric memory transmission gate switch, and the problems of insufficient power consumption and precision of the sensitive amplifier are solved, and the speed of the ferroelectric memory switch is improved, and the static or dynamic power consumption is significantly reduced and the precision is improved.

[0017] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the accompanying drawings, wherein: Figure 1 A block schematic diagram of a data read-write circuit according to an embodiment of the present application is provided; Figure 2 A circuit diagram of a flying capacitor and gate switch according to an embodiment of the present application is provided; Figure 3 A circuit diagram of an improved comparison unit and calibration unit according to an embodiment of the present application is provided; Figure 4 A timing schematic diagram of a data read-write circuit according to an embodiment of the present application is provided; Figure 5 A flowchart of a data read-write method according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0019] Embodiments of the present application are described in detail below with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0020] The following description, with reference to the accompanying drawings, describes a data read / write circuit, a ferroelectric memory, and a data read / write method according to embodiments of this application. Addressing the problems of high impedance and speed limitations of the ferroelectric memory transmission gate switch, and insufficient power consumption and accuracy of the sensitive amplifier mentioned in the background art, this application provides a data read / write circuit. This circuit uses a flying capacitor-assisted switch to sample the input signal without DC offset to obtain an output signal. The output signal is received by a comparison unit in a comparison module, and integrated and positive feedback processing is performed on the output signal to obtain a processed signal. A calibration unit in the comparison module calibrates the processed signal based on a preset calibration period to obtain a calibrated signal. An elimination unit in the comparison module eliminates the influence of threshold voltage mismatch on the calibrated signal, resulting in the final output signal. This solves the problems of high impedance and speed limitations of the ferroelectric memory transmission gate switch, and insufficient power consumption and accuracy of the sensitive amplifier in related technologies. It significantly reduces static or dynamic power consumption and improves accuracy while increasing the switching speed of the ferroelectric memory.

[0021] Specifically, Figure 1 This is a block diagram of a data read / write circuit provided in an embodiment of this application.

[0022] like Figure 1 As shown, the data read / write circuit 10 includes a flying capacitor auxiliary switch 100 and a comparison module 200. The flying capacitor auxiliary switch 100 is used to sample the input signal without DC offset to obtain an output signal. The comparison module 200 includes a comparison unit 201, a calibration unit 202, and an elimination unit 203. The comparison unit 201 receives the output signal and performs integral-level processing and positive feedback-level processing on the output signal to obtain a processed signal. The calibration unit 202 calibrates the processed signal based on a preset calibration period to obtain a calibrated signal. The elimination unit 203 eliminates the influence of threshold voltage mismatch on the calibrated signal to obtain the final output signal.

[0023] Wherein, the data read-write circuit 10 is the core electronic circuit for data storage and reading; the flying capacitor auxiliary switch 100 refers to a circuit module composed of a flying capacitor and a switch component; the comparison module 200 is a module for processing a sampling signal; the input signal refers to an original electrical signal transmitted from an external device; the DC offset-free sampling refers to a sampling mode that suppresses the DC offset of the switch and retains only the valid components of the input signal; the output signal refers to an intermediate signal transmitted from the flying capacitor auxiliary switch to the comparison module after sampling; the comparison unit 201 refers to a unit for integrating and positive feedback processing of the output signal; the calibration unit 202 refers to a unit for correcting the error of the processed signal according to a preset period; the elimination unit 203 refers to a unit for offsetting the influence of threshold voltage mismatch to optimize the calibrated signal; the integral stage processing refers to a processing for accumulating signal energy to reduce noise and improve signal stability; the positive feedback stage processing refers to a processing for amplifying the difference in signal level to enhance the logical recognition degree; the processed signal refers to an intermediate signal that still needs to be calibrated after the comparison unit processing; the preset calibration period refers to a preset calibration time or event condition; the calibrated signal refers to a signal that may still be affected by threshold mismatch after optimization by the calibration unit; the threshold voltage mismatch refers to a phenomenon that the threshold voltages of the paired devices are inconsistent due to process differences; and the final output signal refers to a precise signal after eliminating the mismatch.

[0024] In some embodiments, as Figure 2As shown, the flying capacitor auxiliary switch 100 comprises a first NOT gate 101, a first switch 102, a second switch 103, a second NOT gate 104, a third switch 105, a third NOT gate 106, a fourth switch 107, a fifth switch 108, a sixth switch 109, and a flying capacitor module 110. The input end of the first NOT gate 101 is connected with a signal input node, for receiving an input signal; the control end of the first switch 102 is connected with the output end of the first NOT gate 101, the first end of the first switch 102 is connected with a first power supply access node; the control end of the second switch 103 is connected with the output end of the first NOT gate 101, the first end of the second switch 103 is connected with the second end of the first switch 102, and the second end of the second switch 103 is connected with a ground node; the input end of the second NOT gate 104 is connected with a connection node between the first end of the first switch 102 and the second end of the first switch 102; the control end of the third switch 105 is connected with the output end of the second NOT gate 104, the first end of the third switch 105 is connected with the first power supply access node; the control end of the fourth switch 107 is connected with the output end of the third NOT gate 106, the first end of the fourth switch 107 is connected with the second end of the third switch 105, and the second end of the fourth switch 107 is connected with a signal output node; the first end of the fifth switch 108 is connected with the signal output node, and the second end of the fifth switch 108 is connected with the ground node; the first end of the sixth switch 109 is connected with the signal output node, and the second end of the sixth switch 109 is connected with the ground node; the first end of the flying capacitor module 110 is connected with a second power supply access node, the second end of the flying capacitor module 110 is connected with a third power supply access node, the third end of the flying capacitor module 110 is connected with the input end of the second NOT gate 104, the fourth end of the flying capacitor module 110 is connected with the input end of the third NOT gate 106, the fifth end of the flying capacitor module 110 is connected with the control end of the fifth switch 108, and the sixth end of the flying capacitor module 110 is connected with the control end of the sixth switch 109.

[0025] In some embodiments, the flying capacitor module 110 includes a fourth NOT gate 111, a fifth NOT gate 112, a first flying capacitor switch unit 113, and a second flying capacitor switch unit 114. The input terminal of the fourth NOT gate 111 is connected to the second power supply access node. The input terminal of the fifth NOT gate 112 is connected to the third power supply access node. The first end of the first flying capacitor switch unit 113 is connected to the output terminal of the fourth NOT gate 111. The second end of the first flying capacitor switch unit 113 is connected to the output terminal of the fifth NOT gate 112. The third end of the first flying capacitor switch unit 113 is connected to the input terminal of the second NOT gate 104. The fourth end of the first flying capacitor switch unit 113 is connected to the control terminal of the fifth switch 108. The first end of the second flying capacitor switch unit 114 is connected to the output terminal of the fourth NOT gate 111. The second end of the second flying capacitor switch unit 114 is connected to the output terminal of the fifth NOT gate 112. The third end of the second flying capacitor switch unit 114 is connected to the input terminal of the third NOT gate 106. The fourth end of the second flying capacitor switch unit 114 is connected to the control terminal of the sixth switch 109.

[0026] In some embodiments, the first flying capacitor switch unit 113 includes a seventh switch 115, an eighth switch 116, a ninth switch 117, a tenth switch 118, and a first capacitor 119. One end of the seventh switch 115 is connected to the output terminal of the fourth NOT gate 111. One end of the eighth switch 116 is connected to the other end of the seventh switch 115. The other end of the eighth switch 116 is connected to the input terminal of the second NOT gate 104. One end of the ninth switch 117 is connected to the output terminal of the fifth NOT gate 112. One end of the tenth switch 118 is connected to the other end of the ninth switch 117. The other end of the tenth switch 118 is connected to the control terminal of the eleventh switch 120. One end of the first capacitor 119 is connected to the connection node between the seventh switch 115 and the eighth switch 116. The other end of the first capacitor 119 is connected to the connection node between the ninth switch 117 and the tenth switch 118.

[0027] In some embodiments, the second flying capacitor switching unit 114 includes an eleventh switch 120, a twelfth switch 121, a thirteenth switch 122, a fourteenth switch 123, and a second capacitor 124. One end of the eleventh switch 120 is connected to the output end of the fourth NOT gate 111; one end of the twelfth switch 121 is connected to the other end of the eleventh switch 120, and the other end of the twelfth switch 121 is connected to the input end of the third NOT gate 106; one end of the thirteenth switch 122 is connected to the output end of the fifth NOT gate 112; one end of the fourteenth switch 123 is connected to the other end of the thirteenth switch 122, and the other end of the fourteenth switch 123 is connected to the control end of the twelfth switch 121; one end of the second capacitor 124 is connected to the connection node between the eleventh switch 120 and the twelfth switch 121, and the other end of the second capacitor 124 is connected to the connection node between the thirteenth switch 122 and the fourteenth switch 123.

[0028] Specifically, the flying capacitor auxiliary switch 100 receives an input signal V IN through the input end of the first NOT gate 101, and inputs corresponding control signals to the control ends of the first switch 102, the second switch 103, the third switch 105, the fourth switch 107, the fifth switch 108, and the sixth switch 109, to realize sampling without DC offset to obtain an output signal V out . Meanwhile, appropriate switches and capacitor values can be selected in the embodiments of the present application to minimize the consumption of area, so as to optimize the flying capacitor circuit. Meanwhile, the embodiments of the present application can also mean that each group of flying capacitor circuits is matched on the layout, so as to optimize the flying capacitor layout.

[0029] The flying capacitor auxiliary switch 100 technology works by connecting a series branch composed of an auxiliary switch and a capacitor in parallel with the main power switch tube. Its working principle can be: in the on state (S=high level), a low impedance path (on resistance<100Ω) is formed, and the output signal (OUT) quickly follows the input signal (IN); in the off state (S=low level), the output end is forced to be pulled to ground to avoid high resistance state. Specifically, the flying capacitor auxiliary switch 100 technology utilizes the characteristic that the voltage of the capacitor cannot change abruptly. Before the action of the switch tube, by controlling the conduction and turn-off of the auxiliary switch, the flying capacitor is pre-charged to a certain potential of the input voltage or the output voltage; when it is necessary to switch the state of the main switch tube, the pre-charged flying capacitor will undergo charge redistribution with the parasitic parameters (such as parasitic capacitance) of the circuit, thereby generating a voltage clamping effect across the main switch tube, effectively absorbing the charge between the drain and source of the main switch tube, forcing the voltage of the main switch tube to drop to zero (ZVS) or slowly rise from zero (ZVS / ZCS) before the current is turned on or turned off, thereby realizing soft switching operation. This process can significantly reduce switching loss and voltage stress, suppress electromagnetic interference, and ultimately improve the efficiency and power density of the converter.

[0030] It should be noted that the first switch 102, the second switch 103, the third switch 105, the fourth switch 107, the fifth switch 108 and the sixth switch 109 can all use MOS tubes, and a person skilled in the art can select PMOS tubes or NMOS tubes according to actual needs. The input signal V IN The control signals of the plurality of switches are all designed to be inverted to reduce the output swing, thereby achieving the purposes of low power consumption and high speed.

[0031] Therefore, the embodiment of the present application can replace the traditional transmission gate switch (TG) with the structure of the flying capacitor and gate, and the embodiment of the present application can achieve the following beneficial effects: (1) speed improvement: the signal transmission delay is reduced by 35% compared with the traditional TG; (2) power consumption optimization: the output end is forced to ground when turned off, avoiding charge residue; (3) anti-interference ability: the low-impedance characteristics of the output end reduce crosstalk, and the bit error rate is reduced to below 10^-12; (4) area cost: one MOS tube and one capacitor are added to each switch, and four additional switches are added, but the overall power consumption and performance are significantly improved, which is suitable for high-density FeRAM arrays.

[0032] Further, in some embodiments, as shown in FIG. 2, the comparison unit 201 is an improved double-tail comparator, and the improved double-tail comparator includes a sub-threshold biased integration stage and a cross-coupled positive feedback stage. Figure 3

[0033] Among them, the improved double-tail comparator refers to an optimized double-tail comparator; the sub-threshold biased integration stage refers to an integration amplification unit biased in a sub-threshold operating mode; and the cross-coupled positive feedback stage refers to a circuit unit forming positive feedback in a cross-coupled structure.

[0034] ​Specifically, the pre-amplification stage of the embodiment of the present application adopts sub-threshold bias technology, and the working voltage is reduced to 0.6V to significantly reduce the static power consumption. In order to further improve the gain of the pre-amplification stage, the pre-amplifier is actually implemented by an integrator. In addition, the dynamic latch stage of the embodiment of the present application adopts a cross-coupled structure, accelerates the comparison process through positive feedback, and the response time is less than 0.5ns. At the same time, in order to reduce the power consumption of the dynamic latch stage, the tail current can be controlled within 10μA. Thus, the beneficial effects that can be achieved by the embodiment of the present application include: (1) adopting a double-tail structure: the first stage (integrating stage) adopts a sub-threshold biased differential pair, which is energy-efficient and has lower power consumption than the traditional one; the second stage (positive feedback stage) is composed of cross-coupled NMOS and PMOS, which accelerates the comparison process through positive feedback, and the response time is less than 0.5ns. (2) adopting dynamic voltage regulation: the dynamic adjustment of the working voltage is realized by a binary power supply according to the size of the input signal. When the input is greater than a certain value, the comparator uses a smaller power supply to reduce power consumption. When the output is smaller, a large power supply voltage is used to improve the speed, so as to ensure the speed index while reducing the power consumption of the circuit.

[0035] Optionally, in some embodiments, the calibration unit 202 is specifically configured to short the input end of the comparison unit 201 to a common-mode voltage based on a preset calibration period, and perform a preset successive approximation foreground calibration strategy to generate a digital code word for offsetting random offset, so as to convert the processed signal into a calibrated signal according to the digital code word.

[0036] Optionally, in some embodiments, the calibration unit 202 is specifically configured to short the input end of the comparison unit 201 to a common-mode voltage based on a preset calibration period, and perform a preset successive approximation foreground calibration strategy to generate a digital code word for offsetting random offset, so as to convert the processed signal into a calibrated signal according to the digital code word.

[0037] Specifically, the calibration unit 202 of the embodiment of the present application can adopt an offset calibration mechanism, and the calibration period thereof is that the foreground calibration is triggered once every 1000 comparison times, wherein the foreground calibration refers to the initial calibration performed at power-on; and the calibration process thereof is that, in the calibration period, firstly, the input end of the comparator is shorted to a common-mode voltage, wherein the common-mode voltage VCM=0.5VDD; secondly, the offset voltage is detected through a successive approximation algorithm, and the step precision is controlled by controlling the duty cycle of CAL_CLK.

[0038] Optionally, in some embodiments, the elimination unit 203 is specifically configured to preset the gate-source voltage of the differential input pair of the comparison unit 201 to a corresponding threshold voltage in the circuit initialization stage, so as to eliminate the influence of threshold voltage mismatch on the calibrated signal, and obtain a final output signal.

[0039] Wherein, the circuit initialization stage refers to the preparation stage before the formal signal processing after the circuit power-on; the gate-source voltage of the differential input pair refers to the voltage difference between the gate and the source of the differential input structure in the comparison unit 201; the corresponding threshold voltage refers to the standard threshold voltage matched with the device characteristics.

[0040] Specifically, the elimination unit 203 of the embodiment of the present application can adopt the vth elimination technology, which can eliminate the threshold voltage drift caused by the process deviation. In the initialization stage, the embodiment of the present application biases the gate-source voltage (VGS) of the input tube to Vth in advance, that is In the comparison stage, the VGS of the two input tubes is and The output voltage is related to the drain current (Id1, Id2), that is, related to the transconductance (gm)). Thus, the mismatch caused by Vth is eliminated.

[0041] For example, taking Id1 as an example, Id1 is related to , Similarly, Id2 is only related to V2.

[0042] Therefore, the technical advantages of the embodiments of the present application mainly manifest in the following three aspects: first, power consumption optimization: the total power consumption is reduced compared with the traditional strongarm; second, precision improvement: the precision reaches ±1 mV after the offset voltage is calibrated, and the misjudgment rate is reduced to below 10^10; third, adaptability: supporting on-chip self-calibration, adapting to different process corners and temperature ranges (-40℃~125℃). In addition, the data read-write circuit in the embodiments of the present application can achieve three beneficial effects. On the one hand, in the improvement of the switch structure, the high resistance state can be eliminated, the signal integrity can be improved, the bit error rate can be reduced to 10^-12 level, and at the same time, the speed can be improved by 35%, which is suitable for high-speed low-power FeRAM design; on the other hand, in the optimization of the sensitive amplifier, the power consumption can be reduced by 30% and the precision can be greatly improved, supporting high-reliable data reading, and the self-adaptive calibration mechanism can improve the yield and reliability, reducing the production testing cost; on the other hand, in terms of comprehensive benefits, the energy efficiency ratio (Energy Efficiency) of the overall memory system is improved by 30%, and the read-write speed reaches 1 Gbps; it is suitable for low-power scenarios such as Internet of Things (IoT) devices, edge computing and mobile terminals. In summary, the embodiments of the present application can be mainly applied in the following scenarios: (1) Internet of Things (IoT) devices: the low-power characteristic makes the embodiments of the present application very suitable for non-volatile memories in Internet of Things devices, prolonging the battery life; at the same time, the high-precision comparator and the fast switch structure ensure the reliable reading and writing of data in complex environments. (2) Edge computing: in edge computing devices, the high energy efficiency ratio and high-speed performance of the embodiments of the present application can significantly improve the data processing capability and reduce the delay; at the same time, the self-adaptive calibration mechanism ensures high performance under different temperatures and environmental conditions. (3) Mobile terminal: the embodiments of the present application are suitable for memory modules in mobile terminals such as smartphones and tablet computers, improving the device endurance time and response speed; at the same time, the low-power design reduces heat generation, improving user experience.

[0043] Further, the embodiments of the present application also have the following three potential improvement directions: (1) further reduce power consumption: by optimizing the bias voltage and current of the dynamic bias circuit, further reduce the static power consumption; in the low-frequency mode, the tail current can be further reduced to reduce the standby power consumption. (2) improve speed: use more advanced process nodes to further reduce the on-resistance and parasitic capacitance of MOS tubes, improve the switching speed and comparator response time; at the same time, optimize the layout and wiring to reduce the length of the signal transmission path and reduce the delay. (3) enhance calibration precision: increase the number of bits of the calibration capacitor array to improve the calibration precision to below 0.5 mV; and introduce a deep learning algorithm to dynamically adjust the calibration period and step value to adapt to different working environments.

[0044] The data read-write circuit provided in the embodiment of the present application can sample an input signal through a flying capacitor auxiliary switch to obtain an output signal without DC offset; the comparison unit in the comparison module receives the output signal and performs integral stage processing and positive feedback stage processing on the output signal to obtain a processed signal; the calibration unit in the comparison module calibrates the processed signal based on a preset calibration period to obtain a calibrated signal, and the elimination unit in the comparison module eliminates the influence of threshold voltage mismatch on the calibrated signal to obtain a final output signal. Thus, the problems of high resistance state and speed limitation of a ferroelectric memory transmission gate switch, and insufficient power consumption and precision of a sensitive amplifier in the related art are solved, the switching speed of the ferroelectric memory is improved, and the static or dynamic power consumption of the ferroelectric memory is significantly reduced and the precision is improved.

[0045] The embodiment of the present application also provides a ferroelectric memory comprising the data read-write circuit.

[0046] The ferroelectric memory provided in the embodiment of the present application solves the problems of high resistance state and speed limitation of a ferroelectric memory transmission gate switch, and insufficient power consumption and precision of a sensitive amplifier in the related art through the data read-write circuit, improves the switching speed of the ferroelectric memory, and significantly reduces the static or dynamic power consumption of the ferroelectric memory and improves the precision.

[0047] In addition, the embodiment of the present application also provides a data read-write method as shown in Figure 5

[0048] Figure 5 The flowchart of the data read-write method provided for an embodiment of the present application.

[0049] As shown in Figure 5 The data read-write method comprises the following steps: In step S501, an input signal is sampled through a flying capacitor auxiliary switch to obtain an output signal without DC offset; In step S502, the comparison unit of the comparison module receives the output signal, and performs integral stage processing and positive feedback stage processing on the output signal to obtain a processed signal; the calibration unit of the comparison module calibrates the processed signal based on a preset calibration period to obtain a calibrated signal, and the elimination unit of the comparison module eliminates the influence of threshold voltage mismatch on the calibrated signal to obtain a final output signal.

[0050] The data read-write method provided in the embodiment of the present application solves the problems of high resistance state and speed limitation of a ferroelectric memory transmission gate switch, and insufficient power consumption and precision of a sensitive amplifier in the related art through the data read-write circuit, improves the switching speed of the ferroelectric memory, and significantly reduces the static or dynamic power consumption of the ferroelectric memory and improves the precision.

[0051] ​In the description of the application, reference to "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. In addition, the usage of "N" means at least two, for example two, three or the like, unless explicitly stated otherwise.

[0052] Furthermore, the terms "first", "second", or the like, are used merely as a designation of certain elements or features of the application, and do not imply or connote relative importance or a specific order of precedence. Thus, features defined with "first", "second", etc. can include at least one of the features, either explicitly or implicitly.

[0053] Any process or method descriptions or blocks in flow charts or otherwise described herein represent embodiments of modules, segments, or portions of code which include one or more executable instructions for implementing specific logic functions or steps, and alternate implementations are possible. In some embodiments, the processes or methods described in flow charts or otherwise described herein are not necessarily performed in the order shown or discussed, including, for example, as performed by a computer processor. Alternate implementations can perform functions or steps described in different orders, including substantially concurrently, or in reverse order.

[0054] The logic and / or steps represented in the flowcharts and / or described herein, for example, can be considered as a sequence of executable instructions stored in a computer readable medium, which can be executed by an instruction execution system, apparatus or device, such as a computer-based system, a processor-based system, or other system that can fetch the instructions from the instruction execution system, apparatus or device and execute the instructions, or a combination of the above. For the purposes of this specification, a "computer readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus or device. The computer readable medium can be a computer readable storage medium or a computer readable signal medium. The computer readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a propagation medium. The computer readable signal medium can include, but is not limited to, a computer readable medium that facilitates transfer of the program from one place to another. A specific example of a computer readable medium is a non-transitory computer-readable storage medium. A specific example of a computer readable signal medium is a source or destination of the computer readable medium. Another specific example of a computer readable signal medium is a computer readable signal travelling through space. Thus, a computer readable medium can take many forms of hardware to carry out the program for use by or in connection with the instruction execution system, apparatus or device.

[0055] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware and in another embodiment, the hardware can be implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon an application of data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.

[0056] Those of skill in the art would understand that the steps of the methods carried out above can be carried out wholly or partly by a program instructing relevant hardware, and the program can be stored in a computer readable storage medium, and when executed, includes one or a combination of the steps of the method embodiments.

[0057] In addition, each of the functional units in the various embodiments of the present application can be integrated in one processing module, or each of the units can be physically present separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module. When the integrated module is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0058] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A data read / write circuit, characterized in that, include: A flying capacitor auxiliary switch is used to sample the input signal without DC offset to obtain the output signal; The comparison module includes a comparison unit, a calibration unit, and an elimination unit, wherein... The comparison unit is used to receive the output signal and perform integral-level processing and positive feedback-level processing on the output signal to obtain a processed signal. The calibration unit is used to calibrate the processed signal based on a preset calibration period to obtain a calibrated signal. The elimination unit is used to eliminate the influence of threshold voltage mismatch on the calibrated signal to obtain the final output signal.

2. The data read / write circuit according to claim 1, characterized in that, The flying capacitor auxiliary switch includes: The first NOT gate has its input terminal connected to the signal input node for receiving the input signal; The first switch has its control terminal connected to the output terminal of the first NOT gate, and its first terminal is connected to the first power supply access node. The second switch has its control terminal connected to the output terminal of the first NOT gate, its first terminal connected to the second terminal of the first switch, and its second terminal connected to the grounding node. The second NOT gate is connected to the connection node between the first terminal and the second terminal of the first switch. The third switch has its control terminal connected to the output terminal of the second NOT gate, and its first terminal connected to the first power access node. A third NOT gate and a fourth switch, wherein the control terminal of the fourth switch is connected to the output terminal of the third NOT gate, the first terminal of the fourth switch is connected to the second terminal of the third switch, and the second terminal of the fourth switch is connected to a signal output node; The fifth switch has its first terminal connected to the signal output node and its second terminal connected to the grounding node. The sixth switch has its first end connected to the signal output node and its second end connected to the grounding node. The flying capacitor module has its first terminal connected to the second power access node, its second terminal connected to the third power access node, its third terminal connected to the input terminal of the second NOT gate, its fourth terminal connected to the input terminal of the third NOT gate, its fifth terminal connected to the control terminal of the fifth switch, and its sixth terminal connected to the control terminal of the sixth switch.

3. The data read / write circuit according to claim 2, characterized in that, The flying capacitor module includes: The fourth NOT gate, the input of which is connected to the second power access node; The fifth NOT gate, the input of which is connected to the third power supply access node; The first flying capacitor switch unit has a first terminal connected to the output terminal of the fourth NOT gate, a second terminal connected to the output terminal of the fifth NOT gate, a third terminal connected to the input terminal of the second NOT gate, and a fourth terminal connected to the control terminal of the fifth switch. The second flying capacitor switch unit has its first terminal connected to the output terminal of the fourth NOT gate, its second terminal connected to the output terminal of the fifth NOT gate, its third terminal connected to the input terminal of the third NOT gate, and its fourth terminal connected to the control terminal of the sixth switch.

4. The data read / write circuit according to claim 3, characterized in that, The first flying capacitor switching unit includes: The seventh switch, one end of which is connected to the output of the fourth NOT gate; The eighth switch, one end of which is connected to the other end of the seventh switch, and the other end of which is connected to the input terminal of the second NOT gate; The ninth switch, one end of which is connected to the output terminal of the fifth NOT gate; The tenth switch has one end connected to the other end of the ninth switch, and the other end of the tenth switch is connected to the control terminal of the eleventh switch. A first capacitor, one end of which is connected to the connection node between the seventh switch and the eighth switch, and the other end of which is connected to the connection node between the ninth switch and the tenth switch.

5. The data read / write circuit according to claim 3, characterized in that, The second flying capacitor switching unit includes: The eleventh switch, one end of which is connected to the output of the fourth NOT gate; The twelfth switch, one end of which is connected to the other end of the eleventh switch, and the other end of which is connected to the input terminal of the third NOT gate; The thirteenth switch, one end of which is connected to the output of the fifth NOT gate; The fourteenth switch, one end of which is connected to the other end of the thirteenth switch, and the other end of which is connected to the control terminal of the twelfth switch; The second capacitor has one end connected to the connection node between the eleventh and twelfth switches, and the other end connected to the connection node between the thirteenth and fourteenth switches.

6. The data read / write circuit according to claim 1, characterized in that, The comparison unit is an improved doubletail comparator, which includes a subthreshold biased integral stage and a cross-coupled positive feedback stage.

7. The data read / write circuit according to claim 6, characterized in that, The calibration unit is specifically used to short-circuit the input terminal of the comparison unit to the common-mode voltage based on the preset calibration cycle, and execute a preset successive approximation front-end calibration strategy to generate digital codewords for offsetting random offsets, so as to convert the processed signal into a calibrated signal according to the digital codewords.

8. The data read / write circuit according to claim 7, characterized in that, The elimination unit is specifically used to preset the gate-source voltage of the differential input pair of the comparison unit to the corresponding threshold voltage during the circuit initialization stage, so as to eliminate the influence of threshold voltage mismatch on the calibrated signal and obtain the final output signal.

9. A ferroelectric memory, characterized in that, include: The data read / write circuit as described in any one of claims 1-8.

10. A data read / write method, characterized in that, The method employs the data read / write circuit as described in any one of claims 1-8, wherein the method includes the following steps: The input signal is sampled without DC offset by the flying capacitor auxiliary switch to obtain the output signal; The comparison unit of the comparison module receives the output signal, performs integral-level processing and positive feedback-level processing on the output signal to obtain a processed signal, and calibrates the processed signal based on a preset calibration period through the calibration unit of the comparison module to obtain a calibrated signal. Finally, the elimination unit of the comparison module eliminates the influence of threshold voltage mismatch on the calibrated signal to obtain the final output signal.

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