Packet verification method and device, chip, storage medium and program product

Abstract

The application relates to a message verification method and device, a chip, a storage medium and a program product. The method comprises the following steps: acquiring input data and an input data amount of a current clock beat corresponding to a target verification message; selecting N groups of mask numbers corresponding to a target storage value according to the input data amount of the current clock beat, the target storage value being a cyclic redundancy check value stored in a previous clock beat; performing operation on the N groups of mask numbers and the corresponding target storage value respectively to generate a first logic calculation value of the current clock beat; performing cyclic redundancy iteration operation on the input data of the current clock beat according to the first logic calculation value of the current clock beat to obtain a cyclic redundancy check value corresponding to the current clock beat; and obtaining a final cyclic redundancy check value according to the cyclic redundancy check value corresponding to the current clock beat. The method can reduce the timing convergence and chip wiring difficulty.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a message verification method, apparatus, chip, storage medium, and program product. Background Technology

[0002] Currently, Converged Ethernet Version 2 (RoCEV2) is the mainstream Remote Direct Memory Access (RDMA) technology. The RoCEV2 protocol requires a 4-byte (B) Invariant Cyclic Redundancy Check (ICRC) code to be placed in the message so that the receiving end can verify whether the received message has been accidentally tampered with during network transmission.

[0003] In related technologies, the chip at the message receiving end typically splits the received message into multiple clock cycles and inputs them to the ICRC processing module. The ICRC processing module combines the input data of each clock cycle with the ICRC result registered in the previous clock cycle to calculate a new ICRC result, and then refreshes the registered ICRC result using the new ICRC result until a final ICRC result is obtained. During the calculation of the new ICRC result, the ICRC result registered in the previous clock cycle can be input into multiple different byte-level arithmetic logic operations. Then, based on the amount of input data in the current clock cycle, the logical calculation value of one of the arithmetic logic operations is selected. This logical calculation value is then used in a cyclic redundant iterative operation with the input data of the current clock cycle to obtain the new ICRC result for the current clock cycle.

[0004] However, in the process of calculating a new ICRC result, the ICRC result registered in the previous clock cycle needs to be fan-out into the operation logic of different bytes. As the input bit width increases, the number of operation logics of different bytes also increases accordingly, which increases the difficulty of hardware routing and timing convergence of the chip. Summary of the Invention

[0005] Therefore, it is necessary to provide a message verification method, device, chip, storage medium, and program product that can reduce the difficulty of timing convergence and chip routing in order to address the above-mentioned technical problems.

[0006] Firstly, this application provides a message verification method, including:

[0007] Obtain the input data and input data volume of the current clock tick corresponding to the target verification message;

[0008] Based on the amount of input data at the current clock tick, select N sets of mask numbers corresponding to the target register value. The target register value is the cyclic redundancy check value registered at the previous clock tick. Each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target register value. N is a positive integer determined according to the set rules.

[0009] The N sets of mask numbers and the corresponding target register values ​​are respectively calculated to generate N first logical calculation values ​​of the current clock beat. Each first logical calculation value is the same as the corresponding second logical calculation value. The second logical calculation value is the logical calculation value of the current clock beat obtained by XORing the target register value according to the set rules.

[0010] Based on the N first logical calculation values ​​of the current clock beat, perform cyclic redundancy iterative operation on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat;

[0011] The final cyclic redundancy check value is obtained based on the cyclic redundancy check value corresponding to the current clock beat.

[0012] In one specific embodiment, the method further includes:

[0013] Based on the established rules, determine the bits in the target register value that participate in the XOR calculation;

[0014] The target bit in the masking number is set to 1, and the bits in the masking number other than the target bit are set to 0 to generate a set of masking numbers, wherein the target bit is the bit in the masking number that corresponds to the bit participating in the XOR calculation.

[0015] In one specific implementation, obtaining the final cyclic redundancy check (CRC) value based on the CRC value corresponding to the current clock tick includes:

[0016] If the cyclic redundancy check value corresponding to the current clock beat is the cyclic redundancy check value calculated from the input data of the last time beat, then the final cyclic redundancy check value is calculated based on the cyclic redundancy check value corresponding to the current clock beat.

[0017] If the cyclic redundancy check value corresponding to the current clock tick is not the cyclic redundancy check value calculated from the input data of the last time tick, then the target register value is updated using the cyclic redundancy check value corresponding to the current clock tick. The input data and input data volume of the next clock tick corresponding to the target check message are obtained. Based on the input data volume of the next clock tick, N sets of mask numbers corresponding to the updated target register value are selected. The N sets of mask numbers corresponding to the updated target register value and the updated target register value are calculated respectively to generate N first logical calculation values ​​for the next clock tick. Based on the N first logical calculation values ​​of the next clock tick, cyclic redundancy iteration calculation is performed on the input data of the next clock tick to obtain the cyclic redundancy check value corresponding to the next clock tick. The target register value is updated based on the cyclic redundancy check value corresponding to the next clock tick until the last time tick.

[0018] In one specific implementation, the step of performing calculations on the N sets of mask numbers and the corresponding target register values ​​to generate N first logical calculation values ​​for the current clock tick includes:

[0019] For each group of masking numbers, perform a bitwise AND operation with the corresponding target register value to obtain the logical intermediate value corresponding to each group of masking numbers;

[0020] The logical intermediate values ​​corresponding to each group of masking numbers are XORed to generate a first logical calculation value corresponding to the current clock beat.

[0021] A second aspect of this application also provides a message verification device, the device comprising:

[0022] The acquisition module is used to acquire the input data and input data volume of the current clock tick corresponding to the target verification message;

[0023] The mask selection module is used to select N sets of mask numbers corresponding to the target register value according to the amount of input data of the current clock tick. The target register value is the cyclic redundancy check value registered in the previous clock tick. Each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target register value. N is a positive integer determined according to the set rules.

[0024] The arithmetic module is used to perform calculations on the N sets of masking numbers and the corresponding target registered values ​​to generate N first logical calculation values ​​for the current clock beat. Each first logical calculation value is the same as a corresponding second logical calculation value. The second logical calculation value is the logical calculation value of the current clock beat obtained by XORing the target registered values ​​according to a set rule. Based on the N first logical calculation values ​​of the current clock beat, the module performs cyclic redundancy iterative calculations on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat.

[0025] The cyclic iteration module is used to obtain the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock beat.

[0026] In one specific embodiment, the device further includes:

[0027] The masking number generation module is used to determine the bits in the target register value that participate in the XOR calculation according to the set rules; to determine the value of the target bit in the masking number as 1, and to determine the values ​​of the bits in the masking number other than the target bit as 0, so as to generate a set of the masking numbers, wherein the target bit is the bit in the masking number that corresponds to the bit that participates in the XOR calculation.

[0028] In one specific embodiment, the loop iteration module is further configured to: if the cyclic redundancy check value corresponding to the current clock beat is a cyclic redundancy check value calculated from the input data of the last time beat, then calculate the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock beat; if the cyclic redundancy check value corresponding to the current clock beat is not a cyclic redundancy check value calculated from the input data of the last time beat, then update the target register value using the cyclic redundancy check value corresponding to the current clock beat.

[0029] The acquisition module is also used to acquire the input data and input data volume of the next clock cycle corresponding to the target verification message;

[0030] The shield selection module is also used to select N sets of shield numbers corresponding to the updated target register value based on the amount of input data in the next clock cycle.

[0031] The calculation module is further configured to perform calculations on the N sets of masking numbers corresponding to the updated target register value and the updated target register value respectively to generate N first logical calculation values ​​for the next clock cycle, and perform cyclic redundancy iterative calculations on the input data of the next clock cycle based on the N first logical calculation values ​​of the next clock cycle to obtain the cyclic redundancy check value corresponding to the next clock cycle.

[0032] The cyclic iteration module is also used to update the target register value according to the cyclic redundancy check value corresponding to the next clock tick, until the last time tick.

[0033] In one specific embodiment, the calculation module is further configured to perform a bitwise AND operation on each group of masking numbers and the corresponding target register value to obtain the logical intermediate value corresponding to each group of masking numbers;

[0034] The logical intermediate values ​​corresponding to each group of masking numbers are XORed to generate a first logical calculation value corresponding to the current clock beat.

[0035] Thirdly, this application also provides a chip, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the message verification method of the first aspect described above.

[0036] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the message verification method of the first aspect described above.

[0037] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the message verification method of the first aspect described above.

[0038] The aforementioned message verification method, device, chip, storage medium, and program product acquire the input data and input data volume of the current clock cycle corresponding to the target verification message; based on the input data volume of the current clock cycle, select N sets of mask numbers corresponding to the target registered value, where the target registered value is the cyclic redundancy check value registered in the previous clock cycle, each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target registered value, where N is a positive integer determined according to a set rule; perform calculations on the N sets of mask numbers and the corresponding target registered value respectively to generate the first logical calculation value of the current clock cycle, wherein the first logical calculation value is the same as the second logical calculation value, and the second logical calculation value is the logical calculation value of the current clock cycle obtained by XORing the target registered value according to a set rule; based on the first logical calculation value of the current clock cycle, perform cyclic redundancy iterative calculation on the input data of the current clock cycle to obtain the cyclic redundancy check value corresponding to the current clock cycle; and obtain the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock cycle. By selecting N sets of constant masks corresponding to the target register value based on the input data volume, the first logical value of the current clock cycle is calculated using the N sets of masks and the target register value. This replaces the second logical value obtained by XOR operation according to set rules. Then, using the first logical value, a cyclic redundancy check (CRC) operation is performed on the input data of the current clock cycle to obtain the CRC value corresponding to the current clock cycle. Since the N sets of constant masks are selected based on the input data volume, and the first logical value is calculated using these constant masks, the fan-out of the target register value can be reduced while ensuring the accuracy of the logical value. Even if the input bit width increases, only the corresponding number of masks needs to be increased, thus greatly reducing the difficulty of hardware routing and timing convergence of the chip. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating the principle of calculating ICRC results in related technologies;

[0041] Figure 2 A flowchart illustrating a message verification method provided in an embodiment of this application;

[0042] Figure 3 A schematic diagram illustrating the principle of a message verification method provided in an embodiment of this application;

[0043] Figure 4 A flowchart illustrating another message verification method provided in this application embodiment;

[0044] Figure 5 A structural block diagram of a message verification device provided in an embodiment of this application;

[0045] Figure 6 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] The relevant technologies will be explained below.

[0048] The message receiver can calculate the ICRC result using an XOR operation. To achieve higher processing bandwidth, the internal data bit width and clock frequency of the message receiver chip are increasing, which poses a significant challenge to the ICRC result calculation involved in RoCEV2. For example, if a message has a total length of 640 bytes (depending on the message type, the length of the data carried, etc.), and the ICRC calculation unit's interface bit width is 64 bytes, then the message will require 10 clock cycles to be fully sent to the ICRC calculation unit to obtain the final ICRC result.

[0049] For example, Figure 1 This is a schematic diagram illustrating the principle of calculating ICRC results in related technologies, such as... Figure 1 As shown, the ICRC calculation unit can input the ICRC result (icrc_s) cached in the previous clock cycle into different byte calculation logics, and select the calculated value (calc_in) of one of the calculation logics based on the data volume (num_in) of the input data in the current clock cycle. Then, the calculated value (calc_in) of the selected calculation logic and the input data (data_in) of the current clock cycle are input into the calculation formula (form_0) of the cyclic redundancy iterative operation to obtain a new ICRC result (icrc) for the current clock cycle. Finally, the cached ICRC result (icrc_s) is refreshed using the new ICRC result (icrc). This process is repeated until the ICRC result calculated in the last clock cycle is obtained, and the ICRC result calculated in the last clock cycle is taken as the final ICRC result.

[0050] If the current clock cycle is the first clock cycle of the message, then the ICRC result (icrc_s) cached in the previous clock cycle is the preset initial cyclic redundancy check value. For example, the initial cyclic redundancy check value can be a 32-bit value where all bits are 1.

[0051] The calculation logic for different bytes can be the XOR logic for calculating the ICRC. Since the RoCEV2 protocol requires the 4B ICRC checksum to be 32 bits wide, the calculation logic for different bytes will output a 32-bit ICRC result.

[0052] In related technologies, to optimize the chip's power performance area (PPA), the hardware seeks patterns in the amount of input data per clock cycle during ICRC calculation, thereby reducing the number of "different byte calculation logics". Typically, through logical operations, the amount of data involved in the ICRC calculation for each clock cycle of the RoCEV2 message can be a multiple of 4 bytes. For example, with an input bit width of 64 bytes, there will be 64 / 4 = 16 different possibilities for the amount of data involved in the ICRC calculation per clock cycle.

[0053] It should be understood that different data volumes will use different byte-based computational logic.

[0054] For example, the calculation of a 32-bit calculated value (calc_in_a) output by a 4-byte computation logic (e.g., XOR operation logic) is as follows:

[0055]

[0056] in, to For the 32 bits in the cached ICRC result, to The calculated value is 32 bits for a 4-byte calculation logic. The XOR operation returns 0 if the two bits are the same, and 1 if they are different. For example, XORing 0 and 0 results in 0; XORing 0 and 1 results in 1.

[0057] For example, 8-byte computation logic (e.g., XOR operation logic) differs from 4-byte computation logic (e.g., XOR operation logic), but both output a 32-bit calculated value (calc_in_b), as shown below:

[0058]

[0059] in, to For the 32 bits in the cached ICRC result, to The calculated value is 32 bits for an 8-byte calculation logic.

[0060] It should be noted that the calculation logic for other bytes is similar to that for 4 bytes and 8 bytes. In the 32-bit calculated value output by the calculation logic for other bytes, each bit is also obtained by XORing different bits of the cached ICRC result.

[0061] In related technologies, the calculation formula (form_0) for cyclic redundancy iteration is to perform an XOR operation on the bits of the input data, and then perform an XOR operation on each bit with the corresponding bit of the calculated value (calc_in) of the selected calculation logic to obtain a new ICRC result (icrc) for the current clock cycle. For example, the calculation formula for cyclic redundancy iteration can be as follows:

[0062]

[0063] in, to For the 32 bits in the ICRC result, to For the bits in the input data, to The 32 bits of the calculated value for the selected computation logic.

[0064] It should be understood that each bit of the input data needs to participate in an XOR operation to obtain the ICRC result. Specifically, which bits of the input data need to participate in the calculation of each bit in the ICRC result depends on the chip implementation. Each bit of the calculated value (calc_in) of the selected calculation logic only participates in the calculation of the corresponding ICRC result bit. For example, among all the bits of the calculated value (calc_in) of the calculation logic, only calc_in[0] participates in the calculation of icrc[0], and it appears only once in the calculation of icrc[0]. The input data data_in of each clock cycle will calculate a new ICRC result. After all the data of the message is input, the chip can obtain the final ICRC result of the message.

[0065] However, calculating a new ICRC result requires fanning out the ICRC result registered in the previous clock cycle into different bytes of operational logic. This increases the difficulty of hardware routing, introduces timing closure risks, and excessive fan-out leads to increased chip area and cost. For example, with an input bit width of 64 bytes, and each clock cycle having an input data size that is a multiple of 4 bytes, there are 16 possible operational logic operations. If the input bit width increases to 128 bytes, the number of operational logic operations for different bytes will increase to 256 / 4 = 64. Therefore, as the input bit width increases, the number of operational logic operations for different bytes also increases, further exacerbating the difficulty of hardware routing and timing closure.

[0066] To address the aforementioned issues, this application provides a message verification method, apparatus, chip, storage medium, and program product. It selects N sets of mask numbers corresponding to a target registered value based on the input quantity. These N sets of mask numbers and the target registered value are then used to calculate a first logical value for the current clock cycle, replacing the second logical value obtained by XOR operation according to a set rule. The first logical value is then used to perform cyclic redundancy check (CRC) iterative calculations on the input data for the current clock cycle to obtain the CRC value corresponding to the current clock cycle. Since N sets of constant mask numbers are selected based on the input data quantity, and the first logical value is calculated using these constant mask numbers, the fan-out of the target registered value can be reduced while ensuring the accuracy of the logical value. Even if the input bit width increases, only the corresponding number of mask numbers needs to be increased, thus significantly reducing the difficulty of hardware routing and timing convergence for the chip.

[0067] The message verification method, apparatus, chip, storage medium, and program product provided in this application embodiment can be applied to a message verification device. The message verification device can be any chip or a message verification unit in a chip, and this application embodiment does not impose any restrictions on this.

[0068] In one exemplary embodiment, such as Figure 2 As shown, a message verification method is provided. Taking the application of this method to the message verification device in the aforementioned chip as an example, the method includes steps S201 to S205. Wherein:

[0069] S201. Obtain the input data and input data volume of the current clock tick corresponding to the target verification message.

[0070] In this embodiment of the application, after receiving the target verification message, the chip at the message receiving end can split the target verification message into multiple sub-messages and input the multiple sub-messages as input data into the message verification device in sequence according to multiple clock cycles. The message verification device performs verification. Correspondingly, when verifying each sub-message, the message verification device can obtain the input data and the amount of input data for the current clock cycle.

[0071] The target verification message can be any RoCEV2 message received by the chip at the message receiving end. This RoCEV2 message contains a 4-byte ICRC checksum so that the message receiving end can verify whether the message has been accidentally tampered with during network transmission. Accordingly, the verification of the target verification message can be an ICRC checksum.

[0072] It should be understood that the embodiments of this application do not limit how the target verification message is split. In some embodiments, the message can be split according to the total length of the target verification message and the interface width of the message verification device. For example, if the length of the target verification message is 64 bytes and the interface width of the message verification device is 64 bytes, the target verification message can be split into 10 sub-messages. The 10 sub-messages are then sequentially input to the message verification device for verification over 10 clock cycles to obtain the final cyclic redundancy check value of the target verification message.

[0073] The current clock beat can be any clock beat, and this application embodiment does not impose any restrictions on it.

[0074] For example, if the target verification message is divided into 10 clock cycles for transmission, then the current clock tick can be any one of the first to tenth clock ticks. Correspondingly, the input data and input data volume of the first clock tick can be the input data and input data volume of the first sub-message of the target verification message, and the input data and input data volume of the second clock tick can be the input data and input data volume of the second sub-message of the target verification message.

[0075] S202. Based on the amount of input data at the current clock tick, select the N sets of masking numbers corresponding to the target register value.

[0076] The target register value is the cyclic redundancy check value registered in the previous clock cycle.

[0077] It should be understood that after the message verification device calculates the cyclic redundancy check value (i.e., the ICRC result) for each clock cycle, it will use the cyclic redundancy check value of that clock cycle to update the target register value, and then use the target register value to calculate the cyclic redundancy check value for the next clock cycle, until the last time cycle.

[0078] For example, if the current clock tick is the second clock tick, the target register value of the cache is the cyclic redundancy check value calculated in the first clock tick. If the current clock tick is the third clock tick, the target register value of the cache is the cyclic redundancy check value calculated in the second clock tick.

[0079] For example, if the current clock tick is the first clock tick, the target register value of the cache is the initial cyclic redundancy check (CRC) value. The initial CRC value can be set according to the specific circumstances, for example, to a 32-bit value consisting entirely of 1s.

[0080] The principle of shielding number will be explained below.

[0081] In this system, the number of masks in each group is a constant, and the bit width of each mask group is the same as the bit width of the target registered value. N is a positive integer determined according to a set rule. This set rule is the ICRC calculation rule specified by the Roce protocol, or the ICRC calculation rule specified by other network protocols. For example, in the ICRC calculation specified by the Roce protocol, the fixed bit width of the cyclic redundancy check value can be 32 bits.

[0082] It should be understood that, in the XOR operation logic, if the two bits of the parameter operation are the same (0) and different (1), then the result of XORing 0 with any bit will keep the value of that bit unchanged. For example, XORing 0 with 0 results in 0, and XORing 0 with 1 results in 1. For example, in the calculation of calc_in_a[0] in the 4-byte XOR operation logic, the target register value icrc_s[9] appears only once. If icrc_s[9] appears twice, according to the commutative law of XOR operation ( First, we can calculate the XOR of icrc_s[9] with icrc_s[9], which results in 0. The result of XORing 0 with any bit is to keep the value of that bit unchanged. If icrc_s[9] appears three times, we can first calculate the XOR of two icrc_s[9] to get 0, and then XOR it with icrc_s[9] to get icrc_s[9]. The result of XORing three icrc_s[9] is still icrc_s[9]. Therefore, the repeated icrc_s[9] can be optimized.

[0083] Therefore, it can be seen that each bit in the logically calculated value output by the XOR operation uses a unique bit of the target register value. If a bit of the target register value is repeated, it can be optimized or equal to itself. That is, the extra bits of the target register value are masked in each logical calculation by using a masking factor.

[0084] In some embodiments, the message verification device can determine the bits involved in the XOR calculation in the target register value according to a set rule. Subsequently, the message verification device can set the value of the target bit in the mask number to 1, and set the values ​​of the bits other than the target bit in the mask number to 0, so as to generate a mask number.

[0085] The target bit is the bit in the mask number that corresponds to the bit involved in the XOR calculation.

[0086] For example, for the first logical calculation value calc_in_a[0], the bits of the target register value that are not used during the calculation process can have the corresponding bits of the mask number set to 0, so that the bits of the unused target register value are ANDed with 0 before subsequent calculations are performed, thus achieving the purpose of masking the bits of the unused target register value. The bits of the target register value that are needed during the calculation process can have the corresponding bits of the mask number set to 1, so that the bits of the target register value that are needed are ANDed with 1 before subsequent calculations are performed, thus achieving the purpose of not masking the bits of the target register value that are needed. The specific AND process is shown in the following formula:

[0087]

[0088] Referring to the above formula, the mask number mask_in_a[0] corresponding to the first logical calculation value calc_in_a[0] is 0x80420221. After conversion to binary, bits 0, 5, 9, 17, 22, and 31 of mask_in_a[0] are 1, and the other bits are 0. Thus, during the calculation of the first logical calculation value calc_in_a[0], the bits of the target register value other than bits 0, 5, 9, 17, 22, and 31 are masked. For example, similar to calc_in_a[0], a corresponding mask number is required for each of the four-byte first logical calculation values ​​(e.g., calc_in_a[1], calc_in_a[2], etc.). Since the bit width of the logical calculation value is 32, 32 mask numbers are required. Since the bit width of the target register value is 32, each mask number is 32 bits.

[0089] In some embodiments, N sets of masking numbers can be generated in advance based on masking logic for different data volumes. After obtaining the input data volume of the current clock tick, the N sets of masking numbers corresponding to the target register value under that input data volume can be determined directly based on the correspondence between the input data volume and the N sets of masking numbers.

[0090] For example, taking the first logical calculation value calc_in_a[0] of the 4-byte operation logic as an example, since the constant ANDed with the target register value icrc_s[0] is 1, and the constant ANDed with the target register value icrc_s[1] is 0, the corresponding constants 0 and 1 are extracted sequentially according to icrc_s[0] and icrc_s[1] to form the 32-bit constant corresponding to the masking logic. Among them, the constant extracted from bit 0 is placed in bit 0 of the masking number, and the constant extracted from bit 1 is placed in bit 1 of the masking number.

[0091] S203. Perform calculations on the N sets of mask numbers and their corresponding target register values ​​to generate the N first logic calculation values ​​for the current clock tick.

[0092] The first logical calculation value is the same as the second logical calculation value. The second logical calculation value is the logical calculation value of the current clock tick obtained by XORing the target register value according to the set rules.

[0093] In some embodiments, the message verification device can perform a bitwise AND operation on each group of mask numbers and the corresponding target register value to obtain the logical intermediate value corresponding to each group of mask numbers. Subsequently, the message verification device performs an XOR operation on the logical intermediate value corresponding to each group of mask numbers to generate the first logical calculation value of the current clock cycle.

[0094] Each logical calculation value can include a 32-bit logical intermediate value.

[0095] For example, each data quantity can correspond to 32 groups of 32-bit masks, and each group of 32-bit masks corresponds to a logical intermediate value. For example, mask_in[31:0] is bitwise ANDed with the target register value to obtain the logical intermediate value from bit 0 to bit 31 of the operation logic output. The logical intermediate value from bit 0 to bit 31 is XORed to obtain the first logical calculation value calc_in[0]. The formula is as follows:

[0096]

[0097] Among them, the part outside the parentheses The symbol indicates that an XOR operation will be performed on all bits obtained from the parentheses (i.e., the intermediate values), that is, .

[0098] For example, the first logical calculation value calc_in[0] is the same as the second logical calculation value calc_in1[0] obtained according to the ICRC calculation rules specified in the Roce protocol, the first logical calculation value calc_in[1] is the same as the second logical calculation value calc_in1[1] obtained according to the ICRC calculation rules specified in the Roce protocol, and so on, the first logical calculation value calc_in

[31] is the same as the second logical calculation value calc_in1

[31] obtained according to the ICRC calculation rules specified in the Roce protocol.

[0099] For example, similar to mask_in[31:0], the operation of mask_in[63:32] with the target register value will yield calc_in[1], the operation of mask_in[95:64] with the target register value will yield calc_in[2], and so on, to determine the first logical calculation value for each bit. Finally, each bit of the first logical calculation value is combined to form the final first logical calculation value.

[0100] S204. Based on the first logical calculation value of the current clock beat, perform cyclic redundancy iterative calculation on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat.

[0101] It should be understood that the embodiments of this application do not limit the calculation formula for cyclic redundancy iterative operations, and can be set according to the actual situation.

[0102] In some embodiments, the first logical calculation value of the current clock beat and the input data (data_in) of the current clock beat can be input into the calculation formula (form_0) of the cyclic redundancy iteration operation to perform cyclic redundancy iteration operation and obtain the cyclic redundancy check value corresponding to the current clock beat.

[0103] S205. Obtain the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock tick.

[0104] For example, Figure 3 This is a schematic diagram illustrating the principle of a message verification method provided in an embodiment of this application, as shown below. Figure 3After calculating the cyclic redundancy check (CRUD) value for each clock cycle, it can be determined that the CRUD value corresponding to the current clock cycle is the CRUD value calculated from the input data of the last clock cycle. If the CRUD value corresponding to the current clock cycle is the CRUD value calculated from the input data of the last clock cycle, then the final CRUD value is calculated based on the CRUD value corresponding to the current clock cycle. If the cyclic redundancy check value corresponding to the current clock tick is not the same as the cyclic redundancy check value calculated from the input data of the last clock tick, then the target register value is updated using the cyclic redundancy check value corresponding to the current clock tick. The input data and input data volume of the next clock tick corresponding to the target check message are obtained. Based on the input data volume of the next clock tick, N sets of masking numbers corresponding to the updated target register value are selected. The N sets of masking numbers corresponding to the updated target register value and the updated target register value are calculated respectively to generate the first logical calculation value of the next clock tick. Based on the first logical calculation value of the next clock tick, cyclic redundancy iteration calculation is performed on the input data of the next clock tick to obtain the cyclic redundancy check value corresponding to the next clock tick. The target register value is updated based on the cyclic redundancy check value corresponding to the next clock tick until the last clock tick.

[0105] The message verification method provided in this application embodiment obtains the input data and input data volume of the current clock cycle corresponding to the target verification message; based on the input data volume of the current clock cycle, selects N sets of mask numbers corresponding to the target registered value, where the target registered value is the cyclic redundancy check value registered in the previous clock cycle, each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target registered value, where N is a positive integer determined according to a set rule; performs calculations on the N sets of mask numbers and the corresponding target registered value respectively to generate N first logical calculation values ​​for the current clock cycle, wherein each first logical calculation value is the same as the corresponding second logical calculation value, and the second logical calculation value is the logical calculation value of the current clock cycle obtained by XORing the target registered value according to a set rule; based on the first logical calculation value of the current clock cycle, performs cyclic redundancy iteration calculations on the input data of the current clock cycle to obtain the cyclic redundancy check value corresponding to the current clock cycle; and obtains the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock cycle. By selecting N sets of masking numbers corresponding to the target register value through the input quantity, the first logical value of the current clock cycle is calculated using the N sets of masking numbers and the target register value. This first logical value replaces the second logical value obtained by XOR operation according to the set rules. Then, the first logical value is used to perform cyclic redundancy check (CRC) iterative operation on the input data of the current clock cycle to obtain the CRC value corresponding to the current clock cycle. Since there is no need to select different set rules based on the input data quantity, the fan-out of the target register value can be reduced. Even if the input bit width increases, only the corresponding number of masking numbers needs to be increased, which greatly reduces the difficulty of hardware routing and timing convergence of the chip.

[0106] In one exemplary embodiment, such as Figure 4 As shown, another message verification method is provided. Taking the application of this method to the message verification device in the aforementioned chip as an example, the method includes steps S301 to S308. Wherein:

[0107] S301. Obtain the input data and input data volume of the current clock tick corresponding to the target verification message.

[0108] S302. Based on the amount of input data at the current clock tick, select the N sets of masking numbers corresponding to the target register value.

[0109] The target register value is the cyclic redundancy check value registered in the previous clock cycle. The number of masks in each group is a constant, and the bit width of each mask group is the same as the bit width of the target register value. N is a positive integer determined according to the set rules.

[0110] S303. Perform calculations on the N sets of mask numbers and their corresponding target register values ​​to generate the first logical calculation value of the current clock tick.

[0111] The first logical calculation value is the same as the second logical calculation value. The second logical calculation value is the logical calculation value of the current clock tick obtained by XORing the target register value according to the set rules.

[0112] S304. Based on the first logical calculation value of the current clock beat, perform cyclic redundancy iterative calculation on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat.

[0113] S305. Determine whether the cyclic redundancy check value corresponding to the current clock beat is the cyclic redundancy check value calculated from the input data of the last time beat.

[0114] If yes, then execute S306; otherwise, execute S307.

[0115] S306. Calculate the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock tick.

[0116] S307. Update the target register value using the cyclic redundancy check value corresponding to the current clock tick.

[0117] S308, Increment the current clock beat by one.

[0118] After S308, execute S301.

[0119] The message verification method provided in this application embodiment obtains the input data and input data volume of the current clock cycle corresponding to the target verification message; based on the input data volume of the current clock cycle, selects N sets of mask numbers corresponding to the target registered value, where the target registered value is the cyclic redundancy check value registered in the previous clock cycle, each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target registered value, where N is a positive integer determined according to a set rule; performs calculations on the N sets of mask numbers and the corresponding target registered value respectively to generate the first logical calculation value of the current clock cycle, wherein the first logical calculation value is the same as the second logical calculation value, and the second logical calculation value is the logical calculation value of the current clock cycle obtained by XORing the target registered value according to a set rule; based on the first logical calculation value of the current clock cycle, performs cyclic redundancy iteration calculations on the input data of the current clock cycle to obtain the cyclic redundancy check value corresponding to the current clock cycle; and obtains the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock cycle. By selecting N sets of masking numbers corresponding to the target register value through the input quantity, the N sets of masking numbers and the target register value are used to calculate N first logic values ​​for the current clock cycle. These first logic values ​​replace the second logic value obtained by XOR operation according to the set rules. Then, using the N first logic values, a cyclic redundancy check (CRC) operation is performed on the input data of the current clock cycle to obtain the CRC value corresponding to the current clock cycle. Since the N sets of constant masking numbers are selected based on the input data quantity, and the first logic values ​​are calculated using the N sets of constant masking numbers, the fan-out of the target register value can be reduced while ensuring the accuracy of the logic values. Even if the input bit width increases, only the corresponding number of masking numbers needs to be increased, which greatly reduces the difficulty of hardware routing and timing convergence of the chip.

[0120] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0121] Based on the same inventive concept, this application also provides a message verification device for implementing the message verification method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more message verification device embodiments provided below can be found in the limitations of the message verification method described above, and will not be repeated here.

[0122] In one exemplary embodiment, such as Figure 5 As shown, a message verification device 400 is provided, including: an acquisition module 401, a mask number selection module 402, a calculation module 403, and a loop iteration module 404, wherein:

[0123] The acquisition module 401 is used to acquire the input data and input data volume of the current clock tick corresponding to the target verification message;

[0124] The mask selection module 402 is used to select N sets of mask numbers corresponding to the target register value according to the amount of input data in the current clock cycle. The target register value is the cyclic redundancy check value registered in the previous clock cycle. Each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target register value. N is a positive integer determined according to the set rules.

[0125] The arithmetic module 403 is used to perform calculations on N sets of mask numbers and their corresponding target registered values ​​to generate N first logical calculation values ​​for the current clock beat. Each first logical calculation value is the same as its corresponding second logical calculation value. The second logical calculation value is the logical calculation value of the current clock beat obtained by XORing the target registered values ​​according to a set rule. Based on the first logical calculation values ​​of the current clock beat, the module performs cyclic redundancy iterative calculations on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat.

[0126] The cyclic iteration module 404 is used to obtain the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock tick.

[0127] In some embodiments, the message verification device 400 further includes:

[0128] The mask number generation module is used to determine the bits in the target register value that participate in the XOR calculation according to the set rules; the target bit in the mask number is set to 1, and the bits in the mask number other than the target bit are set to 0, so as to generate a set of mask numbers, wherein the target bit is the bit in the mask number that corresponds to the bit that participates in the XOR calculation.

[0129] In some embodiments, the loop iteration module 404 is further configured to: if the cyclic redundancy check value corresponding to the current clock beat is the cyclic redundancy check value calculated from the input data of the last time beat, then calculate the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock beat; if the cyclic redundancy check value corresponding to the current clock beat is not the cyclic redundancy check value calculated from the input data of the last time beat, then update the target register value using the cyclic redundancy check value corresponding to the current clock beat.

[0130] The acquisition module 401 is also used to acquire the input data and input data volume of the next clock cycle corresponding to the target verification message;

[0131] The mask selection module 402 is also used to select N sets of mask numbers corresponding to the updated target register value based on the amount of input data in the next clock cycle.

[0132] The arithmetic module 403 is also used to perform calculations on the N sets of mask numbers corresponding to the updated target register value and the updated target register value respectively to generate N first logic calculation values ​​for the next clock cycle. Based on the N first logic calculation values ​​for the next clock cycle, the cyclic redundancy iterative calculation is performed on the input data of the next clock cycle to obtain the cyclic redundancy check value corresponding to the next clock cycle.

[0133] The loop iteration module 404 is also used to update the target register value according to the cyclic redundancy check value corresponding to the next clock tick, until the last time tick.

[0134] In some embodiments, the arithmetic module is further configured to perform a bitwise AND operation on each group of masking numbers and the corresponding target register value to obtain the logical intermediate value corresponding to each group of masking numbers;

[0135] Perform an XOR operation on the logical intermediate value corresponding to each group of mask numbers to generate a first logical calculation value corresponding to the current clock beat.

[0136] Each module in the aforementioned message verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0137] In one exemplary embodiment, a computer device is provided, which may be a network device, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a message verification method.

[0138] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0139] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described message verification method.

[0140] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the above-described message verification method.

[0141] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described message verification method.

[0142] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0144] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A message verification method, characterized in that, The method includes: Obtain the input data and input data volume of the current clock tick corresponding to the target verification message; Based on the amount of input data at the current clock tick, select N sets of mask numbers corresponding to the target register value. The target register value is the cyclic redundancy check value registered at the previous clock tick. Each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target register value. N is a positive integer determined according to the set rules. The N sets of mask numbers and the corresponding target register values ​​are respectively calculated to generate N first logical calculation values ​​of the current clock beat. Each first logical calculation value is the same as the corresponding second logical calculation value. The second logical calculation value is the logical calculation value of the current clock beat obtained by XORing the target register value according to the set rules. Based on the N first logical calculation values ​​of the current clock beat, perform cyclic redundancy iterative operation on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat; The final cyclic redundancy check value is obtained based on the cyclic redundancy check value corresponding to the current clock beat.

2. The method according to claim 1, characterized in that, The method further includes: Based on the established rules, determine the bits in the target register value that participate in the XOR calculation; The target bit in the masking number is set to 1, and the bits in the masking number other than the target bit are set to 0 to generate a set of masking numbers, wherein the target bit is the bit in the masking number that corresponds to the bit participating in the XOR calculation.

3. The method according to claim 1, characterized in that, The step of obtaining the final cyclic redundancy check (CRC) value based on the CRC value corresponding to the current clock tick includes: If the cyclic redundancy check value corresponding to the current clock beat is the cyclic redundancy check value calculated from the input data of the last time beat, then the final cyclic redundancy check value is calculated based on the cyclic redundancy check value corresponding to the current clock beat. If the cyclic redundancy check value corresponding to the current clock tick is not the cyclic redundancy check value calculated from the input data of the last time tick, then the target register value is updated using the cyclic redundancy check value corresponding to the current clock tick. The input data and input data volume of the next clock tick corresponding to the target check message are obtained. Based on the input data volume of the next clock tick, N sets of mask numbers corresponding to the updated target register value are selected. The N sets of mask numbers corresponding to the updated target register value and the updated target register value are calculated respectively to generate N first logical calculation values ​​for the next clock tick. Based on the N first logical calculation values ​​of the next clock tick, cyclic redundancy iteration calculation is performed on the input data of the next clock tick to obtain the cyclic redundancy check value corresponding to the next clock tick. The target register value is updated based on the cyclic redundancy check value corresponding to the next clock tick until the last time tick.

4. The method according to claim 1, characterized in that, The step of performing calculations on the N sets of mask numbers and the corresponding target register values ​​to generate N first logical calculation values ​​for the current clock tick includes: For each group of masking numbers, perform a bitwise AND operation with the corresponding target register value to obtain the logical intermediate value corresponding to each group of masking numbers; The logical intermediate values ​​corresponding to each group of masking numbers are XORed to generate a first logical calculation value corresponding to the current clock beat.

5. A message verification device, characterized in that, The device includes: The acquisition module is used to acquire the input data and input data volume of the current clock tick corresponding to the target verification message; The mask selection module is used to select N sets of mask numbers corresponding to the target register value according to the amount of input data of the current clock tick. The target register value is the cyclic redundancy check value registered in the previous clock tick. Each set of mask numbers is a constant, and the bit width of each set of mask numbers is the same as the bit width of the target register value. N is a positive integer determined according to the set rules. The arithmetic module is used to perform calculations on the N sets of masking numbers and the corresponding target registered values ​​to generate N first logical calculation values ​​for the current clock beat. Each first logical calculation value is the same as a corresponding second logical calculation value. The second logical calculation value is the logical calculation value of the current clock beat obtained by XORing the target registered values ​​according to a set rule. Based on the N first logical calculation values ​​of the current clock beat, the module performs cyclic redundancy iterative calculations on the input data of the current clock beat to obtain the cyclic redundancy check value corresponding to the current clock beat. The cyclic iteration module is used to obtain the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock beat.

6. The apparatus according to claim 5, characterized in that, The device further includes: The masking number generation module is used to determine the bits in the target register value that participate in the XOR calculation according to the set rules; to determine the value of the target bit in the masking number as 1, and to determine the values ​​of the bits in the masking number other than the target bit as 0, so as to generate a set of the masking numbers, wherein the target bit is the bit in the masking number that corresponds to the bit that participates in the XOR calculation.

7. The apparatus according to claim 5, characterized in that, The cyclic iteration module is further configured to calculate the final cyclic redundancy check value based on the cyclic redundancy check value corresponding to the current clock beat if the cyclic redundancy check value corresponding to the current clock beat is the cyclic redundancy check value calculated from the input data of the last time beat. If the cyclic redundancy check value corresponding to the current clock beat is not the cyclic redundancy check value calculated from the input data of the last time beat, then the target register value is updated using the cyclic redundancy check value corresponding to the current clock beat. The acquisition module is also used to acquire the input data and input data volume of the next clock cycle corresponding to the target verification message; The shield selection module is also used to select N sets of shield numbers corresponding to the updated target register value based on the amount of input data in the next clock cycle. The calculation module is further configured to perform calculations on the N sets of masking numbers corresponding to the updated target register value and the updated target register value respectively to generate N first logical calculation values ​​for the next clock cycle, and perform cyclic redundancy iterative calculations on the input data of the next clock cycle based on the N first logical calculation values ​​of the next clock cycle to obtain the cyclic redundancy check value corresponding to the next clock cycle. The cyclic iteration module is also used to update the target register value according to the cyclic redundancy check value corresponding to the next clock tick, until the last time tick.

8. The apparatus according to claim 5, characterized in that, The calculation module is also used to perform a bitwise AND operation on each group of masking numbers and the corresponding target register value to obtain the logical intermediate value corresponding to each group of masking numbers; The logical intermediate values ​​corresponding to each group of masking numbers are XORed to generate a first logical calculation value corresponding to the current clock beat.

9. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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