Method, device and equipment for determining risk of timing convergence of module interface in chip

Abstract

This application relates to a method, apparatus, and device for determining timing convergence risks of module interfaces in a chip. The method includes: acquiring interface timing information of module interfaces within each module of the chip, a top-level netlist of the chip, and an empty netlist for each module, wherein the empty netlist contains module interface pin information but has no internal logic; determining the interface timing information of module interfaces at both ends of a target transmission path based on the top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module; determining the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path; and determining whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path. This method can improve the efficiency of timing checks between chip modules.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus and device for determining timing convergence risk of module interface in a chip. Background Technology

[0002] Current timing checks of chip module interfaces require a robust static timing analysis platform environment. This involves preparing top-level design constraints (Synopsys Design Constraints, SDC) files, module physical location information, and probabilistic on-chip variation (POCV) data. Once the platform is built, static timing analysis is used to piece together the module interface information, thereby filtering out interfaces with timing convergence risks.

[0003] Because timing checks of interfaces between chip modules require high standards for the type, accuracy, and completeness of input data, and given that the top-level design decisions for chip projects are not finalized in the early stages and related data preparation is incomplete, setting up an analysis platform typically takes 1-1.5 months. Furthermore, the early iteration of Register Transfer Level (RTL) code and adjustments to the floorplan result in static timing analysis being unable to accurately piece together module interface information. Timing checks start late, and when problems are found, readjustment and verification are required, consuming a significant amount of time, manpower, and resources, resulting in low efficiency for timing checks of interfaces between chip modules. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, and device for determining the timing convergence risk of inter-module interfaces in a chip, which can improve the efficiency of timing inspection between chip modules, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a method for determining timing convergence risk of module interfaces in a chip, including:

[0006] Obtain the interface timing information of the module interfaces within each module in the chip, the chip's top-level netlist, and the empty netlist of each module. The empty netlist contains module interface pin information but has no internal logic.

[0007] Based on the chip top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module, determine the interface timing information of the module interfaces at both ends of the target transmission path;

[0008] Based on the interface timing information of the module interfaces at both ends of the target transmission path, determine the interface timing information corresponding to the target transmission path;

[0009] Based on the timing information of the interfaces corresponding to the target transmission path, determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0010] In one embodiment, determining the interface timing information of the module interfaces at both ends of the target transmission path based on the chip top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module includes:

[0011] The top-level connection information between each module is obtained from the chip's top-level netlist. The top-level connection information is the top-level wiring information between each module used for signal transmission. The top-level connection information includes the interface pin information at both ends of the top-level wiring.

[0012] Obtain the module interface pin information of each module from the empty netlist of each module;

[0013] Based on the top-level connection information and the module interface pin information, the interface connection information between the module interfaces of each module is determined;

[0014] The interface timing information of the module interfaces within each module is associated with the interface connection information of the module interfaces between each module to determine the interface timing information of the module interfaces at both ends of the target transmission path.

[0015] In one embodiment, determining the interface connection information between the modules based on the top-level connection information and the module interface pin information includes:

[0016] Match the pin information at both ends of the top-level connection in the top-level connection information with the module interface pins in the empty netlist of each module to obtain the module input interface and module output interface that have a top-level connection matching relationship;

[0017] The module input interface and module output interface that have a top-level connection matching relationship are determined as the two ends of the target transmission path to obtain the interface connection information between the module interfaces.

[0018] In one embodiment, the interface timing information corresponding to the target transmission path includes the total path delay. Determining the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path includes:

[0019] Extract the data path propagation time of the module input interface and the data path propagation time of the module output interface from the interface timing information of the module interfaces at both ends of the target transmission path;

[0020] The total path delay of the target transmission path is determined based on the data path propagation time of the module input interface and the data path propagation time of the module output interface.

[0021] In one embodiment, determining whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path includes:

[0022] Extract the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path;

[0023] Based on the total path delay and the clock cycle, the timing risk ratio of the target transmission path is determined;

[0024] The timing risk ratio of the target transmission path is compared with a preset risk threshold to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0025] In one embodiment, comparing the timing risk ratio of the target transmission path with a preset risk threshold to determine whether there is timing convergence risk at the module interfaces at both ends of the target transmission path includes:

[0026] If the timing risk ratio is greater than or equal to the preset risk threshold, it is determined that there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0027] If the timing risk ratio is less than the preset risk threshold, then it is determined that there is no timing convergence risk at the module interfaces at both ends of the target transmission path.

[0028] In one embodiment, obtaining the interface timing information of the module interfaces within each module of the chip includes:

[0029] After logic synthesis or place and route are completed for each module in the chip, the interface timing information of the module interfaces in each module in the chip is obtained under the worst timing scenario.

[0030] In the worst-case scenario, the operating temperature exceeds a preset operating temperature threshold, the operating voltage exceeds a preset operating voltage threshold, and the process deviation exceeds a preset process deviation threshold.

[0031] In one embodiment, the method further includes:

[0032] Extract the corresponding data logic depth from the interface timing information of module interfaces that have a risk of timing convergence;

[0033] For module interfaces whose data logic depth is greater than a preset depth threshold, perform logic hierarchy optimization;

[0034] Optimize the transmission path for module interfaces whose data logic depth is less than or equal to a preset depth threshold.

[0035] Secondly, this application also provides a device for determining timing convergence risk of module interface in a chip, comprising:

[0036] The acquisition module is used to acquire the interface timing information of the module interfaces in each module of the chip, the chip top-level netlist, and the empty netlist of each module. The empty netlist is a netlist that contains module interface pin information but has no internal logic.

[0037] The timing determination module is used to determine the interface timing information of the module interfaces at both ends of the target transmission path based on the chip top-level netlist, the empty netlist of each module, and the interface timing information of the module interfaces within each module; and to determine the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path.

[0038] The risk assessment module is used to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path.

[0039] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as shown in the first aspect or any embodiment thereof.

[0040] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as shown in the first aspect or any embodiment thereof.

[0041] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method as shown in the first aspect or any embodiment thereof.

[0042] The aforementioned method, apparatus, and device for determining timing convergence risk of module interfaces in a chip involve acquiring interface timing information of module interfaces within each module of the chip, the chip's top-level netlist, and empty netlists of each module. The empty netlists contain module interface pin information but have no internal logic. Based on the chip's top-level netlist, the empty netlists, and the interface timing information of the module interfaces within each module, the interface timing information of the module interfaces at both ends of a target transmission path is determined. Based on the interface timing information of the module interfaces at both ends of the target transmission path, the interface timing information corresponding to the target transmission path is determined. Based on the interface timing information corresponding to the target transmission path, it is determined whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path. This solution enables timing closure risk assessment of module interfaces using only module interface timing information, top-level netlists, and empty netlists for each module (containing module interface pin information but without internal logic). This eliminates the reliance on complete timing analysis environments such as chip-level SDC and Floorplan, improving the efficiency of inter-module interface timing checks. Furthermore, since the empty netlists contain module interface pin information but lack internal logic, interference from complex internal module logic is avoided, reducing the complexity and computational load of timing analysis and improving efficiency. Simultaneously, because it eliminates the need for a complete timing analysis environment and relies on module interface pin information and top-level connection relationships for assessment, there is no need to build dedicated timing analysis environments for different processes. It is compatible with various chip processes, effectively improving project continuity, reducing redundant development work across different processes and projects, further reducing inspection time, and achieving efficient and universal timing closure risk assessment for module interfaces. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the connection of modules in a chip in one embodiment;

[0045] Figure 2 This is a flowchart illustrating a method for determining timing convergence risk of module interfaces in a chip in one embodiment;

[0046] Figure 3 This is a flowchart illustrating the process of determining interface connection information between modules in one embodiment;

[0047] Figure 4This is a flowchart illustrating the process of determining the interface timing information corresponding to the target transmission path in one embodiment.

[0048] Figure 5 This is a flowchart illustrating the timing convergence risk determination process in one embodiment;

[0049] Figure 6 This is a structural block diagram of a device for determining the timing convergence risk of a module interface in a chip in one embodiment;

[0050] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] Currently, timing checks of interfaces between chip modules require high standards for the variety, accuracy, and completeness of the input data. However, in the early stages of chip projects, much of the data preparation work is still incomplete. For example, preparing the top-level timing constraint file (SDC file) takes two weeks, and debugging the static timing analysis environment requires another month when the project switches processes. Typically, it takes 1-1.5 months after project launch before the first version of timing checks between modules can begin. If interfaces with convergence risks are found during this process, and the issue needs to be resolved by modifying the floorplan, it is necessary to wait for the top-level floorplan to be re-completed, obtain new data, and then redo the verification checks. This entire process consumes a significant amount of time, manpower, and resources.

[0053] To address the aforementioned issues, this application provides a method, apparatus, and device for determining timing convergence risks at module interfaces in a chip. The proposed method precisely fills this gap. In scenarios where the initial project plan is uncertain and frequently modified, this method requires fewer types of input data, needing only module-level information and the chip's top-level netlist, significantly reducing dependence on other top-level data. Simultaneously, it is compatible with multiple processes, exhibits strong project continuity, and has a short inspection time, greatly improving the efficiency of early-stage interface timing iteration optimization.

[0054] The chip-in-module interface timing convergence risk determination method provided in this application embodiment can be applied to a chip-in-module interface timing convergence risk determination device or a computer device. The chip-in-module interface timing convergence risk determination device can be a functional module or functional entity within the computer device that implements the chip-in-module interface timing convergence risk determination method.

[0055] For example, the computer equipment can be dedicated equipment and terminals used in practical applications in the field of chip design. Examples include dedicated workstations for chip design, server clusters, dedicated terminals for integrated circuit design, dedicated computers for Electronic Design Automation (EDA), and cloud computing devices and edge computing devices deployed on the intranet of chip design companies. These devices typically have strong computing power and can efficiently handle tasks such as netlist analysis and data processing in the process of determining timing convergence risks of chip module interface, thus meeting the practical application needs of timing checks in the early stages of chip projects.

[0056] Figure 1 This is a schematic diagram showing the connection of modules in a chip in one embodiment. For example... Figure 1 As shown, the chip integrates multiple functional modules, such as module 1, module 2, ..., module n. Each module is configured with at least one module interface. For example, module 1 includes interfaces A and B, module 2 includes interfaces C and D, and module n includes interfaces X and Y. Information is transmitted between the interfaces of different modules via a transmission path (e.g., the connection between interface B of module 1 and interface C of module 2). In this embodiment, based on this interface connection relationship between modules, by extracting the timing information of the module interfaces and determining the timing information of the interface interfaces at both ends of the same transmission path, the risk of module interface timing convergence can be quickly determined. This eliminates the dependence on a complete timing analysis environment at the top level of the chip, improves the efficiency of interface timing checks in the early stages of chip projects, and solves the problems of long data preparation cycles and low iterative optimization efficiency in existing technologies.

[0057] In one exemplary embodiment, such as Figure 2 As shown, a method for determining timing convergence risk of module interface in a chip is provided, the method including the following steps 201 to 204:

[0058] 201. Obtain the interface timing information of the module interfaces within each module of the chip, the chip's top-level netlist, and the empty netlist of each module.

[0059] The empty netlist contains module interface pin information but has no internal logic. This empty netlist differs from the module netlist, which contains complete internal logic. Its purpose is to provide module interface pin definitions without loading the module's internal computational logic, thus significantly reducing data preparation and loading time.

[0060] The aforementioned top-level netlist of the chip is used to provide the top-level connection relationship between each module and to clarify the connection correspondence between the interfaces of different modules.

[0061] The aforementioned interface timing information refers to the parameter information of the module interface during the timing transmission process, including but not limited to data path propagation time, clock name, clock cycle, data logic depth, etc., which serves as the basis for subsequent timing convergence risk assessment.

[0062] The acquisition of the aforementioned interface timing information requires the basic data after the module logic synthesis or placement and routing is completed. There is no need to wait for complete data such as the top-level timing constraint file (SDC file) and the floorplan, which effectively shortens the data preparation cycle. The chip top-level netlist is the basic data that can be quickly obtained in the early stage of the chip project. The empty netlists of each module can be generated through simple processing without complex debugging, which further reduces the difficulty of obtaining input data.

[0063] The basic data after the module logic synthesis is completed consists of the module netlist and related preliminary timing data after performance, power consumption, and area (PPA) optimization. This netlist is generated by RTL code conversion and contains key contents such as the module's internal logic information, discrete Fourier transform, gated clock, and I / O. It also includes timing estimation data generated during the synthesis process based on the process electrical and physical characteristics, which can initially reflect the timing transmission capability of the module interface. It can be exported through some synthesis tools and has completed the preliminary mapping and optimization of logic units, providing logical support for the extraction of interface timing information.

[0064] The basic data after the placement and routing are completed mainly includes the final optimized physical netlist, timing simulation data, and physical attribute data of the module interface pins. The physical netlist has been converted into a format suitable for layout generation, clearly defining the placement, interconnection, and routing details of each functional circuit within the module. The timing simulation data contains key parameters such as path delay and clock synchronization under different operating scenarios and has undergone static timing analysis verification, accurately reflecting the actual timing performance of the interface. This data can be obtained through placement and routing tools and serves as the basis for extracting interface timing information.

[0065] In some implementations, obtaining the interface timing information of the module interfaces within each module in the chip may include, but is not limited to: after each module in the chip has completed logic synthesis or placement and routing, obtaining the interface timing information of the module interfaces within each module in the chip under the worst-case timing scenario.

[0066] Among them, the worst timing scenario refers to the working scenario where the chip's timing transmission performance is at its worst, such as the timing scenario at the chip's highest operating frequency and the worst operating temperature. The interface timing information obtained under this scenario can maximize the coverage of timing convergence risk points, ensure the accuracy and comprehensiveness of subsequent risk assessment, and avoid risk omission due to improper scenario selection.

[0067] In some embodiments, the worst-case timing scenario is characterized by the operating temperature exceeding a preset operating temperature threshold, the operating voltage exceeding a preset operating voltage threshold, and the process deviation exceeding a preset process deviation threshold.

[0068] For example, the implementation process of step 201 above specifically includes the following sub-steps, corresponding to the extraction process of module interface information:

[0069] 201a. Start the tool corresponding to logic synthesis or place and route, load the data saved by logic synthesis or place and route into the tool, and generate an empty netlist containing only interfaces.

[0070] The empty netlist retains only the name, type, and level of the module interface pins, while removing internal logic units and connections to reduce data redundancy and speed up subsequent platform loading.

[0071] 201b. Switch the scenario to the worst-case timing scenario, distinguish all interfaces according to input and output, and use a script to generate the corresponding interface timing path for different interface types (module input interface, module output interface).

[0072] The module input interface refers to the module interface that receives external data, and the module output interface refers to the module interface that sends internal data to the outside. The script automatically distinguishes the interface type and generates the timing path, eliminating the need for manual operation and improving the acquisition efficiency.

[0073] 201c. Use a script to process the generated timing path, extract detailed timing information, and generate an interface timing report, which serves as the input file for subsequent steps.

[0074] The script processing includes operations such as timing parameter extraction, redundant information filtering, and format standardization. The extracted timing information specifically includes data path propagation time, clock name, clock cycle, and data logic depth. The name of the interface timing report must include the corresponding module name to facilitate subsequent association with module levels.

[0075] 202. Based on the chip's top-level netlist, empty netlist, and the interface timing information of the module interfaces within each module, determine the interface timing information of the module interfaces at both ends of the target transmission path.

[0076] The target transmission path refers to the path through which two modules are directly connected via a top-level connection and used to transmit the same set of data signals. The two ends of this path are the module output interface of one module and the module input interface of another module (if there are multiple module output interfaces, the same module input interface and each module output interface constitute an independent transmission path).

[0077] The purpose of determining the interface timing information of the module interfaces at both ends of the target transmission path (the same transmission path) is to associate the interface timing information scattered in various modules based on the actual top-level connection relationship, clarify the two ends of each transmission path and their timing parameters, and lay the foundation for subsequent total path delay calculation and risk assessment.

[0078] In some implementations, determining the interface timing information of the module interfaces at both ends of the target transmission path may include, but is not limited to, the following sub-steps:

[0079] 202a. Obtain the top-level connection information between modules from the chip's top-level netlist.

[0080] The top-level connection information includes the names of all connections at the top level of the chip, the modules and pin identifiers at both ends of the connection, which clarifies the physical connection relationship between different modules and serves as the basis for associating the interfaces of each module.

[0081] The aforementioned top-level connection information refers to the top-level wiring information used for signal transmission between modules. The top-level connection information includes the interface pin information at both ends of the top-level wiring.

[0082] 202b. Obtain the module interface pin information of each module from the empty netlist of each module.

[0083] The module interface pin information includes pin name, pin type (input / output), pin level, etc., which is used to match the pin identifier in the top-level connection information to determine the specific module interface corresponding to the top-level connection.

[0084] 202c. Based on the top-level connection information and module interface pin information, determine the interface connection information between modules.

[0085] The interface connection information refers to the correspondence between the module interfaces at both ends of the target transmission path, including the module input interface, module output interface module affiliation, pin names, etc. The specific implementation process can be achieved through script matching, which will be discussed later. Figure 3 Detailed explanation.

[0086] 202d. Associate the interface timing information of the module interfaces within each module with the interface connection information of the module interfaces between each module to determine the interface timing information of the module interfaces at both ends of the target transmission path.

[0087] Among them, the timing parameters (data path propagation time, clock cycle, etc.) corresponding to the interfaces at both ends of each transmission path can be associated and bound through the interface connection information to form a complete transmission path timing dataset.

[0088] 203. Based on the interface timing information of the module interfaces at both ends of the target transmission path, determine the interface timing information corresponding to the target transmission path.

[0089] Among them, the interface timing information corresponding to the target transmission path is the total path delay of the path. The total path delay refers to the total time taken for the data signal to be transmitted from the module input interface to the module output interface of the target transmission path. Its magnitude directly determines the timing performance of the target transmission path and is an indicator for subsequent timing convergence risk assessment. In addition, the interface timing information corresponding to the target transmission path may also include the clock cycle corresponding to the path, which is used to calculate the timing risk ratio value.

[0090] For example, the implementation process of step 203 above can be automatically calculated by a script. It can be achieved by superimposing the timing parameters of the interfaces at both ends of the target transmission path. Specific details will be discussed later. Figure 4 Detailed explanations are provided to ensure the accuracy and efficiency of the calculation process, avoiding errors and time-consuming manual calculations.

[0091] 204. Based on the timing information of the interfaces corresponding to the target transmission path, determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0092] Among them, timing convergence risk refers to the risk that the data signal transmission time of the module interface exceeds the allowable range of the clock cycle during the timing transmission process, which leads to abnormal chip operation and performance degradation. This step 204 achieves accurate judgment and sorting of risks by quantitatively analyzing the timing parameters of the transmission path, which makes it easier for staff to quickly locate high-risk interfaces, prioritize optimization, and improve the efficiency of early-stage iteration optimization of the project.

[0093] In some implementations, determining whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path may include, but is not limited to: extracting the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path; determining the timing risk ratio of the target transmission path based on the total path delay and the clock cycle; and comparing the timing risk ratio of the target transmission path with a preset risk threshold to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0094] The timing risk ratio is calculated as follows: Timing risk ratio = Total path delay ÷ Clock cycle. The higher the ratio, the greater the proportion of data signal transmission time to clock cycle, the higher the difficulty of timing convergence, and the higher the risk. The preset risk threshold can be flexibly set according to the design requirements and process characteristics of the chip project.

[0095] For example, the preset risk threshold can be set to 80%, that is, when the daily risk ratio is ≥80%, it is determined that there is a risk of time series convergence. The specific threshold can be adjusted according to the actual scenario.

[0096] The aforementioned method for determining timing convergence risks at chip module interfaces can assess these risks using only module interface timing information, the top-level netlist, and empty netlists for each module (containing module interface pin information but without internal logic). This eliminates the reliance on complete timing analysis environments such as the chip's top-level SDC and Floorplan, improving the efficiency of timing checks between chip modules. Furthermore, since the empty netlists contain module interface pin information but lack internal logic, interference from complex internal logic within the modules is avoided, reducing the complexity and computational load of timing analysis and increasing efficiency. Simultaneously, because it does not rely on a complete timing analysis environment and is based on module interface pin information and top-level connection relationships, there is no need to rebuild dedicated timing analysis environments for different processes. It is compatible with various chip processes, effectively improving project inheritance, reducing redundant development work across different processes and projects, further reducing check time, and achieving efficient and universal module interface timing convergence risk assessment.

[0097] In some embodiments, during the process of determining the interface connection information of the module interfaces between each module, the pin information at both ends of the top-level connection in the top-level connection information can be matched with the module interface pins in the empty netlist of each module to obtain the module input interface and module output interface that have a top-level connection matching relationship, so as to obtain the interface connection information of the module interfaces between each module.

[0098] In one exemplary embodiment, such as Figure 3 The diagram illustrates a flowchart for determining interface connection information between modules. The flowchart includes:

[0099] 301. Match the pin information at both ends of the top-level connection in the top-level connection information with the module interface pins in the empty netlist of each module to obtain the module input interface and module output interface that have a top-level connection matching relationship.

[0100] In this process, the pins at both ends of the top-level connection information correspond to the interface pins of two different modules, one being an output pin (corresponding to the module's output interface) and the other an input pin (corresponding to the module's input interface). This step involves using a script to traverse all the connections in the top-level connection information, extract the pin identifiers at both ends of each connection, and then match them with the interface pin information in the empty netlist of each module. This process clarifies the module's input and output interfaces corresponding to each connection, ensuring the accuracy of the match and avoiding matching errors caused by inconsistent pin identifiers.

[0101] For example, if there is a connection in the top-level connection information, with one end pin identified as "Module 1_Out1" and the other end pin identified as "Module 2_In1", by matching the empty netlists of each module, it is determined that "Module 1_Out1" is the module output interface pin of Module 1 and "Module 2_In1" is the module input interface pin of Module 2. This yields matching module output interfaces of Module 1 and module input interfaces of Module 2. If one end of a connection is an input pin and the other end is connected to multiple output pins (i.e., one module input interface corresponds to multiple module output interfaces), then each output pin is matched with its corresponding module output interface, resulting in multiple sets of matching relationships.

[0102] 302. The module input interface and module output interface with a top-level connection matching relationship are identified as the two ends of the target transmission path to obtain the interface connection information between the module interfaces.

[0103] The interface connection information is stored in the form of signal pairs between module input interfaces and module output interfaces, and is associated with the corresponding top-level connection name, module affiliation and other information, which are used for the association of subsequent interface timing information and the calculation of total path delay. If there is a case where one module input interface corresponds to multiple output interfaces, the module input interface and each output interface are respectively formed into independent signal pairs, which serve as the two ends of different transmission paths, ensuring that all transmission paths are covered without omission.

[0104] The above process can be implemented automatically through Tool Command Language (Tcl) scripts, eliminating the need for manual matching, which greatly improves the efficiency of determining interface connection information and avoids errors caused by manual matching. Through this process, the top-level connection relationship can be quickly associated with the module interface pin information, clarifying the two ends of each transmission path, providing reliable support for subsequent timing information splicing and risk assessment, and effectively solving the problem of cumbersome and time-consuming module interface association in the existing technology.

[0105] In one exemplary embodiment, such as Figure 4 The diagram illustrates a process for determining the timing information of the interface corresponding to the target transmission path. The process includes:

[0106] 401. Extract the data path propagation time of the module input interface and the data path propagation time of the module output interface from the interface timing information of the module interfaces at both ends of the target transmission path.

[0107] Among them, the data path propagation time refers to the transmission time of the data signal within the module interface. The data path propagation time of the module input interface is the time it takes for the data signal to be transmitted from the module input interface pin to the internal logic boundary of the module, and the data path propagation time of the module output interface is the time it takes for the data signal to be transmitted from the internal logic boundary of the module to the module output interface. This parameter has been processed in advance by the script in step 201, extracted into the interface timing report, and back-annotated to the corresponding module interface pin. This step can be directly extracted by the script.

[0108] For example, the two ends of the target transmission path are the module output interface of module A and the module input interface of module B. The data path propagation time of the module output interface of module A is extracted from the interface timing information as 0.8ns, and the data path propagation time of the module input interface of module B is 0.6ns, which are used for the subsequent calculation of the total path delay.

[0109] 402. Based on the data path propagation time of the module input interface and the data path propagation time of the module output interface, determine the total path delay of the target transmission path.

[0110] The timing information of the interface corresponding to the target transmission path includes the total path delay.

[0111] In some embodiments, the total path delay can be used as the interface timing information corresponding to the target transmission path.

[0112] The total path delay can be the sum of the data path propagation time of the module input interface and the data path propagation time of the module output interface. The total time spent by the data signal in the target transmission path is equal to the sum of its transmission time within the module input interface and the transmission time within the module output interface. There is no need to separately calculate the transmission time of the top-level connection (the transmission time of the top-level connection is negligible compared to the time within the interface, or it can be considered to be included in the interface data path propagation time), simplifying the calculation process while ensuring the reasonableness of the calculation results.

[0113] For example, in conjunction with the above example, the data path propagation time of the module output interface of module A is 0.8ns, and the data path propagation time of the module input interface of module B is 0.6ns. Therefore, the total path delay of the target transmission path is 0.8ns + 0.6ns = 1.4ns. At the same time, the clock period corresponding to the transmission path is extracted from the timing information of the two interfaces and is 2ns. Finally, the timing information of the interface corresponding to the target transmission path is determined as follows: total path delay 1.4ns, clock period 2ns, which is used for subsequent timing convergence risk assessment.

[0114] The above process automatically extracts parameters and calculates the total path delay through scripts, enabling rapid determination of the timing information of the target transmission path. This avoids the tediousness and errors of manual calculation and improves the efficiency of timing checks. At the same time, the calculation logic is simple, easy to understand, and verifiable, ensuring the accuracy of the timing information and providing a guarantee for the reliability of subsequent risk assessment.

[0115] In one exemplary embodiment, such as Figure 5 As shown, a flowchart for determining the time series convergence risk is provided. The process includes:

[0116] 501. Extract the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path.

[0117] The clock cycle refers to the period of the chip clock signal, which determines the maximum allowable time for data signal transmission. The module interfaces at both ends of the target transmission path usually correspond to the same clock signal, so the clock cycle can be extracted from the timing information of either end interface. If the clock cycles of the two ends interfaces are inconsistent, the clock cycle with the lower frequency and longer period shall be used to ensure the rigor of risk assessment.

[0118] For example, the clock period corresponding to a certain transmission path is extracted to be 2ns, which means that the maximum transmission time of the data signal allowed by the transmission path is 2ns. Exceeding this time may lead to timing convergence failure.

[0119] 502. Based on the total path delay and clock cycle, determine the timing risk ratio of the target transmission path.

[0120] The formula for calculating the timing risk ratio is: Timing Risk Ratio = Total Path Delay ÷ Clock Cycle. The calculation result is presented as a percentage, which makes it easy to intuitively judge the degree of risk. The significance of this ratio is to quantify the proportion of data transmission time to clock cycle. The higher the ratio, the smaller the timing redundancy and the higher the convergence risk.

[0121] For example, in conjunction with the above example, if the total path delay is 1.4ns and the clock cycle is 2ns, then the timing risk ratio = 1.4ns ÷ 2ns × 100% = 70%. This ratio reflects the timing tension of the target transmission path.

[0122] 503. Determine whether the time-series risk ratio is greater than or equal to the preset risk threshold.

[0123] If the time-series risk ratio is greater than or equal to the preset risk threshold, then proceed to step 504 below; if the time-series risk ratio is less than the preset risk threshold, then proceed to step 505 below.

[0124] The preset risk threshold can be flexibly set according to the design requirements, process nodes, and performance indicators of the chip project. For example, for high-performance chips, the preset risk threshold can be set to 75%, and for ordinary performance chips, the preset risk threshold can be set to 85%. The preset risk threshold needs to be clearly defined before the project starts and written into the script configuration file for easy adjustment and execution.

[0125] 504. It is determined that there is a risk of timing convergence at the module interfaces at both ends of the target transmission path.

[0126] When the timing risk ratio is greater than or equal to the preset risk threshold, it indicates that the data signal transmission time has approached or exceeded the allowable range of the clock cycle, and the timing redundancy is insufficient. If optimization is not performed, timing convergence failure and data transmission errors are likely to occur during subsequent chip operation. For interfaces with risks, information such as the corresponding signal pair, timing risk ratio, total path delay, and clock cycle should be recorded for subsequent optimization.

[0127] 505. Determine that there is no risk of timing convergence at the module interfaces at both ends of the target transmission path.

[0128] When the timing risk ratio is less than the preset risk threshold, it means that the data signal transmission time is much less than the clock cycle allowable range, the timing redundancy is sufficient, no additional optimization is needed, and it can directly enter the subsequent design process; such interfaces can be marked as "risk-free" and do not need to be checked repeatedly, reducing unnecessary workload.

[0129] For example, if the preset risk threshold is set to 80%, and the timing risk ratio in the above example is 70%, then 70% < 80%, it is determined that there is no timing convergence risk at the interfaces at both ends of the transmission path; if the total path delay of another transmission path is 1.7ns, the clock period is 2ns, and the timing risk ratio is 85%, then 85% ≥ 80%, it is determined that there is a timing convergence risk.

[0130] The above process can be implemented automatically by a Tcl script. It iterates through the timing information of all transmission paths, completes the risk assessment, outputs the risk information of all interfaces to form a report, and sorts them from largest to smallest according to the timing risk ratio. This makes it easier for staff to quickly locate high-risk interfaces and prioritize optimization work, greatly improving the efficiency of timing optimization in the early stage of the project and solving the problem of cumbersome and time-consuming risk location in existing technologies.

[0131] In some embodiments, the method for determining the timing convergence risk of module interfaces in a chip may further include: extracting the corresponding data logic depth from the interface timing information of module interfaces with timing convergence risk; performing logic level optimization on module interfaces with data logic depth greater than a preset depth threshold; and performing transmission path optimization on module interfaces with data logic depth less than or equal to the preset depth threshold.

[0132] Among them, data logic depth refers to the number of internal logic layers corresponding to the module interface. The more logic layers there are, the longer the data path propagation time is, and the higher the risk of timing convergence.

[0133] The preset depth threshold can be set according to the complexity of the module design and the characteristics of the process. For example, the preset depth threshold can be set to 10 levels.

[0134] For module interfaces with a data logic depth greater than a preset depth threshold, logic level optimization can be adopted, including logic unit reconstruction, redundant logic deletion, and logic level splitting, to reduce the internal logic levels of the interface and shorten the data path propagation time. For module interfaces with a data logic depth less than or equal to a preset depth threshold, transmission path optimization can be adopted, including top-level connection adjustment, interface pin reallocation, and clock phase optimization, to reduce the total transmission path time.

[0135] By employing targeted optimization methods, the timing convergence risk of high-risk interfaces can be quickly reduced, optimization efficiency can be improved, and the waste of time and manpower caused by blind optimization can be avoided. At the same time, the timing information of the optimized interfaces can be re-entered into the method of this application for secondary risk assessment, forming a closed-loop process to ensure that the timing convergence risk is completely resolved.

[0136] In some implementations, the method of this application can also build a platform that can splice module interface information. The platform construction process specifically includes the following sub-steps to support the smooth execution of the above steps:

[0137] a) Start the static timing analysis tool and read in the top-level netlist and the empty netlist of the module.

[0138] This method eliminates the need to read top-level SDC files, Floorplan data, etc., and avoids the need to debug a complete static time series analysis environment, significantly shortening the platform setup time. Platform setup can usually be completed within 1-2 days, which is a significant improvement in efficiency compared to the one-month environment debugging time of existing technologies.

[0139] b) Back-annotate the module's interface timing report information to the tool platform.

[0140] The above-mentioned method of back-annotating the module's interface timing report information to the tool platform specifically includes:

[0141] (1) Define all information types contained in the module interface timing report as new user attributes on the tool platform; among them, user attributes are used to store interface timing parameters, including data path propagation time, clock name, clock cycle, data logic depth, etc., to ensure that timing information can be recognized and called by the platform.

[0142] (2) Read in all the interface timing reports of the modules that need to be checked. The timing report name should include the module name to facilitate the subsequent association of the corresponding module level and avoid confusion of interface timing information of different modules.

[0143] For example, Table 1 below illustrates the information included in a time series report.

[0144] Table 1

[0145]

[0146] Table 1 above is an example of the core information in the module interface timing report, containing key timing parameters of the transmission path. The timing risk ratio directly corresponds to the ratio of the total delay of the transmission path to the clock cycle. The first four ratios in Table 1 are all 1.595, and the fifth is 1.594, all greater than 1. This indicates that the data transmission time of these transmission paths has exceeded the allowable range of the clock cycle, posing a very high risk of timing convergence.

[0147] The driver-side delay ratio and the load-side delay ratio quantify the proportion of the internal delay of the driver-side and receiver-side interfaces to the clock cycle, respectively. The “driver-side” corresponds to the module output interface (the module interface on the signal sending side) of the transmission path in the previous embodiment, and the “load-side” corresponds to the module input interface (the module interface on the signal receiving side) of the transmission path in the previous embodiment. The main sources of delay can be quickly located through these two ratio values. The driver-side logic level and the load-side logic level reflect the internal logic depth of the interface. Taking “8 (3)” as an example, the “8” outside represents the total number of logic levels inside the interface, and the “3” inside the parentheses represents the number of stacked logic levels inside the interface. The more logic levels there are, the longer the data path propagation time is, and the higher the risk of timing convergence.

[0148] The total logic hierarchy refers to the total number of logic units (such as AND gates, OR gates, flip-flops, etc.) that a data signal passes through when it travels from the module interface pin to the internal logic boundary of the module. This directly determines the basic delay of the data path within the interface. The stacked logic hierarchy refers to the additional logic hierarchy generated by the cascading of logic units in the data signal transmission path within the module interface. These hierarchy levels are typically composed of redundant buffers or multi-level driver units and are a secondary but crucial factor leading to increased interface latency.

[0149] For example, the first driver-side logic level is 8 (3) and the load-side logic level is 33 (4), indicating that the total logic level and stacked logic level inside the load-side (module input interface) are more, which is one of the main reasons for the timing tension of this transmission path. In addition, the combined stacking delay ratio, driver-side stacking delay ratio and load-side stacking delay ratio supplement the delay overhead of the interconnect stacking logic, providing accurate data support for subsequent optimization. These parameters will be automatically back-annotated to the static timing analysis platform through Tcl scripts for transmission path splicing and risk assessment, which is the core data foundation for realizing the rapid identification of timing convergence risks in this application.

[0150] It should be noted that the data in Table 1 above is only an illustrative example. In practice, the timing report of the above module interface may also include clock cycle, driver pin and load pin, etc. The pin information is used to match the connection relationship of the top-level netlist and further clarify the two ends of the transmission path interface.

[0151] (3) Parse the timing report name and its contents of the module interface through the Tcl script, find the corresponding module level, and back-annotate the timing information in the report to the corresponding module level pin in the platform environment in the form of new pin attributes; wherein, the Tcl script can automatically parse the report format, extract timing parameters, associate the module level and pin identifier, realize the automatic back-annotation of timing information, without manual input, improve efficiency and avoid errors.

[0152] c) Based on the top-level connection relationship, the interface information at both ends of the same connection is spliced ​​together and the total timing information is calculated using a script.

[0153] The above-mentioned method involves concatenating the interface information at both ends of the same connection based on the top-level connection relationship and calculating the total timing information using a script. Specifically, this may include:

[0154] (1) Capture all connections in the top-level netlist, clarify the range of transmission paths that the platform needs to process, and ensure that there are no omissions.

[0155] (2) Traverse all connections and mark the module input interface and module output interface of the connection as a pair of signals. If there are multiple module output interfaces, mark the same module input interface and multiple module output interfaces as a pair of signals respectively, corresponding to the interface matching logic in steps 301-302.

[0156] (3) Extract the timing information of the reverse label in step b) of the interface of the same pair of signals and calculate it. Add the data logic path propagation time of the module input interface to the data logic path propagation time of the module output interface to obtain the total path delay of the pair of signals. At the same time, extract the clock cycle on the interface and divide the total path delay by the clock cycle to obtain the timing risk ratio value. Output the corresponding signal pair and the calculated value to form a report.

[0157] (4) View the report and sort the proportion values ​​in the report from largest to smallest to obtain all interface information sorted by risk proportion, so that staff can quickly locate high-risk interfaces and optimize them first.

[0158] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0159] Based on the same inventive concept, this application also provides a device for determining the timing convergence risk of a module interface in a chip, used to implement the aforementioned method for determining the timing convergence risk of a module interface in a chip. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the device for determining the timing convergence risk of a module interface in a chip provided below can be found in the limitations of the method for determining the timing convergence risk of a module interface in a chip described above, and will not be repeated here.

[0160] In one exemplary embodiment, such as Figure 6 As shown, a device for determining timing convergence risk of module interface in a chip is provided, comprising:

[0161] The acquisition module 601 is used to acquire the interface timing information of the module interface in each module of the chip, the top-level netlist of the chip, and the empty netlist of each module. The empty netlist is a netlist that contains module interface pin information but has no internal logic.

[0162] The timing determination module 602 is used to determine the interface timing information of the module interfaces at both ends of the target transmission path based on the top-level netlist of the chip, the empty netlist of each module, and the interface timing information of the module interfaces within each module; and to determine the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path.

[0163] The risk assessment module 603 is used to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path.

[0164] In some embodiments, the timing determination module 602 is specifically used for:

[0165] The top-level connection information between each module is obtained from the chip's top-level netlist. The top-level connection information is the top-level wiring information between each module used for signal transmission. The top-level connection information includes the interface pin information at both ends of the top-level wiring.

[0166] Obtain the module interface pin information of each module from the empty netlist of each module;

[0167] Based on the top-level connection information and the module interface pin information, the interface connection information between the module interfaces of each module is determined;

[0168] The interface timing information of the module interfaces within each module is associated with the interface connection information of the module interfaces between each module to determine the interface timing information of the module interfaces at both ends of the target transmission path.

[0169] In some embodiments, the timing determination module 602 is specifically used for:

[0170] Match the pin information at both ends of the top-level connection in the top-level connection information with the module interface pins in the empty netlist of each module to obtain the module input interface and module output interface with the top-level connection matching relationship, so as to obtain the interface connection information of the module interface between each module.

[0171] In some embodiments, the interface timing information corresponding to the target transmission path includes the total path delay, and the timing determination module 602 is specifically used for:

[0172] Extract the data path propagation time of the module input interface and the data path propagation time of the module output interface from the interface timing information of the module interfaces at both ends of the target transmission path;

[0173] The total path delay of the target transmission path is determined based on the data path propagation time of the module input interface and the data path propagation time of the module output interface.

[0174] In some embodiments, the risk assessment module 603 is used for:

[0175] Extract the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path;

[0176] Based on the total path delay and the clock cycle, the timing risk ratio of the target transmission path is determined;

[0177] The timing risk ratio of the target transmission path is compared with a preset risk threshold to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0178] In some embodiments, the risk assessment module 603 is used for:

[0179] If the timing risk ratio is greater than or equal to the preset risk threshold, it is determined that there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0180] If the timing risk ratio is less than the preset risk threshold, then it is determined that there is no timing convergence risk at the module interfaces at both ends of the target transmission path.

[0181] In some embodiments, the acquisition module 601 is specifically used to: after each module in the chip has completed logic synthesis or placement and routing, acquire the interface timing information of the module interfaces in each module in the chip under the worst-case timing scenario.

[0182] In some embodiments, the apparatus may further include an optimization module for:

[0183] Extract the corresponding data logic depth from the interface timing information of module interfaces that have a risk of timing convergence;

[0184] For module interfaces whose data logic depth is greater than a preset depth threshold, perform logic hierarchy optimization;

[0185] Optimize the transmission path for module interfaces whose data logic depth is less than or equal to a preset depth threshold.

[0186] The modules in the timing convergence risk determination device for the module interface in the aforementioned chip can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in a computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0187] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network. When the computer program is executed by the processor, it implements a method for determining the timing convergence risk of a module interface in a chip.

[0188] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0189] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0190] Obtain the interface timing information of the module interfaces within each module in the chip, the chip's top-level netlist, and the empty netlist of each module. The empty netlist contains module interface pin information but has no internal logic.

[0191] Based on the chip top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module, determine the interface timing information of the module interfaces at both ends of the target transmission path;

[0192] Based on the interface timing information of the module interfaces at both ends of the target transmission path, determine the interface timing information corresponding to the target transmission path;

[0193] Based on the timing information of the interfaces corresponding to the target transmission path, determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0194] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0195] The top-level connection information between each module is obtained from the chip's top-level netlist. The top-level connection information is the top-level wiring information between each module used for signal transmission. The top-level connection information includes the interface pin information at both ends of the top-level wiring.

[0196] Obtain the module interface pin information of each module from the empty netlist of each module;

[0197] Based on the top-level connection information and the module interface pin information, the interface connection information between the module interfaces of each module is determined;

[0198] The interface timing information of the module interfaces within each module is associated with the interface connection information of the module interfaces between each module to determine the interface timing information of the module interfaces at both ends of the target transmission path.

[0199] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0200] Match the pin information at both ends of the top-level connection in the top-level connection information with the module interface pins in the empty netlist of each module to obtain the module input interface and module output interface with the top-level connection matching relationship, so as to obtain the interface connection information of the module interface between each module.

[0201] In one embodiment, the interface timing information corresponding to the target transmission path includes the total path delay, and the processor, when executing the computer program, further implements the following steps:

[0202] Extract the data path propagation time of the module input interface and the data path propagation time of the module output interface from the interface timing information of the module interfaces at both ends of the target transmission path;

[0203] The total path delay of the target transmission path is determined based on the data path propagation time of the module input interface and the data path propagation time of the module output interface.

[0204] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0205] Extract the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path;

[0206] Based on the total path delay and the clock cycle, the timing risk ratio of the target transmission path is determined;

[0207] The timing risk ratio of the target transmission path is compared with a preset risk threshold to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0208] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0209] If the timing risk ratio is greater than or equal to the preset risk threshold, it is determined that there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

[0210] If the timing risk ratio is less than the preset risk threshold, it is determined that there is no timing convergence risk at the module interfaces at both ends of the target transmission path. If the timing risk ratio is greater than or equal to the preset risk threshold, it is determined that there is timing convergence risk at the module interfaces at both ends of the target transmission path.

[0211] If the timing risk ratio is less than the preset risk threshold, then it is determined that there is no timing convergence risk at the module interfaces at both ends of the target transmission path.

[0212] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0213] After logic synthesis or place and route are completed for each module in the chip, the interface timing information of the module interfaces in each module in the chip is obtained under the worst timing scenario.

[0214] In the worst-case scenario, the operating temperature exceeds a preset operating temperature threshold, the operating voltage exceeds a preset operating voltage threshold, and the process deviation exceeds a preset process deviation threshold.

[0215] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0216] Extract the corresponding data logic depth from the interface timing information of module interfaces that have a risk of timing convergence;

[0217] For module interfaces whose data logic depth is greater than a preset depth threshold, perform logic hierarchy optimization;

[0218] Optimize the transmission path for module interfaces whose data logic depth is less than or equal to a preset depth threshold.

[0219] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the various processes shown in the above method embodiments.

[0220] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the various processes shown in the above method embodiments.

[0221] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0222] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0223] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for determining timing convergence risk of module interfaces in a chip, characterized in that, include: Obtain the interface timing information of the module interfaces within each module in the chip, the chip's top-level netlist, and the empty netlist of each module. The empty netlist contains module interface pin information but has no internal logic. Based on the chip top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module, determine the interface timing information of the module interfaces at both ends of the target transmission path; Based on the interface timing information of the module interfaces at both ends of the target transmission path, determine the interface timing information corresponding to the target transmission path; Based on the timing information of the interfaces corresponding to the target transmission path, determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

2. The method according to claim 1, characterized in that, The step of determining the interface timing information of the module interfaces at both ends of the target transmission path based on the chip top-level netlist, the empty netlist, and the interface timing information of the module interfaces within each module includes: The top-level connection information between each module is obtained from the chip's top-level netlist. The top-level connection information is the top-level wiring information between each module used for signal transmission. The top-level connection information includes the interface pin information at both ends of the top-level wiring. Obtain the module interface pin information of each module from the empty netlist of each module; Based on the top-level connection information and the module interface pin information, the interface connection information between the module interfaces of each module is determined; The interface timing information of the module interfaces within each module is associated with the interface connection information of the module interfaces between each module to determine the interface timing information of the module interfaces at both ends of the target transmission path.

3. The method according to claim 2, characterized in that, The step of determining the interface connection information between the modules based on the top-level connection information and the module interface pin information includes: Match the pin information at both ends of the top-level connection in the top-level connection information with the module interface pin information in the empty netlist of each module to obtain the module input interface and module output interface with the top-level connection matching relationship, so as to obtain the interface connection information between the module interfaces of each module.

4. The method according to claim 2, characterized in that, The interface timing information corresponding to the target transmission path includes the total path delay. Determining the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path includes: Extract the data path propagation time of the module input interface and the data path propagation time of the module output interface from the interface timing information of the module interfaces at both ends of the target transmission path; The total path delay of the target transmission path is determined based on the data path propagation time of the module input interface and the data path propagation time of the module output interface.

5. The method according to claim 4, characterized in that, The step of determining whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path includes: Extract the clock cycle corresponding to the target transmission path from the interface timing information of the module interfaces at both ends of the target transmission path; Based on the total path delay and the clock cycle, the timing risk ratio of the target transmission path is determined; The timing risk ratio of the target transmission path is compared with a preset risk threshold to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path.

6. The method according to claim 5, characterized in that, The step of comparing the timing risk ratio of the target transmission path with a preset risk threshold to determine whether there is timing convergence risk at the module interfaces at both ends of the target transmission path includes: If the timing risk ratio is greater than or equal to the preset risk threshold, it is determined that there is a timing convergence risk at the module interfaces at both ends of the target transmission path. If the timing risk ratio is less than the preset risk threshold, then it is determined that there is no timing convergence risk at the module interfaces at both ends of the target transmission path.

7. The method according to any one of claims 1 to 6, characterized in that, The acquisition of interface timing information of module interfaces within each module of the chip includes: After logic synthesis or place and route are completed for each module in the chip, the interface timing information of the module interfaces in each module in the chip is obtained under the worst timing scenario. In the worst-case scenario, the operating temperature exceeds a preset operating temperature threshold, the operating voltage exceeds a preset operating voltage threshold, and the process deviation exceeds a preset process deviation threshold.

8. The method according to any one of claims 1 to 6, characterized in that, The method further includes: Extract the corresponding data logic depth from the interface timing information of module interfaces that have a risk of timing convergence; For module interfaces whose data logic depth is greater than a preset depth threshold, perform logic hierarchy optimization; Optimize the transmission path for module interfaces whose data logic depth is less than or equal to a preset depth threshold.

9. A device for determining timing convergence risk of module interface in a chip, characterized in that, include: The acquisition module is used to acquire the interface timing information of the module interfaces in each module of the chip, the chip top-level netlist, and the empty netlist of each module. The empty netlist is a netlist that contains module interface pin information but has no internal logic. The timing determination module is used to determine the interface timing information of the module interfaces at both ends of the target transmission path based on the chip top-level netlist, the empty netlist of each module, and the interface timing information of the module interfaces within each module; and to determine the interface timing information corresponding to the target transmission path based on the interface timing information of the module interfaces at both ends of the target transmission path. The risk assessment module is used to determine whether there is a timing convergence risk at the module interfaces at both ends of the target transmission path based on the interface timing information corresponding to the target transmission path.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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