Preparation method of capacitor and memory, and dynamic random access memory
By using microwave annealing and electrocrystallization techniques at low temperatures, the thermal damage problem of DRAM devices caused by high-temperature processing was solved, enabling the fabrication of capacitors with high dielectric properties and high integration density, thereby improving the manufacturing yield and reliability of DRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-20
AI Technical Summary
Existing technologies make it difficult to crystallize capacitor dielectric layers with high dielectric properties at low temperatures, leading to thermal damage and performance degradation in DRAM devices during high-temperature processing.
Microwave annealing is used to induce the crystallization of the high-k dielectric layer at low temperature. By combining microwave and electro-crystallization techniques, the dielectric layer is crystallized at temperatures below 400°C through microwave annealing, thus avoiding thermal damage to the underlying transistor structure.
This technology enables efficient crystallization at low temperatures, improving the integration density and reliability of DRAM devices, avoiding damage to transistors caused by high-temperature processing, and ensuring high dielectric performance and manufacturing yield.
Smart Images
Figure CN121712005A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor storage, and particularly relates to a capacitor and a preparation method of a memory and a dynamic random access memory. BACKGROUND
[0002] In the prior art, as the dynamic random access memory (DRAM) continues to evolve towards smaller process nodes, the size of the storage capacitor continues to shrink. In order to maintain sufficient charge storage capacity, high dielectric constant (High-k) materials must be used as the capacitor dielectric layer. Hafnium-based oxides (such as HfO2, ZrO2 and their solid solutions HZO) have become promising candidate materials due to their high k value and potential ferroelectric properties. However, these materials usually require annealing at high temperatures above 600℃ to effectively crystallize and obtain the required high dielectric properties. The problem is that the preparation of the capacitor of the DRAM is located after the completion of the front-end device structure such as the transistor, and these formed devices are extremely sensitive to heat and cannot withstand such a high heat budget. High temperatures not only cause gate oxide degradation, dopant atom diffusion and threshold voltage drift, but also cause the oxidation of commonly used TiN electrodes to form low-k TiO x Although existing technologies such as rapid thermal annealing (RTP) can shorten the high temperature time, the overall process temperature cannot be reduced below 450℃, making it difficult to meet the stringent requirements of low heat budget for advanced DRAM processes.
[0003] Therefore, there is an urgent need for a capacitor and a preparation method of a memory and a dynamic random access memory to improve the above problems. SUMMARY
[0004] The present application provides a capacitor and a preparation method of a memory and a dynamic random access memory, which is used to realize the crystallization of high dielectric performance dielectric layer under low temperature process conditions, and improve the integration density and reliability of the DRAM device.
[0005] According to a first aspect of an embodiment of the present application, a method for manufacturing a capacitor used in a dynamic random access memory is provided. The method comprises: forming a stop layer on a substrate having transistors and a storage node; forming an insulating molding layer on the stop layer; etching the insulating molding layer and the stop layer to form a pillar hole; the pillar hole is used to expose the storage node; depositing a first electrode layer on the insulating molding layer, the inner wall and the bottom of the pillar hole; forming an insulating pillar filling the pillar hole on the surface of the first electrode layer; polishing the surface of the insulating pillar to expose the first electrode layer on the insulating molding layer; etching to remove the first electrode layer and the insulating molding layer between adjacent insulating pillars to form an etching groove to expose the first electrode layer at the bottom of the insulating pillar and the stop layer; forming an electrode extension layer on the sidewall of the insulating pillar, the first electrode layer at the bottom of the insulating pillar and the stop layer; etching to remove the electrode extension layer on the stop layer; forming a dielectric layer on the electrode extension layer and the stop layer; performing a microwave annealing process on the substrate having the dielectric layer to induce crystallization of the dielectric layer; depositing a second electrode layer on the dielectric layer to fill the etching groove; and the first electrode layer, the dielectric layer and the second electrode layer constitute the capacitor.
[0006] In an embodiment, the microwave annealing process on the substrate having the dielectric layer comprises: using a microwave frequency in the range of [2.45, 5.80] GHz to perform the microwave annealing process on the substrate having the dielectric layer.
[0007] In an embodiment, the microwave annealing process on the substrate having the dielectric layer comprises: using a microwave parameter in the pulse or continuous wave mode, the power value in the range of [100, 3000] W, and the time value in the range of [10, 60] s to perform the microwave annealing process on the substrate having the dielectric layer; and the heating temperature of the substrate during the microwave annealing process is less than or equal to 400 ℃.
[0008] In an embodiment, the microwave annealing process on the substrate having the dielectric layer comprises: performing the microwave annealing process on the substrate having the dielectric layer in an inert gas atmosphere or vacuum.
[0009] In an embodiment, the material of the dielectric layer comprises at least one of HfO2, ZrO2 and a solid solution thereof.
[0010] In an embodiment, when the material of the dielectric layer comprises a solid solution and ZrO2, forming the dielectric layer on the electrode extension layer and the stop layer comprises: adjusting the deposition cycle ratio of the solid solution and ZrO2 by an atomic layer deposition process to form a crystallization nucleus during the deposition process; and making the top layer of the dielectric layer be ZrO2; the ZrO2 at the top layer is used to stabilize the morphotropic phase boundary (MPB) of the solid solution through interface strain during the microwave annealing process.
[0011] In an embodiment, the method further comprises: forming a dielectric protective layer on the top layer of the dielectric layer; the material of the dielectric protective layer comprises aluminum oxide; the aluminum oxide is used to constrain the stable solid solution through the amorphous interface.
[0012] In an embodiment, the material of the first electrode layer, the electrode extension layer and the second electrode layer all comprises TiN.
[0013] In an embodiment, after depositing the second electrode layer on the dielectric layer, the method further comprises: polishing the surface of the second electrode layer to expose the insulating pillar; and forming a metal interconnection layer on the second electrode layer.
[0014] According to a second aspect of the embodiments of the present application, a preparation method of a memory is provided, the method comprising: providing a substrate; forming a transistor and a storage node on the substrate; and preparing a capacitor by using any one of the methods of the first aspect to form a dynamic random access memory.
[0015] According to a third aspect of the embodiments of the present application, a dynamic random access memory is provided, the memory comprising: a substrate, a transistor, a storage node, a stop layer, a first electrode layer, an electrode extension layer, an insulating pillar, a dielectric layer and a second electrode layer; the transistor and the storage node are both located between the substrate and the stop layer; the stop layer is formed with the dielectric layer; the number of the dielectric layer is M, M is a positive integer greater than 1; the dielectric layer is induced to crystallize after being subjected to a microwave annealing treatment; the first electrode layer is arranged between adjacent dielectric layers; the first electrode layer penetrates through the stop layer and connects the storage node; the first electrode layer is arranged in a cylindrical shape with a first opening, the first opening is directed away from the storage node; the insulating pillar is located in the first electrode layer; the longitudinal section of the dielectric layer is arranged in a U shape, the longitudinal section passes through the axis of the insulating pillar; the dielectric layer wraps the second electrode layer; the first electrode layer, the dielectric layer and the second electrode layer constitute a capacitor.
[0016] Compared with the prior art, the capacitor preparation method provided by the present application has the following beneficial effects: by constructing a columnar capacitor structure on the substrate formed with the transistor and the storage node, and by using a microwave annealing treatment to induce crystallization after depositing a high-K dielectric layer, while controlling the heating temperature of the substrate during the annealing process below 400℃, the low-temperature efficient crystallization and the reliability of the device are synergistically optimized. Since the microwave energy can be selectively absorbed by the dielectric layer, the internal atoms can obtain sufficient energy to complete the crystal phase transformation, such as forming an orthorhombic phase with high dielectric constant, while the overall temperature of the substrate remains at a low level, significantly reducing the process thermal budget. This low-temperature condition effectively avoids thermal damage to the lower layer of the transistor structure that has been formed, prevents the diffusion of doped atoms, the degradation of gate oxide, and the oxidation of TiN electrode to form low-k TiO xand manufacturing yield of DRAM memory cells, especially suitable for advanced nodes with strict requirements on thermal sensitivity in the back-end process of DRAM. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 is a flow chart of a preparation method of a capacitor and a memory and a dynamic random access memory method according to an exemplary embodiment.
[0018] Figure 2 is a structural diagram of forming a stop layer and an insulating molding layer according to an exemplary embodiment.
[0019] Figure 3 is a structural diagram of etching a pillar hole for forming a contact storage node according to an exemplary embodiment.
[0020] Figure 4 is a structural diagram after depositing a first electrode layer according to an exemplary embodiment.
[0021] Figure 5 is a structural diagram after filling and forming an insulating pillar according to an exemplary embodiment.
[0022] Figure 6 is a structural diagram after planarization and etching to form an etching groove according to an exemplary embodiment.
[0023] Figure 7 is a structural diagram after forming an electrode extension layer and removing excess parts according to an exemplary embodiment.
[0024] Figure 8 is a structural diagram of forming a dielectric layer on the electrode extension layer and the stop layer according to an exemplary embodiment.
[0025] Figure 9 is a structural diagram after depositing a second electrode layer to fill the etching groove according to an exemplary embodiment.
[0026] Figure 10 is a structural diagram after polishing the surface of the second electrode layer to expose the insulating pillar according to an exemplary embodiment.
[0027] BRIEF DESCRIPTION OF DRAWINGS 1, substrate; 2, storage node; 3, isolation layer; 4, stop layer; 5, insulating molding layer; 6, pillar hole; 7, first electrode layer; 71, electrode extension layer; 8, insulating pillar; 9, etching groove; 10, dielectric layer; 11, second electrode layer. DETAILED DESCRIPTION
[0028] Unless otherwise defined, all technical and scientific terms used in this specification shall have the meaning commonly understood by one of ordinary skill in the art to which this application pertains. The description of the application given herein is based on specific embodiments and examples, but the application is not limited thereto since modifications and equivalents of the application will be apparent to those skilled in the art. The disclosures herein are not specifically limited to the exact embodiments described and illustrated, as variations of those embodiments could be made and still be within the scope of the disclosure.
[0029] As shown in FIG. 1, a first embodiment of the present application provides a method for manufacturing a capacitor used for constructing a dynamic random access memory, the method comprising the following steps S1-S9: Figure 1 Step S1, forming a stop layer 4 on a substrate 1 in which transistors and storage nodes 2 are formed; forming an insulating molding layer 5 on the stop layer 4, obtaining an intermediate structure as shown in FIG. 2. Figure 2 Step S2, etching the insulating molding layer 5 and the stop layer 4 to form a pillar hole 6; the pillar hole 6 is used to expose the storage node 2, obtaining an intermediate structure as shown in FIG. 3.
[0030] Step S3, depositing a first electrode layer 7 on the insulating molding layer 5, the inner wall and the bottom of the pillar hole 6, obtaining an intermediate structure as shown in FIG. 4. Figure 3
[0031] Step S4, forming an insulating pillar 8 filling the pillar hole 6 on the surface of the first electrode layer 7, obtaining an intermediate structure as shown in FIG. 5. Figure 4
[0032] Step S5, polishing the surface of the insulating pillar 8 to expose the first electrode layer 7 on the insulating molding layer 5; etching to remove the first electrode layer 7 and the insulating molding layer 5 between adjacent insulating pillars 8, forming an etching groove 9 to expose the first electrode layer 7 and the stop layer 4 at the bottom of the insulating pillar 8, obtaining an intermediate structure as shown in FIG. 6. Figure 5
[0033] Step S6, forming an electrode extension layer 71 on the sidewall of the insulating pillar 8, the first electrode layer 7 and the stop layer 4 at the bottom of the insulating pillar 8; etching to remove the electrode extension layer 71 on the stop layer 4, obtaining an intermediate structure as shown in FIG. 7. Figure 6
[0034] Step S7, forming a second electrode layer 8 on the electrode extension layer 71, obtaining an intermediate structure as shown in FIG. 8. Figure 7
[0035] Step S7, forming a dielectric layer 10 on the electrode extension layer 71 and the stop layer 4, to obtain an intermediate structure as shown in FIG. 7. Figure 8
[0036] Step S8, performing a microwave annealing process on the substrate 1 with the dielectric layer 10 formed thereon, to induce crystallization of the dielectric layer 10.
[0037] Step S9, depositing a second electrode layer 11 on the dielectric layer 10, to fill the etching groove 9, to obtain an intermediate structure as shown in FIG. 8. Figure 9
[0038] In some specific embodiments, in step S2, the number of the pillar holes 6 is a positive integer. The pillar holes 6 are used to define the position and size of the insulating pillars 8.
[0039] In some other specific embodiments, in step S3, an Atomic Layer Deposition (ALD) process is used to deposit the first electrode layer 7 on the insulating forming layer 5, the inner wall and bottom of the pillar holes 6.
[0040] In some other specific embodiments, in step S5, the polishing process on the upper surface of the insulating pillars 8 includes a Chemical Mechanical Polishing (CMP) process on the upper surface of the insulating pillars 8, to improve the flatness of the upper surface of the insulating pillars 8.
[0041] In some other specific embodiments, in step S6, the etching process to remove the electrode extension layer 71 on the stop layer 4 includes an anisotropic etching process to remove the electrode extension layer 71 on the stop layer 4, leaving only the electrode extension layer 71 on the sidewall of the insulating pillars 8.
[0042] In some examples, the electrode extension layer 71 on the upper surface of the insulating pillars 8 can be removed by the polishing process in S5, or can be removed together with the electrode extension layer 71 on the stop layer 4 in the anisotropic etching process in S6.
[0043] In one implementation, the microwave annealing process on the substrate 1 with the dielectric layer 10 formed thereon includes a microwave annealing process on the substrate 1 with the dielectric layer 10 formed thereon using a microwave frequency range of [2.45, 5.80] GHz.
[0044] In some examples, the microwave annealing process on the substrate 1 with the dielectric layer 10 formed thereon uses a microwave frequency of 2.45 GHz.
[0045] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment in a microwave frequency band of 5.80 GHz.
[0046] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment in a microwave frequency band of 4.125 GHz.
[0047] In one embodiment, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment, including: the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment by using microwave parameters in a pulse or continuous wave mode, with a power range of [100, 3000] W and a time range of [10, 60] s; and the heating temperature of the substrate is less than or equal to 400 ℃ during the microwave annealing treatment.
[0048] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment by using microwave parameters in a pulse mode, with a power of 100 W and a time of 10 s.
[0049] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment by using microwave parameters in a continuous wave mode, with a power of 3000 W and a time of 60 s.
[0050] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment by using microwave parameters in a continuous wave mode, with a power of 1550 W and a time of 35 s.
[0051] In one embodiment, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment, including: the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment in an inert gas atmosphere or vacuum.
[0052] In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment in an inert gas atmosphere. In some examples, the substrate 1 with the dielectric layer 10 is subjected to microwave annealing treatment in a vacuum.
[0053] In one embodiment, the material of the dielectric layer 10 includes at least one of HfO2, ZrO2 and a solid solution thereof.
[0054] In some specific embodiments, when the material of the dielectric layer 10 includes a solid solution and ZrO2, the dielectric layer 10 is formed on the electrode extension layer 71 and the stop layer 4, including: the deposition cycle ratio of the solid solution and ZrO2 is adjusted by an atomic layer deposition process to form a crystal nucleus in the deposition process; and the top layer of the dielectric layer 10 is ZrO2; the ZrO2 at the top layer is used to stabilize the morphotropic phase boundary of the solid solution by interface strain during the microwave annealing process.
[0055] It is worth mentioning that the ZrO2 on the top layer is used to introduce moderate compressive strain at the interface during the microwave annealing process by using the difference in lattice constant between the ZrO2 and the underlying hafnium-zirconium oxide solid solution (HZO), thereby inhibiting the transformation of HZO to the monoclinic phase (M phase) and promoting the formation and stability of the morphotropic phase boundary structure of the coexistence of the ferroelectric orthorhombic phase (O phase) and the antiferroelectric tetragonal phase (T phase), thereby improving the effective dielectric constant and electrical properties of the dielectric layer 10.
[0056] In an embodiment, the method further comprises: forming a dielectric protective layer on the top layer of the dielectric layer 10; the material of the dielectric protective layer comprises aluminum oxide; and the aluminum oxide is used to constrain the morphotropic phase boundary of the stable solid solution through the amorphous interface.
[0057] It is worth mentioning that the aluminum oxide is used to exert interface constraint on the surface of the underlying hafnium-zirconium oxide solid solution (HZO) through its amorphous structure during the microwave annealing and subsequent processes, limit the excessive growth of grains and phase separation, thereby inhibiting the generation of the thermodynamically stable monoclinic phase and effectively maintaining the morphotropic phase boundary state of the coexistence of the ferroelectric orthorhombic phase and the antiferroelectric tetragonal phase; at the same time, the aluminum oxide as a dense dielectric barrier layer can prevent the diffusion of oxygen, moisture or metal impurities in the environment into the HZO layer, further ensuring the structural integrity and electrical stability of the morphotropic phase boundary.
[0058] In an embodiment, the material of the first electrode layer 7, the electrode extension layer 71 and the second electrode layer 11 all comprises TiN.
[0059] In some specific embodiments, the material of the first electrode layer 7, the electrode extension layer 71 and the second electrode layer 11 is TiN.
[0060] In an embodiment, after depositing the second electrode layer 11 on the dielectric layer 10, the method further comprises: polishing the surface of the second electrode layer 11 to expose the insulating pillar 8; and forming a metal interconnection layer (not shown in the figure) on the second electrode layer 11.
[0061] It is worth mentioning that the surface of the second electrode layer 11 is subjected to chemical mechanical polishing to remove the excess second electrode material between the top of the insulating pillar 8 and the adjacent capacitor structure, thereby exposing the top surface of the insulating pillar 8 and achieving planarization of the overall structure; then, the interlayer dielectric layer 10 is formed on the planarized surface, a contact hole is defined in the interlayer dielectric layer 10 by a photolithography and etching process, and the contact hole at least partially covers the second electrode layer 11; finally, a metal material is deposited in the contact hole and on the surface of the interlayer dielectric layer 10 and is patterned to form a metal interconnection layer electrically connected to the second electrode layer 11, so as to achieve electrical integration of the DRAM storage unit and the peripheral circuit.
[0062] In an embodiment, after step S9, the method further comprises applying a crystallization voltage on the second electrode layer 11. The crystallization voltage is a direct current voltage or a pulse voltage; when the crystallization voltage is a pulse voltage, the pulse width of the pulse voltage is in the order of microseconds to milliseconds.
[0063] In some specific embodiments, since the electrocrystallization relies on the electric field driving ion migration and the local Joule heating effect, a short pulse in the order of microseconds to milliseconds can provide sufficient energy to trigger nucleation in a single action, while leaving sufficient time for heat dissipation, effectively suppressing temperature rise accumulation, thereby achieving controllable crystallization without damaging the integrity of the medium. By adjusting the pulse width, the ion migration response time of the medium layer 10 material can be matched; if the pulse width is too narrow, it is insufficient to drive nucleation, and if the pulse width is too wide, it tends to be a direct current effect; the range of microseconds to milliseconds exactly covers the typical migration relaxation time scale of Hf / Zr ions in the oxide lattice, which is conducive to efficient induction of crystal nucleus formation and guiding its ordered growth along the direction of the electric field, promoting the preferred orientation of high-k tetragonal phase or ferroelectric orthorhombic phase.
[0064] In an embodiment, before applying the crystallization voltage on the second electrode layer 11, the method further comprises: performing a pre-annealing treatment on the medium layer 10, and the temperature of the pre-annealing treatment is lower than 400°C.
[0065] It is worth mentioning that the pre-annealing treatment can promote the formation of initial crystal nuclei in the medium layer 10 or relieve deposition stress without damaging the underlying device. Although this temperature is much lower than the high temperature (>600°C) required for traditional crystallization, it is sufficient to activate partial atomic migration, allowing the amorphous HfO2 / ZrO2-based medium to produce local ordered regions or defect states, thereby significantly reducing the nucleation barrier required for subsequent electrocrystallization. This makes the crystal nucleus density higher and the crystallization more uniform when the same crystallization voltage is applied, effectively improving the dielectric performance consistency of the medium layer 10.
[0066] In another embodiment, after applying the crystallization voltage on the second electrode layer 11, the method further comprises: performing a post-annealing treatment on the medium layer 10, and the temperature of the post-annealing treatment is lower than 400°C.
[0067] It is worth mentioning that the post-annealing process is used to optimize the crystal phase structure formed by the electric field induction. The electrocrystallization can trigger the formation of functional crystal phase (such as tetragonal phase or orthorhombic phase), but the grain size is small and the interface defect is more. The low-temperature post-annealing can promote the moderate growth of the grain, repair part of the point defects, and stabilize the target crystal phase, thereby further improving the dielectric constant and reducing the leakage current, while avoiding the phase transition back (such as the transition from orthorhombic phase to monoclinic phase) caused by high temperature.
[0068] In some specific embodiments, the pre-annealing process and the post-annealing process can be in the same manufacturing process of the capacitor.
[0069] It is worth mentioning that the combination of pre-annealing and post-annealing realizes a "thermal-electric synergistic regulation" mechanism, which provides crystal nuclei for electrocrystallization through pre-annealing process, realizes directional induction of the crystallization process through electric field in the electrocrystallization process, and completes the crystal phase stabilization and improves the grain quality through post-annealing process. Through the above synergistic effect, the crystal quality can be significantly improved under the premise that the overall thermal budget is still strictly controlled below 400°C. This integrated strategy of phased and low thermal budget not only avoids the damage of high temperature to the transistor and interconnection structure, but also fully utilizes the advantages of thermal activation and electric field driving, thereby providing a high-reliability and high-yield process path for low-temperature manufacturing of high-performance DRAM capacitors.
[0070] In some possible embodiments, the microwave annealing is used first to realize the preliminary low-temperature crystallization of the dielectric layer 10 in the same manufacturing process, and then the electrocrystallization voltage is applied to optimize the crystal phase orientation, thereby forming a "microwave-electric field" synergistic crystallization mechanism. The microwave annealing can make the HZO dielectric layer 10 quickly form uniformly distributed initial crystal nuclei and enter the quasi-eutectic phase boundary region under the condition that the overall substrate 1 temperature is ≤400°C; the subsequently applied electrocrystallization voltage (such as microsecond to millisecond pulse) can further induce the preferential orientation growth of the grain along the electric field direction on the basis of the existing crystal nucleus, and strengthen the order of the ferroelectric orthorhombic phase or high-k tetragonal phase. The combination of the two crystallization strategies can avoid the randomness of the crystal phase in the single microwave annealing, and overcome the dependence of pure electrocrystallization on the insufficient nucleation density, which is conducive to improving the dielectric constant, polarization response consistency and fatigue durability of the dielectric layer 10. The whole process is always maintained in a low thermal budget window, without high-temperature process, and is fully compatible with the requirements of advanced DRAM back-end integration.
[0071] As Figure 10As shown, in one embodiment, after depositing the second electrode layer 11 on the dielectric layer 10, the method further includes: polishing the surface of the second electrode layer 11 to expose the insulating pillar 8; forming a metal interconnect layer (not shown) on the second electrode layer 11; the metal interconnect layer is used to conduct voltage to the second electrode layer 11.
[0072] In some specific embodiments, when the memory is working normally, the metal interconnect layer serves as the interconnect wire of the second electrode, realizing the electrical connection between the capacitor and the peripheral driving circuit.
[0073] In some examples, during the anisotropic etching process in S6, the top of the electrode extension layer 71 is partially etched, forming a step with the insulating pillar 8. The surface of the second electrode layer 11 is then polished, including polishing until the electrode extension layer 71 is exposed to eliminate the step.
[0074] A second embodiment of the present invention provides a method for fabricating a memory, the method comprising: providing a substrate 1; forming a transistor (not shown) and a memory node 2 on the substrate 1; and fabricating a capacitor using any of the methods described in the above embodiments to constitute a dynamic random access memory.
[0075] In some specific embodiments, forming transistors and memory nodes 2 on substrate 1 includes: forming an active region on substrate 1 and constructing transistors through gate stacking structure, sidewall and source-drain injection processes; forming memory nodes 2 electrically connected to the source or drain region of the transistor.
[0076] like Figure 10 The third embodiment of the invention provided is a dynamic random access memory (DRAM), comprising: a substrate 1, a transistor, a memory node 2, a stop layer 4, a first electrode layer 7, an electrode extension layer 71, an insulating pillar 8, a dielectric layer 10, and a second electrode layer 11; the transistor and the memory node 2 are both located between the substrate 1 and the stop layer 4; a dielectric layer 10 is formed on the stop layer 4; the number of dielectric layers 10 is M, where M is a positive integer greater than 1; the dielectric layers 10 are induced to crystallize after microwave annealing; a first electrode layer 7 is provided between adjacent dielectric layers 10; the first electrode layer 7 penetrates the stop layer 4 and connects to the memory node 2; the first electrode layer 7 is cylindrical with a first opening, the first opening facing away from the memory node 2; the insulating pillar 8 is located inside the first electrode layer 7; the longitudinal section of the dielectric layer 10 is U-shaped, the longitudinal section passing through the axis of the insulating pillar 8; the dielectric layer 10 encloses the second electrode layer 11; the first electrode layer 7, the dielectric layer 10, and the second electrode layer 11 constitute a capacitor.
[0077] It is worth mentioning that through the three-dimensional surrounding configuration of the cylindrical first electrode, the U-shaped dielectric layer 10 and the second electrode located in the dielectric layer 10, the unit area capacitance is significantly increased; at the same time, the design of the multi-layer dielectric layer 10 further improves the integrated capacitance density; more importantly, the whole structure supports the completion of functional crystallization in the low-temperature process window in the back end, avoids the damage of high temperature to the front-end transistor, and realizes the unity of high performance and high compatibility.
[0078] In some embodiments, the number of storage nodes 2 is multiple, and an isolation layer 3 is arranged between adjacent storage nodes 2, forming a structure in which the isolation layer 3 and the storage node 2 are arranged alternately on the substrate 1. The isolation layer 3 is mainly used to realize electrical isolation between adjacent storage nodes 2, effectively preventing the formation of charge crosstalk or leakage path, thereby ensuring that each storage unit works independently and the data is accurate and reliable.
[0079] In some examples, the isolation layer 3 is composed of dielectric materials (such as silicon dioxide, silicon nitride or low-k dielectric), which not only has good insulation performance, but also can provide necessary mechanical support during device manufacturing process, enhancing the stability of the overall structure. In addition, since the isolation layer 3 blocks the lateral diffusion of heat and charge carriers, it also helps to improve local thermal management and improve the reliability of the device. By reasonably designing the width and material of the isolation layer 3, the device integration density can be further optimized, more storage units can be arranged in a limited chip area, and the integration requirements of high performance and high density DRAM are considered.
[0080] In the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood or implied to indicate or imply relative importance. The term "a plurality of" means two or more, unless otherwise explicitly limited.
[0081] The above description of the embodiments is to facilitate those skilled in the art to understand and apply the present application. Those skilled in the art can easily make various modifications to these embodiments, and apply the general principles described herein to other embodiments without creative labor. Therefore, the present application is not limited to the embodiments herein, and the improvements and modifications made by those skilled in the art based on the disclosure of the present application without departing from the scope and spirit of the present application are within the scope of the present application.
Claims
1. A method for manufacturing a capacitor, wherein the capacitor is used to construct a dynamic random access memory, characterized in that, The method includes: A stop layer is formed on a substrate on which transistors and memory nodes are formed; an insulating molding layer is formed on the stop layer; The insulating molding layer and the stop layer are etched to form pillar holes; the pillar holes are used to expose the memory nodes. A first electrode layer is deposited on the insulating molding layer, the inner wall of the support hole, and the bottom. An insulating post is formed on the surface of the first electrode layer to fill the post hole; The surface of the insulating pillar is polished to expose the first electrode layer on the insulating molding layer; the first electrode layer and the insulating molding layer between adjacent insulating pillars are etched to form an etching groove to expose the first electrode layer and the stop layer located at the bottom of the insulating pillar. An electrode extension layer is formed on the sidewall of the insulating pillar, on the first electrode layer and the stop layer at the bottom of the insulating pillar; the electrode extension layer on the stop layer is etched away. A dielectric layer is formed on the electrode extension layer and the stop layer; The substrate on which the dielectric layer is formed is subjected to microwave annealing to induce the crystallization of the dielectric layer; A second electrode layer is deposited on the dielectric layer to fill the etched trench; the first electrode layer, the dielectric layer, and the second electrode layer constitute a capacitor.
2. The preparation method according to claim 1, characterized in that, The substrate on which the dielectric layer is formed is subjected to microwave annealing, which includes: performing microwave annealing on the substrate on which the dielectric layer is formed using a microwave frequency band in the range of [2.45, 5.80] GHz.
3. The preparation method according to claim 1, characterized in that, The substrate on which the dielectric layer is formed is subjected to microwave annealing, which includes: using microwave parameters of pulse or continuous wave mode, power range of [100, 3000] W, and time range of [10, 60] s to perform microwave annealing on the substrate on which the dielectric layer is formed; during the microwave annealing, the heating temperature of the substrate is less than or equal to 400°C.
4. The preparation method according to claim 1, characterized in that, Microwave annealing of the substrate on which the dielectric layer is formed includes: microwave annealing of the substrate on which the dielectric layer is formed in an inert gas atmosphere or in a vacuum.
5. The preparation method according to claim 1, characterized in that, The material of the dielectric layer includes at least one of HfO2, ZrO2 and their solid solutions.
6. The preparation method according to claim 5, characterized in that, When the material of the dielectric layer includes the solid solution and ZrO2, a dielectric layer is formed on the electrode extension layer and the stop layer, including: The deposition cycle ratio of the solid solution and ZrO2 is adjusted by atomic layer deposition process to form crystal nuclei during deposition and to make the top layer of the medium layer ZrO2; the ZrO2 on the top layer is used to stabilize the quasi-isomorphic phase boundary of the solid solution through interfacial strain during microwave annealing.
7. The preparation method according to claim 1 or 6, characterized in that, The method further includes: forming a dielectric protective layer on the top layer of the dielectric layer; the dielectric protective layer is made of alumina; the alumina is used to stabilize the quasi-isomorphic phase boundary of the solid solution through amorphous interface constraint.
8. The preparation method according to claim 1, characterized in that, The first electrode layer, the electrode extension layer, and the second electrode layer are all made of TiN.
9. The preparation method according to claim 1, characterized in that, After depositing the second electrode layer on the dielectric layer, the method further includes: polishing the surface of the second electrode layer to expose the insulating pillar; and forming a metal interconnect layer on the second electrode layer.
10. A method for fabricating a memory, characterized in that, The method includes: A substrate is provided; transistors and memory nodes are formed on the substrate; The capacitor is prepared using the method described in any one of claims 1 to 9 to form a dynamic random access memory.
11. A dynamic random access memory, characterized in that, The memory includes: a substrate, a transistor, a memory node, a stop layer, a first electrode layer, an electrode extension layer, an insulating pillar, a dielectric layer, and a second electrode layer; Both the transistor and the memory node are located between the substrate and the stop layer; A dielectric layer is formed on the stop layer; the number of dielectric layers is M, where M is a positive integer greater than 1; the dielectric layer is induced to crystallize after microwave annealing. A first electrode layer is provided between adjacent dielectric layers; the first electrode layer penetrates the stop layer and connects to the storage node; the first electrode layer is arranged in a cylindrical shape with a first opening, the first opening being oriented away from the storage node; the insulating pillar is located inside the first electrode layer; The dielectric layer has a U-shaped longitudinal section, which passes through the axis of the insulating support; the dielectric layer encloses the second electrode layer; the first electrode layer, the dielectric layer, and the second electrode layer constitute a capacitor.