Vertical led chip and method of manufacturing the same

Abstract

The application discloses a vertical LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The preparation method of the LED chip comprises the following steps: providing an epitaxial wafer; sequentially forming a first dielectric layer, a first reflective layer and a bonding layer; bonding with a second substrate and removing the first substrate to expose an N-type contact layer; etching the N-type contact layer to form a boss with a preset shape and expose the N-type roughening layer outside the boss; forming a first photoresist layer; exposing and developing to form a plurality of first photoresist patterns; heat reflowing the first photoresist patterns to form a plurality of second photoresist patterns; etching the exposed N-type roughening layer to form a plurality of protrusions in a first preset area on the N-type roughening layer; forming a second dielectric layer and a second reflective layer on the protrusions; forming an N electrode and a P electrode; and the N electrode is at least partially located on the first preset area. By implementing the application, the light extraction efficiency and reliability of the vertical LED chip can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic devices, and more particularly to a vertical LED chip and its fabrication method. Background Technology

[0002] Currently, improving the light extraction efficiency of LED chips is one of the key research directions in the industry. In traditional vertical LED chips, the light extraction efficiency is low due to electrode obstruction, making it difficult to meet the needs of high-performance lighting. A common approach is to use reflective electrodes, which involves introducing highly reflective metals such as Al into the electrode structure to increase light reflectivity and reduce light loss due to electrode absorption. However, while this metal reflective layer can improve reflectivity, it has high absorption loss and poor adhesion to semiconductor materials, which can easily lead to a decrease in device reliability. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a vertical LED chip and its preparation method, which has high light extraction efficiency and high reliability.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a vertical LED chip, comprising the following steps:

[0005] S1. Provide an epitaxial wafer, the epitaxial wafer comprising a first substrate and an N-type contact layer, an N-type roughening layer, an N-type semiconductor layer, an MQW layer and a P-type semiconductor layer sequentially disposed on the first substrate;

[0006] S2. A first dielectric layer, a first reflective layer, and a bonding layer are sequentially formed on the P-type semiconductor layer;

[0007] S3. Bond the epitaxial wafer obtained in step S2 to the second substrate, and remove the first substrate to expose the N-type contact layer;

[0008] S4. Etch the N-type contact layer to form a boss of a preset shape and expose the N-type roughening layer outside the boss;

[0009] S5. A first photoresist layer is formed on the exposed N-type roughened layer and the protrusion;

[0010] S6. Expose and develop the first photoresist layer to form a plurality of first photoresist patterns; wherein, the first photoresist pattern is a columnar body or a mesa-shaped body;

[0011] S7. The first photoresist pattern is thermally reflowed to make the top of the first photoresist pattern become an arc surface, forming multiple second photoresist patterns;

[0012] S8. Etch the exposed N-type roughened layer to form multiple protrusions in a first predetermined region on the N-type roughened layer;

[0013] S9. A second dielectric layer and a second reflective layer are formed on the protrusion; wherein the refractive index of the second dielectric layer is less than the refractive index of the N-type roughening layer;

[0014] S10, forming an N electrode and a P electrode; the N electrode is at least partially located on the first preset region.

[0015] As an improvement to the above technical solution, in step S7, the temperature of the thermal reflow is higher than the T value of the photoresist used in the first photoresist layer. g Temperature range: 20℃~100℃, reflux time: 5min~30min.

[0016] As an improvement to the above technical solution, the second dielectric layer is a stacked structure formed by one or more of the following: SiO2 layer, MgF2 layer, TiO2 layer, and Ti2O5 layer; the thickness of the second dielectric layer is 0.3 μm to 3 μm; and / or

[0017] The second reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the second reflective layer is 100 nm to 3000 nm; and / or

[0018] The protrusion is hemispherical or ellipsoidal, with a height of 0.5μm to 2μm and a distance of 0.1μm to 1μm between adjacent protrusions.

[0019] As an improvement to the above technical solution, in step S8, multiple protrusions are formed in the first and second preset regions of the N-type roughening layer;

[0020] The second preset area is the area between the first preset area and the cutting channel, and the second preset area is not covered by the N electrode.

[0021] As an improvement to the above technical solution, the N electrode includes an ohmic contact portion and a bonding wire portion, wherein the bonding wire portion is disposed on the first preset area;

[0022] The boss is circular in shape.

[0023] The ohmic contact portion is located above the boss, below the bonding wire portion, and is covered by the bonding wire portion.

[0024] As an improvement to the above technical solution, the N electrode includes an ohmic contact portion and a bonding wire portion, wherein the bonding wire portion is disposed on the first preset area;

[0025] The protrusion extends from the N electrode toward the edge of the vertical LED chip, and the protrusion is offset from the protrusion located in the second preset region;

[0026] The ohmic contact portion is located above the boss and surrounds the outside of the solder wire portion.

[0027] As an improvement to the above technical solution, an N-type electrode bonding layer is further provided between the N-type contact layer and the N-type roughening layer;

[0028] Step S4 includes:

[0029] S41. A second photoresist layer is formed on the N-type contact layer and exposed and developed to expose the N-type contact layer in a predetermined area.

[0030] S42. The N-type contact layer is etched using a wet etching process to form the first protrusion and expose the N-type electrode bonding layer.

[0031] S43. The exposed N-type electrode bonding layer is etched using a dry etching process to form a second protrusion below the first protrusion; wherein the width of the second protrusion is greater than the width of the first protrusion.

[0032] S44. Remove the remaining second photoresist layer.

[0033] As an improvement to the above technical solution, the first dielectric layer is provided with a plurality of conductive parts, and the conductive parts are made of a transparent conductive layer;

[0034] The first reflective layer includes a DBR reflective layer, a transparent conductive adhesive layer, and a metal reflective layer stacked sequentially on the first dielectric layer; the DBR reflective layer has a plurality of pits exposing the conductive parts, and the conductive adhesive layer contacts the conductive parts through the pits;

[0035] The first dielectric layer is one or more of SiO2, MgF2, TiO2, and Ti2O5; the thickness of the first dielectric layer is 0.3 μm to 3 μm.

[0036] The transparent conductive layer is one or more of ITO, IZO, IGZO, and IGO layers; the thickness of the transparent conductive layer is 1 nm to 200 nm.

[0037] The DBR reflective layer comprises alternating layers of TiO2 and SiO2, or the DBR reflective layer comprises alternating layers of TiO2 and MgF2.

[0038] The transparent conductive adhesive layer is one or more of ITO, IZO, IGZO, and IGO layers; the thickness of the transparent conductive adhesive layer is 2nm to 20nm.

[0039] The metal reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the metal reflective layer is 100nm~3000nm.

[0040] As an improvement to the above technical solution, the first substrate is a GaAs substrate;

[0041] The N-type contact layer is an N-type GaAs ohmic contact layer, the N-type roughening layer is an N-type AlGaInP roughening layer, and the N-type semiconductor layer is an N-type AlGaInP confinement layer;

[0042] The second substrate is a P-type silicon wafer or an N-type silicon wafer.

[0043] Accordingly, the present invention also discloses a vertical LED chip, which is prepared by the above-described preparation method.

[0044] Implementing this invention has the following beneficial effects:

[0045] In one embodiment of the present invention, the method for fabricating a vertical LED chip includes forming a first photoresist layer on an N-type roughened layer; exposure and development to form multiple first photoresist patterns; thermal reflow to form multiple second photoresist patterns; etching the N-type roughened layer to form multiple protrusions; and then forming a second dielectric layer and a second reflective layer. Based on the above technical solution, firstly, the hemispherical or ellipsoidal protrusions are formed, which, combined with the subsequently formed second dielectric layer and second reflective layer, increase the reflective area, reflecting light incident on the N electrode and thus improving light extraction efficiency. Secondly, the protrusions can enhance the bonding force between the N electrode and the N-type roughened layer, effectively solving the problem of the N electrode easily detaching under stress during subsequent wire bonding and packaging processes, thus improving the reliability of the vertical LED chip. Thirdly, the second dielectric layer can block current, guiding current injection from the periphery of the electrode, significantly optimizing the uniformity of current distribution and improving the uniformity of light emission. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of an epitaxial wafer in one embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the structure of a vertical LED chip in one embodiment of the present invention;

[0048] Figure 3 yes Figure 2 A magnified view of a section at point A in the middle;

[0049] Figure 4 This is a schematic diagram of the structure of the first boss after step S42 in one embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of the first boss and the second boss after step S43 in one embodiment of the present invention;

[0051] Figure 6This is a schematic diagram of the structure of the first photoresist pattern after step S6 in one embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure of the second photoresist pattern after step S7 in one embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the structure in which the protrusion is formed after step S8 in one embodiment of the present invention;

[0054] Figure 9 This is a schematic diagram of the distribution structure of the N electrode and the protrusion in one embodiment of the present invention;

[0055] Figure 10 This is a schematic diagram of the distribution structure of the N electrode and the protrusion in another embodiment of the present invention.

[0056] In the figure, 110 is the first substrate, 121 is an N-type GaAs buffer layer, 122 is an N-type GaInP etching stop layer, 123 is an N-type contact layer, 124 is an N-type electrode bonding layer, 125 is an N-type roughening layer, 126 is an N-type semiconductor layer, 130 is an MQW layer, 140 is a P-type semiconductor layer, 141 is a P-type AlGaInP confinement layer, 142 is a P-type GaP window layer, 210 is a conductive part, 220 is the first dielectric layer, 231 is a DBR reflective layer, 232 is a transparent conductive adhesion layer, and 233 is... The structure includes a metal reflective layer, a bonding layer (240), a boss (300), a first boss (310), a second boss (320), a dicing channel (330), a second photoresist layer (340), a first photoresist pattern (410), a second photoresist pattern (420), a protrusion (500), a first preset area (510), a second preset area (520), a second dielectric layer (610), a second reflective layer (620), an N-electrode (710), an ohmic contact (711), a bonding wire (712), a P-electrode (720), a second substrate (800), and a passivation layer (900). Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0058] This invention provides a method for fabricating a vertical LED chip, which includes the following steps:

[0059] S1. Provide epitaxial wafers;

[0060] Please see Figure 1The epitaxial wafer includes a first substrate 110, and an N-type contact layer 123, an N-type roughening layer 125, an N-type semiconductor layer 126, an MQW layer 130, and a P-type semiconductor layer 140 sequentially disposed on the first substrate 110. Specifically, the LED chip of the present invention can be a blue, red, green, yellow, or purple LED chip, and different types of semiconductor layers can be selected based on the control of the emission wavelength. Exemplarily, in one embodiment, when the LED chip is a blue LED chip, the N-type contact layer 123 is a Si-doped GaN layer, the N-type roughening layer 125 is a Si-doped GaN layer, the N-type semiconductor layer 126 is an N-type GaN layer, the MQW layer 130 is an InGaN-GaN type multiple quantum well layer, and the P-type semiconductor layer 140 can be a P-type GaN layer, but is not limited thereto.

[0061] Preferably, in one embodiment, the vertical LED chip is a red LED chip, and the epitaxial wafer includes, sequentially disposed on a first substrate 110, an N-type GaAs buffer layer 121, an N-type GaInP etching stop layer 122, an N-type contact layer 123 (N-type GaAs material), an N-type electrode bonding layer 124 (N-type GaInP material), an N-type roughening layer 125 (N-type AlGaInP material), an N-type semiconductor layer 126 (N-type AlGaInP material), an MQW layer 130, a P-type AlGaInP confinement layer 141, and a P-type GaP window layer 142. The following steps are described using a red LED chip, but the technical solution of the present invention is not limited to the red LED chip described herein.

[0062] S2. A first dielectric layer 220, a first reflective layer and a bonding layer 240 are sequentially formed on the P-type semiconductor layer 140.

[0063] Specifically, the refractive index of the first dielectric layer 220 is less than that of the P-type semiconductor layer 140. The first dielectric layer 220 and the first reflective layer together form an ODR reflector structure to reflect the light emitted by the MQW layer 130, thereby improving the light extraction efficiency.

[0064] Specifically, in some embodiments, the first dielectric layer 220 is one or more of SiO2, MgF2, TiO2, and Ti2O5; the thickness of the first dielectric layer is 0.3 μm to 3 μm. The first reflective layer is one or more of Au, Ag, and Al, and its thickness is 100 nm to 3000 nm.

[0065] Specifically, depending on the subsequent bonding process, bonding layers 240 of different materials can be formed. For example, when using a eutectic bonding process, Au, Cu, In, Pb, or Sn layers can be used, but not limited to these. As another example, when using a hot-press bonding process, Au, Cu, Ag, or Al layers can be used as bonding layers 240, but not limited to these.

[0066] Preferably, in some embodiments, please refer to Figure 2 and Figure 3 The first reflective layer includes a DBR reflective layer 231, a transparent conductive adhesive layer 232, and a metal reflective layer 233, which are sequentially stacked on a first dielectric layer 220. Further, a plurality of conductive portions 210 are provided in the first dielectric layer 220. One side of each conductive portion 210 is connected to the P-type semiconductor layer 140, and the other side is connected to the transparent conductive adhesive layer 232. A plurality of recesses corresponding to the conductive portions 210 and penetrating the DBR reflective layer 231 are provided on the DBR reflective layer 231. The transparent conductive adhesive layer 232 is connected to the conductive portions 210 through these recesses. Based on this structure, firstly, the introduction of the DBR reflective layer 231 and the metal reflective layer 233 further improves the light extraction efficiency. Secondly, the introduction of the conductive portions 210 (transparent conductive layer) effectively improves the ohmic contact between the metal reflective layer 233 and the P-type semiconductor layer 140, thereby improving the luminous efficiency. Thirdly, the introduction of the recesses effectively increases the reflective area of ​​the micromirror, further improving the light extraction efficiency. Fourthly, the introduction of the transparent conductive adhesive layer 232 enhances the adhesion between the DBR reflective layer 231 and the metal reflective layer 233, effectively preventing the metal reflective layer 233 from falling off and improving the reliability of the vertical LED chip.

[0067] Specifically, in the above embodiments, the first dielectric layer 220 is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer, but is not limited thereto. Preferably, the first dielectric layer 220 is a MgF2 layer or a SiO2 layer. The thickness of the first dielectric layer 220 is 0.3 μm to 3 μm, exemplarily 0.3 μm, 0.5 μm, 1.4 μm, 1.8 μm, 2.2 μm, 2.6 μm, and 3.0 μm, but is not limited thereto.

[0068] Specifically, in the above embodiments, the transparent conductive layer is one or more of ITO, IZO, IGZO, and IGO layers, but is not limited thereto. Preferably, the transparent conductive layer is an ITO layer. The thickness of the transparent conductive layer is 1 nm to 200 nm, exemplarily 5 nm, 25 nm, 45 nm, 65 nm, 85 nm, 105 nm, 125 nm, 145 nm, 165 nm, or 185 nm, but is not limited thereto. Preferably, it is 50 nm to 120 nm.

[0069] Specifically, in the above embodiments, the DBR reflective layer 231 is a TiO2 / SiO2 type DBR layer, a Ti2O5 / SiO2 type DBR layer, or a MgF2 / TiO2 type DBR layer, but is not limited to these. Preferably, the DBR reflective layer 231 includes alternating layers of TiO2 and SiO2.

[0070] Specifically, in the above embodiments, the transparent conductive adhesive layer 232 is one or more of ITO, IZO, IGZO, and IGO layers, but is not limited thereto. Preferably, the transparent conductive adhesive layer is an IZO layer. The thickness of the transparent conductive adhesive layer is 2nm to 20nm, exemplarily 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, or 18nm, but is not limited thereto.

[0071] Specifically, in the above embodiments, the metal reflective layer 233 is one or more of Au, Ag, and Al layers, but is not limited thereto. Preferably, the metal reflective layer 233 is an Ag layer. More preferably, the metal reflective layer 233 includes an Ag layer and a TiW barrier layer. The thickness of the metal reflective layer 233 is 100nm to 3000nm, exemplarily 150nm, 300nm, 500nm, 1000nm, 1500nm, 2000nm, or 2500nm, but is not limited thereto.

[0072] Specifically, based on this structure, step S2 includes:

[0073] S21: A transparent conductive layer is formed on the P-type semiconductor layer;

[0074] S22: Etch the transparent conductive layer to expose the P-type semiconductor layer in a preset area to form a conductive part;

[0075] S23: Form a first dielectric layer and remove the first dielectric layer above the conductive portion;

[0076] S24: Forms a DBR reflective layer;

[0077] S25: Etch the DBR reflective layer to form pits that expose the conductive parts;

[0078] S26: A transparent conductive adhesion layer, a metal reflective layer, and a bonding layer are formed sequentially.

[0079] S3: Bond the epitaxial wafer obtained in step S2 to the second substrate, and remove the first substrate to expose the N-type contact layer;

[0080] Specifically, the epitaxial wafer obtained in step S2 can be bonded to the second substrate 800 using bonding methods such as eutectic bonding and thermo-press bonding, but is not limited to these methods. Preferably, thermo-press bonding is used. During thermo-press bonding, the bonding layer 240 and the metal reflective layer 233 are heated and stretched, which can fill the gaps on the surface of the epitaxial wafer, making the interior of the vertical LED chip seamless and preventing cracking during subsequent die bonding and wire bonding processes, thus improving reliability.

[0081] Specifically, the second substrate 800 is a conductive substrate, which may be a P-type silicon wafer or an N-type silicon wafer, but is not limited to this.

[0082] Specifically, the first substrate 110 can be removed by alkaline polishing or laser lift-off, but is not limited thereto. Preferably, the first substrate 110 is removed by laser lift-off. Furthermore, during the removal of the first substrate 110, the buffer layer and the like on its surface are also removed. In one embodiment of the present invention, when the vertical LED chip is a red LED chip, the first substrate 110, the N-type GaAs buffer layer 121, and the N-type GaInP etching stop layer 122 are removed.

[0083] S4: Etch the N-type contact layer to form a boss of a preset shape and expose the N-type roughening layer outside the boss;

[0084] Specifically, a mask layer can be formed on the N-type contact layer 123 first, then the mask layer of the preset area can be removed, and then the boss 300 of the preset shape can be etched, but it is not limited to this.

[0085] Specifically, please refer to Figure 4 , Figure 5 , Figure 9 and Figure 10 The protrusion 300 can be strip-shaped or annular, but is not limited to these forms. Preferably, in some embodiments, the protrusion 300 is annular, and the N-electrode 710 is disposed above the protrusion 300. The protrusion 300 can effectively improve the ohmic contact between the N-electrode 710 and the N-type roughening layer 125, thereby improving luminous efficiency. In other embodiments, the protrusion 300 is strip-shaped and extends between the N-electrode 710 and the edge of the vertical LED chip, that is, the protrusion 300 is not covered by the N-electrode 710. Based on this structure, the current distribution can be optimized, and the luminous uniformity can be improved.

[0086] Preferably, in some embodiments, in this step, a dicing channel 330 is also etched to form a dicing channel 330, which is used to cut the epitaxial wafer into dicings later to form grains.

[0087] Preferably, in some embodiments, an N-type electrode bonding layer 124 is further provided between the N-type contact layer 123 and the N-type roughening layer 125. The N-type electrode bonding layer 124 can improve the bonding force between the N-electrode 710 and the N-type roughening layer 125, thereby improving the reliability of the vertical LED chip.

[0088] Specifically, based on this implementation method, step S4 includes:

[0089] S41: Form a second photoresist layer on the N-type contact layer and expose and develop it to expose the N-type contact layer in a predetermined area;

[0090] S42: The N-type contact layer is etched using a wet etching process to form the first protrusion and expose the N-type electrode bonding layer;

[0091] S43: The exposed N-type electrode bonding layer is etched using a dry etching process to form a second boss below the first boss;

[0092] S44: Remove the remaining second photoresist layer.

[0093] More preferably, please refer to Figure 5 In some implementations, the width of the second protrusion 320 is greater than the width of the first protrusion 310. Based on this structure, the reliability of the vertical LED chip can be further improved. It should be noted that wet etching will cause a side etching effect, and the photoresist will collapse and expand outward during dry etching. Therefore, based on the process of wet etching followed by dry etching, a second protrusion 320 with a width greater than that of the first protrusion 310 will be formed.

[0094] S5: A first photoresist layer is formed on the exposed N-type roughening layer 125 and the boss 300;

[0095] Specifically, the first photoresist layer can be formed using either a positive or negative photoresist, but is not limited to this. Preferably, the photoresist used in the first photoresist layer has a Tg... g The temperature should be ≤150℃ to facilitate the formation of specific morphologies through subsequent thermal reflow processes. More preferably, the first photoresist layer uses a photoresist with a T0... g The temperature range is 120℃ to 140℃.

[0096] S6: Expose and develop the first photoresist layer to form multiple first photoresist patterns;

[0097] Please refer to Figure 6 The first photoresist pattern 410 is a columnar or mesa-shaped body. Through the exposure and development process, the morphology of the first photoresist pattern 410 can be well controlled, thus laying a good foundation for the subsequent formation of a second photoresist pattern 420 with a specific shape.

[0098] S7: The first photoresist pattern is thermally reflowed to form multiple second photoresist patterns;

[0099] Specifically, please refer to Figure 7 Through a thermal reflow process, the first photoresist pattern 410 is softened, and under the action of surface tension and internal pressure, the sharp edges collapse and round the corners, that is, the top of the first photoresist pattern 410 becomes an arc surface, thus forming the second photoresist pattern 420. More specifically, the second photoresist pattern 420 is hemispherical or ellipsoidal.

[0100] Specifically, the reflow temperature should be lower than the melting temperature of the first photoresist layer, but higher than its glass transition temperature (T0). g This allows the first photoresist layer to soften and flow.

[0101] Specifically, in some implementations, the reflow temperature is higher than the T0 temperature of the photoresist used in the first photoresist layer. g The temperature is 20℃~100℃, and the reflux time is 5min~30min.

[0102] S8: Etch the exposed N-type roughened layer to form multiple protrusions in a first predetermined region on the N-type roughened layer;

[0103] Specifically, through an etching process, the morphology of the second photoresist can be transferred to the surface of the N-type roughening layer 125, thereby forming multiple protrusions 500. Correspondingly, each protrusion 500 is hemispherical or ellipsoidal. Specifically, the protrusion 500 can be disposed only in the first preset region 510, which is used to form the N-electrode 710; that is, the protrusion 500 is disposed only below the N-electrode 710. Based on this structure, firstly, it can improve the bonding force between the N-electrode 710 and the N-type roughening layer 125, effectively solving the problem of the N-electrode 710 easily detaching under stress during subsequent wire bonding and packaging processes, thus improving the reliability of the vertical LED chip. Secondly, after the second dielectric layer 610 and the second reflective layer 620 are formed on the protrusion, the protrusion can increase the reflective area, reflecting the light incident on the N-electrode 710, thereby improving the light extraction efficiency. Thirdly, the second dielectric layer 610 can block current and guide current injection from the periphery of the electrode, which greatly optimizes the uniformity of current distribution and improves the uniformity of light emission.

[0104] Preferably, in some embodiments, a plurality of protrusions 500 are also provided in the second preset region 520 of the N-type roughened layer 125, which is the region between the first preset region 510 and the cutting channel 330. That is, the protrusions 500 located in the second preset region 520 are not covered by the N electrode 710. By providing such protrusions 500, the probability of light emanating from the surface of the N-type roughened layer 125 can be increased, further improving the light extraction efficiency.

[0105] Specifically, the height of the protrusion 500 is 0.5μm to 2μm, exemplarily 0.7μm, 0.9μm, 1.1μm, 1.3μm, 1.5μm, 1.7μm or 1.9μm, but not limited thereto.

[0106] Specifically, the distance between adjacent protrusions 500 is 0.1μm to 1μm, exemplarily 0.2μm, 0.4μm, 0.6μm, and 0.8μm, but not limited thereto. Preferably, it is 0.1μm to 0.8μm.

[0107] S9. A second dielectric layer and a second reflective layer are formed on the protrusion;

[0108] The second dielectric layer 610 is one or more of SiO2, MgF2, TiO2, and Ti2O5, but is not limited thereto. Preferably, the second dielectric layer 610 is a SiO2 or MgF2 layer. The refractive index of the second dielectric layer 610 is lower than that of the N-type roughening layer 125 to further improve the light extraction efficiency.

[0109] Specifically, the thickness of the second dielectric layer 610 is 0.3μm to 3μm, and exemplary thicknesses are 0.3μm, 0.5μm, 1.4μm, 1.8μm, 2.2μm, 2.6μm, and 3.0μm, but it is not limited thereto.

[0110] Specifically, the second reflective layer 620 is one or more of Au, Ag, and Al layers, but is not limited thereto. Preferably, the second reflective layer 620 is an Ag layer. The thickness of the second reflective layer 620 is 100nm to 3000nm, exemplarily 150nm, 300nm, 500nm, 1000nm, 1500nm, 2000nm, or 2500nm, but is not limited thereto.

[0111] By setting the second dielectric layer 610 and the second reflective layer 620, the light rays incident on the N electrode 710 can be effectively reflected, thereby improving the light extraction efficiency.

[0112] S10, forming N-electrode and P-electrode;

[0113] The N electrode 710 and P electrode 720 can be formed by processes such as vapor deposition and sputtering. The N electrode 710 and P electrode 720 can be formed by one or more of the Cr layer, Al layer, Pt layer, Au layer, etc. commonly used in the art, but are not limited to these.

[0114] Preferably, in some embodiments, step S10 includes:

[0115] S101: An N-electrode 710 is formed on the epitaxial wafer obtained in step S9;

[0116] Specifically, please refer to Figure 9 In some embodiments, the N-electrode 710 includes an ohmic contact portion 711 and a bonding portion 712, with the bonding portion 712 disposed on the first preset region 510; the boss 300 is annular, with the ohmic contact portion 711 disposed above the boss 300, below the bonding portion 712, and covered by the bonding portion 712. Based on the above embodiments, the current distribution can be optimized and the N-electrode 710 formation process can be simplified.

[0117] Specifically, please refer to Figure 10In other embodiments, the N-electrode 710 includes an ohmic contact portion 711 and a bonding portion 712; the bonding portion 712 is disposed on the first preset region 510; a boss 300 extends from the N-electrode 710 toward the edge perpendicular to the LED chip, and the boss 300 is offset from the protrusion 500 located in the second preset region 520; an ohmic contact layer is disposed above the boss 300; and the ohmic contact surrounds the outside of the bonding portion 712. Based on the above embodiments, the current distribution can be further optimized and the light emission uniformity can be improved.

[0118] S102: Etch along the cleavage path to the P-type semiconductor layer and form a passivation layer;

[0119] The passivation layer is a silicon nitride layer, a silicon oxide layer, or an aluminum oxide layer, but is not limited to these.

[0120] S103: Form a P electrode on the second substrate to obtain an LED wafer;

[0121] Preferably, in some embodiments, the second substrate 800 is first thinned by grinding before the P electrode 720 is formed.

[0122] S104: Cut the LED wafer to obtain vertical LED chips.

[0123] Specifically, through tangenting, back-cutting, and dicing processes, the LED wafer is cut into separate vertical LED chips, the structure of which is as follows: Figure 2 , Figure 3 As shown.

[0124] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for fabricating a vertical LED chip, characterized in that, Includes the following steps: S1. Provide an epitaxial wafer, the epitaxial wafer comprising a first substrate and an N-type contact layer, an N-type roughening layer, an N-type semiconductor layer, an MQW layer and a P-type semiconductor layer sequentially disposed on the first substrate; S2. A first dielectric layer, a first reflective layer, and a bonding layer are sequentially formed on the P-type semiconductor layer; S3. Bond the epitaxial wafer obtained in step S2 to the second substrate, and remove the first substrate to expose the N-type contact layer; S4. Etch the N-type contact layer to form a boss of a preset shape and expose the N-type roughening layer outside the boss; S5. A first photoresist layer is formed on the exposed N-type roughened layer and the protrusion; S6. Expose and develop the first photoresist layer to form a plurality of first photoresist patterns; wherein, the first photoresist pattern is a columnar body or a mesa-shaped body; S7. The first photoresist pattern is thermally reflowed to make the top of the first photoresist pattern become an arc surface, forming multiple second photoresist patterns; S8. Etch the exposed N-type roughened layer to form multiple protrusions in a first predetermined region on the N-type roughened layer; S9. A second dielectric layer and a second reflective layer are formed on the protrusion; wherein the refractive index of the second dielectric layer is less than the refractive index of the N-type roughening layer; S10, forming an N electrode and a P electrode; the N electrode is at least partially located on the first preset region.

2. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, In step S7, the reflow temperature is higher than the T value of the photoresist used in the first photoresist layer. g Temperature range: 20℃~100℃, reflux time: 5min~30min.

3. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The second dielectric layer is a stacked structure formed by one or more of the following: SiO2 layer, MgF2 layer, TiO2 layer, and Ti2O5 layer; the thickness of the second dielectric layer is 0.3 μm to 3 μm; and / or The second reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the second reflective layer is 100 nm to 3000 nm; and / or The protrusion is hemispherical or ellipsoidal, with a height of 0.5μm to 2μm and a distance of 0.1μm to 1μm between adjacent protrusions.

4. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, In step S8, multiple protrusions are formed in the first and second preset regions of the N-type roughening layer; The second preset area is the area between the first preset area and the cutting channel, and the second preset area is not covered by the N electrode.

5. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The N electrode includes an ohmic contact portion and a bonding wire portion, wherein the bonding wire portion is disposed on the first preset area; The boss is circular in shape. The ohmic contact portion is located above the boss, below the bonding wire portion, and is covered by the bonding wire portion.

6. The method for fabricating a vertical LED chip as described in claim 4, characterized in that, The N electrode includes an ohmic contact portion and a bonding wire portion, wherein the bonding wire portion is disposed on the first preset area; The protrusion extends from the N electrode toward the edge of the vertical LED chip, and the protrusion is offset from the protrusion located in the second preset region; The ohmic contact portion is located above the boss and surrounds the outside of the solder wire portion.

7. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, An N-type electrode bonding layer is further provided between the N-type contact layer and the N-type roughening layer; Step S4 includes: S41. A second photoresist layer is formed on the N-type contact layer and exposed and developed to expose the N-type contact layer in a predetermined area. S42. The N-type contact layer is etched using a wet etching process to form the first protrusion and expose the N-type electrode bonding layer. S43. The exposed N-type electrode bonding layer is etched using a dry etching process to form a second protrusion below the first protrusion; wherein the width of the second protrusion is greater than the width of the first protrusion. S44. Remove the remaining second photoresist layer.

8. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The first dielectric layer has a plurality of conductive parts, and the conductive parts are made of a transparent conductive layer; The first reflective layer includes a DBR reflective layer, a transparent conductive adhesive layer, and a metal reflective layer stacked sequentially on the first dielectric layer; the DBR reflective layer has a plurality of pits exposing the conductive parts, and the conductive adhesive layer contacts the conductive parts through the pits; The first dielectric layer is one or more of SiO2, MgF2, TiO2, and Ti2O5; the thickness of the first dielectric layer is 0.3 μm to 3 μm. The transparent conductive layer is one or more of ITO, IZO, IGZO, and IGO layers; the thickness of the transparent conductive layer is 1 nm to 200 nm. The DBR reflective layer comprises alternating layers of TiO2 and SiO2, or the DBR reflective layer comprises alternating layers of TiO2 and MgF2. The transparent conductive adhesive layer is one or more of ITO, IZO, IGZO, and IGO layers; the thickness of the transparent conductive adhesive layer is 2nm to 20nm. The metal reflective layer is one or more of Au, Ag, and Al layers, and the thickness of the metal reflective layer is 100nm~3000nm.

9. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The first substrate is a GaAs substrate; The N-type contact layer is an N-type GaAs ohmic contact layer, the N-type roughening layer is an N-type AlGaInP roughening layer, and the N-type semiconductor layer is an N-type AlGaInP confinement layer; The second substrate is a P-type silicon wafer or an N-type silicon wafer.

10. A vertical LED chip, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 9.

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