Cover plate for wafer level packaging, manufacturing method and MEMS wafer level packaging method

Abstract

The invention relates to the technical field of wafer packaging, in particular to a universal cover plate for wafer-level packaging, a manufacturing method and an MEMS wafer-level packaging method.The universal cover plate for wafer-level packaging comprises an electrode layer, the electrode layer comprises a plurality of electrodes, the electrodes are distributed in an array mode, and the electrodes are arranged on the electrode layer; the two end faces, in the axial direction, of the electrode are a first surface and a second surface respectively. And the contact layer is connected to the first surface of at least one electrode. The universal cover plate can be produced and processed in batches in advance, and when MEMS devices of different structures are researched and developed, the contact layer can be subjected to graphical processing according to the condition of electrodes needing to be led out. Compared with a conventional customized universal cover plate, the method can effectively shorten the research and development period of the device, reduces the research and development cost, and is of great significance to research and development work of MEMS devices of new structures.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer packaging, in particular to a general cover plate for wafer-level packaging, a manufacturing method and a MEMS wafer-level packaging method. BACKGROUND

[0002] The MEMS (Micro-Electro-Mechanical System) wafer-level packaging technology is a technology of directly packaging the whole wafer after the wafer manufacturing is completed, and then cutting into a single chip. It can significantly improve the performance and reliability of the MEMS device, realize the miniaturization and low cost of the device, and is one of the key technologies for manufacturing the MEMS device and the basis for ensuring the practicality of the MEMS device.

[0003] The cover plate of the MEMS wafer-level packaging is mainly used for providing mechanical protection for sensitive MEMS devices, realizing airtight sealing and forming electrical interconnection. Modern MEMS packaging tends to be system integration, and adopts a vertical interconnection scheme, which can significantly reduce the packaging area. Therefore, vertical interconnection and three-dimensional stacking have always been the focus of research in the field of MEMS. As a key structural layer in three-dimensional integration, the cover plate is responsible for signal lead-out, and the common implementation method is to complete it based on the through-silicon via (TSV), glass through-hole (GSV) and GIS (glass-silicon composite structure) scheme.

[0004] Different MEMS devices need different electrode structures, numbers and distribution positions in the wafer, so different through-hole electrode designs are also needed in the corresponding cover plate structure design to form effective contact with the electrodes on the wafer. The conventional method is to customize the cover plate for each structure of the device, and the design and processing of the cover plate need time, which usually accounts for about 1 / 3 of the device development cycle. SUMMARY

[0005] The present application provides a cover plate for wafer-level packaging, a manufacturing method and a MEMS wafer-level packaging method to solve one of the defects in the prior art. The general cover plate of the present application can be mass-produced in advance, and when developing different structure MEMS devices, the contact layer can be patterned according to the electrode to be drawn. Compared with the conventional customized general cover plate direction, the present application can effectively shorten the development cycle of the device and reduce the development cost, which has important significance for the research and development of new structure MEMS devices.

[0006] The present application provides a general cover plate for wafer-level packaging, comprising: an electrode layer, comprising: a plurality of electrodes, the plurality of electrodes are distributed in an array, and the electrodes have first surfaces and second surfaces at two ends along the axial direction thereof; a contact layer connected to the first surface of at least one of the electrodes.

[0007] The universal cover plate for wafer level packaging provided by the present application is characterized in that the contact layer and the electrodes connected thereto are integrated.

[0008] The universal cover plate for wafer level packaging provided by the present application is further characterized in that: The base is connected to the side surface of each electrode.

[0009] The universal cover plate for wafer level packaging provided by the present application is further characterized in that the base is also connected to the second surface of each electrode.

[0010] The universal cover plate for wafer level packaging provided by the present application is further characterized in that the two side surfaces of the base are flush with the first surface and the second surface of the electrodes respectively.

[0011] The universal cover plate for wafer level packaging provided by the present application is further characterized in that the base is a conductor, and an insulating layer is arranged between the side surface of each electrode and the base and between the base and the contact layer.

[0012] The present application also provides a MEMS wafer level packaging method, comprising: The universal cover plate for wafer level packaging is used to form a pattern structure on the contact layer of the universal cover plate, which matches the contact electrodes of the wafer to be packaged, and the contact electrodes of the wafer to be packaged are bonded.

[0013] The present application also provides a manufacturing method of a universal cover plate for wafer level packaging, which is applied to the universal cover plate for wafer level packaging as described above, and comprises: The base plate is etched to form electrodes arranged in an array and a contact layer connected to the first surface of all the electrodes; The electrodes are anodically bonded to the base; The base is annealed at a set temperature, and after the base is melted at the set temperature, the side surface and the second surface of the electrodes are coated; The base and the contact layer are respectively polished until the thickness of the cover plate reaches a set thickness.

[0014] The manufacturing method of a universal cover plate for wafer level packaging provided by the present application further comprises: The contact layer is etched to form a pattern structure required for bonding the contact electrodes of the wafer level to be packaged.

[0015] The manufacturing method of a universal cover plate for wafer level packaging provided by the present application further comprises: forming a substrate with through holes arranged in an array by etching; attaching an insulating layer to the inner wall of the through hole and the surface of the substrate; filling the electrode into the through hole; polishing the two surfaces of the substrate respectively until the thickness of the universal cover plate reaches the set thickness; forming a contact layer on the first surface of the electrode.

[0016] The universal cover plate for wafer-level packaging of the application mainly comprises an electrode layer, which mainly comprises a plurality of electrodes and a contact layer. The plurality of electrodes are arranged in an array in the same plane, and the two end surfaces of the electrode in the axial direction are a first surface and a second surface, respectively. The contact layer is stacked on the first surface of the electrode, so that the second surface of the electrode and the surface of the contact layer not connected with the electrode form two surfaces arranged on the two sides of the electrode layer, and the contact layer is connected with at least one electrode, thereby ensuring the conductive performance of the universal cover plate.

[0017] The surface of the contact layer not connected with the electrode serves as the back surface of the universal cover plate, and the electrode is a structure arranged in an array within the range of the contact layer. By removing part of the contact layer and retaining a pattern structure suitable for connecting the contact electrode of the wafer, some electrodes arranged in an array can be selected flexibly, thereby adapting to the bonding requirements of the MEMS structure. After the patterning of the contact layer, the contact layer is in contact with the contact electrode required to be led out on the MEMS structure, thereby realizing electrode selection and ensuring electrical connection. The electrode is a structure arranged in an array and uniformly distributed on the contact layer, which can ensure that the number of electrodes after the patterning of the contact layer is sufficient and meet the diversity adaptation requirements of the patterning, and the array distribution can ensure the density and comprehensive coverage effect of the electrode.

[0018] The commonly used scheme is to customize the cover plate according to each device, design the through hole electrode of the cover plate according to the electrode condition of the device, and take the cover plate with a GIS (glass-silicon composite) structure as an example. The universal cover plate needs to go through the processes of photolithography, etching, anode bonding, high-temperature annealing, and double-sided polishing, and needs more than ten processes. Each time a new structure device is developed, these processes need to be repeated, and generally only 4-6 wafers of the device are needed. The universal cover plate of the application can be mass-produced, and the universal cover plate required for wafer-level packaging of the device can be completed through only one photolithography and etching process subsequently.

[0019] The universal cover plate of the application can be mass-produced in advance. When developing different structures of MEMS devices, the contact layer can be patterned according to the electrode condition required to be led out. Compared with the conventional customized universal cover plate, the application can effectively shorten the development cycle of the device and reduce the development cost, and has important significance for the development of new structure MEMS devices. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the present application or the prior art, the drawings required to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0021] Figure 1 is one of the structural schematic diagrams of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 2 is the second structural schematic diagram of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 3 is the third structural schematic diagram of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 4 is the fourth structural schematic diagram of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 5 is the fifth structural schematic diagram of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 6 is the sixth structural schematic diagram of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 7 is the schematic diagram of step S100 of the manufacturing method of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 8 is one of the schematic diagrams of step S200 of the manufacturing method of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 9 is the second schematic diagram of step S200 of the manufacturing method of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 10 is the schematic diagram of step S300 of the manufacturing method of the cover plate for wafer level packaging provided by the embodiments of the present application; Figure 11 is the schematic diagram of step S400 of the manufacturing method of the cover plate for wafer level packaging provided by the embodiments of the present application.

[0022] Reference signs: 100, electrode layer; 110, electrode; 120, contact layer; 200, base body; 300, insulating layer. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the present application clearer, the following will clearly and completely describe the technical solutions in the present application with reference to the drawings in the present application. Obviously, the described embodiments are only a part of embodiments of the present application, but not all embodiments of the present application. Based upon the embodiments in the present application, all other embodiments obtained by those ordinarily skilled in the art without creative effort should fall into the scope of the present application.

[0024] In the description of the embodiments of the present application, it should be noted that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the embodiments of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0025] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0026] In the embodiments of the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be that the first feature is directly above or obliquely above the second feature, or it can only mean that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be that the first feature is directly below or obliquely below the second feature, or it can only mean that the horizontal height of the first feature is less than that of the second feature.

[0027] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0028] As shown in Figures 1 to 5 The universal cover plate for wafer level packaging provided by the embodiments of the present application includes an electrode layer 100, the electrode layer 100 includes a plurality of electrodes 110 and a contact layer 120, the plurality of electrodes 110 are distributed in an array, and the two end faces of the electrode 110 along its axial direction are respectively a first surface and a second surface; the contact layer 120 is connected to the first surface of at least one electrode 110.

[0029] The universal cover plate for wafer level packaging of the embodiments of the present application is mainly composed of an electrode layer 100, the electrode layer 100 is mainly composed of a plurality of electrodes 110 and a contact layer 120, the plurality of electrodes 110 are distributed in an array in the same plane, the two end faces of the electrode 110 along its axial direction are respectively a first surface and a second surface, the contact layer 120 is stacked on the first surface of the electrode 110, the electrode 110 and the contact layer 120 are stacked, and thus the second surface of the electrode 110 and the surface of the contact layer 120 which is not connected with the electrode 110 form two surfaces arranged oppositely on both sides of the electrode layer 100, and the contact layer 120 is connected with at least one electrode 110, thereby ensuring the conductive performance of the universal cover plate.

[0030] The surface of the contact layer 120 which is not connected with the electrode 110 serves as the back surface of the universal cover plate, and the electrode 110 is a structure designed to be distributed in an array within the range of the contact layer 120, and some of the electrodes 110 distributed in an array can be selected flexibly by removing part of the contact layer 120 to retain a pattern structure suitable for connecting the contact electrodes of the wafer, thereby adapting to the bonding requirements of the MEMS structure. After the contact layer 120 is patterned, it is contacted with the contact electrodes needed to be led out on the MEMS structure, thereby realizing the selection of the electrode 110 and ensuring the electrical connection. The electrode 110 is a structure distributed in an array and uniformly distributed on the contact layer 120, which can ensure that the number of electrodes 110 after the pattern processing of the contact layer 120 is sufficient and meets the diversity adaptation requirements of the pattern processing, and the array distribution can ensure the density and comprehensive coverage effect of the electrode 110.

[0031] The commonly used scheme is that the cover plate is customized according to each device, the through-hole electrode 110 of the cover plate is designed according to the electrode 110 of the device, and the general cover plate is manufactured by using the cover plate with a GIS (glass-silicon composite) structure, which needs to go through photoetching, etching, anodic bonding, high-temperature annealing, and double-sided polishing processes, and needs more than ten processes. When a new structure device is developed each time, these processes need to be repeated, and generally only 4-6 wafers of the device are developed. The general cover plate of the application can be mass-produced, and the general cover plate required for wafer-level packaging of the device can be completed through only one photoetching and etching process subsequently.

[0032] The general cover plate of the application can be mass-produced in advance, and when different structure MEMS devices are developed, the contact layer 120 can be patterned according to the electrode 110 to be led out. Compared with the conventional customized general cover plate, the application can effectively shorten the development cycle of the device and reduce the development cost, and has important significance for the development of new structure MEMS devices.

[0033] In the embodiment, the electrode 110 can be a metal material, a low-resistance silicon or other conductive material, and the contact layer 120 can be low-resistance silicon.

[0034] According to one embodiment of the application, the contact layer 120 and the electrode 110 connected thereto are an integral structure.

[0035] In the embodiment, the electrode 110 is formed in an array distribution process: the substrate is etched, the etched part forms a groove, and the remaining part forms the array distributed electrode 110 and the continuous and complete contact layer 120 connected with the first surface of the electrode 110, that is, one side of the substrate is the second surface of the electrode 110, and the other side of the substrate is the surface of the contact layer 120 not connected with the electrode 110. Therefore, the contact layer 120 and the electrode layer 100 are an integral structure formed after the substrate is etched, which is a pattern structure matched with the contact electrode of the wafer, and by removing part of the contact layer 120, some of the array distributed electrodes 110 can be flexibly selected and applied to realize the matched connection between the contact electrode of the wafer and the contact layer 120.

[0036] In the embodiment, the contact layer 120 and the electrode layer 100 are integrally formed, which is simpler and faster to process and manufacture, ensures that the contact layer 120 has a connection part with each electrode 110, the connection strength of the contact layer 120 and the electrode 110 is higher, and each electrode 110 can be selected and applied, and the change mode of the contact layer 120 of the general cover plate and the adaptability to the contact electrodes of various shapes are higher.

[0037] When the electrode 110 and the contact layer 120 are in an integrated structure, the electrode 110 and the contact layer 120 are made of the same material, and when the electrode 110 and the contact layer 120 are made of different materials, the electrode 110 and the contact layer 120 need to be connected into an integrated whole by other processes and then bonded to the substrate 200, for example, the electrode 110 is made of metal material and the contact layer 120 is made of low-resistance silicon.

[0038] According to one embodiment of the present application, the universal cover plate for wafer-level packaging further comprises a substrate 200 connected to the side surfaces of the electrodes 110.

[0039] In the embodiment, the universal cover plate for wafer-level packaging mainly comprises an electrode layer 100 and a substrate 200, the substrate 200 is formed with a through hole, the through hole is the internal space formed after the substrate 200 is in a molten state and surrounds the electrode 110 during bonding and then is annealed and cooled, the electrode 110 is embedded in the through hole, the contact layer 120 is stacked on the first surface of the electrode 110, the electrode 110 and the contact layer 120 are stacked, and the contact layer 120 is connected to the electrode 110 in the through hole, so as to ensure the electrical conductivity of the universal cover plate. The electrode 110 is located in the through hole formed by the substrate 200, which not only ensures the stable position of the electrode 110, but also isolates the adjacent electrodes 110.

[0040] In the embodiment, the electrode 110 can be made of metal material, low-resistance silicon or other conductive material, the substrate 200 is an insulating structure and can be made of silicon oxide, silicon nitride, glass or other insulating material, and the contact layer 120 can be made of low-resistance silicon.

[0041] The present application provides a universal cover plate for MEMS wafer-level packaging, the electrode 110 adopts an array structure and is connected to the low-resistance silicon on the back of the universal cover plate, and some through-hole electrode 110 structures in the array can be selected flexibly according to the requirements of the MEMS structure, the low-resistance silicon is patterned and then contacts the electrode 110 to be led out on the MEMS structure, so as to realize electrical connection and isolation between the electrodes 110. The universal cover plate can be processed in batches in advance, and when developing MEMS devices with different structures, some through-hole electrode 110 structures in the array can be selected flexibly according to the electrode 110 to be led out, the low-resistance silicon on the back is patterned, and the selection and isolation of the electrode 110 are realized. Compared with the conventional customized universal cover plate, the universal cover plate of the present application can greatly shorten the development cycle of new devices and reduce the development cost, and has important significance for the development of new structure MEMS devices.

[0042] According to one embodiment of the present application, the substrate 200 is further connected to the second surfaces of the electrodes 110.

[0043] In this embodiment, a non-through blind hole can be provided on the substrate 200. That is, the second surface of the electrode 110 within the blind hole of the substrate 200 is not exposed and is in contact with the bottom of the blind hole. If the depth of the blind hole is greater than or equal to the height of the electrode 110, the substrate 200 effectively surrounds the electrode 110 completely. If the depth of the blind hole is less than the height of the electrode 110, the substrate 200 effectively surrounds the electrode 110 partially from the second surface to the first surface. The thickness of the substrate 200 affects the overall thickness of the electrode layer 100. Therefore, the blind hole design can further improve the protection and isolation effect of the electrode 110, and also provide space for adjusting the thickness of the electrode layer 100.

[0044] According to one embodiment of the present invention, the two side surfaces of the substrate 200 are flush with the first and second surfaces of the electrode 110, respectively.

[0045] In this embodiment, the first and second surfaces of the electrode 110 are also two opposing surfaces on the substrate 200. A through-hole extending from the first surface to the second surface is formed on the substrate 200. The shape and size of the electrode 110 are consistent with the shape and size of the through-hole. The electrode 110 completely fills the internal space of the positioning hole, resulting in a tighter fit between the electrode 110 and the substrate 200. Simultaneously, the filled state of the electrode 110 ensures that its end face is flush with the first surface of the substrate 200. Therefore, when the contact layer 120 is laminated with the first surface of the substrate 200, it ensures that the surface of the contact layer 120 and the end face of the electrode 110 are in contact and conductive communication.

[0046] like Figure 6 As shown, according to an embodiment of the present invention, the substrate 200 is a conductor, and an insulating layer 300 is provided between the substrate 200 and the side surfaces of each electrode 110 and between the substrate 200 and the contact layer 120.

[0047] In this embodiment, when the substrate 200 is made of a conductive material, an insulating layer 300 can be added between the substrate 200 and the electrode 110. For example, when the substrate 200 is a high-resistivity silicon, through holes or blind holes on the substrate 200 can be formed first, that is, an array of holes can be formed on the substrate 200. Then, an insulating material is covered on the surface of the substrate 200 and the inner side of the holes to form an insulating layer 300. After that, the electrode 110 is embedded in the holes of the substrate 200 to form an array of electrodes 110. Finally, the contact layer 120 is connected to the first surface of the electrode 110, thereby realizing the function of the insulating layer 300 separating and insulating the substrate 200 from the electrode 110 and separating and insulating the substrate 200 from the contact layer 120.

[0048] In the above embodiment, the general cover plate for wafer level packaging provides a general cover plate application scheme of GIS structure, and can be extended to TSV (through silicon via) general cover plate and TGV (through glass via) general cover plate. As shown in Figure 6 In the TSV general cover plate, the substrate 200 is high resistance silicon, the insulating layer 300 is made of insulating material, the electrode 110 is a metal electrode 110, and the contact layer 120 is low resistance silicon. As shown in Figure 5 In the TGV general cover plate, the substrate 200 is glass, the electrode 110 is a metal electrode 110, and the contact layer 120 is low resistance silicon.

[0049] The MEMS wafer level packaging method provided by the present application is described below, and the MEMS wafer level packaging method described below can be referred to each other corresponding to the general cover plate for wafer level packaging described above.

[0050] As shown in Figure 11 The embodiment of the present application also provides a MEMS wafer level packaging method, which comprises using the general cover plate for wafer level packaging as described above to form a pattern structure on the contact layer 120 of the general cover plate, which matches the contact electrode of the wafer to be packaged, and to bond the contact electrode of the wafer to be packaged.

[0051] The MEMS wafer level packaging method of the embodiment of the present application uses the general cover plate to complete the wafer level packaging of the MEMS suspended structure. The MEMS structure to be bonded is completed by using conventional MEMS process. When the wafer level packaging of the MEMS structure is completed by using the bonding process, the bonding process can use anode bonding, eutectic bonding, hot-press bonding and direct bonding, etc., which is determined according to the actual situation of the sample.

[0052] The manufacturing method of the general cover plate for wafer level packaging provided by the present application is described below, and the manufacturing method of the general cover plate for wafer level packaging described below can be referred to each other corresponding to the general cover plate for wafer level packaging described above.

[0053] As shown in Figures 7 to 10 The embodiment of the present application provides a manufacturing method of a general cover plate for wafer level packaging, which comprises: Step S100, forming the electrodes 110 distributed in an array and the contact layer 120 connected with the first surface of all the electrodes 110 by etching the substrate; Step S200, anode bonding the electrodes 110 and the substrate 200; Step S300, annealing at a set temperature, and coating the side surface and the second surface of the electrode 110 after the substrate 200 is melted at the set temperature.

[0054] Step S400, polishing the substrate 200 and the contact layer 120 respectively until the thickness of the cover plate reaches the set thickness.

[0055] The manufacturing method of the universal cover plate for wafer-level packaging in the embodiment of the application etches the columnar electrodes 110 on the upper surface of the substrate, and the electrodes 110 are distributed in an array, and the unetched part becomes the contact layer 120 connected with the electrodes 110. The substrate 200 is anodically bonded with the electrodes 110. After the substrate 200 is melted, it can flow into the grooves formed by etching between the electrodes 110, so that the surface of the contact layer 120 can be completely covered by the electrodes 110. Finally, the contact layer 120 is the front surface of the universal cover plate, and the electrodes 110 and the substrate 200 are the back surface of the universal cover plate. The contact layer 120 and the substrate 200 are polished to change the thickness of the contact layer 120 and the substrate 200, so as to adjust the overall thickness of the universal cover plate, until the thickness of the universal cover plate reaches the set thickness required for packaging.

[0056] Compared with the conventional customized universal cover plate, the electrodes 110 and the contact layer 120 in an array are formed by etching in the application, the substrate 200 is anodically bonded with the electrodes 110 and is melted at a set temperature, which can ensure that the connection between the substrate 200 and the electrodes 110 is fully complete, the process method is simple and efficient, the contact layer 120 can be changed in shape through subsequent process means, and different electrode 110 structures on the MEMS structure can be adapted. At the same time, the research and development cycle of the device can be effectively shortened, the research and development cost can be reduced, and the research and development work of new structure MEMS devices has important significance.

[0057] In the embodiment, the universal cover plate adopts a GIS (glass-silicon composite structure) structure. The substrate adopts low-resistance silicon, the substrate 200 adopts glass, the low-resistance silicon is patterned by photolithography, deep silicon etching is performed to obtain the electrodes 110 and the contact layer 120, and then the glass is anodically bonded. The glass is in a molten state at high temperature, flows into the grooves formed on the substrate by etching, and the universal cover plate is polished on both sides. The three-layer structure reaches the designed thickness to form the universal cover plate structure required for final packaging.

[0058] As shown in FIG. 1, Figure 11 According to one embodiment of the application, the manufacturing method of the universal cover plate for wafer-level packaging further comprises: Step S500, etching the contact layer 120 to form a pattern structure required for bonding with the contact electrodes of the wafer to be packaged.

[0059] In the actual packaging process, the contact layer 120 is patterned by using photolithography and silicon etching process according to the design of the bonding area of the MEMS structure to be bonded, and a contact area is formed.

[0060] After the universal cover plate with thickness polishing is completed, the contact layer 120 is etched to pattern the contact layer 120, and the contact layer 120 is in contact with the electrode 110 to be led out on the MEMS structure after the patterning, so that the electrode 110 is selected and the electrical connection is ensured. The electrode 110 is located in the positioning hole formed by the base 200, which can not only ensure the position stability of the electrode 110, but also isolate the adjacent electrodes 110. The universal cover plate of the application can be mass-produced in advance. When the MEMS device with different structures is developed, the contact layer 120 can be patterned according to the situation of the electrode 110 to be led out.

[0061] The manufacturing method of the universal cover plate for wafer-level packaging provided by the application will be described below. The manufacturing method of the universal cover plate for wafer-level packaging described below can be correspondingly referred to the universal cover plate for wafer-level packaging described above.

[0062] As shown in Figure 6 The manufacturing method of the universal cover plate for wafer-level packaging provided by the application is applied to the universal cover plate for wafer-level packaging of the above-mentioned embodiments, which comprises the following steps: The base 200 with through holes in array distribution is formed by etching the substrate; The insulating layer 300 is attached to the inner wall of the through hole and the surface of the base 200; The electrode 110 is filled in the through hole; The two surfaces of the base 200 are polished respectively until the thickness of the universal cover plate reaches the set thickness; The contact layer 120 is formed on the first surface of the electrode 110.

[0063] The manufacturing method of the universal cover plate for wafer-level packaging of the embodiments of the application is applied to the universal cover plate with the base 200 made of conductive material. When the base 200 is made of conductive material, an insulating layer 300 can be additionally arranged between the base 200 and the electrode 110. For example, when the base 200 is made of high-resistance silicon, the through hole on the base 200 is formed first, that is, the through hole in array distribution is formed on the base 200, then the insulating material is covered on the surface of the base 200 and the inner side of the through hole to form the insulating layer 300, and then the electrode 110 made of metal material is embedded in the through hole of the base 200 to form the electrode 110 in array distribution. At this time, the electrode 110 and the base 200 are a whole, and the front and back surfaces of the whole are polished until the thickness of the universal cover plate reaches the set thickness. Finally, the contact layer 120 made of low-resistance silicon is arranged on the first surface of the electrode 110 by evaporation process. At this time, the contact layer 120 made of low-resistance silicon is also connected with the surface of the base 200, and the insulating layer 300 is also formed on the connection position.

[0064] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A universal cover plate for wafer-level packaging, characterized in that, include: The electrode layer (100) includes: Multiple electrodes (110) are arranged in an array, and the two end faces of the electrodes (110) along their axial direction are respectively the first surface and the second surface. A contact layer (120) is attached to the first surface of at least one of the electrodes (110).

2. The universal cover plate for wafer-level packaging according to claim 1, characterized in that, The contact layer (120) and the electrode (110) to which it is connected are an integral structure.

3. The universal cover plate for wafer-level packaging according to claim 1 or 2, characterized in that, Also includes: A substrate (200) is connected to the side surfaces of each of the electrodes (110).

4. The universal cover plate for wafer-level packaging according to claim 3, characterized in that, The substrate (200) is also connected to the second surface of each of the electrodes (110).

5. The universal cover plate for wafer-level packaging according to claim 3, characterized in that, The two side surfaces of the substrate (200) are flush with the first and second surfaces of the electrode (110), respectively.

6. The universal cover plate for wafer-level packaging according to claim 3, characterized in that, The substrate is a conductor, and an insulating layer (300) is provided between the substrate (200) and the side of each electrode (110) and between the substrate (200) and the contact layer (120).

7. A MEMS wafer-level packaging method, characterized in that, include: Using the universal cover plate for wafer-level packaging as described in any one of claims 1 to 6, a pattern structure is formed on the contact layer (120) of the universal cover plate to cooperate with the contact electrodes of the wafer to be packaged, and the pattern structure is bonded to the contact electrodes of the wafer to be packaged.

8. A method for manufacturing a universal cover plate for wafer-level packaging, characterized in that, The universal cover plate for wafer-level packaging as described in any one of claims 1 to 5 comprises: The substrate is etched to form an array of electrodes (110) and a contact layer (120) connected to the first surface of all electrodes (110). The electrode (110) is anodicly bonded to the substrate (200); Annealing at a set temperature, the substrate (200) melts at the set temperature and then coats the side surface and second surface of the electrode (110); The substrate (200) and the contact layer (120) are polished separately until the thickness of the cover plate reaches the set thickness.

9. The method for manufacturing a universal cover plate for wafer-level packaging according to claim 8, characterized in that, Also includes: The contact layer (120) is etched to form the pattern structure required for bonding with the contact electrodes of the wafer to be packaged.

10. A method for manufacturing a universal cover plate for wafer-level packaging, characterized in that, The universal cover plate for wafer-level packaging as described in claim 6 comprises: The substrate is etched to form a substrate (200) with an array of through holes. An insulating layer (300) is attached to the inner wall of the through hole and the surface of the substrate (200); The electrode (110) is filled into the through hole; The two sides of the substrate (200) are polished until the thickness of the universal cover plate reaches the set thickness. A contact layer (120) is formed on the first surface of the electrode (110).

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