Data operation method and device, equipment and storage medium

Abstract

The invention discloses a data operation method and device, equipment and a storage medium. The data operation method comprises the steps that data operation information is received through a specified operation interface of the storage; determining a current operation pointer in the memory cache region, and determining a data operation mode according to the current operation pointer and the data operation information; performing data operation in a memory cache region by taking the current operation pointer as a starting point and referring to a data operation mode; and updating the current operation pointer in the memory cache region according to a data operation result. Based on the fact that the pointer makes the read-write operation of the data no longer fix the constraint of the data bit width in the cache region, non-aligned read-write of any byte data can be efficiently processed, waste of the storage bandwidth is eliminated, the corresponding operation of the data is achieved through the dynamic change of the pointer in the cache region, and the data storage efficiency is improved. Therefore, complex operations such as splitting, merging and carrying of the data by additionally adding hardware resources up and down are avoided, and the hardware resources are saved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a data manipulation method, apparatus, device, and storage medium. Background Technology

[0002] In the field of application-specific integrated circuit (ASIC) chip data processing, first-in-first-out (FIFO) memory is a core component in the data path, widely used in scenarios such as data caching, cross-clock domain data transmission, and interface protocol adaptation. With increasing chip functional complexity and faster data transmission rates, higher demands are placed on the flexibility, bandwidth utilization, and data processing efficiency of FIFOs.

[0003] In current data transmission, the demand for variable-length data packets and unaligned data reading and writing is becoming increasingly common, making the fixed-width design of traditional FIFOs difficult to adapt to diverse data processing scenarios. In particular, the fixed-width design limits flexibility. Reading and writing unaligned or variable-length data requires additional processing logic, increasing system complexity and latency. Bandwidth waste is also common during data transmission; for example, when using a 32-bit FIFO to transmit 8 bytes of data, the remaining 24 bits of bandwidth are idle. Separating packet boundary markers from data transmission poses a synchronization risk, potentially leading to data parsing errors. The additional splitting, splicing, and alignment logic consumes more hardware resources, reducing the overall chip integration and energy efficiency. Summary of the Invention

[0004] This invention provides a data manipulation method, apparatus, device, and storage medium to achieve flexible data manipulation while saving hardware resources.

[0005] According to a first aspect of the present invention, a data operation method is provided, comprising: receiving data operation information through a designated operation interface of a memory, wherein the data operation information includes read-related operation information or write-related operation information;

[0006] The current operation pointer in the memory cache is determined, and the data operation mode is determined based on the current operation pointer and the data operation information. The operation pointer includes a block pointer, an intra-block pointer, and an intra-block horizontal pointer. The data operation mode includes a cross-cache line operation mode or a non-cross-cache line operation mode.

[0007] Starting from the current operation pointer, data operations are performed in the memory cache according to the data operation mode;

[0008] The current operation pointer in the memory cache is updated based on the result of the data operation.

[0009] According to another aspect of the present invention, a data operation apparatus is provided, the apparatus comprising: a data operation information receiving module, configured to receive data operation information through a specified operation interface of a memory, wherein the data operation information includes read-related operation information or write-related operation information;

[0010] The data operation mode determination module is used to determine the current operation pointer in the memory cache and determine the data operation mode based on the current operation pointer and the data operation information. The operation pointer includes a block pointer, an intra-block pointer, and an intra-block horizontal pointer. The data operation mode includes a cross-cache line operation mode or a non-cross-cache line operation mode.

[0011] A data operation mode determination module is used to perform data operations in the memory cache area with the current operation pointer as the starting point and in accordance with the data operation mode.

[0012] An update module is used to update the current operation pointer in the memory cache based on the result of the data operation.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: one or more processors;

[0014] Storage device for storing one or more programs.

[0015] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any embodiment of the present invention.

[0016] According to another aspect of the present invention, a storage medium for computer-executable instructions is provided, on which a computer program is stored, which, when executed by a processor, implements the method as described in any of the embodiments of the present invention.

[0017] The technical solution of this invention determines the data operation mode by using the current operation pointer in the memory cache and the data operation information received by the specified operation interface, and performs data operations in the memory cache based on the data operation mode. Thus, based on the pointer in the cache, the data read and write operations are no longer constrained by the fixed data bit width, which can efficiently handle the unaligned read and write of arbitrary byte data and eliminate the waste of storage bandwidth. Since the corresponding data operation is realized by the dynamic change of the pointer in the cache, the complex operations such as splitting, merging and moving data by adding additional hardware resources are avoided, thus saving hardware resources.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a data manipulation method provided in Embodiment 1 of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure of a memory according to Embodiment 1 of the present invention;

[0022] Figure 3 This is a schematic diagram of a data operation mode for a cross-cache row write operation according to Embodiment 1 of the present invention;

[0023] Figure 4 This is a timing diagram of a cross-cache line write operation mode according to Embodiment 1 of the present invention;

[0024] Figure 5 This is a schematic diagram of a data operation mode that does not cross cache line write operation according to Embodiment 1 of the present invention;

[0025] Figure 6 A timing diagram of a write operation mode that does not cross cache lines according to Embodiment 1 of the present invention;

[0026] Figure 7 This is a schematic diagram of a data operation mode for a cross-cache row read operation according to Embodiment 1 of the present invention;

[0027] Figure 8 This is a schematic diagram of a data operation mode that does not cross cache line read operation according to Embodiment 1 of the present invention;

[0028] Figure 9 This is a flowchart of another data operation method provided in Embodiment 2 of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of a data manipulation device provided in Embodiment 3 of the present invention;

[0030] Figure 11 This is a structural block diagram of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or terminal device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or terminal devices.

[0033] Example 1

[0034] Figure 1 This is a flowchart of a data operation method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where data is read and written based on pointers. The method can be executed by a data operation device, which can be implemented in hardware and / or software, and can be integrated into an electronic device with data processing capabilities. Figure 1 As shown, the method includes:

[0035] S101 receives data operation information through the designated operation interface of the memory.

[0036] Optionally, data operation information is received through a specified operation interface of the memory, including: receiving data to be written through the write data interface of the memory, receiving the number of bytes of data to be written through the write byte count interface, receiving a write instruction through the write enable interface, and receiving a write block end marker through the write end interface; using the data to be written, the number of bytes of data to be written, the write instruction, and the write block end marker as write-related operation information; receiving a read instruction through the read enable interface of the memory, receiving the number of bytes of data to be read through the read byte count interface; using the read instruction and the number of bytes of data to be read as read-related operation information.

[0037] Specifically, such as Figure 2 The diagram shows the structure of the memory used in this embodiment. The memory includes multiple operation results for information exchange with upstream and downstream components. Table 1 below shows the descriptions of each interface:

[0038]

[0039] Compared to conventional storage chips, this embodiment adds a write byte count interface (Wr_byte_num), a write end interface (Wr_last), and an idle byte count interface (Idle_level) to the write interface side. In this embodiment, while receiving the data to be written from the upstream via the write data interface (Wr_data), it also obtains the number of bytes to be written via the write byte count interface (Wr_byte_num), thus describing the size of the data to be written. When the write enable interface receives a write instruction of 1 from wr_en, the data to be written needs to be written. The write end interface (Wr_last) is used to receive the write block end marker. When the write block end marker is 0, it indicates that the current block is not finished writing and data writing needs to continue from the current block. By adding the write end interface, this embodiment can clearly define or locate the boundaries of each data block, thereby achieving precise marking of the boundaries of variable-length data packets. For the read interface side, a read end interface (Rd_last), a read byte count interface (Rd_byte_num), and a read / write same block interface (Same_block) are added. The number of bytes to be read can be obtained through the read byte count interface Rd_byte_num, which describes the size of the data to be read. The read end interface Rd_last is used to output a read end flag. When the read end flag is 1, it indicates that the data in the current block has been read completely, thus accurately marking the boundary of variable-length data packets and informing downstream devices that no further data reading from the current block is required. The relevant parameters of the memory involved in this embodiment are shown in Table 2 below:

[0040]

[0041] In this embodiment, the above parameters are used as examples for illustration only, and no specific parameters related to the memory are limited. Furthermore, the memory not only improves the read / write interface but also includes a dynamically changing cache. The size of the data blocks stored in the cache can change dynamically, but the maximum number of data blocks (BLOCK_MAX) cannot exceed the maximum depth (DEPTH) of the cache. Each data block can consist of multiple cache lines, for example... Figure 2 BLOCK1, as shown, consists of more than two cache lines. A block statistics counter is also configured in the memory. , It is a two-dimensional array. The first dimension records the number of bytes remaining in the current block. When the read pointer and write pointer are not in the same data block, it can notify the read interface how much space is left to read. The second dimension is used to indicate the current block number. Furthermore, this embodiment sets up three sets of pointers for the memory cache: block pointer, intra-block pointer, and intra-block horizontal pointer. For example, for write operations, these are specifically the write block pointer wr_block_ptr, the intra-block write pointer wr_ptr, and the intra-block write horizontal pointer wr_ptr_hori; for read operations, these are specifically the read block pointer rd_block_ptr, the intra-block read pointer rd_ptr, and the intra-block read horizontal pointer rd_ptr_hori. This achieves the function of writing and reading data on demand. Of course, this embodiment is only an example and does not limit the interface type or internal structure of the memory.

[0042] S102, determine the current operation pointer in the memory cache, and determine the data operation mode based on the current operation pointer and data operation information.

[0043] Optionally, the data operation mode is determined based on the current operation pointer and data operation information, including: obtaining the maximum width of the cache line and the result of adding the number of bytes of the horizontal pointer in the current block to the number of bytes of the specified data, wherein the specified data includes data to be written or data to be read; determining whether the sum is greater than the maximum width, if so, the data operation mode is determined to be a cross-cache line operation mode, otherwise, the data operation mode is determined to be a non-cross-cache line operation mode; wherein, the cross-cache line operation mode includes a cross-cache line write operation mode or a cross-cache line read operation mode, and the non-cross-cache line operation mode includes a non-cross-cache line write operation mode or a non-cross-cache line read operation mode.

[0044] Specifically, in this embodiment, a data block includes multiple cache lines, and each cache line has a maximum bandwidth (DW), for example, DW = 128 bytes. This is merely an example and does not limit the specific value of the maximum bandwidth. In this embodiment, the horizontal pointer within the current block is added to the number of bytes of specified data to obtain the sum. The specified data here specifically includes data to be written or data to be read, i.e., it addresses both read and write scenarios. Different data operation modes are determined based on the comparison between the sum and the maximum bandwidth. These data operation modes specifically include cross-cache line operation modes or non-cross-cache line operation modes. For example, during a write operation, if the block write pointer wr_ptr = 0, the current block write horizontal pointer wr_ptr_hori = 80, the number of bytes to be written is 30, and DW = 128 bytes, since 80 + 30 = 110 < 128, the remaining space on the current cache line Buf[0] indicated by the block write pointer wr_ptr is sufficient to hold the data to be written. In this case, it is determined that there is no need to cross cache lines to the next cache line to write the data. Therefore, the determined data operation mode is the non-cache line write operation mode. In addition, when the number of bytes to be written is 50, since 80 + 50 = 130 > 128, the data operation mode is determined to be the cross-cache line write operation mode. Of course, this embodiment only uses the write operation as an example for explanation. For the read operation, the corresponding data operation mode also includes the cross-cache line read operation mode or the non-cache line read operation mode, and the principle is roughly the same as the judgment principle of the operation mode corresponding to the write operation. In this embodiment, it will not be elaborated again.

[0045] S103, starting from the current operation pointer, performs data operations in the memory cache according to the data operation mode.

[0046] Optionally, data operations are performed in the memory cache area with reference to the data operation mode, starting from the current operation pointer. This includes: determining the latest write block pointer based on the content of the write end marker, wherein the latest write block pointer is the same as the current write block pointer or is the current write block pointer plus 1; when the data operation mode is a non-cache line write operation mode, determining that the latest intra-block write pointer is the same as the current intra-block write pointer, writing the data to be written to the free space of the current cache line indicated by the current intra-block write pointer as the starting point, and taking the starting point of the remaining free space of the current cache line after writing the data as the latest intra-block write pointer; when the data operation mode is a cross-cache line write operation mode, determining that the latest intra-block write pointer is the current intra-block write pointer plus 1, filling the current cache line indicated by the current intra-block write pointer with the first part of the data to be written as the starting point, writing the second part of the data to be written from the starting point of the free space of the next cache line indicated by the latest intra-block write pointer, and taking the starting point of the remaining space of the next cache line as the latest intra-block write pointer.

[0047] In a specific implementation, such as Figure 3 The diagram illustrates a data operation method for a cross-line write operation. In this embodiment, the write end marker can be used as a reference. The content determines the latest write block pointer, when If the current data block pointer is not yet complete, then the latest write block pointer needs to be determined. Same as the current write block pin, when When the current data block is written, it indicates that the writing of the current data block has been completed, and the writing of the next data block begins. At this point, the latest write block pointer is set to the current write block pointer plus 1. When DW = 128 bytes, the current block's write horizontal pointer is 100, and the number of bytes to be written is... , write enable In this case, when performing cross-cache line write operations, one write operation needs to be processed in one clock cycle. Writing across cache line boundaries requires combinational logic calculations. Assign to That is, the data to be written is shifted 100 bits to the left; then the high-order 28 bytes of data are ORed with the original data of Buf[0], thereby changing the first part of the 28 bytes. Fill it with writing; then Assign to The data to be written will be shifted right by 28 bytes, thus saving the second part (the high 72 bytes) to the next cache line. Because this is a cross-cache line operation, the latest block write pointer is incremented by 1 from the current block write pointer. , Furthermore, the number of free bytes remaining in the cache is equal to the total number of remaining bytes minus the number of bytes currently written. ,in This indicates that there is no remaining block space. ,otherwise ,and Therefore, when the second timing logic is... Assign to , Assign to , Assign to Assign to Assign to Assign to Assign to ,like Figure 4 The diagram shown is a timing diagram of the cross-cache line write operation mode. Of course, this embodiment is only an example and does not specifically limit the data operation mode of the cross-cache line write operation mode.

[0048] In another specific implementation, Figure 5 This is a schematic diagram of a data operation mode that does not cross cache lines. Referring to the cross cache line write operation mode, when the data operation mode is a non-cross cache line write operation mode, the latest internal write pointer wr_ptr is determined to be the same as the current block internal write pointer, which is 0. The data to be written (30 bytes) is written into the free space of the current cache line Buf[0] indicated by the current block internal write pointer wr_ptr_hori=80 as the starting point. The starting point of the remaining free space of the current cache line after writing the data is taken as the latest internal write pointer wr_ptr_hori=110. Figure 6 According to Embodiment 1 of the present invention, a timing diagram of a non-cache row write operation mode is provided. Of course, this embodiment is only an example and does not limit the specific data operation mode of the non-cache row write operation.

[0049] Optionally, data operations are performed in the memory cache area with reference to the data operation mode, starting from the current operation pointer. This includes: when the data operation mode is a non-cross-cache-line read operation mode, determining that the latest intra-block read pointer is the same as the current intra-block read pointer, reading the specified number of bytes of data from the current cache line indicated by the current intra-block read pointer, and using the current intra-block read horizontal pointer as the starting point, and taking the starting point of the remaining data in the current cache after the data reading as the latest intra-block read horizontal pointer; when the data operation mode is a cross-cache-line read operation mode, determining that the latest intra-block read pointer is the current intra-block read pointer plus 1, reading all the remaining data in the current cache line indicated by the current intra-block read pointer as the starting point, reading data from the starting point of the next cache line indicated by the latest intra-block read pointer according to the number of bytes of remaining data to be read, and taking the starting point of the remaining data in the next cache line as the latest intra-block read horizontal pointer; when it is determined that the data in the data block pointed to by the current read block pointer has been read completely, a read end mark is generated, and the current read block pointer is incremented by 1 according to the read end mark as the latest read block pointer.

[0050] In a specific implementation Figure 7 This is a schematic diagram of a data operation mode for cross-cache line read operation. When the data operation mode is cross-cache line read operation mode, the latest block read pointer rd_ptr is determined to be the current block read pointer plus 1, that is, the latest rd_ptr=1. Starting from the current block read horizontal pointer rd_ptr_hori=80, all the remaining data in the current cache line Buf[0] indicated by the current block read pointer is read. When DW=128, the remaining data is 48. According to the number of bytes of remaining data to be read 100-48=52, the data is read from the starting point of the next cache line Buf[1] indicated by the latest block read pointer, and the starting point of the remaining data in the next cache line is taken as the latest block read horizontal pointer rd_ptr_hori=52. In addition, once it is determined that the data in the data block pointed to by the current read block pointer rd_block_ptr has been read completely, a read end marker rd_last=1 is generated, and the current read block pointer is incremented by 1 according to the read end marker to become the latest block pointer. When rd_last=0, it means that the data in the currently read data block has not been read completely. At this time, it is determined that the latest read block pointer is the same as the current read block pointer, and the result of the read end marker will be output through the rd_last interface.

[0051] In another specific implementation, Figure 8This is a schematic diagram of the data operation mode of non-cross-cache line read operation mode. When the data operation mode is non-cross-cache line read operation mode, the latest intra-block read pointer rd_ptr is determined to be the same as the current intra-block read pointer, that is, rd_ptr=0. Starting from the current intra-block read horizontal pointer rd_ptr_hori=80, the specified number of bytes, that is, 30 bytes of data, are read from the current cache line Buf[0] indicated by the current intra-block read pointer. The starting point of the remaining data in the current cache after the data is read is taken as the latest intra-block read horizontal pointer rd_ptr_hori=110.

[0052] Optionally, after performing data operations in the memory cache area with reference to the data operation mode starting from the current operation pointer, the method further includes: when it is determined that the data to be written has been written in the memory cache area, obtaining the number of free bytes in each block of the memory cache area; storing the number of free bytes in the block statistics counter, so that the block statistics counter outputs the number of free bytes through the memory's free byte count interface.

[0053] Specifically, in this embodiment, the block counter (Block cnt) can record the number of empty bytes in each database based on the data writing status. Therefore, the block counter can output the number of free bytes in each data block through the Idle_level interface of the memory. On the other hand, based on the statistical results in the block counter, the number of remaining readable bytes in the current data block can be determined by combining the output results of the Same_block interface, and then output through the Vld_level interface.

[0054] S104, update the current operation pointer in the memory cache based on the result of the data operation.

[0055] Optionally, the result of the data operation updates the current operation pointer in the memory cache, including: obtaining the latest operation pointer based on the result of the data operation; and dynamically updating the current operation pointer with the latest operation pointer.

[0056] Specifically, in this embodiment, the latest operation pointer is obtained based on the result of the data operation, such as the latest block pointer, the latest intra-block pointer, and the latest intra-block horizontal pointer. The latest operation pointer is then dynamically updated to the current operation pointer, so that the current operation pointer always points to the latest data operation location in the memory cache. In this embodiment, the specific location of the current operation pointer is not limited.

[0057] In this embodiment, the storage capacity of the memory storage area is the product of the maximum cache depth (DEPTH) and the maximum cache width (DW), i.e., DEPTH × DW (bits), dynamically allocated according to actual data demand, with no additional redundant storage. Furthermore, the logical resources in this embodiment include three sets of pointer control logic, a block statistics counter, and read / write data splicing / splitting combination logic. Although the overall number of logic gates is slightly increased compared to a traditional fixed-width FIFO, it eliminates the need for additional data alignment and packet synchronization modules, resulting in better overall resource utilization.

[0058] This implementation offers significantly improved flexibility, supporting unaligned read and write operations of any number of bytes without requiring additional data processing modules, thus adapting to variable-length data packet scenarios. Packet boundary marking and data synchronization eliminate the risk of synchronization deviation and improve data parsing accuracy. Simplified system design eliminates the need for additional splitting, splicing, alignment, and packet synchronization logic, reducing hardware resource consumption and increasing chip integration. Read and write operations are completed in a single clock cycle, ensuring high timing performance, adapting to high-speed data transmission scenarios, and reducing system latency.

[0059] The technical solution of this invention determines the data operation mode by using the current operation pointer in the memory cache and the data operation information received by the specified operation interface, and performs data operations in the memory cache based on the data operation mode. Thus, based on the pointer in the cache, the data read and write operations are no longer constrained by the fixed data bit width, which can efficiently handle the unaligned read and write of arbitrary byte data and eliminate the waste of storage bandwidth. Since the corresponding data operation is realized by the dynamic change of the pointer in the cache, the complex operations such as splitting, merging and moving data by adding additional hardware resources are avoided, thus saving hardware resources.

[0060] Example 2

[0061] Figure 9 This is a flowchart of another data operation method provided by an embodiment of the present invention. Based on the above embodiment, after updating the current operation pointer in the memory cache according to the result of the data operation, it further includes detecting the data operation result in the memory cache, such as... Figure 9 As shown, the method includes:

[0062] S201 receives data operation information through the designated operation interface of the memory.

[0063] Optionally, data operation information is received through a specified operation interface of the memory, including: receiving data to be written through the write data interface of the memory, receiving the number of bytes of data to be written through the write byte count interface, receiving a write instruction through the write enable interface, and receiving a write block end marker through the write end interface; using the data to be written, the number of bytes of data to be written, the write instruction, and the write block end marker as write-related operation information; receiving a read instruction through the read enable interface of the memory, receiving the number of bytes of data to be read through the read byte count interface; using the read instruction and the number of bytes of data to be read as read-related operation information.

[0064] S202, determine the current operation pointer in the memory cache, and determine the data operation mode based on the current operation pointer and data operation information.

[0065] Optionally, the data operation mode is determined based on the current operation pointer and data operation information, including: obtaining the maximum width of the cache line and the result of adding the number of bytes of the horizontal pointer in the current block to the number of bytes of the specified data, wherein the specified data includes data to be written or data to be read; determining whether the sum is greater than the maximum width, if so, the data operation mode is determined to be a cross-cache line operation mode, otherwise, the data operation mode is determined to be a non-cross-cache line operation mode; wherein, the cross-cache line operation mode includes a cross-cache line write operation mode or a cross-cache line read operation mode, and the non-cross-cache line operation mode includes a non-cross-cache line write operation mode or a non-cross-cache line read operation mode.

[0066] S203, starting from the current operation pointer, performs data operations in the memory cache according to the data operation mode.

[0067] Optionally, data operations are performed in the memory cache area with reference to the data operation mode, starting from the current operation pointer. This includes: determining the latest write block pointer based on the content of the write end marker, wherein the latest write block pointer is the same as the current write block pointer or is the current write block pointer plus 1; when the data operation mode is a non-cache line write operation mode, determining that the latest intra-block write pointer is the same as the current intra-block write pointer, writing the data to be written to the free space of the current cache line indicated by the current intra-block write pointer as the starting point, and taking the starting point of the remaining free space of the current cache line after writing the data as the latest intra-block write pointer; when the data operation mode is a cross-cache line write operation mode, determining that the latest intra-block write pointer is the current intra-block write pointer plus 1, filling the current cache line indicated by the current intra-block write pointer with the first part of the data to be written as the starting point, writing the second part of the data to be written from the starting point of the free space of the next cache line indicated by the latest intra-block write pointer, and taking the starting point of the remaining space of the next cache line as the latest intra-block write pointer.

[0068] Optionally, data operations are performed in the memory cache area with reference to the data operation mode, starting from the current operation pointer. This includes: when the data operation mode is a non-cross-cache-line read operation mode, determining that the latest intra-block read pointer is the same as the current intra-block read pointer, reading the specified number of bytes of data from the current cache line indicated by the current intra-block read pointer, and using the current intra-block read horizontal pointer as the starting point, and taking the starting point of the remaining data in the current cache after the data reading as the latest intra-block read horizontal pointer; when the data operation mode is a cross-cache-line read operation mode, determining that the latest intra-block read pointer is the current intra-block read pointer plus 1, reading all the remaining data in the current cache line indicated by the current intra-block read pointer as the starting point, reading data from the starting point of the next cache line indicated by the latest intra-block read pointer according to the number of bytes of remaining data to be read, and taking the starting point of the remaining data in the next cache line as the latest intra-block read horizontal pointer; when it is determined that the data in the data block pointed to by the current read block pointer has been read completely, a read end mark is generated, and the current read block pointer is incremented by 1 according to the read end mark as the latest read block pointer.

[0069] Optionally, after performing data operations in the memory cache area with reference to the data operation mode starting from the current operation pointer, the method further includes: when it is determined that the data to be written has been written in the memory cache area, obtaining the number of free bytes in each block of the memory cache area; storing the number of free bytes in the block statistics counter, so that the block statistics counter outputs the number of free bytes through the memory's free byte count interface.

[0070] S204, update the current operation pointer in the memory cache based on the result of the data operation.

[0071] Optionally, the result of the data operation updates the current operation pointer in the memory cache, including: obtaining the latest operation pointer based on the result of the data operation; and dynamically updating the current operation pointer with the latest operation pointer.

[0072] S205 detects the results of data operations in the memory cache.

[0073] Specifically, in this embodiment, after obtaining the data operation results from the memory cache, the data operation results are also checked. This involves checking whether the data was correctly written to the memory cache according to the write operation instruction, or whether the data was read out according to the read operation instruction. For example, when data to be written is obtained through the Wr_data interface, and the number of bytes to be written is 100 according to the Wr_byte_num interface, after the data is written to the specified data block in the memory cache, but according to the block counter, the number of free bytes in the corresponding data block only decreases by 90, meaning that theoretically, writing 100 bytes should reduce the number of free bytes by 100, the current 90 indicates that 10 bytes of data were missed. The cause of this situation could be a link interruption or a fault in the chip's cache. This embodiment does not limit the specific cause of the fault. Of course, this embodiment only illustrates the write operation results; the detection method for read operation results is largely the same and will not be elaborated upon here.

[0074] It should be noted that when an abnormal data operation is detected, an alarm will be generated and displayed as an image on the front-end interface. This will help remind users to promptly inspect and maintain the chip, thereby improving the efficiency and accuracy of data operations.

[0075] The technical solution of this invention determines the data operation mode by using the current operation pointer in the memory cache and the data operation information received by the specified operation interface, and performs data operations in the memory cache based on the data operation mode. Thus, based on the pointer in the cache, the data read and write operations are no longer constrained by the fixed data bit width, which can efficiently handle the unaligned read and write of arbitrary byte data and eliminate the waste of storage bandwidth. Since the corresponding data operation is realized by the dynamic change of the pointer in the cache, the complex operations such as splitting, merging and moving data by adding additional hardware resources are avoided, thus saving hardware resources.

[0076] Example 3

[0077] Figure 10 This is a schematic diagram of a data manipulation device provided in an embodiment of the present invention. Figure 10 As shown, the device includes: a data operation information receiving module 310, a data operation mode determining module 320, a data operation mode determining module 330, and an updating module 340.

[0078] The data operation information receiving module 310 is used to receive data operation information through a specified operation interface of the memory, wherein the data operation information includes read-related operation information or write-related operation information.

[0079] The data operation mode determination module 320 is used to determine the current operation pointer in the memory cache and determine the data operation mode based on the current operation pointer and data operation information. The operation pointer includes a block pointer, an intra-block pointer, and an intra-block horizontal pointer. The data operation mode includes an operation mode across cache lines or an operation mode without crossing cache lines.

[0080] The data operation module 330 is used to perform data operations in the memory cache area with reference to the data operation mode, starting from the current operation pointer;

[0081] The update module 340 is used to update the current operation pointer in the memory cache based on the result of the data operation.

[0082] Optionally, the data operation information receiving module 310 is used to receive the data to be written through the write data interface of the memory, receive the number of bytes of the data to be written through the write byte count interface, receive the write instruction through the write enable interface, and receive the write block end marker through the write end interface.

[0083] The data to be written, the number of bytes of data to be written, the write instruction, and the end marker of the write block are used as write-related operation information;

[0084] The read command is received through the memory read enable interface, and the number of bytes of data to be read is received through the read byte count interface.

[0085] The read instruction and the number of bytes of data to be read are used as read-related operation information.

[0086] Optionally, the data operation mode determination module 320 is used to obtain the maximum width of the cache line and the result of adding the number of bytes of the horizontal pointer in the current block to the specified data, wherein the specified data includes data to be written or data to be read;

[0087] Determine if the sum is greater than the maximum width. If it is, determine that the data operation mode is the cross-cache line operation mode; otherwise, determine that the data operation mode is the non-cross-cache line operation mode.

[0088] Among them, cross-cache line operation mode includes cross-cache line write operation mode or cross-cache line read operation mode, and non-cross-cache line operation mode includes non-cross-cache line write operation mode or non-cross-cache line read operation mode.

[0089] Optionally, the data operation module 330 is used to determine the latest write block pointer based on the content of the write end marker, wherein the latest write block pointer is the same as the current write block pointer or is the current write block pointer plus 1;

[0090] When the data operation mode is a write operation mode that does not cross cache lines, it is determined that the latest intra-block write pointer is the same as the current intra-block write pointer. The data to be written is written to the free interval of the current cache line indicated by the current intra-block write pointer, and the starting point of the remaining free interval of the current cache line after writing the data is taken as the latest intra-block write pointer.

[0091] When the data operation mode is cross-cache line write operation mode, the latest intra-block write pointer is determined to be the current intra-block write pointer plus 1. Starting from the current intra-block write horizontal pointer, the first part of the data to be written is filled in the current cache line indicated by the current intra-block write pointer. The second part of the data to be written is written from the start of the free space of the next cache line indicated by the latest intra-block write pointer, and the start of the remaining space space of the next cache line is used as the latest intra-block write horizontal pointer.

[0092] Optionally, the device also includes a free byte count output module, used to obtain the number of free bytes in each block of the memory cache after determining that the data to be written has been written in the memory cache;

[0093] The number of free bytes is stored in the block statistics counter so that the block statistics counter can output the number of free bytes through the memory's free byte count interface.

[0094] Optionally, the data operation module 330 is used to determine that the latest intra-block read pointer is the same as the current intra-block read pointer when the data operation mode is the non-cross-cache line read operation mode, read the specified number of bytes of data from the current cache line indicated by the current intra-block read pointer as the starting point, and take the starting point of the remaining data in the current cache after the data is read as the latest intra-block read pointer.

[0095] When the data operation mode is cross-cache line read operation mode, the latest intra-block read pointer is determined to be the current intra-block read pointer plus 1. Starting from the current intra-block read horizontal pointer, all the remaining data in the current cache line indicated by the current intra-block read pointer is read. Based on the number of bytes of remaining data to be read, the data is read from the starting point of the next cache line indicated by the latest intra-block read pointer, and the starting point of the remaining data in the next cache line is used as the latest intra-block read horizontal pointer.

[0096] Once it is determined that the data in the data block pointed to by the current read block pointer has been read completely, a read end marker is generated, and the current read block pointer is incremented by 1 based on the read end marker to become the latest read block pointer.

[0097] Optionally, update module 340 is used to obtain the latest operation pointer based on the result of data operation;

[0098] The latest operation pointer is dynamically updated to the current operation pointer.

[0099] The data manipulation device provided in this embodiment of the invention can execute a data manipulation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0100] Example 4

[0101] Figure 4 A schematic diagram of an electronic device 11 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0102] The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0103] like Figure 11 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0104] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other electronic devices through computer networks such as the Internet and / or various telecommunications networks.

[0105] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data manipulation methods.

[0106] That is, data operation information is received through the designated operation interface of the memory, wherein the data operation information includes read-related operation information or write-related operation information;

[0107] Determine the current operation pointer in the memory cache, and determine the data operation mode based on the current operation pointer and data operation information. The operation pointer includes block pointer, intra-block pointer, and intra-block horizontal pointer, and the data operation mode includes cross-cache line operation mode or non-cross-cache line operation mode.

[0108] Starting from the current operation pointer, data operations are performed in the memory cache based on the data operation mode.

[0109] The current operation pointer in the memory cache is updated based on the result of the data operation.

[0110] In some embodiments, the data manipulation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data manipulation method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the data manipulation method by any other suitable means (e.g., by means of firmware).

[0111] Various embodiments of the apparatuses and techniques described above herein can be implemented in digital electronic circuit devices, integrated circuit devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), device-on-a-chip (SoC) devices, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable device including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage device, at least one input device, and at least one output device, and transmitting data and instructions to the storage device, the at least one input device, and the at least one output device.

[0112] Computer programs used to implement the data operation methods of this invention can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer, or other non-stop data migration device, such that when executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution apparatus, device, or electronic device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage electronics, magnetic storage electronics, or any suitable combination thereof.

[0114] To provide interaction with a user, the apparatus and techniques described herein can be implemented on an electronic device having: a display device (e.g., a touchscreen) for displaying information to the user; and buttons through which the user can provide input to the electronic device. Other types of apparatus can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0115] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for manipulating data, characterized in that, The method includes: Data operation information is received through a specified operation interface of the memory, wherein the data operation information includes read-related operation information or write-related operation information; The current operation pointer in the memory cache is determined, and the data operation mode is determined based on the current operation pointer and the data operation information. The operation pointer includes a block pointer, an intra-block pointer, and an intra-block horizontal pointer. The data operation mode includes a cross-cache line operation mode or a non-cross-cache line operation mode. Starting from the current operation pointer, data operations are performed in the memory cache according to the data operation mode; The current operation pointer in the memory cache is updated based on the result of the data operation.

2. The method according to claim 1, characterized in that, The receiving of data operation information through the designated operation interface of the memory includes: The memory receives data to be written through its write data interface, receives the number of bytes of the data to be written through its write byte count interface, receives a write instruction through its write enable interface, and receives a write block end marker through its write end interface. The data to be written, the number of bytes of the data to be written, the write instruction, and the end marker of the write block are used as the write-related operation information. The read instruction is received through the read enable interface of the memory, and the number of bytes of data to be read is received through the read byte count interface. The read instruction and the number of bytes of the data to be read are used as the read-related operation information.

3. The method according to claim 2, characterized in that, The step of determining the data operation mode based on the current operation pointer and the data operation information includes: Get the maximum width of the cache line and the sum of the number of bytes of the horizontal pointer in the current block and the specified data, wherein the specified data includes data to be written or data to be read; Determine whether the summation result is greater than the maximum width. If so, determine that the data operation mode is the cross-cache line operation mode; otherwise, determine that the data operation mode is the non-cross-cache line operation mode. The cross-cache line operation mode includes a cross-cache line write operation mode or a cross-cache line read operation mode, and the non-cross-cache line operation mode includes a non-cross-cache line write operation mode or a non-cross-cache line read operation mode.

4. The method according to claim 3, characterized in that, The step of performing data operations in the memory cache based on the current operation pointer and referring to the data operation mode includes: The latest write block pointer is determined based on the content of the write end marker, wherein the latest write block pointer is the same as the current write block pointer or is the current write block pointer plus 1; When the data operation mode is a non-cache line write operation mode, it is determined that the latest block write pointer is the same as the current block write pointer. The data to be written is written to the free interval of the current cache line indicated by the current block write pointer, with the current block write horizontal pointer as the starting point. The starting point of the remaining free interval of the current cache line after writing the data is taken as the latest block write horizontal pointer. When the data operation mode is cross-cache line write operation mode, the latest intra-block write pointer is determined to be the current intra-block write pointer plus 1. Starting from the current intra-block write horizontal pointer, the first part of the data to be written is filled in the current cache line indicated by the current intra-block write pointer. The second part of the data to be written is written from the start of the free interval of the next cache line indicated by the latest intra-block write pointer, and the start of the remaining space interval of the next cache line is used as the latest intra-block write horizontal pointer.

5. The method according to claim 4, characterized in that, After performing data operations in the memory cache based on the current operation pointer and the data operation mode, the method further includes: Once it is determined that the data to be written has been written to the memory cache, the number of free bytes in each block of the memory cache is obtained; The number of free bytes is stored in a block statistics counter, so that the block statistics counter outputs the number of free bytes through the free byte count interface of the memory.

6. The method according to claim 3, characterized in that, The step of performing data operations in the memory cache based on the current operation pointer and referring to the data operation mode includes: When the data operation mode is a non-cross-cache line read operation mode, it is determined that the latest intra-block read pointer is the same as the current intra-block read pointer. The specified number of bytes of data are read from the current cache line indicated by the current intra-block read pointer, starting from the current intra-block read pointer. The starting point of the remaining data in the current cache after the data is read is taken as the latest intra-block read pointer. When the data operation mode is cross-cache line read operation mode, the latest intra-block read pointer is determined to be the current intra-block read pointer plus 1. Starting from the current intra-block read horizontal pointer, all the remaining data in the current cache line indicated by the current intra-block read pointer is read. According to the number of bytes of remaining data to be read, the data is read from the starting point of the next cache line indicated by the latest intra-block read pointer, and the starting point of the remaining data in the next cache line is used as the latest intra-block read horizontal pointer. Once it is determined that the data in the data block pointed to by the current read block pointer has been read completely, a read end marker is generated, and the current read block pointer is incremented by 1 according to the read end marker to become the latest read block pointer.

7. The method according to claim 1, characterized in that, The result of the data operation updates the current operation pointer in the memory cache, including: Obtain the latest operation pointer based on the result of the data operation; The latest operation pointer is dynamically updated to the current operation pointer.

8. A data manipulation device, characterized in that, The device includes: A data operation information receiving module is used to receive data operation information through a specified operation interface of the memory, wherein the data operation information includes read-related operation information or write-related operation information; The data operation mode determination module is used to determine the current operation pointer in the memory cache and determine the data operation mode based on the current operation pointer and the data operation information. The operation pointer includes a block pointer, an intra-block pointer, and an intra-block horizontal pointer. The data operation mode includes a cross-cache line operation mode or a non-cross-cache line operation mode. The data operation module is used to perform data operations in the memory cache area with the current operation pointer as the starting point and in accordance with the data operation mode; An update module is used to update the current operation pointer in the memory cache based on the result of the data operation.

9. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-7.

10. A storage medium for computer-executable instructions, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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