Instruction translation method and device, electronic equipment, storage medium and computer program product

Abstract

The invention relates to an instruction translation method and device, electronic equipment, a storage medium and a computer program product. The method comprises the steps of obtaining a to-be-translated source instruction; obtaining a to-be-translated intermediate instruction sequence from the to-be-translated source instruction; an instruction related to an intermediate result in the intermediate instruction sequence is simplified, a simplified intermediate instruction sequence is obtained, and the intermediate result is an intermediate process calculation result generated in the instruction calculation process and except a final calculation result; and translating the simplified intermediate instruction sequence to obtain a target instruction corresponding to the semantics of the simplified intermediate instruction sequence.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to instruction translation methods, apparatus, electronic devices, storage media, and computer program products. Background Technology

[0002] Binary translation technology can convert binary code from one instruction set architecture to another, enabling binary applications from the source platform to run directly on the target platform without recompiling the source code. For example, the source instructions may belong to the Complex Instruction Set Computing (CISC) architecture, while the target instructions may belong to the Reduced Instruction Set Computer (RISC) architecture.

[0003] It's important to note that different instruction sets differ significantly. Therefore, translating instructions from one instruction set to another requires additional instructions to compensate for these differences. For instance, a single CISC instruction often requires a combination of multiple RISC instructions to complete the translation. For example, for 32-bit integers, additional high 32-bit sign extension and high 32-bit clearing instructions are needed to process the high 32-bit register contents, ensuring that the translated 32-bit integer result in the RISC instruction set matches the register state in the CISC instruction set. Simultaneously, the 32-bit integer passed to the RISC instruction set must conform to its format conventions; for example, the high 32 bits must undergo sign extension.

[0004] The additional instructions used to bridge the differences between the CISC and RISC instruction sets are repeatedly used during the translation process. As a result, most of the instructions used to generate intermediate processes accumulate into redundant instructions, causing instruction bloat. This reduces the translation and execution efficiency of CISC instruction set binary applications. Summary of the Invention

[0005] This disclosure provides instruction translation methods, apparatus, electronic devices, storage media, and computer program products to at least solve the problem in the aforementioned related technologies that most of the instructions used in the intermediate generation process accumulate into redundant instructions, causing instruction bloat and reducing the translation and execution efficiency of CISC instruction set binary applications.

[0006] According to a first aspect of the present disclosure, an instruction translation method is provided, comprising: obtaining a source instruction to be translated; obtaining an intermediate instruction sequence to be translated from the source instruction; simplifying instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence, wherein the intermediate results are intermediate process calculation results generated during instruction calculation and other than the final calculation result; translating the simplified intermediate instruction sequence to obtain a target instruction semantically corresponding to the simplified intermediate instruction sequence.

[0007] According to an example embodiment of this disclosure, obtaining the intermediate instruction sequence to be translated from the source instruction to be translated includes: parsing the source instruction to obtain intermediate instructions; performing forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence, wherein the forward analysis is used to obtain the upstream intermediate computation instructions on which the intermediate instructions depend, and the subsequent analysis is used to obtain the downstream intermediate computation instructions that use the computation results of the intermediate instructions.

[0008] According to an example embodiment of this disclosure, the step of performing forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: if the type of the intermediate instruction is a 32-bit def class operation instruction, determining whether the def target data of the use node of the 32-bit def class operation instruction is 32 bits; if the def target data of the use node is 32 bits, adding the def target data of the use node to the intermediate instruction sequence; otherwise, prohibiting the addition of the def target data of the use node to the intermediate instruction sequence.

[0009] According to an example embodiment of this disclosure, the step of performing forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: if the type of the intermediate instruction is a 32-bit use-type operation instruction, determining whether the operation instruction of the def target data of the def node of the 32-bit use-type operation instruction is 32-bit; if the operation instruction of the def target data is 32-bit, adding the operation instruction of the def target data to the intermediate instruction sequence; otherwise, prohibiting the addition of the operation instruction of the def target data to the intermediate instruction sequence.

[0010] According to an example embodiment of this disclosure, before performing forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence, the method further includes: identifying 32-bit integer arithmetic instructions in the intermediate instructions; the step of performing forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: performing forward analysis and / or subsequent analysis on the identified 32-bit integer arithmetic instructions to obtain the intermediate instruction sequence; wherein the 32-bit integer arithmetic instructions are identified by at least one of the following methods: the data width involved in the operation is 4 bytes, the operation result is 4 bytes, and the operation instruction is a 32-bit arithmetic instruction.

[0011] According to an example embodiment of this disclosure, the instruction translation method further includes: setting a tracking constraint, wherein the tracking constraint is used to limit the coverage of instruction simplification; obtaining the intermediate instruction sequence to be translated from the source instruction to be translated includes: obtaining the intermediate instruction sequence to be translated from the source instruction to be translated according to the tracking constraint.

[0012] According to an example embodiment of this disclosure, before obtaining the source instruction to be translated, the method further includes: constructing a target instruction container; deploying a target application and the runtime environment on which the target application depends within the target instruction container; obtaining the source instruction to be translated includes: responding to a user operation, starting and running the target application deployed within the target instruction container; and obtaining instructions generated during the execution of the target application as the source instruction to be translated.

[0013] According to an example embodiment of this disclosure, simplifying the instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence includes: deleting the high-order 0 clearing instruction and / or high-order sign extension instruction of the intermediate result calculated by the 32-bit integer in the intermediate instruction sequence.

[0014] According to an example embodiment of this disclosure, the step of simplifying the instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence includes: replacing the 32-bit integer instructions that generate intermediate calculation results in the intermediate instruction sequence with intermediate instructions that do not require clearing the high-order bits to 0 or intermediate instructions that do not require sign extension of the high-order bits.

[0015] According to a second aspect of the present disclosure, an instruction translation apparatus is provided, comprising: a source instruction acquisition module configured to acquire a source instruction to be translated; an intermediate instruction sequence acquisition module configured to acquire an intermediate instruction sequence to be translated from the source instruction; a simplification module configured to simplify instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence, wherein the intermediate results are intermediate process calculation results generated during instruction calculation, excluding the final calculation result; and a translation module configured to translate the simplified intermediate instruction sequence to obtain a target instruction semantically corresponding to the simplified intermediate instruction sequence.

[0016] According to an example embodiment of this disclosure, the intermediate instruction sequence acquisition module is configured to: parse the source instruction to obtain intermediate instructions; perform forward analysis and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence, wherein the forward analysis is used to obtain the upstream intermediate computation instructions on which the intermediate instructions depend, and the subsequent analysis is used to obtain the downstream intermediate computation instructions that use the computation results of the intermediate instructions.

[0017] According to an example embodiment of this disclosure, the intermediate instruction sequence acquisition module is configured to: when the type of the intermediate instruction is a 32-bit def class operation instruction, determine whether the def target data of the use node of the 32-bit def class operation instruction is 32 bits; when the def target data of the use node is 32 bits, add the def target data of the use node to the intermediate instruction sequence; otherwise, prohibit adding the def target data of the use node to the intermediate instruction sequence.

[0018] According to an example embodiment of this disclosure, the intermediate instruction sequence acquisition module is configured to: when the type of the intermediate instruction is a 32-bit use-type operation instruction, determine whether the operation instruction of the def target data of the def node of the 32-bit use-type operation instruction is 32-bit; when the operation instruction of the def target data is 32-bit, add the operation instruction of the def target data into the intermediate instruction sequence; otherwise, prohibit adding the operation instruction of the def target data into the intermediate instruction sequence.

[0019] According to an example embodiment of this disclosure, the instruction translation device further includes: an instruction recognition module configured to recognize 32-bit integer arithmetic instructions in the intermediate instructions; and an intermediate instruction sequence acquisition module configured to: perform forward analysis and / or subsequent analysis on the recognized 32-bit integer arithmetic instructions to obtain the intermediate instruction sequence; wherein the 32-bit integer arithmetic instructions are recognized by at least one of the following methods: the data width involved in the operation is 4 bytes, the operation result is 4 bytes, and the operation instruction is a 32-bit arithmetic instruction.

[0020] According to an example embodiment of this disclosure, the instruction translation apparatus further includes: a tracking constraint setting module configured to set tracking constraints, wherein the tracking constraints are used to limit the coverage of instruction simplification; and an intermediate instruction sequence acquisition module configured to obtain an intermediate instruction sequence to be translated from the source instruction to be translated according to the tracking constraints.

[0021] According to an example embodiment of this disclosure, the instruction translation device further includes: a container building module configured to build a target instruction container; a deployment module configured to deploy a target application and the runtime environment on which the target application depends within the target instruction container; and a source instruction acquisition module configured to: in response to a user operation, start and run the target application deployed within the target instruction container; and acquire instructions generated during the execution of the target application as the source instructions to be translated.

[0022] According to an example embodiment of this disclosure, the simplification module is configured to delete the high-order 0 clearing instruction and / or high-order sign extension instruction of the intermediate result of the 32-bit integer calculation in the intermediate instruction sequence.

[0023] According to an example embodiment of this disclosure, the simplification module is configured to replace the 32-bit integer instruction that generates the intermediate calculation result in the intermediate instruction sequence with an intermediate instruction whose high-order bits do not need to be cleared to 0 or an intermediate instruction whose high-order bits do not need to be sign-extended.

[0024] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement an instruction translation method according to the present disclosure.

[0025] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform an instruction translation method according to the present disclosure.

[0026] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the instruction translation method according to the present disclosure.

[0027] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects: In this disclosure, during the translation of source instructions into target instructions, the number of redundant instructions can be reduced by simplifying the instructions involving intermediate results in the intermediate instruction sequence. This reduces the translation code bloat rate, thereby improving the translation and execution efficiency of binary applications and making the binary applications running under the source instruction set under the target instruction set run more smoothly.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0030] Figure 1 This is a schematic diagram illustrating the configuration of a binary application translator according to an exemplary embodiment of the present disclosure; Figure 2 This is a flowchart illustrating an instruction translation method according to an exemplary embodiment of the present disclosure; Figure 3 This is a flowchart illustrating a specific implementation of an instruction translation method according to an exemplary embodiment of the present disclosure; Figure 4 This is a block diagram illustrating an instruction translation apparatus according to an exemplary embodiment of the present disclosure; Figure 5 This is a block diagram illustrating an electronic device according to exemplary embodiments of the present disclosure. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0032] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following examples do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0033] It should be noted that the phrase "at least one of several items" in this disclosure refers to three parallel cases: "any one of the several items", "a combination of any number of the several items", and "all of the several items". For example, "including at least one of A and B" includes the following three parallel cases: (1) including A; (2) including B; (3) including A and B. Another example is "performing at least one of step one and step two", which means the following three parallel cases: (1) performing step one; (2) performing step two; (3) performing both step one and step two.

[0034] As mentioned earlier, there are significant differences between different instruction sets. Therefore, when translating instructions from one instruction set to another, a certain number of additional instructions are needed to compensate for these differences. For example, in the case of 32-bit integers, the main difference between instruction sets lies in the 32-bit data format. For instance, the memory states of 32-bit integers in the RISC and CISC instruction sets are the same, but their register states differ. For example, in the CISC instruction set, a 32-bit integer has the lower 32 bits valid and the higher 32 bits 0 in its register state; while in the RISC instruction set, a 32-bit integer has the lower 32 bits valid and the higher 32 bits are sign-extended, meaning the higher 32 bits are semantically unclean. For example, when the lower 32 bits are greater than 0, the higher 32 bits are all 0s; when the lower 32 bits are less than 0, the higher 32 bits are all 1s. A comparison of the 32-bit data formats between the RISC and CISC instruction sets is shown in Table 1.

[0035] Table 1 Comparison of 32-bit Integer Instruction Sets between CISC and RISC Instruction Sets The additional instructions mentioned above, used to bridge the differences between the CISC and RISC instruction sets, are repeatedly used during translation. This leads to a buildup of redundant instructions, causing instruction bloat and reducing the translation efficiency of CISC binary applications. For example, if the high 32 bits of the previous addition result are cleared to 0, but a sign extension is needed before performing a subtraction operation on the same result, it's equivalent to directly using the result of the previous addition instruction for subtraction. This means that repeatedly clearing the high 32 bits and performing sign extension on intermediate results are redundant instructions.

[0036] To address the aforementioned problems in related technologies, this disclosure provides instruction translation methods, apparatus, electronic devices, storage media, and computer program products. Figure 1 This is a schematic diagram illustrating the configuration of a binary application translator according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 The translator can include: a CISC application loading module, a CISC instruction parsing module, an intermediate instruction (IR) optimization module, an IR instruction translation module, and a RISC instruction scheduling and execution module. These modules can complete the entire workflow of CISC program loading, instruction parsing, instruction optimization, instruction translation, and instruction execution.

[0037] The CISC application loading module analyzes and loads the CISC platform binary application, building a program translation and execution environment. The CISC instruction parsing module decodes the CISC instruction blocks in the loaded binary application to generate intermediate instructions. The IR instruction optimization module performs semantic analysis on the generated intermediate instructions and optimizes them in conjunction with RISC instruction characteristics. The IR instruction translation module translates the optimized intermediate instructions to generate instructions corresponding to the RISC platform. The RISC instruction scheduling and execution module schedules and executes the translated RISC instruction blocks, and after execution, continues to translate new CISC instruction blocks until the application exits.

[0038] Figure 2 This is a flowchart illustrating an instruction translation method according to an exemplary embodiment of the present disclosure.

[0039] Reference Figure 2 In step 201, the source instructions to be translated can be obtained. For example, in response to a user action, a target application can be started and run. Then, the instructions generated during the execution of the target application can be used as the source instructions to be translated.

[0040] In step 202, the intermediate instruction sequence to be translated, i.e. the IR instruction sequence to be translated, can be obtained from the source instruction to be translated.

[0041] According to exemplary embodiments of this disclosure, source instructions can be parsed to obtain IR instructions. For example, after parsing a CISC instruction code block, the translator can generate a corresponding IR instruction code block, and the IR instruction code block can be managed using IR nodes. For instance, information for each IR instruction can be stored in an IR node data structure, and the IR instruction code block can begin with a Begin node and end with an End node. Scanning can begin from the Begin node and continue until the End node.

[0042] Next, forward and / or backward analysis can be performed on the IR instructions to obtain the IR instruction sequence. Forward analysis can be used to obtain the upstream intermediate computation instructions that the IR instructions depend on; backward analysis can be used to obtain the downstream intermediate computation instructions that use the computation results of the IR instructions. That is, semantic analysis can be performed on 32-bit instructions to determine the features of the IR instruction sequence to be optimized. It should be noted that the essence of semantic analysis is to start from the instructions of interest, reconstruct the context of the instructions through forward and / or backward analysis, thereby obtaining a semantically complete IR instruction sequence, and then optimizing the IR instruction sequence as a whole.

[0043] Furthermore, a forward instruction can refer to an upstream intermediate computation instruction that the current instruction depends on. For example, if the current instruction is A+B=C, then the computation instructions used to calculate A and B are the forward instructions of the current instruction. A successor instruction can refer to a downstream intermediate computation instruction that uses the result of the current instruction. For example, if the current instruction is A+B=C, since the instruction C+D=E uses the result C of the current instruction, the instruction C+D=E is the successor instruction of the current instruction A+B=C.

[0044] According to exemplary embodiments of this disclosure, a target instruction container can be constructed before obtaining the source instructions to be translated, i.e., before starting and running the target application in response to a user operation. For example, a RISC container base image carrying C, C++ shared libraries, etc., can be constructed. The target application and its dependent runtime environment (i.e., rootfs) can then be deployed within the target instruction container. Next, in response to a user operation, the target application deployed within the target instruction container can be started and run. Then, instructions generated during the execution of the target application can be obtained as the aforementioned source instructions to be translated.

[0045] Thus, to facilitate the translation and execution of CISC applications, this disclosure uses a containerized deployment approach to build a RISC container base image carrying C and C++ shared libraries, and deploys the translator, CISC program, and the runtime environment of the CISC program within the RISC container, thereby enabling the portable and flexible execution of CISC applications in a container environment.

[0046] According to exemplary embodiments of this disclosure, 32-bit integer arithmetic instructions in the IR instructions can also be identified. Then, forward analysis and / or follow-up analysis can be performed on the identified 32-bit integer arithmetic instructions to obtain the IR instruction sequence. It should be noted that 32-bit integer arithmetic instructions can be identified by at least one of the following methods: the data width involved in the operation is 4 bytes, the operation result is 4 bytes, and the operation instruction is a 32-bit arithmetic instruction.

[0047] For example, during IR node scanning, the instruction information within the node can be analyzed, identifying it based on information such as whether the width of the data involved in the operation is 4 bytes, whether the operation result is 4 bytes, and whether the operation instruction is a 32-bit operation instruction. Furthermore, instructions can include two types: the first is the `def` type 32-bit integer operation instruction, which refers to an instruction in a Static Single Assignment (SSA) node that uses a 32-bit integer operation instruction and generates 32-bit target data conforming to CISC semantics; the second is the `use` type 32-bit integer reference instruction, which refers to an SSA node that uses a non-32-bit integer operation instruction (e.g., 64-bit integer operation), but the referenced parameter is generated by a 32-bit integer instruction. In general, the goal is to find any SSA node whose operation elements are 32-bit, including but not limited to: operation results, one or more operation parameters, and operation instructions.

[0048] It should be noted that the CISC to RISC 32-bit integer arithmetic binary translation optimization method provided in this disclosure targets IR instructions that mainly fall into two categories: def and use.

[0049] `def` instructions refer to instruction nodes that produce 32-bit operation results based on 32-bit arithmetic instructions. For example, in the instruction A+B=C, C is the `def` node (i.e., the result node). `def` 32-bit integer arithmetic instructions can include, but are not limited to, addition, subtraction, multiplication, division, modulo, memory read, and memory write instructions that output 32-bit integers. Furthermore, `def` instructions are also used to indicate instructions that define or assign values ​​to variables. For example, in the instruction c<- c + b, the `def` set is {c}, indicating that variable c is modified (i.e., defined) in this instruction. `def` instructions mark the generation of variable values ​​and are the starting point for data flow analysis.

[0050] The `use` class of instructions refers to instruction nodes that include 32-bit operation parameters. For example, in the instruction A+B=C, A and B are `use` nodes (parameter nodes). It's important to note that the operation instructions can be 32-bit or not, but at least one parameter must be 32-bit. That is, `use` class 32-bit integer operation instructions can include not only those included in the `def` class, but also all operation instructions that accept 32-bit integers as input, such as 64-bit integer operation instructions that take 32-bit integers as parameters. `use` class instructions are also used to indicate that variables are read or referenced. For example, in `c<- c + b`, the `use` set is `{c, b}`, indicating that variables `c` and `b` are used in this instruction. `use` instructions represent the consumption of variable values ​​and are used to establish data dependencies.

[0051] According to an exemplary embodiment of this disclosure, when the IR instruction is a 32-bit def-type operation instruction, it can be determined whether the def target data of the use node of the 32-bit def-type operation instruction is 32 bits. That is, for a 32-bit def-type operation instruction, the SSA node information of its use node can be extracted to determine whether the def target data of its use node is 32 bits. If it is determined that the def target data of the use node is 32 bits, the def target data of the use node can be added to the IR instruction sequence; otherwise, that is, if it is determined that the def target data of the use node is not 32 bits, it can be prevented from adding the def target data of the use node to the IR instruction sequence.

[0052] According to an exemplary embodiment of this disclosure, when the IR instruction is a 32-bit use-type operation instruction, it can be determined whether the operation instruction for the target data of the def node of the 32-bit use-type operation instruction is 32-bit. That is, for a 32-bit use-type operation instruction, the SSA node information of its def node can be extracted to determine whether the operation instruction for the target data of the def node is 32-bit. If the operation instruction for the target data is 32-bit, the operation instruction for the target data can be added to the IR instruction sequence; otherwise, that is, if the operation instruction for the target data is not 32-bit, the addition of the operation instruction for the target data to the IR instruction sequence can be prohibited.

[0053] It should be noted that the above forward and successor analysis process can be a recursive loop. By extending and iterating forward and backward through def and use instructions, various combinations of IR instruction sequences can be generated. For example, performing consecutive 32-bit addition and subtraction and then writing the result to memory; or, the two parameters of a 64-bit integer operation are generated from 32-bit addition; or, the two parameters of a 64-bit integer operation are generated from 32-bit memory reads, and so on.

[0054] Next, redundancy analysis can be performed on the constructed IR instruction sequence. According to an exemplary embodiment of this disclosure, a data flow propagation graph can be constructed, and based on the constructed data flow propagation graph, it can be determined whether optimization can be performed for a specific instruction.

[0055] For example, based on the aforementioned semantic analysis method, successor propagation analysis can be performed on def-type operation instructions in the IR instruction sequence to extract the use count and use instruction scenario of the def-type instruction target data; alternatively, forward and successor propagation analysis can be performed on use-type operation instructions in the IR instruction sequence to extract the def target data, reference count, and other corresponding reference scenarios of the use-type instructions. Then, the forward / successor analysis results can be used to determine whether the corresponding instructions can be optimized.

[0056] For example, suppose the target data of a def instruction is immediately stored in a register, indicating that this target data may be later restored from the register. This means that the stored target data must be completely consistent with the CISC semantics. In this case, the target data of the def instruction cannot be optimized. This is because such optimization is unsafe and may affect the correctness of program execution. Alternatively, if the target data of a def instruction is immediately referenced by a 32-bit addition instruction, it means that the target data of this def instruction can be optimized, i.e., the high-order bits of the result do not need to be cleared to 0, and the addition does not need to be sign-extended. This is because such optimization is safe and will not affect the correctness of program execution.

[0057] According to exemplary embodiments of this disclosure, a tracking constraint can also be set, wherein the tracking constraint can be used to limit the coverage of instruction simplification. Then, the IR instruction sequence to be translated can be obtained from the source instruction to be translated according to the tracking constraint. Furthermore, the tracking constraint may include, but is not limited to: tracking depth, the number of scan rounds of the instruction, and the number of features incorporated into the optimized IR instruction sequence.

[0058] For example, the tracing depth of forward analysis and / or subsequent analysis can be set, whereby the tracing depth can be used to characterize the number of instructions being analyzed, and the greater the tracing depth, the more instructions are analyzed. Then, forward analysis and / or subsequent analysis can be performed on the IR instructions according to the set tracing depth of forward analysis and / or subsequent analysis to obtain the IR instruction sequence.

[0059] It should be noted that optimization incurs overhead, primarily manifested in the repeated scanning of IR instructions, the recursive data flow tracing of preceding and succeeding instructions, and the construction of IR instruction sequence features. Therefore, in this disclosure, the number of IR instruction scanning rounds, the tracing depth of preceding and succeeding instructions, and the number of IR instruction sequence features included in the optimization can be appropriately controlled. This can effectively accelerate instruction translation speed and improve translation efficiency.

[0060] In step 203, instructions involving intermediate results in the IR instruction sequence can be simplified to obtain a simplified IR instruction sequence. The intermediate results can be intermediate calculation results generated during instruction calculation, other than the final calculation result.

[0061] It's important to note that when simplifying source instructions, it's necessary to establish a correspondence between the entire IR instruction sequence and the original CISC instructions. This means understanding the semantics of IR instructions is akin to the reverse engineering of generating IR instructions from CISC instructions. Only with this level of semantic understanding can the original CISC semantic requirements be fully grasped, allowing for targeted optimization. For example, which instructions are truly redundant and can be deleted; which instructions, while seemingly redundant, must be retained. For instance, the instruction to clear the high-order bits of a 32-bit integer calculation is one that cannot be deleted. Alternatively, which IR instruction sequences can be replaced with a simpler, alternative form; and which cannot. For example, the 32-bit integer instruction that produces the final calculation result cannot be replaced with an IR instruction that doesn't require clearing the high-order bits.

[0062] According to an exemplary embodiment of this disclosure, the high-order bit clearing instruction and / or high-order sign extension instruction of the intermediate result of 32-bit integer calculation can be removed from the IR instruction sequence. Thus, by removing the high-order bit clearing instruction and / or high-order sign extension instruction of the intermediate result of 32-bit integer calculation, the redundancy of the IR instruction sequence can be reduced, thereby accelerating instruction translation speed and improving translation efficiency.

[0063] According to exemplary embodiments of this disclosure, the 32-bit integer instruction that generates intermediate calculation results in the IR instruction sequence can be replaced with an IR instruction that does not require clearing the high-order bits to 0 or an IR instruction that does not require sign extension of the high-order bits. In this way, by replacing the 32-bit integer instruction that generates intermediate calculation results in the IR instruction sequence with an IR instruction that does not require clearing the high-order bits to 0 or an IR instruction that does not require sign extension of the high-order bits, the redundancy of the IR instruction sequence can be reduced, thereby accelerating instruction translation speed and improving translation efficiency.

[0064] Next, further optimization can be performed on the semantically optimized IR instructions. The optimized IR instructions must maintain the same computational semantics as the original IR instructions, but their input / output data formats must differ. For example, the construction logic of the original 32-bit integer addition instruction could be: sign extension of the first parameter, sign extension of the second parameter, 32-bit addition operation, and clearing the high-order bits of the result to 0. However, the construction logic of the optimized new IR instructions can contain only the 32-bit addition operation, omitting the sign extension and high-order bit clearing instructions. Thus, after semantic and construction optimization, the newly generated IR instruction sequence maintains the same input and output as the original CISC instruction sequence, but the intermediate computation results may differ due to IR instruction optimization. In other words, the semantics of the new IR instruction sequence must be consistent with the original IR instruction sequence, but the intermediate processes can differ.

[0065] In step 204, the simplified IR instruction sequence can be translated to obtain the target instruction corresponding to the semantics of the simplified IR instruction sequence. For example, the IR instructions obtained after semantic optimization and construction optimization can be translated one by one to obtain the RISC target instruction after redundancy removal.

[0066] After translating the target instructions, they can be executed. It should be noted that although the input and output of the optimized IR instruction sequence are consistent with the unoptimized IR instruction sequence, intermediate results may differ, potentially leading to execution errors in complex application scenarios. Therefore, this disclosure also allows for testing of the translated RISC instructions. Furthermore, if errors occur during testing, the IR instructions can be adjusted based on the location and cause of the error until the test is error-free, thus ensuring smooth instruction translation.

[0067] Figure 3 This is a flowchart illustrating a specific implementation of an instruction translation method according to an exemplary embodiment of the present disclosure.

[0068] Reference Figure 3 In step 301, in response to a user action, the target application can be launched and run.

[0069] In step 302, source instructions generated during the execution of the target application can be parsed into IR instructions. For example, after parsing the CISC instruction code block, the translator can generate the corresponding IR instruction code block, and the IR instruction code block can be managed using IR nodes.

[0070] In step 303, the IR instruction code block can be scanned to identify 32-bit integer arithmetic instructions.

[0071] For example, as mentioned above, during the IR node scanning process, the instruction information in the node can be analyzed, and identification can be performed based on information such as whether the width of the data involved in the operation is 4 bytes, whether the operation result is 4 bytes, and whether the operation instruction is a 32-bit operation instruction.

[0072] In step 304, semantic analysis can be performed on the 32-bit instructions to determine the IR instruction sequence.

[0073] It should be noted that the essence of semantic analysis is to start from the instruction of interest, reconstruct the context of the instruction through forward and / or subsequent analysis, thereby obtaining a semantically complete IR instruction sequence, and then optimizing the IR instruction sequence as a whole.

[0074] In step 305, it is determined whether a specific instruction in the IR instruction sequence can be optimized.

[0075] For example, a data flow propagation graph can be constructed, and the constructed data flow propagation graph can be used to determine whether optimization can be performed for specific instructions.

[0076] In step 306, if it is determined that a certain instruction can be optimized, semantic optimization and construction optimization are performed on the instruction to obtain the optimized and reconstructed IR instruction.

[0077] In step 307, the optimized and reconstructed IR instructions are translated to obtain RISC instructions.

[0078] In step 308, the translated RISC instructions are tested, and the IR instructions are corrected based on the test results.

[0079] In step 309, the correct RISC instructions obtained after testing and correction are executed.

[0080] Table 2 is a comparison diagram of the optimized instructions obtained using the instruction translation method provided in this disclosure and the original IR instructions before optimization. Referring to Table 2, the original IR instruction sequence to be optimized can be: Sub i32 + Sbfei64 + S4Add i64; the optimized IR instruction sequence can be: Sub i32 + S4Add i64. Compared with the original IR instructions, the IR instructions obtained after semantic optimization and construction optimization have reduced 9 redundant instructions, effectively reducing redundancy.

[0081]

[0082] Table 2 Examples of IR instruction sequence optimization Figure 4 This is a block diagram illustrating an instruction translation apparatus 400 according to an exemplary embodiment of the present disclosure.

[0083] Reference Figure 4 The instruction translation device 400 may include a source instruction acquisition module 401, an intermediate instruction sequence acquisition module 402, a simplification module 403, and a translation module 404.

[0084] The source instruction acquisition module 401 can acquire the source instructions to be translated.

[0085] The intermediate instruction sequence acquisition module 402 can obtain the intermediate instruction sequence to be translated from the source instruction to be translated.

[0086] According to an exemplary embodiment of this disclosure, the intermediate instruction sequence acquisition module 402 can parse the source instruction to obtain IR instructions. Next, the intermediate instruction sequence acquisition module 402 can perform forward analysis and / or subsequent analysis on the IR instructions to obtain an IR instruction sequence. Forward analysis can be used to obtain the upstream intermediate computation instructions on which the IR instructions depend; subsequent analysis can be used to obtain the downstream intermediate computation instructions that use the computation results of the IR instructions.

[0087] According to an exemplary embodiment of this disclosure, the instruction translation apparatus 400 may further include a container building module and a deployment module.

[0088] The container building module can construct a target instruction container. Then, the deployment module can deploy the target application and its dependent runtime environment within the target instruction container. Next, in response to user input, the source instruction acquisition module 401 can start and run the target application deployed within the target instruction container. Then, the source instruction acquisition module 401 can acquire instructions generated during the execution of the target application as the source instructions to be translated.

[0089] According to an exemplary embodiment of this disclosure, the instruction translation apparatus 400 may further include an instruction recognition module.

[0090] The instruction recognition module can identify 32-bit integer arithmetic instructions in the IR instructions. Then, the intermediate instruction sequence acquisition module 402 can perform forward and / or subsequent analysis on the identified 32-bit integer arithmetic instructions to obtain the IR instruction sequence. It should be noted that 32-bit integer arithmetic instructions can be identified by at least one of the following methods: the data width involved in the operation is 4 bytes, the operation result is 4 bytes, and the operation instruction is a 32-bit arithmetic instruction.

[0091] According to an exemplary embodiment of this disclosure, when the IR instruction is a 32-bit def-type operation instruction, the intermediate instruction sequence acquisition module 402 can determine whether the def target data of the use node of the 32-bit def-type operation instruction is 32 bits. That is, for a 32-bit def-type operation instruction, the intermediate instruction sequence acquisition module 402 can extract the SSA node information of its use node to determine whether the def target data of its use node is 32 bits. If it is determined that the def target data of the use node is 32 bits, the intermediate instruction sequence acquisition module 402 can add the def target data of the use node to the IR instruction sequence; otherwise, that is, if it is determined that the def target data of the use node is not 32 bits, the intermediate instruction sequence acquisition module 402 can prevent the addition of the def target data of the use node to the IR instruction sequence.

[0092] According to an exemplary embodiment of this disclosure, when the IR instruction is a 32-bit use-type operation instruction, the intermediate instruction sequence acquisition module 402 can determine whether the operation instruction of the def target data of the def node of the 32-bit use-type operation instruction is 32-bit. That is, for a 32-bit use-type operation instruction, the intermediate instruction sequence acquisition module 402 can extract the SSA node information of its def node to determine whether the operation instruction of the def target data of the def node is 32-bit. If the operation instruction of the def target data is 32-bit, the intermediate instruction sequence acquisition module 402 can add the operation instruction of the def target data into the IR instruction sequence; otherwise, that is, if the operation instruction of the def target data is not 32-bit, the intermediate instruction sequence acquisition module 402 can prevent the addition of the operation instruction of the def target data into the IR instruction sequence.

[0093] According to an exemplary embodiment of this disclosure, the instruction translation apparatus 400 may further include a tracking constraint setting module.

[0094] The tracking constraint setting module can set tracking constraints, which can be used to limit the coverage of instruction simplification. Then, the intermediate instruction sequence acquisition module 402 can obtain the IR instruction sequence to be translated from the source instruction to be translated according to the tracking constraints. Furthermore, the tracking constraints may include, but are not limited to: tracking depth, the number of scan rounds of the instruction, and the number of IR instruction sequence features incorporated into the optimization.

[0095] The simplification module 403 can simplify the instructions involving intermediate results in the IR instruction sequence to obtain a simplified IR instruction sequence. The intermediate results can be intermediate process calculation results generated during the instruction calculation process, other than the final calculation result.

[0096] According to an exemplary embodiment of this disclosure, the simplification module 403 can delete the high-order clearing instruction and / or high-order sign extension instruction of the intermediate result of the 32-bit integer calculation in the IR instruction sequence.

[0097] According to an exemplary embodiment of this disclosure, the simplification module 403 can replace the 32-bit integer instruction that produces intermediate calculation results in the IR instruction sequence with an IR instruction that does not require clearing the high-order bits to 0 or an IR instruction that does not require sign extension of the high-order bits.

[0098] The translation module 404 can translate the simplified IR instruction sequence to obtain the target instruction that corresponds to the semantics of the simplified IR instruction sequence.

[0099] Figure 5 This is a block diagram illustrating an electronic device 500 according to an exemplary embodiment of the present disclosure.

[0100] Reference Figure 5 The electronic device 500 includes at least one memory 501 and at least one processor 502. The at least one memory 501 stores a set of computer-executable instructions. When the set of computer-executable instructions is executed by the at least one processor 502, an instruction translation method according to an exemplary embodiment of the present disclosure is performed.

[0101] As an example, electronic device 500 may be a PC, tablet, personal digital assistant, smartphone, or other device capable of executing the aforementioned set of instructions. Here, electronic device 500 is not necessarily a single electronic device, but may be a collection of any devices or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. Electronic device 500 may also be part of an integrated control system or system manager, or may be configured to interconnect with a portable electronic device locally or remotely (e.g., via wireless transmission) through an interface.

[0102] In electronic device 500, processor 502 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor may also include analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc.

[0103] The processor 502 can execute instructions or code stored in the memory 501, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transmission protocol.

[0104] The memory 501 may be integrated with the processor 502, for example, by arranging RAM or flash memory within an integrated circuit microprocessor. Alternatively, the memory 501 may include a separate device, such as an external disk drive, a storage array, or other storage device usable by any database system. The memory 501 and the processor 502 may be operatively coupled, or may communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor 502 to read files stored in the memory.

[0105] In addition, electronic device 500 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of electronic device 500 can be interconnected via a bus and / or network.

[0106] According to exemplary embodiments of the present disclosure, a computer-readable storage medium storing instructions may also be provided, wherein when the instructions are executed by at least one processor, they cause at least one processor to perform an instruction translation method according to the present disclosure. Examples of computer-readable storage media herein include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the aforementioned computer-readable storage medium can run in an environment deployed in computer devices such as clients, hosts, agent devices, servers, etc. Furthermore, in one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0107] According to exemplary embodiments of the present disclosure, a computer program product may also be provided, wherein the instructions in the computer program product are executable by a processor of a computer device to perform the instruction translation method according to exemplary embodiments of the present disclosure.

[0108] According to the instruction translation method, apparatus, electronic device, storage medium, and computer program product disclosed herein, in the process of translating source instructions into target instructions, by simplifying the instructions involving intermediate results in the intermediate instruction sequence, the number of redundant instructions can be reduced, thereby reducing the translation code bloat rate, which can improve the translation and execution efficiency of binary applications, making the binary applications under the source instruction set run more smoothly under the target instruction set.

[0109] According to exemplary embodiments of this disclosure, in order to facilitate the translation and execution of CISC applications, this disclosure uses a containerized deployment method to build a RISC container base image carrying C, C++ shared libraries and other content, and deploys the translator, CISC program and the runtime environment of the CISC program in the RISC container, thereby enabling the portable and flexible execution of CISC applications in a container environment.

[0110] According to the exemplary embodiments of this disclosure, optimization incurs overhead, primarily manifested in the repeated scanning of IR instructions, recursively tracing the data flow of preceding and succeeding instructions, and constructing intermediate instruction sequence features. Therefore, in this disclosure, the number of IR instruction scanning rounds, the tracing depth of preceding and succeeding instructions, and the number of intermediate instruction sequence features incorporated into the optimization can be appropriately controlled. This effectively accelerates instruction translation speed and improves translation efficiency.

[0111] According to an exemplary embodiment of this disclosure, by deleting the high-order bit clearing instruction and / or high-order bit sign extension instruction of the intermediate result of 32-bit integer calculation, the redundancy of the intermediate instruction sequence can be reduced, thereby accelerating the instruction translation speed and improving translation efficiency.

[0112] According to an exemplary embodiment of this disclosure, by replacing the 32-bit integer instruction that generates intermediate calculation results in the intermediate instruction sequence with an intermediate instruction that does not require clearing the high-order bits to 0 or an intermediate instruction that does not require sign extension of the high-order bits, the redundancy of the intermediate instruction sequence can be reduced, thereby accelerating the instruction translation speed and improving the translation efficiency.

[0113] According to exemplary embodiments of this disclosure, the translated RISC instructions can also be tested. Furthermore, if errors occur during testing, the IR instructions can be adjusted based on the location and cause of the error until the test is error-free, thus ensuring smooth instruction translation.

[0114] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0115] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for translating instructions, characterized in that, include: Obtain the source instructions to be translated; Obtain the intermediate instruction sequence to be translated from the source instructions to be translated; The instructions involving intermediate results in the intermediate instruction sequence are simplified to obtain a simplified intermediate instruction sequence, wherein the intermediate result is the intermediate process calculation result generated during the instruction calculation process, excluding the final calculation result; The simplified intermediate instruction sequence is translated to obtain the target instruction that corresponds to the semantics of the simplified intermediate instruction sequence.

2. The instruction translation method as described in claim 1, characterized in that, The step of obtaining the intermediate instruction sequence to be translated from the source instruction to be translated includes: The source instruction is parsed to obtain intermediate instructions; Forward analysis and / or successor analysis are performed on the intermediate instructions to obtain the intermediate instruction sequence, wherein the forward analysis is used to obtain the upstream intermediate computation instructions on which the intermediate instructions depend, and the successor analysis is used to obtain the downstream intermediate computation instructions that use the computation results of the intermediate instructions.

3. The instruction translation method as described in claim 2, characterized in that, The step of performing forward analysis and / or follow-up analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: In the case that the intermediate instruction is a 32-bit def class operation instruction, determine whether the def target data of the use node of the 32-bit def class operation instruction is 32 bits; If the def target data of the use node is 32 bits, the def target data of the use node is added to the intermediate instruction sequence; Otherwise, adding the def target data of the use node to the intermediate instruction sequence is prohibited.

4. The instruction translation method as described in claim 2, characterized in that, The step of performing forward analysis and / or follow-up analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: When the intermediate instruction is a 32-bit use-type operation instruction, determine whether the operation instruction of the def target data of the def node of the 32-bit use-type operation instruction is 32-bit; If the operation instructions for the target data are 32-bit, the operation instructions for the target data are added to the intermediate instruction sequence. Otherwise, it is prohibited to add the operation instructions of the def target data into the intermediate instruction sequence.

5. The instruction translation method as described in claim 2, characterized in that, Before performing forward and / or subsequent analysis on the intermediate instructions to obtain the intermediate instruction sequence, the method further includes: Identify the 32-bit integer arithmetic instructions in the intermediate instructions; The step of performing forward analysis and / or follow-up analysis on the intermediate instructions to obtain the intermediate instruction sequence includes: Perform forward and / or follow-up analysis on the identified 32-bit integer arithmetic instructions to obtain the intermediate instruction sequence; The 32-bit integer arithmetic instruction is identified by at least one of the following methods: The data width involved in the operation is 4 bytes, the operation result is 4 bytes, and the operation instructions are 32-bit operation instructions.

6. The instruction translation method as described in claim 1, characterized in that, The instruction translation method also includes: Set a tracking constraint, wherein the tracking constraint is used to limit the coverage of instruction simplification; The step of obtaining the intermediate instruction sequence to be translated from the source instruction to be translated includes: According to the tracing constraints, the sequence of intermediate instructions to be translated is obtained from the source instructions to be translated.

7. The instruction translation method as described in claim 1, characterized in that, Before obtaining the source instructions to be translated, the following steps are also included: Construct the target instruction container; The target application and the runtime environment on which the target application depends are deployed within the target instruction container; The process of obtaining the source instructions to be translated includes: In response to a user action, the target application deployed within the target instruction container is launched and run; The instructions generated during the execution of the target application are obtained as the source instructions to be translated.

8. The instruction translation method as described in claim 1, characterized in that, The step of simplifying the instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence includes: Remove the high-order 0 clearing instruction and / or high-order sign extension instruction of the intermediate result of the 32-bit integer calculation in the intermediate instruction sequence.

9. The instruction translation method as described in claim 1, characterized in that, The step of simplifying the instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence includes: Replace the 32-bit integer instruction that generates the intermediate calculation result in the intermediate instruction sequence with an intermediate instruction that does not require clearing the high-order bits to 0 or an intermediate instruction that does not require sign extension of the high-order bits.

10. An instruction translation device, characterized in that, include: The source instruction acquisition module is configured to acquire the source instructions to be translated; The intermediate instruction sequence acquisition module is configured to obtain the intermediate instruction sequence to be translated from the source instruction to be translated; A simplification module is configured to simplify instructions involving intermediate results in the intermediate instruction sequence to obtain a simplified intermediate instruction sequence, wherein the intermediate results are intermediate process calculation results generated during instruction calculation, excluding the final calculation result; The translation module is configured to translate the simplified intermediate instruction sequence to obtain a target instruction that corresponds to the semantics of the simplified intermediate instruction sequence.

11. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the instruction translation method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the instruction translation method as described in any one of claims 1 to 9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction translation method as described in any one of claims 1 to 9.

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