ZYNQ-based dual-channel DMA ping-pong caching method and embedded system

Abstract

The invention provides a ZYNQ-based dual-channel DMA ping-pong caching method and an embedded system. The method comprises the following steps: establishing a first storage area and a second storage area in a memory; configuring a first transmission channel to be associated with the first storage area and a second transmission channel to be associated with the second storage area; controlling the first transmission channel to write data into the first storage area; when a preset switching condition is met, stopping writing of the first transmission channel, and starting the second transmission channel to write data into the second storage area; meanwhile, starting a data processing operation on the written data in the first storage area; when the switching condition is met again, writing of the second transmission channel is stopped, and the first transmission channel is restarted to write data into the first storage area; meanwhile, starting a data processing operation on the written data in the second storage area; the channel switching operation is repeatedly performed so that the data writing operation and the data processing operation are performed in parallel.

Description

Technical Field

[0001] This application relates to the field of embedded system data transmission technology, specifically to a dual-channel DMA ping-pong buffer method based on ZYNQ and an embedded system. Background Technology

[0002] In high-speed data acquisition and transmission systems, the traditional single-channel DMA (direct memory access) scheme has the following technical bottlenecks: (1) Low transmission efficiency: single-channel DMA requires alternating waiting during data transmission and processing, and the bus utilization rate is less than 50%; (2) Uneven CPU load: data processing and transmission cannot be parallelized, resulting in intermittent high CPU load; (3) Limited real-time performance: under the single buffer mechanism, data reception and processing need to be executed serially; (4) Waste of resources: the DMA channel idle time accounts for a high proportion, and the utilization rate of hardware acceleration units is insufficient. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide a dual-channel DMA ping-pong cache method and embedded system based on ZYNQ; In a first aspect, this application proposes a dual-channel DMA ping-pong caching method based on ZYNQ, characterized by the following steps: Establish a first storage region and a second storage region in memory; Configure a first transmission channel to be associated with the first storage area, and a second transmission channel to be associated with the second storage area; Control the first transmission channel to write data to the first storage area; When the preset switching conditions are met, a channel switching operation is performed, including: stopping the writing of the first transmission channel and starting the second transmission channel to write data to the second storage area; at the same time, starting the data processing operation on the data already written to the first storage area. When the switching condition is met again, the next channel switching operation is performed, including: stopping the writing of the second transmission channel and restarting the first transmission channel to write data to the first storage area; at the same time, starting the data processing operation on the data already written to the second storage area; Repeat the channel switching operation so that the data writing operation and the data processing operation are executed in parallel.

[0004] According to the technical solution provided in the embodiments of this application, configuring the first transmission channel to be associated with the first storage area and the second transmission channel to be associated with the second storage area includes the following steps: Configure the first transmission channel as DMA channel A and the second transmission channel as DMA channel B; Set the transmission target address of the DMA channel A to the starting physical address of the first storage area; Set the transmission target address of the DMA channel B to the starting physical address of the second storage area; Configure the burst transfer length of the DMA to optimize bus utilization efficiency.

[0005] According to the technical solution provided in the embodiments of this application, the preset switching condition is triggered when any one of the following conditions is met: The amount of data written to the storage area has reached its capacity threshold. The time elapsed since the start of the current transmission channel has reached a preset time threshold.

[0006] According to the technical solution provided in the embodiments of this application, the method further includes exception handling, which is performed during the channel switching operation or data processing operation, and includes the following steps: When a data transmission timeout is detected on any transmission channel, a channel switching operation is forcibly executed; When data verification fails for any storage area, the corresponding transmission channel is controlled to retransmit the data for that storage area.

[0007] According to the technical solution provided in the embodiments of this application, the method further includes dynamic parameter adjustment; dynamic parameter adjustment includes the following steps: The size of the first and second storage areas, the burst transmission length, or a preset time threshold can be dynamically adjusted by configuring the bus.

[0008] According to the technical solution provided in the embodiments of this application, the method further includes managing the activation state of the transmission channel through a state machine; the state machine includes at least a first state and a second state; When in the first state, it indicates that the first transmission channel is in the active write state and the second transmission channel is in the disabled state; When in the second state, it indicates that the second transmission channel is in the active write state and the first transmission channel is in the disabled state; The execution channel switching operation includes switching the state of the state machine.

[0009] According to the technical solution provided in the embodiments of this application, the channel switching operation is executed by an interrupt service routine; When the preset switching conditions are met, the currently active transmission channel triggers a transmission completion interruption; the interrupt service routine responds to the interruption by stopping the current transmission channel, starting another transmission channel, and updating the state machine.

[0010] According to the technical solution provided in the embodiments of this application, the data verification adopts a cyclic redundancy check method; when the verification fails, the retransmission resumes from the last data frame that was verified correctly.

[0011] According to the technical solution provided in the embodiments of this application, the method further includes a data flow control step: Monitor the execution rate of the data processing operations in real time; Based on the monitoring results, the capacity threshold or time threshold in the preset switching conditions are dynamically adjusted to match the data writing rate with the data processing rate.

[0012] Secondly, this application proposes a ZYNQ-based embedded system, comprising: Memory, used to store executable programs; A processor, when executing the executable program, implements the dual-channel DMA ping-pong cache method as described above.

[0013] Compared with existing technologies, the beneficial effects of this application are as follows: This invention aims to solve the problems of low transmission efficiency, unbalanced CPU load, and poor real-time performance of existing single-channel DMA, and provides a dual-channel DMA ping-pong caching method based on ZYNQ. The main operation flow includes system initialization, data transmission and ping-pong switching process, exception handling mechanism, and dynamic parameter adjustment. The dual-channel ping-pong caching method significantly improves the utilization rate of the data bus, realizes full parallelism of reception and processing, and ensures that the system does not put excessive pressure on the main processor while transmitting data at high speed, ensuring that the CPU can perform other tasks without affecting the efficiency of data transmission. At the same time, a verification and timeout retransmission mechanism is introduced to prevent data from being damaged or tampered with during transmission. If a data verification error is found, the system can automatically retransmit lost or damaged data to ensure that the received data is error-free. Compared with existing technologies, this invention solves the transmission bottleneck problem of single-channel schemes in high-speed data acquisition, enabling the system to cope with higher bandwidth requirements, and fully utilizes the efficiency of data transmission under multi-channel parallel operation. By adopting an exception handling mechanism, the fault tolerance of the system is effectively improved, ensuring that data can be transmitted completely and accurately under any circumstances. Attached Figure Description

[0014] Figure 1 A flowchart illustrating the steps of the dual-channel DMA ping-pong caching method based on ZYNQ provided in this application embodiment. Detailed Implementation

[0015] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0016] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0017] Example 1 As mentioned in the background section, to address the problems in the existing technology, this application proposes a dual-channel DMA ping-pong caching method based on ZYNQ, such as... Figure 1 As shown, it includes the following steps: S1. Establish the first and second storage areas in memory; S2. Configure the first transmission channel to be associated with the first storage area, and the second transmission channel to be associated with the second storage area; S3. Control the first transmission channel to write data to the first storage area; S4. When the preset switching conditions are met, perform a channel switching operation, including: stopping the writing of the first transmission channel and starting the second transmission channel to write data to the second storage area; at the same time, start the data processing operation on the data already written in the first storage area. S5. When the switching condition is met again, perform the next channel switching operation, including: stopping the writing of the second transmission channel and restarting the first transmission channel to write data to the first storage area; at the same time, start the data processing operation on the data already written in the second storage area; S6. Repeat the channel switching operation so that the data writing operation and the data processing operation are executed in parallel.

[0018] In a preferred embodiment, configuring the first transmission channel to be associated with the first storage region and the second transmission channel to be associated with the second storage region includes the following steps: Configure the first transmission channel as DMA channel A and the second transmission channel as DMA channel B; Set the transmission target address of the DMA channel A to the starting physical address of the first storage area; Set the transmission target address of the DMA channel B to the starting physical address of the second storage area; Configure the burst transfer length of the DMA to optimize bus utilization efficiency.

[0019] In a preferred embodiment, the preset switching condition is triggered when any one of the following conditions is met: The amount of data written to the storage area has reached its capacity threshold. The time elapsed since the start of the current transmission channel has reached a preset time threshold.

[0020] In a preferred embodiment, the method further includes exception handling, which is performed during the channel switching operation or data processing operation, and includes the following steps: When a data transmission timeout is detected on any transmission channel, a channel switching operation is forcibly executed; When data verification fails for any storage area, the corresponding transmission channel is controlled to retransmit the data for that storage area.

[0021] In a preferred embodiment, the method further includes dynamic parameter adjustment; dynamic parameter adjustment includes the following steps: The size of the first and second storage areas, the burst transmission length, or a preset time threshold can be dynamically adjusted by configuring the bus.

[0022] In a preferred embodiment, the method further includes managing the activation state of the transmission channel through a state machine; the state machine includes at least a first state and a second state; When in the first state, it indicates that the first transmission channel is in the active write state and the second transmission channel is in the disabled state; When in the second state, it indicates that the second transmission channel is in the active write state and the first transmission channel is in the disabled state; The execution channel switching operation includes switching the state of the state machine.

[0023] In a preferred embodiment, the channel switching operation is performed by an interrupt service routine; When the preset switching conditions are met, the currently active transmission channel triggers a transmission completion interruption; the interrupt service routine responds to the interruption by stopping the current transmission channel, starting another transmission channel, and updating the state machine.

[0024] In a preferred embodiment, the data verification adopts a cyclic redundancy check method; when the verification fails, the retransmission resumes from the last data frame that has been verified correctly.

[0025] In a preferred embodiment, the method further includes a data flow control step: Monitor the execution rate of the data processing operations in real time; Based on the monitoring results, the capacity threshold or time threshold in the preset switching conditions are dynamically adjusted to match the data writing rate with the data processing rate.

[0026] Specifically, this invention provides a dual-channel DMA ping-pong cache method based on ZYNQ. The hardware foundation of this method is the Xilinx ZYNQ-7000 series SoC, which adopts a heterogeneous architecture of "PS (dual-core ARM Cortex-A9) + PL (programmable logic)". The PS is connected to the PL via a high-performance HP port, providing the hardware foundation for dual-channel DMA design.

[0027] In practical implementation, the PL side is configured with two independent AXI DMA controllers, serving as DMA channel A and DMA channel B respectively. The DDR3 memory on the PS side serves as the primary storage medium, used for allocating dual buffers. The AXI bus acts as the data transmission channel, with AXI4-Stream used for high-speed data stream transmission and AXI4-Lite used for control register configuration.

[0028] Detailed implementation methods for each step: System initialization phase Memory allocation: Two buffers, Buffer0 and Buffer1, are allocated in DDR3 memory as the first and second storage areas. The size of each buffer can be configured according to application requirements, with a typical value of 4MB. The allocated buffers are ensured to be physically contiguous through the Linux kernel's dma_alloc_coherent function or memory mapping in bare-metal programming, allowing direct access by the DMA controller.

[0029] Transmission Channel Configuration: Configure the first AXI DMA controller on the PL side as DMA channel A and the second AXI DMA controller as DMA channel B. Set the transmission destination address of DMA channel A to the starting physical address of Buffer0, and the transmission destination address of DMA channel B to the starting physical address of Buffer1. Configure the DMA burst transfer length to 512 bytes; this value has been optimized and tested to effectively utilize the bandwidth of the AXI bus.

[0030] State Machine Initialization: Initialize the system state machine, which is a two-state machine: state S0 indicates that channel A is active and channel B is disabled; state S1 indicates that channel B is active and channel A is disabled. The initial system state is set to S0. At this time, channel A begins writing data to Buffer0, and channel B is in a waiting state.

[0031] Other initialization tasks: Configure the AXI bus width to 64 bits and the clock frequency to 150MHz; initialize all control registers of the DMA controller; set the interrupt controller and enable the DMA transfer completion interrupt.

[0032] Data transmission and ping-pong switching phase: Switching condition settings: The preset switching conditions include two independent conditions, and the one that is met first shall prevail: Capacity threshold condition: Triggered when the amount of data written to the buffer reaches 95% of its capacity. Time threshold condition: Timing starts from channel startup and triggers when 1ms has elapsed. The specific execution of the channel switching operation: When DMA channel A meets the switching conditions, a transfer completion interrupt is triggered. The interrupt service routine performs the following operations: Disable DMA channel A and stop writing data to Buffer0. Enable DMA channel B and start writing data to Buffer1. Update the state machine from S0 to S1. Notify the CPU to begin processing the data already written to Buffer0. Similarly, when DMA channel B meets the switching conditions, the opposite operation sequence is executed to achieve alternating operation of the channel.

[0033] Parallel processing mechanism: While the CPU processes data in Buffer0, DMA channel B continuously writes new data to Buffer1; while the CPU processes data in Buffer1, DMA channel A continuously writes new data to Buffer0. This mechanism ensures continuous parallel execution of data reception and processing.

[0034] Exception handling mechanism: Transmission timeout handling: The transmission timeout threshold is set to 2ms. When any DMA channel fails to complete a transmission within 2ms, the system forcibly switches to another channel and logs the error via the AXI4-Lite bus.

[0035] Data verification and retransmission: A 32-bit CRC cyclic redundancy check is used. A CRC checksum is added to the end of each data frame. When verification fails, the system automatically retransmits from the last correctly verified data frame. The retransmission mechanism is implemented through the hash table mode of the DMA controller, retransmitting only the erroneous data blocks.

[0036] Dynamic parameter adjustment: The configuration program is run on the ARM processor at the PS end, and the following parameters are dynamically adjusted via the AXI4-Lite bus: Buffer size: Adjustable from 1MB to 16MB Burst transmission length: Adjustable from 64 to 1024 bytes Time threshold: adjustable within the range of 0.5ms-5ms Capacity threshold ratio: can be adjusted within the range of 80%-98%. For example, taking a high-speed data acquisition system as an example, the specific implementation process is as follows: During system initialization, two 4MB buffers are allocated, the burst transfer length is set to 512 bytes, and the time threshold is 1ms. After startup, DMA channel A begins receiving sampled data from the ADC and writing it to Buffer0.

[0037] When the data volume in Buffer0 reaches 3.8MB (95% capacity), an interrupt service routine is triggered. The system disables channel A, enables channel B to start writing data to Buffer1, and the CPU begins real-time spectrum analysis of the data in Buffer0.

[0038] While the CPU is processing data in Buffer0, DMA channel B continuously receives new sampled data. When the write time to Buffer1 reaches 1ms, the system switches again, enabling channel A and writing new data to Buffer0, while the CPU processes the data in Buffer1.

[0039] When the system detects a CRC check error in data transmission, it automatically retransmits the lost data packet from the location of the error to ensure data integrity.

[0040] Furthermore, performance test results: After actual testing, this embodiment achieved the following technical indicators on the ZYNQ XC7Z020 chip: Data transfer rate: Stable at 1.2GB / s; Bus utilization: Increased from less than 50% in traditional solutions to over 92%; Switching latency: Channel switching operation completed within 10μs; CPU load: CPU utilization remained balanced during data processing, with peak utilization reduced by 40%; Error handling: CRC check can detect and correct 99.99% of transmission errors. Advantages: Compared with the background technology, this specific implementation effectively solves the four major technical bottlenecks of the traditional single-channel DMA solution through a dual-channel DMA ping-pong buffer mechanism: achieving nearly 100% bus utilization through dual-channel alternating operation; making the CPU load more balanced through parallel processing; eliminating the blocking of data reception by data processing through ping-pong buffering; and optimizing system resource utilization through dynamic parameter adjustment.

[0041] Example 2 This embodiment proposes an embedded system based on ZYNQ, including: Memory, used to store executable programs; A processor, when executing the executable program, implements the dual-channel DMA ping-pong cache method as described above.

[0042] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A dual-channel DMA ping-pong buffer method based on ZYNQ, characterized in that, Includes the following steps: Establish a first storage region and a second storage region in memory; Configure a first transmission channel to be associated with the first storage area, and a second transmission channel to be associated with the second storage area; Control the first transmission channel to write data to the first storage area; When the preset switching conditions are met, a channel switching operation is performed, including: stopping the writing of the first transmission channel and starting the second transmission channel to write data to the second storage area; at the same time, starting the data processing operation on the data already written to the first storage area. When the switching condition is met again, the next channel switching operation is performed, including: stopping the writing of the second transmission channel and restarting the first transmission channel to write data to the first storage area; at the same time, starting the data processing operation on the data already written to the second storage area; Repeat the channel switching operation so that the data writing operation and the data processing operation are executed in parallel.

2. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 1, characterized in that: The configuration of associating the first transmission channel with the first storage area and the second transmission channel with the second storage area includes the following steps: Configure the first transmission channel as DMA channel A and the second transmission channel as DMA channel B; Set the transmission target address of the DMA channel A to the starting physical address of the first storage area; Set the transmission target address of the DMA channel B to the starting physical address of the second storage area; Configure the burst transfer length of the DMA to optimize bus utilization efficiency.

3. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 1, characterized in that: The preset switching condition is triggered when any one of the following conditions is met: The amount of data written to the storage area has reached its capacity threshold. The time elapsed since the start of the current transmission channel has reached a preset time threshold.

4. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 1, characterized in that: The method further includes exception handling, which is performed during the channel switching operation or data processing operation, and includes the following steps: When a data transmission timeout is detected on any transmission channel, a channel switching operation is forcibly executed; When data verification fails for any storage area, the corresponding transmission channel is controlled to retransmit the data for that storage area.

5. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 2, characterized in that: The method further includes dynamic parameter adjustment; dynamic parameter adjustment includes the following steps: The size of the first and second storage areas, the burst transmission length, or a preset time threshold can be dynamically adjusted by configuring the bus.

6. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 1, characterized in that: The method further includes managing the activation state of the transmission channel through a state machine; the state machine includes at least a first state and a second state; When in the first state, it indicates that the first transmission channel is in the active write state and the second transmission channel is in the disabled state; When in the second state, it indicates that the second transmission channel is in the active write state and the first transmission channel is in the disabled state; The execution channel switching operation includes switching the state of the state machine.

7. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 6, characterized in that: The channel switching operation is performed by the interrupt service routine; When the preset switching conditions are met, the currently active transmission channel triggers a transmission completion interruption. The interrupt service routine responds to an interrupt by performing operations such as stopping the current transmission channel, starting another transmission channel, and updating the state machine.

8. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 4, characterized in that: The data verification adopts a cyclic redundancy check method; when the verification fails, the retransmission resumes from the last data frame that has been verified correctly.

9. The dual-channel DMA ping-pong buffer method based on ZYNQ according to claim 1, characterized in that: The method also includes a data flow control step: Monitor the execution rate of the data processing operations in real time; Based on the monitoring results, the capacity threshold or time threshold in the preset switching conditions are dynamically adjusted to match the data writing rate with the data processing rate.

10. An embedded system based on ZYNQ, characterized in that, include: Memory, used to store executable programs; A processor, when executing the executable program, implements the dual-channel DMA ping-pong cache method as described in any one of claims 1 to 9.

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