Error correction bit configurable ECC error correction IP core design verification implementation method
By receiving the error correction bit configuration parameters, the system automatically generates ECC error correction matrix data and simultaneously generates hardware design and verification code. This solves the problem that ECC error correction IP cores cannot simultaneously achieve high reliability and low power consumption, realizes automated design verification, and improves efficiency and applicability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-03-24
AI Technical Summary
Existing ECC error correction IP cores cannot flexibly adapt to the different application scenarios requiring high reliability and low power consumption, and the traditional design verification process is inefficient and highly inconsistent.
By receiving the error correction bit configuration parameters, the system automatically generates ECC error correction matrix data and simultaneously generates hardware design and verification code, forming an ECC error correction IP core design verification environment with configurable error correction bit, thus achieving an automated process.
It enables flexible configuration of ECC error correction capabilities, improves the efficiency and quality of design verification, ensures the stability and applicability of output, and expands the reuse scope and long-term value of IP cores.
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Figure CN121723944A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit design verification technology, specifically to a design verification implementation method for an ECC error correction IP core with configurable error correction bit width. Background Technology
[0002] During the manufacturing process of NAND Flash memory, defects may occur due to its inherent characteristics. In particular, the use of multi-cell structures to increase storage capacity can lead to decreased yield and reliability, resulting in random data errors during read and write operations. Therefore, it is necessary to verify that the data read is consistent with the data written. A common method is to use an encoder to generate ECC check bits during data writing and store them in a redundant area outside the flash memory data region. During data reading, a decoder verifies the received data to confirm whether it is error-free or has been interfered with by various noises. If interference or errors are confirmed, further investigation is needed to locate the error location and recover the correct data.
[0003] As the data and program storage requirements of electronic systems continue to increase, the demand for reliable NAND Flash applications is also gradually rising. To adapt to specific operating environments, FPGAs are often used as NAND Flash memory controllers to directly access and process NAND Flash chips. Therefore, ECC error correction IP cores need to be integrated to perform data error detection and correction. In some harsh applications requiring long-term operation and high reliability, the ECC error correction IP core needs to have a higher error correction capability; while in other applications that are more sensitive to resources and power consumption, the number of ECC error correction bits needs to be appropriately reduced, thus shrinking the size of the implementation circuit. Considering these requirements, a suitable ECC error correction algorithm needs to be selected, and the design implementation needs to have configurable and adjustable functions. Summary of the Invention
[0004] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide a design verification and implementation method for an ECC error correction IP core with configurable error correction bits, including the following steps: Receive error correction bit configuration parameters; Based on the error correction bit configuration parameters, the corresponding ECC error correction matrix data is generated; Based on the ECC error correction matrix data, the hardware design code constituting the ECC error correction IP core is automatically generated; Based on the error correction bit configuration parameters, verification code for verifying the ECC error correction IP core is generated synchronously; The hardware design code and the verification code are integrated to form an ECC error correction IP core design verification environment with configurable error correction bits.
[0005] According to the technical solution provided in the embodiments of this application, the step of automatically generating hardware design code constituting the ECC error correction IP core based on the ECC error correction matrix data includes the following steps: The ECC error correction matrix data is parsed into multiple key design component codes that constitute the ECC error correction IP core; The code of multiple key design components is integrated to generate complete ECC error correction IP core hardware design code.
[0006] According to the technical solution provided in the embodiments of this application, the step of synchronously generating verification code for verifying the ECC error correction IP core based on the error correction bit configuration parameters includes the following steps: Based on the error correction bit configuration parameters, generate key verification component code corresponding to the ECC error correction IP core function; The code of the key verification components is integrated to construct a verification environment code for simulating and verifying the ECC error correction IP core.
[0007] According to the technical solution provided in the embodiments of this application, after the method integrates to form a design verification environment, it further includes the following steps: Outputs hardware design code and verification environment code for ECC error correction IP core with configurable error correction bits; The hardware design code and verification environment code are directly associated with the error correction bit configuration parameters, and no manual secondary modification is required for different error correction bit values.
[0008] According to the technical solution provided in the embodiments of this application, the step of generating the corresponding ECC error correction matrix data based on the error correction bit configuration parameters includes the following steps: Based on the error correction bit configuration parameters, determine the algorithm type and order of the ECC error correction algorithm; Based on the determined algorithm type and order, the ECC error correction matrix data used for hardware implementation of the encoding and decoding logic is calculated.
[0009] According to the technical solution provided in the embodiments of this application, the hardware design code is synthesizable register-transfer level hardware description language code; the verification code is test platform code suitable for simulation verification, including a test stimulus generation module and a response checking module.
[0010] According to the technical solution provided in the embodiments of this application, the multiple key design component codes include: encoder module code, decoder module code, and error correction logic module code; The encoder module code, decoder module code, and error correction logic module code are all generated based on the ECC error correction matrix data, and their internal logic structures are adapted to the error correction bit configuration parameters.
[0011] According to the technical solution provided in the embodiments of this application, the step of parsing the ECC error correction matrix data into multiple key design component codes constituting the ECC error correction IP core includes the following steps: Identify the parity check matrix and generator matrix in the ECC error correction matrix data; Based on the structure and elements of the parity check matrix, generate decoder module code for verifying data and producing syntactic data. Based on the structure and elements of the generated matrix, encoder module code for calculating and attaching check bits is generated; Based on the parity check matrix and the preset error location algorithm, error correction logic module code is generated to locate and correct data bit errors according to the syndrome.
[0012] According to the technical solution provided in the embodiments of this application, the step of generating key verification component code corresponding to the ECC error correction IP core function based on the error correction bit configuration parameters includes the following steps: The code for the test stimulus generation module is configured to automatically generate test data vectors covering different error correction bits and corresponding injection error modes based on the error correction bit configuration parameters. Generate reference model module code, which is configured to implement a behavioral-level model consistent with the expected function of the ECC error correction IP core based on the error correction bit configuration parameters, and to generate the expected output; Generate response checking module code, which is configured to compare the actual output of the ECC error correction IP core with the expected output of the reference model module and automatically report the verification results.
[0013] According to the technical solution provided in the embodiments of this application, the integration of the hardware design code and the verification code to form an ECC error correction IP core design verification environment with configurable error correction bits includes the following steps: Configure the hardware design code as the design-to-test module in the verification environment; Configure the verification code as a core verification component for stimulus generation, response checking, and environmental control. According to the predefined verification platform architecture and communication interface, the design under test module and the core verification component are interconnected and encapsulated to generate a complete top-level test platform module that can directly drive simulation.
[0014] Compared with the prior art, the beneficial effects of this application are as follows: I. This application achieves flexible and configurable ECC error correction capabilities, resolving the core contradiction of differentiated application scenarios: Background technology indicates that high-reliability scenarios require multi-bit error correction capabilities, while resource-sensitive scenarios require reduced circuit size to lower power consumption. This application receives error correction bit configuration parameters and uses these as the core driving force to generate all subsequent code, enabling an IP core design to directly adapt to different needs from high reliability to resource sensitivity through parameter adjustments. This fundamentally solves the contradiction that traditional fixed-bit ECC IP cores cannot simultaneously achieve "high performance" and "low power consumption."
[0015] II. This solution provides a fully automated design and verification process from parameters to finished product, significantly improving development efficiency and quality: Background technology inherently involves a huge workload of designing, implementing, and verifying IP cores for different bit widths. This solution constructs a complete automated process (generating a matrix → generating hardware code → synchronously generating verification code → integration environment), integrating the originally separate and manual design and verification tasks into a coherent, parameterized automated process. This not only "shortens the design verification cycle" (efficiency) but also ensures a high degree of consistency between the verification environment and the design itself through "synchronous generation" of verification code, improving the correctness and reliability of the design (quality).
[0016] Third, the solution generates a directly usable code product deeply bound to the configuration, ensuring the stability and applicability of the output: the final output is a "configurable error correction bit ECC error correction IP core design verification environment". This means that for each specific configuration parameter, the method will produce a complete "solution package" containing verified design code and the corresponding verification environment. This avoids the uncertainty of manual code modification, adaptation, and debugging for new bit requirements in traditional methods, making the output stable, reliable, and "no secondary modification required," ready to use immediately, reducing the application threshold and integration risk.
[0017] Fourth, the parametric design approach enhances the reusability and long-term value of IP cores: This application establishes an IP core generator based on configurable parameters. This allows for the development of not just single-function IP cores, but a "family of IP cores" capable of covering a range of error correction bits. This significantly expands the applicability and lifecycle of individual design deliverables, enabling rapid response to future changes in error correction bit requirements due to NAND Flash process evolution or new application needs, protecting investment and demonstrating a significant superior advantage. Attached Figure Description
[0018] Figure 1 A flowchart illustrating the steps of the design verification and implementation method for an ECC error correction IP core with configurable error correction bits provided in this application embodiment; Figure 2This is a schematic diagram illustrating the design verification and implementation system of an ECC error correction IP core with configurable error correction bit width provided in this application embodiment. Detailed Implementation
[0019] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0021] Example 1 As mentioned in the background section, to address the problems in the existing technology, this application proposes a design verification and implementation method for an ECC error correction IP core with configurable error correction bits, such as... Figure 1-2 As shown, it includes the following steps: S101, Receive error correction bit configuration parameters; S102. Based on the error correction bit configuration parameters, generate the corresponding ECC error correction matrix data; S103. Based on the ECC error correction matrix data, automatically generate the hardware design code that constitutes the ECC error correction IP core; In a preferred embodiment, the step of automatically generating the hardware design code constituting the ECC error correction IP core based on the ECC error correction matrix data includes the following steps: The ECC error correction matrix data is parsed into multiple key design component codes that constitute the ECC error correction IP core; The code of multiple key design components is integrated to generate complete ECC error correction IP core hardware design code.
[0022] In a preferred embodiment, the step of synchronously generating verification code for verifying the ECC error correction IP core based on the error correction bit configuration parameter includes the following steps: Based on the error correction bit configuration parameters, generate key verification component code corresponding to the ECC error correction IP core function; The code of the key verification components is integrated to construct a verification environment code for simulating and verifying the ECC error correction IP core.
[0023] In a preferred embodiment, after the method integrates to form a design verification environment, it further includes the following steps: Outputs hardware design code and verification environment code for ECC error correction IP core with configurable error correction bits; The hardware design code and verification environment code are directly associated with the error correction bit configuration parameters, and no manual secondary modification is required for different error correction bit values.
[0024] In a preferred embodiment, generating the corresponding ECC error correction matrix data based on the error correction bit configuration parameters includes the following steps: Based on the error correction bit configuration parameters, determine the algorithm type and order of the ECC error correction algorithm; Based on the determined algorithm type and order, the ECC error correction matrix data used for hardware implementation of the encoding and decoding logic is calculated.
[0025] In a preferred embodiment, the hardware design code is synthesizable register-transfer level hardware description language code; the verification code is test platform code suitable for simulation verification, including a test stimulus generation module and a response checking module.
[0026] In a preferred embodiment, the multiple key design component codes include: encoder module code, decoder module code, and error correction logic module code; The encoder module code, decoder module code, and error correction logic module code are all generated based on the ECC error correction matrix data, and their internal logic structures are adapted to the error correction bit configuration parameters.
[0027] In a preferred embodiment, parsing the ECC error correction matrix data into multiple key design component codes constituting the ECC error correction IP core includes the following steps: Identify the parity check matrix and generator matrix in the ECC error correction matrix data; Based on the structure and elements of the parity check matrix, generate decoder module code for verifying data and producing syntactic data. Based on the structure and elements of the generated matrix, encoder module code for calculating and attaching check bits is generated; Based on the parity check matrix and the preset error location algorithm, error correction logic module code is generated to locate and correct data bit errors according to the syndrome.
[0028] In a preferred embodiment, generating the key verification component code corresponding to the ECC error correction IP core function according to the error correction bit configuration parameter includes the following steps: The code for the test stimulus generation module is configured to automatically generate test data vectors covering different error correction bits and corresponding injection error modes based on the error correction bit configuration parameters. Generate reference model module code, which is configured to implement a behavioral-level model consistent with the expected function of the ECC error correction IP core based on the error correction bit configuration parameters, and to generate the expected output; Generate response checking module code, which is configured to compare the actual output of the ECC error correction IP core with the expected output of the reference model module and automatically report the verification results.
[0029] In a preferred embodiment, integrating the hardware design code with the verification code to form a design verification environment for an ECC error correction IP core with configurable error correction bits includes the following steps: Configure the hardware design code as the design-to-test module in the verification environment; Configure the verification code as a core verification component for stimulus generation, response checking, and environmental control. According to the predefined verification platform architecture and communication interface, the design under test module and the core verification component are interconnected and encapsulated to generate a complete top-level test platform module that can directly drive simulation.
[0030] Specifically, this solution provides a design verification implementation method for an ECC error correction IP core with configurable error correction bit width. Its core lies in using a unified error correction bit width configuration parameter as input to drive an automated process that synchronously generates hardware design code and its corresponding dedicated verification environment code that perfectly match the configuration parameter, ultimately outputting a complete and directly usable design verification solution. This method is particularly suitable for NAND Flash storage systems using FPGAs as controllers, and can flexibly adapt to the needs of different application scenarios, from high reliability to low power consumption.
[0031] The following is in conjunction with the appendix Figure 1 The overall technical solution block diagram shown illustrates the specific implementation steps of the method of the present invention in detail.
[0032] For example, suppose a user needs to generate an ECC IP core and its verification environment that can correct up to 4 errors for a project, then the input configuration parameter is: error correction bit t = 4.
[0033] Step S101: Receive error correction bit configuration parameters: The system receives a key configuration parameter from external input: the maximum number of error-correctable bits (t). This parameter is typically input as an integer, such as t = 1, 2, 3, 4, ... In this embodiment, the input is t = 4. This parameter will serve as the sole basis for all subsequent code generation processes.
[0034] Step S102: Based on the configuration parameters, generate the corresponding ECC error correction matrix data: This step corresponds to the "ECC error correction matrix generation module" in the attached diagram. Based on the input error correction bit length t=4, the system automatically determines to use BCH code (Bose–Chaudhuri–Hocquenghem Code) as the error correction algorithm, because BCH code is widely used in NAND Flash ECC in engineering, and its error correction capability has a clear mathematical relationship with the parameters.
[0035] Determine the algorithm parameters: Based on t=4 and the required data bit length (e.g., 256 bits), determine the codeword length n and information bit length k of the BCH code, and determine the order of the generator polynomial g(x).
[0036] Calculate the key matrices: Based on the above parameters, calculate the two core ECC error correction matrix data: Generating matrix (G matrix): Used in the encoding process, its structure determines how the parity bits are calculated from the original data bits.
[0037] Parity check matrix (H matrix): Used in the decoding and error correction process, its structure corresponds one-to-one with the syndrome generated by any error mode.
[0038] These matrix data form the mathematical basis for the subsequent generation of hardware logic.
[0039] Step S103: Based on the ECC error correction matrix data, automatically generate the hardware design code that constitutes the ECC error correction IP core: This step corresponds to the "ECC Key Component Generation Module" and "ECC Component Integration Module" in the attached diagram. The system automatically translates the mathematical matrices (G matrix and H matrix) calculated in the previous step into synthesizable hardware description language (HDL) code, such as Verilog or VHDL code (Register Transfer Level, RTL).
[0040] Parse the matrix and generate code for key components (key component generation): Encoder module code generation: Analyze the structure of the generator matrix (G) and automatically generate an encoder module. The RTL code of this module implements matrix multiplication logic, with k-bit raw data as input and n-bit codewords as output (containing raw data and parity bits). When t=4, the encoder logic will automatically adapt to generate parity bits of the corresponding number of bits.
[0041] Decoder and Error Correction Logic Module Code Generation: This module analyzes the structure of the parity check matrix (H) and integrates pre-defined error localization algorithms (such as the Berlekamp-Massey algorithm and the Qian search algorithm) to automatically generate the decoder and error correction logic module. The RTL code for this module includes: Syndrome calculation unit: Calculates the syndrome of the received codeword using the H matrix.
[0042] Error location polynomial calculation unit (based on a preset algorithm).
[0043] Error location search and correction unit.
[0044] When t=4, all generated computational units (such as register width, number of iterations, and lookup table size) will be automatically constructed to correct 4-bit errors.
[0045] Integrate key components to generate complete IP core design code (component integration): The automatically generated encoder module, decoder, and error correction logic module are instantiated and interconnected according to a predetermined data flow interface (such as AXI-Stream or a custom parallel interface). Simultaneously, necessary input / output ports, clock and reset logic are added, integrating them into a complete top-level module code file named ecc_core_t4, which is an ECC error correction IP core. This code is synthesizable and can be directly used for FPGA or ASIC logic synthesis.
[0046] Step S104: Based on the configuration parameters, synchronously generate verification code for verifying the ECC error correction IP core. The system synchronously generates a set of dedicated verification environment code for ecc_core_t4 based on the same configuration parameter t=4, typically using SystemVerilog / UVM or a similar verification methodology.
[0047] Generate key verification component code: Test stimulus generation module code: This module is configured to know t=4. It can automatically generate a large number of test vectors, including: random data, boundary case data, and, crucially, error patterns that can simulate injecting 1-bit, 2-bit, 3-bit, and even 4-bit random errors. It ensures that the test fully covers the error correction capabilities claimed by the IP core.
[0048] Reference Model Module Code: This module is a behavioral-level (non-RTL) software model whose functionality strictly matches the expected behavior of ecc_core_t4. It receives the same test stimuli (data and injected errors) and computes the corrected error-corrected result as the expected output (Golden Reference) through a software algorithm.
[0049] Response inspection module code: This module automatically compares the actual output of ecc_core_t4 (the design under test) with the expected output of the reference model. If an inconsistency is found, it immediately logs the error and reports it, indicating the test stimulus under which the problem occurred.
[0050] Integrate verification components and build verification environment code (simulation verification environment integration): Integrate the above-mentioned stimulus generator, reference model and checker, along with necessary clock generator, scoreboard, coverage collection module, etc., according to the standard verification platform architecture to form a complete test platform (Testbench) top-level module tb_ecc_core_t4.
[0051] Step S105: Integrate the hardware design code with the verification code to form the final design verification environment: This step corresponds to the output integration of the entire process. The system encapsulates the ecc_core_t4.v (design) generated in step S103 and the tb_ecc_core_t4.sv (verification environment) generated in step S104.
[0052] In the verification environment, the ecc_core_t4 module is instantiated as the design under test (DUT).
[0053] All verification components in the verification environment connect to the DUT through defined interfaces.
[0054] The final product is a ready-to-use project package. Users only need to run a simulation tool (such as ModelSim, VCS, etc.), load this project package, and they can begin a comprehensive functional verification of the ECC error correction IP core with t=4, without any manual setup or modification.
[0055] Output and Effects: After completing all the above steps, the system outputs two core files: Synthesizable ECC error correction IP core hardware design code (ecc_core_t4.v).
[0056] The corresponding complete simulation verification environment code (tb_ecc_core_t4.sv).
[0057] Both code snippets originate from the initial parameter t=4 and are a perfect match. If the user requirement changes to t=2, simply re-enter the parameter, and the above process will run automatically, outputting ecc_core_t2.v and tb_ecc_core_t2.sv. The entire process requires no manual intervention or secondary modification of the code by designers or verifiers, achieving full automation from parameters to finished product. This greatly improves the efficiency and reliability of design verification and ensures the configurability and flexibility of the IP core.
[0058] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.
Claims
1. A design verification and implementation method for an ECC error correction IP core with configurable error correction bit width, characterized in that, Includes the following steps: Receive error correction bit configuration parameters; Based on the error correction bit configuration parameters, the corresponding ECC error correction matrix data is generated; Based on the ECC error correction matrix data, the hardware design code constituting the ECC error correction IP core is automatically generated; Based on the error correction bit configuration parameters, verification code for verifying the ECC error correction IP core is generated synchronously; The hardware design code and the verification code are integrated to form an ECC error correction IP core design verification environment with configurable error correction bits.
2. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 1, characterized in that: The step of automatically generating hardware design code that constitutes the ECC error correction IP core based on the ECC error correction matrix data includes the following steps: The ECC error correction matrix data is parsed into multiple key design component codes that constitute the ECC error correction IP core; The code of multiple key design components is integrated to generate complete ECC error correction IP core hardware design code.
3. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 2, characterized in that: The step of synchronously generating verification code for verifying the ECC error correction IP core based on the error correction bit configuration parameters includes the following steps: Based on the error correction bit configuration parameters, generate key verification component code corresponding to the ECC error correction IP core function; The code of the key verification components is integrated to construct a verification environment code for simulating and verifying the ECC error correction IP core.
4. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 1, characterized in that: After the method is integrated to form a design verification environment, it also includes the following steps: Outputs hardware design code and verification environment code for ECC error correction IP core with configurable error correction bits; The hardware design code and verification environment code are directly associated with the error correction bit configuration parameters, and no manual secondary modification is required for different error correction bit values.
5. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 1, characterized in that: The step of generating the corresponding ECC error correction matrix data based on the error correction bit configuration parameters includes the following steps: Based on the error correction bit configuration parameters, determine the algorithm type and order of the ECC error correction algorithm; Based on the determined algorithm type and order, the ECC error correction matrix data used for hardware implementation of the encoding and decoding logic is calculated.
6. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 1, characterized in that: The hardware design code is synthesizable register-transfer level hardware description language code; the verification code is test platform code suitable for simulation verification, including a test stimulus generation module and a response checking module.
7. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 2, characterized in that: The code for the multiple key design components includes: encoder module code, decoder module code, and error correction logic module code; The encoder module code, decoder module code, and error correction logic module code are all generated based on the ECC error correction matrix data, and their internal logic structures are adapted to the error correction bit configuration parameters.
8. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 2, characterized in that: The step of parsing the ECC error correction matrix data into multiple key design component codes constituting the ECC error correction IP core includes the following steps: Identify the parity check matrix and generator matrix in the ECC error correction matrix data; Based on the structure and elements of the parity check matrix, generate decoder module code for verifying data and producing syntactic data. Based on the structure and elements of the generated matrix, encoder module code for calculating and attaching check bits is generated; Based on the parity check matrix and the preset error location algorithm, error correction logic module code is generated to locate and correct data bit errors according to the syndrome.
9. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 3, characterized in that: The step of generating key verification component code corresponding to the ECC error correction IP core function based on the error correction bit configuration parameters includes the following steps: The code for the test stimulus generation module is configured to automatically generate test data vectors covering different error correction bits and corresponding injection error modes based on the error correction bit configuration parameters. Generate reference model module code, which is configured to implement a behavioral-level model consistent with the expected function of the ECC error correction IP core based on the error correction bit configuration parameters, and to generate the expected output; Generate response checking module code, which is configured to compare the actual output of the ECC error correction IP core with the expected output of the reference model module and automatically report the verification results.
10. The design verification and implementation method of the ECC error correction IP core with configurable error correction bits according to claim 1, characterized in that: The process of integrating the hardware design code with the verification code to form a design verification environment for an ECC error correction IP core with configurable error correction bits includes the following steps: Configure the hardware design code as the design-to-test module in the verification environment; Configure the verification code as a core verification component for stimulus generation, response checking, and environmental control. According to the predefined verification platform architecture and communication interface, the design under test module and the core verification component are interconnected and encapsulated to generate a complete top-level test platform module that can directly drive simulation.