Clock tree design method for JESD204B and JESD204C interface converters

Abstract

The invention discloses a clock tree design method for JESD204B and JESD204C interface converters. The clock tree design method comprises the steps of clock source switching design, adjustable reference clock design, sampling clock and interface clock generation and the like. According to the invention, a clock chip is adopted to realize switching between a crystal oscillator clock source and an external clock source, and various clock source configuration schemes are realized; a clock source is connected to an adjustable clock chip, two paths of adjustable reference clocks are generated, and high flexibility is achieved; one path of reference clock is connected to a clock chip capable of adjusting the output frequency in a large range and is used for providing a sampling clock for the converter; and the other reference clock is connected to a clock chip which can output clocks meeting the requirements of JESD204B and JESD204C interfaces and is used for providing the interface clocks. Through the method provided by the invention, the sampling clock and the interface clock can be provided for JESD204B and JESD204C interface converters, and the sampling clock and the interface clock can be flexibly adjusted, so that the clock requirements of various converters are met.

Description

TECHNICAL FIELD

[0001] The application relates to a clock tree design method for a JESD204B and JESD204C interface converter and belongs to the technical field of integrated circuit testing. BACKGROUND

[0002] With the development of ADC and DAC performance towards high speed and high precision, the converter data transmission interface rate is continuously improved, from the traditional CMOS to LVDS, and then to CML, and the interface complexity is continuously improved. The JESD204B and JESD204C protocols can respectively realize a maximum single Lane rate of 12.5 Gbps and 32.45 Gbps, and support up to 8 lanes, have the advantages of fast transmission rate and few occupied pins, and are widely applied to converters such as ADCs and DACs. However, the JESD204B and JESD204C protocol interfaces are more complex, and the clock tree design during device operation has a certain complexity. In addition, the required clock signal frequencies are different between different converters and between different sampling rates of the same converter. Therefore, a clock tree design method with flexible adjustable output clock frequency to meet the working requirements of JESD204B and JESD204C interface converters is needed, which is suitable for the working requirements of multiple different converters, so as to improve the universality and applicability of the design. SUMMARY

[0003] The technical problem solved by the application is to overcome the shortcomings of the prior art and provide a clock tree design method with flexible adjustable output clock frequency to meet the working requirements of JESD204B and JESD204C interface converters. Through a series of clock chips, switching of different clock sources and output of different sampling frequencies are realized, and the method has high flexibility and applicability. Through the method, the working requirements of multiple different converters can be met by one-time design, thereby improving the clock design efficiency and reducing the design time.

[0004] The object of the application is achieved by the following technical scheme:

[0005] A clock tree design method for a JESD204B and JESD204C interface converter, comprising:

[0006] Step S1: clock source switching design is performed, a clock chip T1 is used to realize switching of a crystal oscillator clock source and an external clock source, and a plurality of clock source configurations are realized;

[0007] Step S2: reference clock design is performed, the clock source output by the clock chip T1 in step S1 is connected to an output frequency adjustable clock chip T2, and two frequency adjustable reference clocks are generated;

[0008] Step S3: Design the converter sampling clock by connecting one of the reference clocks generated in step S2 to a clock chip T3 with a wide range of adjustable output frequency to generate the converter sampling clock.

[0009] Step S4: Design the interface clock for JESD204B and JESD204C. Connect the other reference clock generated in step S2 to a clock chip T4 that can output clocks that meet the requirements of the JESD204B and JESD204C interface clocks to generate the interface clock.

[0010] Furthermore, in step S1, the clock source switching design refers to providing the same clock source for the converter sampling, the converter's JESD204B or JESD204C interface, and the JESD204B or JESD204C interface of the chip used in conjunction with the converter.

[0011] Furthermore, the chip used in conjunction with the converter refers to the chip that is connected to the converter when the converter is working and transmits data or instructions with the converter.

[0012] Furthermore, in step S1, the clock chip T1 refers to a clock chip with at least two input clock signals and at least two output clock signals; the clock chip T1 has an input clock signal selection function to realize the switching of input clock signals; the input clock path supports single-ended clock signals or differential clock signals, and the output clock path supports differential clock signals; the frequency range of the input and output clock signals supported by the clock chip T1 covers a frequency point of 10MHz.

[0013] Furthermore, in step S2, the reference clock design refers to generating two adjustable frequency reference clocks using a clock chip with an adjustable output frequency, based on the clock source provided by clock chip T1 in step S1; the clock chip T2 refers to a clock chip with fractional frequency division function; the clock chip T2 outputs clock signal frequencies covering 10MHz-500MHz, with at least two output clock paths, and the output clock paths support differential clock signals.

[0014] Furthermore, in step S3, the converter sampling clock design refers to using an adjustable output frequency clock chip to provide an adjustable sampling clock for the ADC and DAC based on the reference clock signal provided by the clock chip T2 in step S2.

[0015] Furthermore, in step S3, the clock chip T3 refers to a clock chip with a fractional frequency division function. The clock chip T3 outputs a clock signal frequency that can be adjusted over a wide range, covering 10MHz-15GHz, and the output clock path supports differential clock signals.

[0016] Furthermore, in step S4, the JESD204B and JESD204C interface clock design refers to using a clock chip T4, based on the reference clock signal provided by clock chip T3 in step S3, to provide the working clock for the JESD204B or JESD204C interface of the converter and the JESD204B or JESD204C interface of the chip used in conjunction with the converter; the clock chip T4 refers to a clock chip whose output meets the clock requirements of the JESD204B and JESD204C interface, and whose output clock path supports differential clock signals.

[0017] Furthermore, clock chip T1 uses the LMK00304 chip; clock chip T2 uses the LMX2594 chip; clock chip T3 uses either the LMX2594 or LMX2595 chip; and clock chip T4 uses the HMC7044 chip.

[0018] This invention employs a series of clock chips to achieve switching between different clock sources and flexible adjustment of different sampling clocks and interface operating clocks, offering the following advantages compared to existing methods:

[0019] 1) The frequency of the clock signal generated by the method of the present invention can be adjusted over a wide range, thus it can be applied to different models of ADC and DAC products, has wide applicability, can improve clock design efficiency and reduce design time;

[0020] 2) The method of the present invention can switch between crystal oscillator clock and external reference clock, thereby enabling the selection of multiple clock sources and making it suitable for a wider range of application scenarios. Attached Figure Description

[0021] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0022] Figure 1 This is a schematic diagram of the overall framework of the method of the present invention;

[0023] Figure 2 This is a schematic diagram illustrating one implementation of the method of the present invention; Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Converters with JESD204B and JESD204C interfaces require multiple clock sets for operation, including the converter sampling clock, the converter's JESD204B or JESD204C interface clock, and the JESD204B or JESD204C interface clock of the chip used with the converter. Furthermore, the required clock signal frequencies differ between different converters and between different sampling rates of the same converter. Repeatedly designing clock trees for different converters increases design complexity. This invention proposes a clock tree design method with flexibly adjustable output clock frequencies to meet the operational requirements of JESD204B and JESD204C interface converters. Through a series of clock chips, it achieves switching between different clock sources and output at different sampling frequencies, offering high flexibility and applicability. This method allows for a single design to meet the operational requirements of multiple different converters, thereby improving clock design efficiency and reducing design time.

[0026] The meanings of the English abbreviations used in this invention are as follows:

[0027] JESD204B: A high-speed data transmission interface;

[0028] JESD204C: A high-speed data transmission interface;

[0029] ADC: Analog-to-Digital Converter;

[0030] DAC: Digital-to-Analog Converter;

[0031] ATE: Automatic Test Equipment;

[0032] FPGA: Field-Programmable Gate Array;

[0033] Lane: The physical channel for data transmission;

[0034] ASIC: Application Specific Integrated Circuit.

[0035] Figure 1 This is a schematic diagram of the overall framework of the method of the present invention. Figure 1 The arrows in the image represent clock signals, and their specific meanings are as follows:

[0036] ①: The crystal oscillator provides the clock source signal for the clock chip T1;

[0037] ②: The signal source is the clock source signal provided by the clock chip T1;

[0038] ③: Clock chip T1 provides the clock source signal for clock chip T2;

[0039] ④: Clock chip T2 provides the reference clock signal for clock chip T3;

[0040] ⑤: Clock chip T2 provides the reference clock signal for clock chip T4;

[0041] ⑥: Clock chip T3 provides the clock signal for the converter;

[0042] ⑦: Clock chip T4 provides the clock signal for the converter and the working clock signal for the converter and the interfaces of the JESD204B and JESD204C chips used with the converter.

[0043] This invention proposes a clock tree design method for JESD204B and JESD204C interface converters, the steps of which include:

[0044] Step S1: Clock source switching design. A clock chip T1 is used to switch between the crystal oscillator clock source and the external clock source, realizing multiple clock source configuration schemes.

[0045] Step S2: Reference clock design. Connect the clock source from step S1 to a clock chip T2 with an adjustable output frequency to generate two adjustable reference clocks.

[0046] Step S3: Converter sampling clock design. Connect one of the reference clocks from step S2 to a clock chip T3 with a wide range of adjustable output frequency to generate the converter sampling clock.

[0047] Step S4: JESD204B and JESD204C interface clock design. Connect the other reference clock from step S2 to a clock chip T4 that can output clocks that meet the requirements of the JESD204B and JESD204C interface clocks, and use it to generate the interface clock.

[0048] In step S1, the clock source switching design refers to providing a common clock source for the converter sampling, the converter's JESD204B or JESD204C interface, and the JESD204B or JESD204C interface of the chip used with the converter. In step S1, the chip used with the converter refers to a chip connected to the converter during operation, transmitting data or instructions with it, such as an FPGA or ASIC. In step S1, the clock chip T1 refers to a clock chip with at least two input clock signals and at least two output clock signals. This clock chip has an input clock signal selection function, enabling switching of the input clock signals. The input clock path should support single-ended clock signals or differential clock signals, and the output clock path should support differential clock signals. The frequency range of the input and output clock signals supported by the clock chip should cover a 10MHz frequency point.

[0049] In step S2, the reference clock design refers to generating two adjustable-frequency reference clocks using a clock chip with an adjustable output frequency, based on the source clock provided in step S1. In step S2, the clock chip T2 refers to a clock chip with fractional divider functionality. This clock chip outputs a clock signal frequency covering 10MHz-500MHz, has at least two output clock paths, and these output clock paths should support differential clock signals.

[0050] In step S3, the converter sampling clock design refers to using an adjustable-frequency clock chip to provide an adjustable sampling clock for the ADC and DAC based on the reference clock signal provided in step S2. In step S3, the clock chip T3 refers to a clock chip with fractional division functionality. The output clock signal frequency of this clock chip can be adjusted over a wide range, covering 10MHz-15GHz, and the output clock path should support differential clock signals.

[0051] In step S4, the JESD204B and JESD204C interface clock design refers to using a clock chip T4, based on the reference clock signal provided in step S2, to provide the operating clock for the JESD204B or JESD204C interface of the converter and the JESD204B or JESD204C interface of the chip used with the converter. In step S4, the clock chip T4 refers to a clock chip capable of outputting clocks that meet the requirements of the JESD204B and JESD204C interface clocks, and the output clock path should support differential clock signals.

[0052] Example:

[0053] Figure 2This is a schematic diagram of one implementation of the method of the present invention, comprising one LMK00304 chip, two LMX2594 chips, and one HMC7044 chip, capable of implementing a sampling clock and corresponding interface operating clock within the range of 10MHz-15GHz. Figure 2 The method of the present invention will be described in detail using examples.

[0054] A clock tree design method for JESD204B and JESD204C interface converters, comprising the following steps:

[0055] Step S1: Use clock chip LMK00304 to switch the clock source.

[0056] The LMK00304 can switch between three inputs: two are general-purpose input channels supporting signal frequencies up to 3.1 GHz and supporting LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks; the other is a crystal clock input supporting crystal clocks from 10 MHz to 40 MHz or single-ended clocks. The LMK00304 outputs are divided into two groups, each with two differential outputs, supporting LVPECL, LVDS, HCSL, or Hi-Z modes. Using the LMK00304, switching between the three input clock sources can be achieved, providing four differential clocks, meeting the method requirements.

[0057] Step S2: Implement the reference clock design using the LMX2594 clock chip.

[0058] Connect one output clock signal of the LMK00304 to the input channel of the LMX2594. By configuring the LMX2594 chip, two adjustable output clocks can be generated. The LMX2594 input clock range is 5MHz-1400MHz, and the output clock range is 10MHz-15GHz. The output clock can be single-ended or differential, meeting the method requirements.

[0059] Step S3: Use the clock chip LMX2594 to generate a sampling clock for the converter.

[0060] Connect one clock output signal of the LMX2594 chip from step S2 to the input channel of another LMX2594 chip. By configuring this LMX2594 chip, two adjustable clock signals are output to provide sampling clocks for the converter. Due to the inherent characteristics of the LMX2594, the output clock range is 10MHz-15GHz, which meets the method requirements.

[0061] It is worth noting that replacing the LMX2594 chip in this step with other chips can produce clock signals in other frequency ranges. For example, replacing it with an LMX2595 chip can generate clock signals in the 10MHz-20GHz frequency range. This chip can be selected according to the actual sampling clock range of the converter required for the application.

[0062] Step S4: Use the HMC7044 chip to generate the JESD204B and JESD204C interface clocks.

[0063] Connect the other clock output signal of LMX2594 in step S2 to the CLKIN1 / FIN channel of an HMC7044. By programming the HMC7044, the clock signal required for the operation of the converter and the JESD204B or JESD204C interface of the chip used with the converter can be generated.

[0064] Taking an FPGA chip as an example, which is used in conjunction with the converter, Figure 2 The functions of each output signal are as follows:

[0065] JESD_REFCLK0, JESD_REFCLK1, JESD_REFCLK3, and JESD_REFCLK4 are high-speed interface reference clock signals connecting the FPGA to the converter data path. Different signals can be connected to different high-speed interfaces of the FPGA, thereby enabling parallel use of multiple converters. This embodiment can directly provide four independent clock signals to the four high-speed interfaces of the FPGA, which can meet the clock requirements of multiple JESD204B and JESD204C interfaces with different numbers of transmission channels from 1 to 8 lanes.

[0066] TO_DUT_SYSREF0, TO_DUT_SYSREF1, and TO_DUT_SYSREF2: These are the converter interface synchronization clocks, used to synchronize multiple converters. In this embodiment, three independent synchronization clocks can be directly provided to different converters.

[0067] DUT_CLK0, DUT_CLK1, and DUT_CLK2: These are the converter sampling clocks. Different output signals can provide sampling signals for different converters. In this embodiment, three independent sampling signals can be directly provided to different converters. The clock range of the LMX2594 output is any frequency within the range of 10MHz-15GHz, and the clock range of the HMC7044 output is 2.4GHz-3.2GHz and its integer division range.

[0068] JESD_GLBCLK0, JESD_GLBCLK1, and JESD_GLBCLK2 are the core clocks required for the JESD204B and JESD204C interfaces in the FPGA. They are integer multiples of the high-speed interface line rate and are related to the interface type used. For example, for the JESD204B interface, the core clock frequency is 1 / 40th of the line rate. In this embodiment, three independent core clocks can be directly provided to different JESD204B and JESD204C interfaces on the FPGA.

[0069] JESD_SYSREF0, JESD_SYSREF1, and JESD_SYSREF2: These are the synchronization clocks for the JESD204B and JESD204C interfaces in the FPGA. They function identically to the TO_DUT_SYSREF0 signal and are used to synchronize multiple JESD204B and JESD204C interfaces. In this embodiment, three independent synchronization clocks can be directly provided to different JESD204B and JESD204C interfaces on the FPGA.

[0070] 10MHz signal source clock: A 10MHz clock provided by a signal source or other instrument is used to provide the clock source for the clock tree. It should be noted that this clock does not have to be 10MHz. Since most instruments can generate a 10MHz reference clock, this embodiment uses 10MHz for ease of application.

[0071] 10MHz Crystal Clock: A 10MHz clock generated by a crystal oscillator is used to provide the clock source for the clock tree. It should be noted that this clock does not have to be 10MHz. Considering that matching the clock provided by the instrument reduces the difficulty of clock tree programming, this embodiment uses 10MHz for ease of application.

[0072] Signal source clock: Connected to the CLKIN2 / OSCOUT channel of the HMC7044 chip. A clock signal that meets the input requirements of the HMC7044 can be provided by instruments.

[0073] 100MHz Crystal Clock: A 100MHz clock generated by the crystal oscillator is used to provide a reference for the HMC7044. It should be noted that this clock does not have to be 100MHz. Considering the usage of the HMC7044 chip, for ease of application, this embodiment is set to 100MHz.

[0074] It should be noted that the allocation of the clock signal output by the LMX2594 chip in step S3 and the clock signal output by the HMC7044 chip in step S4 can be changed according to actual needs and is not limited to the allocation scheme shown in this embodiment.

[0075] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A clock tree design method for JESD204B and JESD204C interface converters, characterized in that, include: Step S1: Design a clock source switching mechanism, using clock chip T1 to switch between crystal oscillator clock source and external clock source, enabling multiple clock source configurations; Step S2: Design a reference clock by connecting the clock source output by clock chip T1 in step S1 to clock chip T2 with adjustable output frequency to generate two adjustable reference clocks. Step S3: Design the converter sampling clock by connecting one of the reference clocks generated in step S2 to a clock chip T3 with a wide range of adjustable output frequency to generate the converter sampling clock. Step S4: Design the interface clock for JESD204B and JESD204C. Connect the other reference clock generated in step S2 to a clock chip T4 that can output clocks that meet the requirements of the JESD204B and JESD204C interface clocks to generate the interface clock.

2. The clock tree design method for JESD204B and JESD204C interface converters according to claim 1, characterized in that: In step S1, the clock source switching design refers to providing the same clock source for the converter sampling, the converter's JESD204B or JESD204C interface, and the JESD204B or JESD204C interface of the chip used with the converter.

3. The clock tree design method for JESD204B and JESD204C interface converters according to claim 2, characterized in that: The chip used in conjunction with the converter refers to the chip that is connected to the converter when the converter is working and transmits data or instructions to the converter.

4. The clock tree design method for JESD204B and JESD204C interface converters according to claim 2, characterized in that: In step S1, the clock chip T1 refers to a clock chip with at least two input clock signals and at least two output clock signals; the clock chip T1 has an input clock signal selection function to realize the switching of input clock signals; The input clock path supports single-ended clock signals or differential clock signals, and the output clock path supports differential clock signals. The clock chip T1 supports input and output clock signals with a frequency range covering 10MHz.

5. The clock tree design method for JESD204B and JESD204C interface converters according to claim 1, characterized in that: In step S2, the reference clock design refers to generating two adjustable reference clocks using a clock chip with an adjustable output frequency, based on the clock source provided by the clock chip T1 in step S1. The clock chip T2 is a clock chip with a fractional frequency division function; the clock chip T2 outputs clock signals with a frequency range of 10MHz-500MHz, has at least two output clock paths, and the output clock paths support differential clock signals.

6. The clock tree design method for JESD204B and JESD204C interface converters according to claim 1, characterized in that: In step S3, the converter sampling clock design refers to using an adjustable output frequency clock chip to provide an adjustable sampling clock for the ADC and DAC based on the reference clock signal provided by the clock chip T2 in step S2.

7. A clock tree design method for JESD204B and JESD204C interface converters according to claim 6, characterized in that: In step S3, the clock chip T3 refers to a clock chip with fractional frequency division function. The clock chip T3 outputs a clock signal frequency that can be adjusted over a wide range, covering 10MHz-15GHz, and the output clock path supports differential clock signals.

8. A clock tree design method for JESD204B and JESD204C interface converters according to claim 1, characterized in that: In step S4, the JESD204B and JESD204C interface clock design refers to using a clock chip T4, based on the reference clock signal provided by clock chip T3 in step S3, to provide the working clock for the JESD204B or JESD204C interface of the converter and the JESD204B or JESD204C interface of the chip used in conjunction with the converter; the clock chip T4 refers to a clock chip whose output meets the clock requirements of the JESD204B and JESD204C interfaces, and whose output clock path supports differential clock signals.

9. A clock tree design method for JESD204B and JESD204C interface converters according to claim 1, characterized in that: Clock chip T1 uses the LMK00304 chip; clock chip T2 uses the LMX2594 chip; clock chip T3 uses either the LMX2594 or LMX2595 chip; and clock chip T4 uses the HMC7044 chip.

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