Graph neural network sampling accelerator

Abstract

The invention discloses a graph neural network sampling accelerator, which belongs to the technical field of hardware acceleration, and comprises a scheduling control module, a cache module and a sampling execution module, wherein the cache module realizes prefetching of blocks required by tasks through double cache units and multi-channel loading, and the cache units are alternately switched to realize overlapping of memory access and calculation, so that the off-chip memory access delay is remarkably reduced, and the off-chip bandwidth utilization rate is improved; on the basis, the scheduling control module dynamically segments high-load tasks and combines low-load tasks according to node degrees, one sub-neighbor node sampling task corresponds to one independent thread, neighbor node sampling tasks of a plurality of low-degree nodes correspond to one independent thread after being combined, and the task slices are combined with the low-degree nodes through degree sensing. The problem of load imbalance caused by a long tail node is solved, multiple threads can efficiently work in parallel, and the overall sampling throughput rate is increased.

Description

Technical Field

[0001] This invention belongs to the field of hardware acceleration technology, and more specifically, relates to a graph neural network sampling accelerator. Background Technology

[0002] The training / inference of Graph Neural Networks (GNNs) can be divided into two processes: neighbor sampling and model training / inference. It can train large datasets with relatively low computational complexity. By sampling a given number of neighboring nodes and aggregating only their information during training, networks that perform sampling and aggregation can train large graphs at a relatively low cost while maintaining test accuracy. However, compared to other processes in GNNs, the sampling process still consumes a significant amount of time and computational resources, limiting the training speed. For example, on the Reddit dataset, when training with a traditional GraphSAGE network, the sampling process accounts for 62.7% to 85.6% of the total training / inference time. This is because the traditional sampling process frequently accesses the graph structure and feature vectors, and existing general-purpose processors (CPUs, GPUs) are not well-suited for sampling-based GNN training. Therefore, hardware acceleration of the sampling process is essential.

[0003] However, during the sampling process, ① the program needs to frequently access the degree table and edge table stored off-chip. The access patterns are highly random and span a large range, resulting in high memory access latency and low bandwidth utilization, leading to long waiting times for computing units and overall pipeline stalls. ② In addition, the node degree distribution of actual graph data exhibits a long-tail characteristic, with sampling time for high-degree nodes being significantly longer than that for low-degree nodes. If tasks are statically allocated, it is easy for some pipelines to be idle while others are blocked, resulting in an unbalanced load and a decrease in overall throughput.

[0004] To address these issues, existing research often employs multi-threaded CPU or GPU kernels for sampling, or performs sampling as a preprocessing step. However, the CSR / edge table is highly discrete off-chip, making it difficult for random long-distance accesses initiated by threads / warps to achieve merged accesses and cache hits. Simultaneously, the power-law degree distribution leads to abnormally high task latency for individual height nodes, and static or coarse-grained scheduling results in long-tail blocking. Furthermore, preprocessing sampling introduces massive storage / I / O overhead for persistent subgraphs and lacks adaptability to parameter changes and runtime load, still failing to avoid random accesses and long-tail blocking during training. Therefore, these methods cannot fundamentally solve the problems of high off-chip memory access latency and unbalanced load, making it difficult to fully utilize the hardware's potential in large-scale training scenarios. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a graph neural network sampling accelerator to solve the problems that the existing technology cannot fundamentally solve, such as the high cost of off-chip random access during graph neural network sampling and the unbalanced task load caused by the long tail of node degree distribution.

[0006] To achieve the above objectives, the present invention provides a graph neural network sampling accelerator for sampling graph data during the training process of a graph neural network; the graph data includes multiple nodes and edges representing connections between nodes; wherein, nodes connected to a node are considered as neighboring nodes of that node; The sampling accelerator is implemented in hardware and includes: a scheduling control module, a cache module, and a sampling execution module; The scheduling and control module reads the degree table corresponding to the graph data to be computed from the off-chip storage module, and designates nodes with a degree greater than or equal to a preset degree as height nodes and nodes with a degree less than a preset degree as low-degree nodes. It divides the neighbor node sampling task of each height node into multiple sub-neighbor node sampling tasks, and sets them together with the neighbor node sampling tasks of each low-degree node in a task sequence. It allocates a corresponding thread to each task to be executed in the task sequence; where one sub-neighbor node sampling task corresponds to one independent thread; multiple low-degree node neighbor node sampling tasks are merged and correspond to one independent thread. The caching module includes two caching units. The caching module reads the edge table corresponding to the graph data to be computed from the off-chip storage module, thereby obtaining the n-order neighbor nodes of each node to be computed, forming a node set S. The node sets corresponding to the current task to be executed and the next task to be executed in the task sequence are cached into the two caching units respectively; n≥1; when the node to be computed is a height node, the node set S is divided into node sets corresponding to each subtask according to the subtask partitioning method. The sampling execution module is used to sequentially execute the tasks to be executed in the task sequence: for each task to be executed, the corresponding thread is called to obtain the corresponding node set from the cache unit corresponding to the task to be executed and sample it. After sampling is completed, the corresponding cache unit is notified to clear the cache and start executing the next task to be executed in the task sequence until all tasks in the task sequence are completed. In this process, while one buffer unit is used by the sampling execution module to read the corresponding node set, another buffer unit reads the node set corresponding to the next task to be executed in parallel.

[0007] More preferably, the scheduling control module samples and allocates threads for tasks to neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. When there are still low-degree nodes in the node sequence that have not been selected, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. The placement operation performed on any thread t' includes: selecting a low-degree node that has not been selected before. and low-degree nodes The neighbor node sampling task is placed in thread t'; it sequentially selects a neighbor node from all currently unselected low-degree nodes. The most similar low-degree node is selected, and its neighbor node sampling tasks are placed sequentially in thread t'. The higher the overlap between the nth-order neighbor nodes of two low-degree nodes, the more similar they are.

[0008] More preferably, the above node sequence is a sequence of all nodes in the graph data sorted according to the topological order of the graph data; The above-mentioned placement operation for any thread t' includes: sequentially obtaining an unselected low-degree node from the node sequence, and placing its neighbor node sampling task in thread t' in turn.

[0009] More preferably, the off-chip storage module is used to divide the edge table and degree table corresponding to the graph data to be calculated into multiple storage areas for storage.

[0010] More preferably, the scheduling control module samples and allocates threads for tasks to neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Establish multiple arrays that correspond one-to-one with multiple storage areas in the off-chip storage module that store the edge tables and degrees corresponding to the graph data to be computed; Traverse the node sequence, selecting one low-degree node that has not been selected before at each step. ,Will Stored in storage The arrays corresponding to each storage area of ​​the edge table; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. When there are still unselected low-degree nodes in any array, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. The placement operation performed on any thread t' includes: When the number of sampling tasks in thread t' is 0: count the number of unselected low-degree nodes in each array. If the number is the same, select any array as the current execution array; otherwise, select the array with the most unselected low-degree nodes as the current execution array; determine if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, select the unselected low-degree node in the current execution array as the current execution node; if it is not 1, calculate the sum of similarities between each unselected low-degree node in the current execution array and other low-degree nodes, and select the unselected low-degree node with the largest sum of similarities as the current execution node; place the sampling tasks of the neighbor nodes of the current execution node in thread t', and use the current execution array as the source array of the current execution node. When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... If there are unselected low-degree nodes in the source array: use the source array as the current execution array; check if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, use the unselected low-degree nodes in the current execution array as the current execution nodes; otherwise, use the nodes in the current execution array that are not selected as the current execution nodes. The low-score node with the highest similarity that has not been selected is selected as the current execution node; the sampling task of the neighbor nodes of the current execution node is placed in thread t', and the current execution array is used as the source array of the current execution node; When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... When there are no unselected low-degree nodes in the source array: count the storage area where the edge table of the low-degree node corresponding to each neighbor node sampling task in thread t' is located, and take the storage area of ​​the storage area that appears most frequently and whose corresponding array contains unselected low-degree nodes as the target storage area; take the array corresponding to the target storage area as the current execution array; determine whether the number of unselected low-degree nodes in the current execution array is 1. If it is 1, take the unselected low-degree node in the current execution array as the current execution node; if it is not 1, take the unselected low-degree node in the current execution array that has the highest similarity to the low-degree node corresponding to the latest neighbor node sampling task in thread t' as the current execution node; put the neighbor node sampling task of the current execution node in thread t', and take the current execution array as the source array of the current execution node. For any low-degree nodes u and v, their similarity is:

[0011] in, Low-degree nodes The set of numbers of the storage area where the edge table is located; Low-degree nodes The set of numbers of the storage area where the edge table is located.

[0012] More preferably, the tasks to be executed in the task sequence are arranged in descending order according to their first priority score; Among them, any task to be executed The first priority rating is:

[0013] , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time.

[0014] More preferably, the scheduling control module is also used to calculate the second priority score of each task to be executed in the task sequence in real time during the operation of the accelerator, and to arrange the tasks to be executed in the task sequence in descending order according to their second priority scores, so as to update the task sequence in real time. Among them, any task to be executed The second priority rating is:

[0015] , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time; Tasks to be performed The waiting time.

[0016] More preferably, for each task to be executed, the sampling execution module calls the corresponding thread to obtain the corresponding node set from the cache unit corresponding to the task to be executed, and then performs the sampling operation in the following way: calling the parallel random number generator to generate multiple sampling indices, and sampling in parallel from the corresponding node set based on each sampling index.

[0017] More preferably, the preset degree is the degree of the sequence of all nodes in the degree table corresponding to the graph data to be calculated, arranged in ascending order, at the quantile q; where q is 90–95%.

[0018] More preferably, the preset degree is the degree of the sampled degree sequence at quantile p; wherein, the sampled degree sequence is the sequence of degrees obtained by randomly sampling all the node degrees in the degree table corresponding to the graph data to be calculated according to a ratio p and sorting each degree in ascending order; p is 1–5%.

[0019] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: 1. This invention provides a graph neural network sampling accelerator, comprising: a scheduling control module, a cache module, and a sampling execution module. The cache module prefetches the blocks required for a task through dual buffer units and multi-channel loading. One buffer unit allows the sampling execution module to read the corresponding node set, while the other buffer unit prefetches the node set corresponding to the next task to be executed in parallel. The cache units alternate to achieve overlap between memory access and computation, significantly reducing off-chip memory access latency and improving off-chip bandwidth utilization. Based on this, the scheduling control module dynamically segments high-load tasks and merges low-load tasks according to node degree. A sampling task for a child neighbor node corresponds to an independent thread, and the sampling tasks of multiple low-degree nodes' neighbor nodes are merged to correspond to an independent thread. By merging degree-aware task slices with low-degree nodes, the load imbalance problem caused by long-tail nodes is solved, enabling multiple threads to work efficiently in parallel and improving the overall sampling throughput. Therefore, this invention fundamentally solves the problems of high random memory access costs in graph neural network sampling and the task load imbalance caused by long-tail node degree distribution, significantly shortening the training time of graph neural networks, especially the training time of large-scale graph neural networks.

[0020] 2. Furthermore, the graph neural network sampling accelerator provided by the present invention prioritizes merging the neighbor node sampling tasks of multiple low-degree nodes with high overlap of n-order neighbor nodes into an independent thread, which better avoids the load imbalance problem caused by long-tail nodes and further improves the overall sampling throughput.

[0021] 3. Furthermore, the graph neural network sampling accelerator provided by the present invention makes full use of the topological characteristics of graph data to determine the selection order of low-degree nodes that have not been selected, and merges the sampling tasks of the neighbor nodes of low-degree nodes into an independent thread according to the topological order of graph data, so that the similarity does not need to be calculated repeatedly each time it is merged, thereby further improving the computational efficiency.

[0022] 4. Furthermore, the graph neural network sampling accelerator provided by this invention considers that the neighbor set of low-degree nodes is small and the task granularity is fine, but their adjacency lists often fall in nearby edge table blocks. This invention merges multiple low-degree nodes with highly overlapping edge table blocks into the same batch of tasks, which can significantly reuse loaded storage area blocks, reduce the number of off-chip accesses and cross-block jumps, thereby improving bandwidth utilization and cache hit rate. On this basis, this invention introduces overlap (i.e., similarity) estimation, only merging those tasks with "highly overlapping data footprints" to avoid invalid merging.

[0023] 5. Furthermore, in the graph neural network sampling accelerator provided by the present invention, the tasks to be executed in the task sequence are arranged in descending order according to their first priority score; the first priority is determined based on the number of nodes in the node set corresponding to the task, the number of preset neighbor node samples, and the number of storage area blocks in the off-chip storage module expected to be accessed when executing the task. Through priority scheduling, the overall sampling throughput is further improved.

[0024] 6. Furthermore, in the graph neural network sampling accelerator provided by this invention, in order to further avoid long-waiting small tasks repeatedly preempting scheduling resources, leading to fragmentation of the scheduling cycle, frequent interruptions of off-chip prefetching, and reduced pipeline utilization and overall throughput, the scheduling control module is also used to calculate the second priority score of each task to be executed in the task sequence in real time during the operation of the accelerator, and arrange the tasks to be executed in the task sequence in descending order according to their second priority scores, so as to update the task sequence in real time; wherein, the second priority score not only takes into account the number of nodes in the node set corresponding to the task, the number of preset neighbor node samples, and the number of storage area blocks in the off-chip storage module expected to be accessed when executing the task, but also takes into account the waiting time of the task to be executed, so as to update the task sequence in real time, enabling task migration when blocked, and further improving the overall sampling throughput. Attached Figure Description

[0025] Figure 1 This is an architecture diagram of a graph neural network sampling accelerator provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the operation process of the graph neural network sampling accelerator provided in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] To achieve the above objectives, the present invention provides a graph neural network sampling accelerator for sampling graph data during the training process of a graph neural network; the graph data includes multiple nodes and edges representing connections between nodes; wherein, nodes connected to a node are considered as neighboring nodes of that node; The sampling accelerator is implemented in hardware and includes: a scheduling control module, a cache module, and a sampling execution module; The scheduling and control module reads the degree table corresponding to the graph data to be computed from the off-chip storage module, and designates nodes with a degree greater than or equal to a preset degree as height nodes and nodes with a degree less than a preset degree as low-degree nodes. It divides the neighbor node sampling task of each height node into multiple sub-neighbor node sampling tasks, and sets them together with the neighbor node sampling tasks of each low-degree node in a task sequence. It allocates a corresponding thread to each task to be executed in the task sequence; where one sub-neighbor node sampling task corresponds to one independent thread; multiple low-degree node neighbor node sampling tasks are merged and correspond to one independent thread. The caching module includes two caching units. The caching module reads the edge table corresponding to the graph data to be computed from the off-chip storage module, thereby obtaining the n-order neighbor nodes of each node to be computed, forming a node set S. The node sets corresponding to the current task to be executed and the next task to be executed in the task sequence are cached into the two caching units respectively; n≥1; when the node to be computed is a height node, the node set S is divided into node sets corresponding to each subtask according to the subtask partitioning method. The sampling execution module is used to sequentially execute the tasks to be executed in the task sequence: for each task to be executed, the corresponding thread is called to obtain the corresponding node set from the cache unit corresponding to the task to be executed and sample it. After sampling is completed, the corresponding cache unit is notified to clear the cache and start executing the next task to be executed in the task sequence until all tasks in the task sequence are completed. In this process, while one buffer unit is used by the sampling execution module to read the corresponding node set, another buffer unit reads the node set corresponding to the next task to be executed in parallel.

[0028] In one optional implementation, the scheduling control module samples and allocates threads for tasks to the neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. When there are still low-degree nodes in the node sequence that have not been selected, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. The placement operation performed on any thread t' includes: selecting a low-degree node that has not been selected before. and low-degree nodes The neighbor node sampling task is placed in thread t'; it sequentially selects a neighbor node from all currently unselected low-degree nodes. The most similar low-degree node is selected, and its neighbor node sampling tasks are placed sequentially in thread t'. The higher the overlap between the nth-order neighbor nodes of two low-degree nodes, the more similar they are.

[0029] Preferably, the above-mentioned node sequence is a sequence of all nodes in the graph data sorted according to the topological order of the graph data; wherein, firstly, the graph data is topologically sorted to calculate the topological level of each node, and the original node sequence is reordered based on the topological level; specifically, the nodes of each level are arranged into the node sequence in the order of the levels from front to back, thereby obtaining a hierarchical node sequence.

[0030] The above-mentioned placement operation for any thread t' includes: sequentially obtaining an unselected low-degree node from the node sequence, and placing its neighbor node sampling task in thread t' in turn.

[0031] The above method eliminates the need to repeatedly calculate similarity during each merge, and instead fully utilizes the topological characteristics of graph data to determine the selection order of low-degree nodes that have not been selected before, further improving computational efficiency.

[0032] In one optional implementation, the off-chip storage module is used to divide the edge table and degree table corresponding to the graph data to be calculated into multiple storage areas for storage.

[0033] In one optional implementation, the scheduling control module samples and allocates threads for tasks to the neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Establish multiple arrays that correspond one-to-one with multiple storage areas in the off-chip storage module that store the edge tables and degrees corresponding to the graph data to be computed; Traverse the node sequence, selecting one low-degree node that has not been selected before at each step. ,Will Stored in storage The arrays corresponding to each storage area of ​​the edge table; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. When there are still unselected low-degree nodes in any array, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. The placement operation performed on any thread t' includes: When the number of sampling tasks in thread t' is 0: count the number of unselected low-degree nodes in each array. If the number is the same, select any array as the current execution array; otherwise, select the array with the most unselected low-degree nodes as the current execution array; determine if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, select the unselected low-degree node in the current execution array as the current execution node; if it is not 1, calculate the sum of similarities between each unselected low-degree node in the current execution array and other low-degree nodes, and select the unselected low-degree node with the largest sum of similarities as the current execution node; place the sampling tasks of the neighbor nodes of the current execution node in thread t', and use the current execution array as the source array of the current execution node. When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... If there are unselected low-degree nodes in the source array: use the source array as the current execution array; check if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, use the unselected low-degree nodes in the current execution array as the current execution nodes; otherwise, use the nodes in the current execution array that are not selected as the current execution nodes. The low-score node with the highest similarity that has not been selected is selected as the current execution node; the sampling task of the neighbor nodes of the current execution node is placed in thread t', and the current execution array is used as the source array of the current execution node; When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... When there are no unselected low-degree nodes in the source array: count the storage area where the edge table of the low-degree node corresponding to each neighbor node sampling task in thread t' is located, and take the storage area of ​​the storage area that appears most frequently and whose corresponding array contains unselected low-degree nodes as the target storage area; take the array corresponding to the target storage area as the current execution array; determine whether the number of unselected low-degree nodes in the current execution array is 1. If it is 1, take the unselected low-degree node in the current execution array as the current execution node; if it is not 1, take the unselected low-degree node in the current execution array that has the highest similarity to the low-degree node corresponding to the latest neighbor node sampling task in thread t' as the current execution node; put the neighbor node sampling task of the current execution node in thread t', and take the current execution array as the source array of the current execution node. For any low-degree nodes u and v, their similarity is:

[0034] in, Low-degree nodes The set of numbers of the storage area where the edge table is located; Low-degree nodes The set of numbers of the storage area where the edge table is located.

[0035] Existing systems often mitigate random memory access by organizing degree / edge tables into tiles and using prefetching. However, in neighborhood sampling scenarios, access remains highly discrete, and the load fluctuates significantly with the long tail of node degree, making it difficult to consistently achieve high bandwidth and balanced parallelism. Therefore, more optimization methods are needed.

[0036] The degree table and edge table are physically divided into blocks in off-chip memory according to a configurable block size B (preferably 2–16KB) and alignment granularity (preferably 64–128B). Data within the same block is stored contiguously, and cross-block boundaries are filled according to alignment rules to ensure sequential access within the block. An index mapping table of tile_id→{channel_id, base_addr, length} is established and hot entries are cached on-chip. At runtime, based on the first PD tasks in the scheduling queue, the set of blocks that the task will access is predicted. After removing duplicates and sorting by physical address, multi-channel parallel prefetching is driven to double buffering. This degenerates the access to the discrete adjacency list during the sampling phase into a sequential retrieval of a small number of blocks, significantly reducing the average random memory access cost and improving the effective bandwidth utilization.

[0037] Considering that low-degree nodes have small neighbor sets and fine-grained tasks, but their adjacency lists often fall within nearby edge tiles, merging multiple low-degree nodes with highly overlapping neighbor sets / edge tiles into a single batch of tasks can significantly reuse loaded blocks, reduce off-chip accesses and cross-block jumps, thereby improving bandwidth utilization and cache hit rate. The above implementation, based on "low-degree task merging," introduces overlap (i.e., similarity) estimation, merging only tasks with "highly overlapping data footprints" to avoid ineffective merging. Loading and sampling are performed once and point-by-point within the same pipeline, thereby reusing prefetched data and reducing jumps and random memory accesses.

[0038] In one alternative implementation, the tasks to be executed in the task sequence are arranged in descending order according to their first priority score; Among them, any task to be executed The first priority rating is:

[0039] , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time.

[0040] To further avoid long-waiting small tasks repeatedly preempting scheduling resources, leading to fragmented scheduling cycles, frequent interruptions of off-chip prefetching, and reduced pipeline utilization and overall throughput, preferably, in another optional implementation, the scheduling control module is also used to calculate the second priority score of each task to be executed in the task sequence in real time during accelerator operation, and to arrange the tasks to be executed in the task sequence in descending order according to their second priority scores, so as to update the task sequence in real time; Among them, any task to be executed The second priority rating is:

[0041] , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time; Tasks to be performed The waiting time.

[0042] In an optional implementation, for each task to be executed, the sampling execution module calls the corresponding thread to obtain the corresponding node set from the cache unit corresponding to the task to be executed, and then performs the sampling operation in the following way: calling the parallel random number generator to generate multiple sampling indices, and sampling in parallel from the corresponding node set based on each sampling index.

[0043] It should be noted that the above preset degrees are obtained through empirical settings. The following are two preferred setting methods: In one optional implementation, the preset degree is the degree of the sequence of all nodes in the degree table corresponding to the graph data to be calculated, arranged in ascending order, at the quantile q; where q is 90–95%. This is a more precise setting method, typically used when the number of samples is insufficient or the statistical variance exceeds a threshold. In this method, the preset degree is the node with the highest degree among all nodes in the degree table corresponding to the graph data to be calculated. The minimum degree of a node; The value is 5% to 10% of the total number of nodes in the degree table corresponding to the graph data to be calculated.

[0044] In an optional second implementation, the preset degree is the degree of the sampled degree sequence at quantile p; wherein, the sampled degree sequence is the sequence of degrees obtained by randomly sampling all node degrees in the degree table corresponding to the graph data to be calculated according to a proportion p and sorting the degrees in ascending order; p is 1–5%. This is a sampling approximation method, which is usually used in scenarios where the number of sampled samples is sufficient.

[0045] To further illustrate the graph neural network sampling accelerator provided by this invention, a specific embodiment is described in detail below: like Figure 1 The diagram shown is an architecture diagram of the graph neural network sampling hardware accelerator provided in this embodiment. Figure 1 As shown in this embodiment, the graph neural network sampling accelerator includes three main functional modules: a scheduling control module, a cache module, and a sampling execution module. It interacts with the upper-layer system through an off-chip storage interface and a host interface.

[0046] The scheduling control module reads the degree table corresponding to the graph data to be computed from the off-chip storage module, and designates nodes with a degree greater than or equal to a preset degree as height nodes and nodes with a degree less than a preset degree as low-degree nodes. It divides the neighbor node sampling task of each height node into multiple sub-neighbor node sampling tasks, and sets them together with the neighbor node sampling tasks of each low-degree node in the task sequence. It assigns a corresponding thread to each task to be executed in the task sequence; one sub-neighbor node sampling task corresponds to one independent thread; multiple low-degree node neighbor node sampling tasks are merged to correspond to one independent thread. It also monitors the pipeline (thread) execution status and triggers task migration to balance the load when lag or blocking is detected.

[0047] The caching module includes two caching units. The caching module reads the edge table corresponding to the graph data to be computed from the off-chip storage module, thereby obtaining the n-order neighbor nodes of each node to be computed, forming a node set S. The node sets corresponding to the current task to be executed and the next task to be executed in the task sequence are cached into the two caching units respectively; n≥1. When the node to be computed is a height node, the node set S is divided into node sets corresponding to each subtask according to the subtask partitioning method. The caching module prefetches the blocks required by the task through dual buffer units and multi-channel loading. One buffer unit is used for reading by the sampling execution module, and the other buffer unit prefetches the next task to be executed in parallel. The caching units alternate to achieve overlap between memory access and computation, significantly reducing off-chip memory access latency.

[0048] The sampling execution module is used to execute the current task to be executed in the task sequence: it obtains the set of nodes corresponding to the current task to be executed from the cache unit corresponding to the current task to be executed, and performs sampling (i.e., executes the corresponding neighbor node sampling task), then notifies the corresponding cache unit to clear the cache, and starts executing the next task to be executed in the task sequence.

[0049] The sampling execution module includes multiple parallel sampling pipelines (i.e. threads). Each pipeline contains neighbor reading logic, a random index generator, and neighbor selection and supplementary sampling logic (i.e. sampling task execution logic). It can complete a preset number of neighbor samples with a high throughput and write the results into the output buffer, which is then sent back to the host via DMA or bus or directly fed to the aggregation unit.

[0050] The three modules exchange task descriptors, prefetch cues, sampling results, and status information via an internal interconnect bus, thus forming a hardware and software co-working sampling accelerator architecture.

[0051] Figure 2 This is a schematic diagram of the operation flow of the graph neural network sampling accelerator provided in this embodiment. Figure 2 As shown, the scheduling control module first retrieves the target node task from the task queue and divides the task into high-degree node tasks and low-degree node tasks according to the node degree and a preset threshold. For high-degree node tasks, a slicing operation is performed to split a large task into multiple sub-tasks to shorten the execution latency of a single task; for low-degree node tasks, a merging operation is performed to package multiple adjacent low-degree node tasks into a batch task to reduce scheduling overhead and memory access switching frequency.

[0052] After being sliced ​​and merged, the tasks are written into the task sequence. The scheduling control module dynamically allocates tasks to multiple sampling pipelines for execution based on the task sequence and the current pipeline (thread) load. When a pipeline is detected to have a long tail or be blocked, the scheduler triggers task migration, moving the remaining unfinished task slices to idle pipelines for continued execution, thereby achieving load balancing and throughput improvement across multiple pipelines.

[0053] The hardware accelerator design includes the following three parts: (1) Cache module: Parallel prefetching and switching are achieved through double buffering and multi-channel loading, reducing the latency caused by random memory access. Specifically, the cache management unit includes: The control register is used to receive block loading instructions issued by the scheduling control module, store control information such as the task block address list, prefetch start flag, and buffer switching command, and trigger prefetch operations.

[0054] Dual buffer unit: includes main buffer unit BUF_A and backup buffer unit BUF_B, which realize the alternating switching of data reading and writing through buffer control logic; the current buffer is used for reading by the sampling execution module, and the backup buffer prefetches the data required by the next batch of tasks in the background, realizing the overlapping execution of data loading and sampling calculation.

[0055] Configuration register group: Used to set configurable parameters such as block size B, alignment, index table cache depth, prefetch distance, etc., to adapt to different dataset sizes and bandwidth utilization.

[0056] (2) Sampling Execution Module: This module reads the set of nodes corresponding to the current task from the buffer unit, and in parallel calls the random number generator to generate the sampling index, completing neighbor sampling and result output. Specifically, the sampling execution module includes: The control register is used to receive the task allocation results issued by the scheduling control module, store information such as node ID, hop layer number, preset neighbor node sampling quantity (fanout), random seed offset, and supplementary sampling flag, and trigger the start of the corresponding pipeline; when the task is completed, it can generate an interrupt signal to write back to the scheduling control module.

[0057] Sampling pipeline (thread): includes neighbor read unit, random index generator, neighbor selection logic and supplementary sampling logic, supports multi-node parallel sampling to ensure that the set number of fanouts is met.

[0058] Output buffer: Used to store sampling results (node ​​ID, hop number, neighbor set) in a streaming manner, and transmit them back to the host or directly feed them to subsequent aggregation units via DMA or bus interface.

[0059] (3) Scheduling control module: This module parses the task parameters issued by the host, generates task descriptors and writes them into the task sequence, and distributes the tasks to multiple sampling pipelines after splitting or merging them; it also monitors the pipeline execution status and triggers task migration to balance the load when blocked. Specifically, the scheduling control module includes: The task control register is used to receive and store task parameters issued by the host or upper-layer framework, including the target node set Seeds, the number of sampling layers L, the preset number of neighbor nodes sampled in each layer fanout, the sampling strategy identifier pol, and the random seed, etc.

[0060] Task sequence (i.e. priority queue): used to store task descriptors TD(u,hop) generated based on the above parameters (the task descriptor at least contains fields such as node_id, hop level number, fanout[hop], deg(u), high / low degree flag, random seed index, etc.), and is dequeued and allocated to the sampling pipeline according to priority in subsequent scheduling steps to ensure that high priority tasks are allocated first.

[0061] Scheduling and migration logic: used to calculate task priorities, execute high-level task slices and merge low-level tasks, allocate tasks to multiple pipelines, and monitor pipeline execution status in real time; when lag or blockage is detected, task slicing and reallocation are triggered, and the remaining tasks are migrated to idle pipelines to improve overall throughput.

[0062] To facilitate understanding of the graph neural network sampling accelerator provided in this embodiment, the key concepts and overall approach are explained below. Large-scale graphs in the real world typically exhibit a power-law degree distribution, where the number of neighbors (node ​​degree) of a few nodes is significantly higher than that of most nodes. This results in spatially discrete and temporally unbalanced accesses to the edge table and degree table during the sampling phase, leading to two bottlenecks: high latency of off-chip random memory access and imbalanced load across multiple pipelines. To address this, this embodiment, based on the block storage and double-buffered prefetching provided by the hardware accelerator, introduces "degree-aware task slicing and priority scheduling." This involves splitting and parallelizing tasks for high-degree nodes and merging and batching tasks for low-degree nodes, thereby improving bandwidth utilization while balancing the load across each sampling pipeline.

[0063] This embodiment, supported by hardware accelerators, transforms off-chip random access into predictable block prefetching, and alleviates long-tail load through degree-aware task slicing and priority scheduling, thereby improving the overall throughput and parallel efficiency of the sampling phase. Specifically, it includes the following design: Sampling preprocessing: Receives the target node set, sampling layer number L, fanout of each layer, sampling strategy identifier pol and random seed from the host or framework, and generates batch task descriptors.

[0064] Graph data partitioning and address mapping: The degree table and edge table are laid out in blocks in off-chip storage, and an address mapping table is established. The block size and alignment are configurable parameters.

[0065] Double buffering prefetching and multi-channel loading: Enable double buffering: while the current buffer provides data to the sampling execution module, the background buffer prefetches the data required for the next batch of tasks; multi-channel block loading is used to distribute random access latency.

[0066] Task slicing and priority scheduling: Batch tasks are divided into fine-grained units and written into a scheduling queue (i.e., task sequence). Priority is calculated based on information such as node degree, fanout, and expected number of accessed blocks. The tasks are dynamically allocated to multiple sampling pipelines. High-degree node tasks are split and low-degree node tasks are merged to balance the load.

[0067] Lag detection and reallocation: Real-time monitoring of execution latency and queue depth of each pipeline; when long tail / blocking (exceeding threshold T) is detected, the executing tasks are sliced ​​and migrated to idle pipelines to alleviate load imbalance.

[0068] Parallel Neighbor Sampling: The sampling pipeline reads the neighbor list from the on-chip cache, calls the parallel random number generator to generate the sampling index, and selects neighbors according to the set fanout; when there are not enough neighbors, the supplementary sampling logic is triggered (supplementing with spare blocks or degenerating to full sampling) to ensure that the number meets the target; the sampling results are output in streaming mode.

[0069] Results feedback: The sampling results are fed back to the host in batches or sent directly to the subsequent aggregation / update unit; if there is multi-hop sampling, the neighbor set obtained from the current layer is used as the target node set for the next layer.

[0070] Without limiting the scope of protection of this invention, the terminology and parameters in this embodiment are as follows: (1) Preset degree, i.e., node degree threshold ( ): The threshold used to distinguish between "high-degree nodes" and "low-degree nodes".

[0071] (2) Height / lowness node: degree greater than or equal to The node is the height node; the degree is less than The nodes are low-degree nodes. High-degree node tasks are split and executed by default, while low-degree node tasks can be merged into batches.

[0072] (3) Tiles and tile size (B): The degree table and edge table are laid out in tiles outside the tile; the tile size B and alignment method are configurable parameters.

[0073] (4) Prefetch Distance (PD) and Double Buffering: While the current buffer is used for sampling and reading, the required blocks of PD tasks are moved to the backup buffer in advance according to the task sequence. The two buffers are switched in a cycle to hide off-chip delay.

[0074] (5) Estimated number of accessed blocks (tiles(u)): The estimated number of blocks to be accessed for sampling the target node u can be calculated from the edge table index range and block boundaries or obtained from historical statistics cache.

[0075] (6) Number of samples (fanout): refers to the number of nodes sampled from the neighbors of the target node in each layer. It can be a fixed value or a dynamic value that is adaptively adjusted.

[0076] (7) Priority scoring (this embodiment uses the second priority scoring as an example): The following can be used during scheduling:

[0077] , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time; Tasks to be performed The waiting time.

[0078] Tasks with higher priority scores are scheduled or sliced ​​first.

[0079] (8) Hysteresis threshold (T): When the execution delay of a pipeline exceeds the threshold T or the queue depth is lower than the threshold, a reassignment is triggered to avoid the long tail slowing down the batch completion time.

[0080] (9) Supplementary sampling strategy: When the actual available neighbors are less than fanout, the spare block is supplemented or degraded to full sampling to ensure that the quantity meets the target and reproducibility.

[0081] The following is a detailed description of the operation process of the graph neural network sampling accelerator, specifically including the following steps: S1 sampling preprocessing (executed by the scheduling control module) S1.1 Load task parameters: Receive task requests issued by the host or upper-layer framework. The task requests include the target node set Seeds, the number of sampling layers L, the number of samples in each layer fanout[0..L-1], the sampling strategy identifier pol, and the random seed rng_seed. Store the above parameters in the task control register and set the "task valid" flag. S1.2 Degree Value Query and Statistics: Traverse the target node set Seeds, and read the degree information deg(u) of the node in the degree table through the degree table query interface provided by the cache module; construct the degree value quantile statistics, and record the number of samples, maximum / minimum value. If the query fails, set the degree information deg(u)=0 and record the anomaly count; S1.3 Calculate the preset degree Preferably, the preset degree is the degree corresponding to quantile q after sorting the degrees of all nodes in the degree table corresponding to the graph data to be computed in ascending order; q is 90–95%; or the degree of the sampled degree sequence at quantile p; wherein, the sampled degree sequence is the sequence of degrees obtained by randomly sampling the degrees of all nodes in the degree table corresponding to the graph data to be computed according to a proportion p and sorting them in ascending order; p is 1–5%.

[0082] S1.4 Node Grouping and Labeling: Based on a preset degree θ, each node in the graph data to be calculated is divided into a set of height nodes H={u|deg(u)≥ } and the set of low-degree nodes L={u|deg(u)< }, and write the flag bit in the subsequent task descriptor; S1.5 Generate Task Descriptors: Generate a task descriptor TD(u,hop) for each target node u, containing the node ID (node_id), layer number hop, the preset number of neighbor nodes sampled under layer hop (fanout[hop]), the degree of node u (deg(u)), high / low degree flags, and a random seed index; and write it into the task sequence (i.e., priority queue) of the scheduling control module. When the task sequence is full, backpressure is triggered, and the host's distribution is temporarily suspended; once all tasks are enqueued, the "preprocessing complete" flag is set.

[0083] Note: After S1 is completed, the scheduling control module has generated a schedulable task sequence, providing input for S4; the cache management module can establish a block index in step S2 based on the task node addresses in the task sequence, and generate a prefetch sequence in step S3.

[0084] S2 Graph Data Blocking and Address Mapping (Executed by Cache Management Module) S2.1 Block Parameter Setting: Divide the degree table into fixed block sizes B (default 4KB, can be 2 / 4 / 8KB) and write the parameters into the configuration register of the cache management module.

[0085] S2.2 Degree Table Blocking: Divide the degree table into degree table blocks according to the continuous interval of node ID, and record the starting address base_addr and length len of each block.

[0086] S2.3 Edge table block division: The adjacency list is divided into edge table blocks according to the node interval, and alignment padding is performed at the block boundaries to ensure sequential access within the block.

[0087] S2.4 Establish index mapping: Establish an index mapping table for each block, with tile_id → {base_addr, length}, and load the mapping entries of hot blocks into the on-chip index cache.

[0088] S2.5 parameters are configurable: block size B, alignment, and index table cache depth are all set through the configuration register of the cache management module and can be dynamically adjusted according to the dataset size and bandwidth.

[0089] Explanation: S2 produces block-level mappings, providing contiguous block addresses for S3's double-buffered prefetch and S6's neighbor reads.

[0090] S3 Double-Buffered Prefetching and Multi-Channel Loading (Executed by the Cache Module) S3.1 Buffer initialization: Allocate two on-chip buffers as primary buffer BUF_A and backup buffer BUF_B, and record their capacities and current valid data ranges respectively; the prefetch distance PD is set to 2 by default.

[0091] S3.2 Prefetch strategy: Based on the node_id, hop, fanout and mapping table of the first PD tasks in the task sequence, calculate and sort the required block set, eliminate gaps between adjacent blocks, and generate a prefetch instruction sequence.

[0092] S3.3 Multi-channel loading: Utilizes multiple channels (AXI / DDR / HBM) to pull multiple block data to BUF_B in parallel, and distributes them across channels according to block number parity or hash to reduce collisions; records the arrival marker of each block.

[0093] S3.4 Buffer Switching: When the main buffer BUF_A has finished consuming data (i.e., the consumption pointer reaches the end or the available data is insufficient to meet the threshold), if BUF_B prefetching is completed, the backup buffer BUF_B is quickly switched to the new main buffer, and the original main buffer BUF_A begins to prefetch the data required for the next batch of tasks; if the backup buffer is not completed, the most urgently needed block is temporarily fetched to make up the difference.

[0094] S3.5 Prefetch Distance Adjustment: The prefetch distance PD can be adaptively adjusted according to the runtime queue depth and bandwidth utilization to avoid cache overflow or idle time.

[0095] Note: S3 transforms off-chip random access into block-level sequential loading through "buffer switching," hiding memory access latency; the switching timing can be triggered by a threshold / interrupt.

[0096] S4 Task Slicing and Priority Scheduling (Executed by the Scheduling Control Module) S4.1 Priority Calculation: Calculate task priority based on node degree deg(u), fanout, expected number of accessed blocks, waiting time, etc., and write the task into the task sequence; S4.2 Height Task Slicing: For tasks with deg(u)≥θ, divide them into several subtasks according to node intervals (4 by default), and generate an independent descriptor for each subtask; the priority of subtasks is inherited or adjusted according to the remaining workload.

[0097] S4.3 Low-degree task merging: Group multiple low-degree tasks by block proximity (8 low-degree nodes per group by default) and merge them into a single batch of tasks to reduce scheduling and switching overhead.

[0098] S4.4 Pipeline Allocation: The scheduling control module retrieves tasks from the task sequence and allocates them to N sampling pipelines according to the "most idle first" strategy to ensure maximum pipeline utilization.

[0099] S4.5 Schedule Writeback: After writing the scheduling results (task → pipeline number, prefetch hint) back to the control registers of the cache module and the sampling execution module, the next round of data loading and sampling pipeline startup is triggered.

[0100] S5 Hysteresis Detection and Redistribution S5.1 Status Monitoring: Collect the number of tasks in progress, average processing latency, queue depth and idle time for each pipeline on a periodic basis; S5.2 Hysteresis Detection: If the execution time of a pipeline exceeds the hysteresis threshold T, and there are other idle or lightly loaded pipelines, then "long tail / blocking" is determined to have occurred.

[0101] S5.3 Task Migration: Unfinished tasks on blocked pipelines are sliced ​​a second time, and the unfinished parts are migrated to idle pipelines or pipelines with lighter loads to continue execution; during migration, a random seed offset and the completed progress are carried to ensure replayability and no duplication.

[0102] S5.4 Parameter Adaptation: If long tails are continuously detected, increase the number of slices for high-degree tasks or decrease the batch size for merging low-degree tasks; otherwise, revert to the default value to avoid jitter from frequent migrations.

[0103] S5.5 Completion Condition: When all pipelines have no in-process tasks in the current batch and the queue is empty, set the "Batch Complete" flag and proceed to the next level or S7.

[0104] S6 Parallel Neighbor Sampling (executed by the sampling execution module) S6.1 Neighbor Reading: The sampling pipeline reads the adjacency list of the target node in parallel from the primary / backup buffer according to the scheduling instruction; if the hit fails, a direct fetch request is sent to the cache management unit.

[0105] S6.2 Random Index Generation: Call the parallel random number generator to generate fanout number of sampling indices for each node; the random number stream is jointly determined by rng_seed and the subtask offset to ensure batch replayability.

[0106] S6.3 Neighbor Selection: Select neighbors by index. When the actual available number of neighbors is less than fanout, supplementary sampling is triggered: first, supplement the remaining neighbors within the same block, and then degrade to full fetch; if it is still insufficient, output according to the "existing" principle and record the insufficient flag.

[0107] S6.4 Streaming Output of Results: Write the sampling results (u, hop, neighbors) into the output buffer in a streaming output manner to reduce the burst write latency.

[0108] Note: S6 is the data plane, responsible for sampling and outputting the data provided by S2 / S3 with high throughput, ensuring decoupling from the control planes of S4 / S5.

[0109] S7 Result Return S7.1 Result Packing and Return: Pack the sampling results in the output buffer by batch, and return them to the host through the PCIe / AXI bus or directly send them to the subsequent aggregation unit; the return includes batch ID, layer number, nodes and their neighbor lists.

[0110] S7.2 Inter-layer Iterative Control: If hop < L - 1, the scheduling control module uses the neighbor set sampled in this layer as the Seeds for the next layer, clears the task sequence and repeats S3 - S7; if hop = L - 1, set the "all sampling completed" flag; S7.3 Resource Reset and Statistics: After the batch is completed, reset the relevant registers and buffer pointers, and summarize the statistical information such as throughput rate, hit rate, and latency times and return it to the host for subsequent parameter tuning.

[0111] In summary, the main idea of the graph neural network sampling accelerator proposed in this embodiment is as follows: Block Storage and Double-buffer Prefetch: Store the degree table and edge table in blocks, and overlap memory access and sampling calculations in the on-chip buffer through double-buffering and multi-channel loading, significantly reducing the random memory access latency; Degree-aware task slicing and priority scheduling: Dynamically slicing high-load tasks and merging low-load tasks based on node degree, scheduling multiple sampling pipelines through priority queues, and triggering task migration when blockage is detected, thereby mitigating the long-tail effect and improving overall throughput.

[0112] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A graph neural network sampling accelerator, characterized in that, This is used to sample graph data during the training of a graph neural network; the graph data includes multiple nodes and edges representing connections between nodes; wherein, nodes connected to a node are considered its neighbor nodes; the sampling accelerator is implemented in hardware and includes: a scheduling control module, a cache module, and a sampling execution module; The scheduling control module is used to read the degree table corresponding to the graph data to be computed from the off-chip storage module, and to designate nodes with a degree greater than or equal to a preset degree as height nodes and nodes with a degree less than a preset degree as low-degree nodes; to divide the neighbor node sampling task of each height node into multiple sub-neighbor node sampling tasks, and to set them together with the neighbor node sampling tasks of each low-degree node in the task sequence; to allocate a corresponding thread to each task to be executed in the task sequence; wherein, one sub-neighbor node sampling task corresponds to one independent thread; and multiple low-degree node neighbor node sampling tasks are merged to correspond to one independent thread; The caching module includes two caching units. The caching module reads the edge table corresponding to the graph data to be computed from the off-chip storage module, thereby obtaining the n-order neighbor nodes of each node to be computed, forming a node set S. The node sets corresponding to the current task to be executed and the next task to be executed in the task sequence are cached into the two caching units respectively; n≥1; when the node to be computed is a height node, the node set S is divided into node sets corresponding to each subtask according to the subtask partitioning method. The sampling execution module is used to sequentially execute the tasks to be executed in the task sequence: for each task to be executed, the corresponding thread is called to obtain the corresponding node set from the cache unit corresponding to the task to be executed and sample it. After sampling is completed, the corresponding cache unit is notified to clear the cache and start executing the next task to be executed in the task sequence until all tasks in the task sequence are executed. In this process, while one buffer unit is used by the sampling execution module to read the corresponding node set, another buffer unit reads the node set corresponding to the next task to be executed in parallel.

2. The sampling accelerator according to claim 1, characterized in that, The scheduling control module samples and allocates threads for tasks to the neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. When there are still low-degree nodes in the node sequence that have not been selected, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or all low-degree nodes in the node sequence have been selected. The placement operation performed on any thread t' includes: selecting a low-degree node that has not been selected before from the node sequence. and low-degree nodes The neighbor node sampling task is placed in thread t'; it sequentially selects a neighbor node from all currently unselected low-degree nodes. The most similar low-degree node is selected, and its neighbor node sampling tasks are placed sequentially in thread t'. The higher the overlap between the nth-order neighbor nodes of two low-degree nodes, the more similar they are.

3. The sampling accelerator according to claim 2, characterized in that, The node sequence is a sequence of all nodes in the graph data sorted according to the topological order of the graph data; The placement operation performed on any thread t' includes: sequentially obtaining an unselected low-degree node from the node sequence, and placing its neighbor node sampling tasks in thread t' in turn.

4. The sampling accelerator according to claim 1, characterized in that, The off-chip storage module is used to divide the edge table and degree table corresponding to the graph data to be calculated into multiple storage areas for storage.

5. The sampling accelerator according to claim 4, characterized in that, The scheduling control module samples and allocates threads for tasks to the neighboring nodes of low-degree nodes in the task sequence in the following manner: Read the node sequence consisting of all nodes in the graph data to be computed from the off-chip storage module; Establish multiple arrays that correspond one-to-one with multiple storage areas in the off-chip storage module that store the edge tables and degrees corresponding to the graph data to be computed; Traverse the node sequence, selecting one low-degree node that has not been selected before at each step. ,Will Stored in storage The arrays corresponding to each storage area of ​​the edge table; Select a thread t and perform placement operations on thread t until the number of tasks in thread t reaches the corresponding preset threshold or all the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. When there are still unselected low-degree nodes in any array, select another thread and place the operation on the currently selected thread until the number of tasks in the currently selected thread reaches the corresponding preset threshold or the sampling tasks of the neighbor nodes of all low-degree nodes in the node sequence are assigned to threads. The placement operation performed on any thread t' includes: When the number of sampling tasks in thread t' is 0: count the number of unselected low-degree nodes in each array. If the number is the same, select any array as the current execution array; otherwise, select the array with the most unselected low-degree nodes as the current execution array; determine if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, select the unselected low-degree node in the current execution array as the current execution node; if it is not 1, calculate the sum of similarities between each unselected low-degree node in the current execution array and other low-degree nodes, and select the unselected low-degree node with the largest sum of similarities as the current execution node; place the sampling tasks of the neighbor nodes of the current execution node in thread t', and use the current execution array as the source array of the current execution node. When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... If there are unselected low-degree nodes in the source array: use the source array as the current execution array; check if the number of unselected low-degree nodes in the current execution array is 1. If it is 1, use the unselected low-degree nodes in the current execution array as the current execution nodes; otherwise, use the nodes in the current execution array that are not selected as the current execution nodes. The low-score node with the highest similarity that has not been selected is selected as the current execution node; the sampling task of the neighbor nodes of the current execution node is placed in thread t', and the current execution array is used as the source array of the current execution node; When the number of sampling tasks in thread t' is not 0, and the low-degree node corresponding to the most recently placed neighbor node sampling task in thread t' is... When there are no unselected low-degree nodes in the source array: count the storage area where the edge table of the low-degree node corresponding to each neighbor node sampling task in thread t' is located, and take the storage area of ​​the storage area that appears most frequently and whose corresponding array contains unselected low-degree nodes as the target storage area; take the array corresponding to the target storage area as the current execution array; determine whether the number of unselected low-degree nodes in the current execution array is 1. If it is 1, take the unselected low-degree node in the current execution array as the current execution node; if it is not 1, take the unselected low-degree node in the current execution array that has the highest similarity to the low-degree node corresponding to the latest neighbor node sampling task in thread t' as the current execution node; put the neighbor node sampling task of the current execution node in thread t', and take the current execution array as the source array of the current execution node. For any low-degree nodes u and v, their similarity is: Low-degree nodes The set of numbers for the storage region where the edge table is located; Low-degree nodes The set of numbers of the storage area where the edge table is located.

6. The sampling accelerator according to claim 4, characterized in that, The tasks to be executed in the task sequence are arranged in descending order according to their first priority score; Among them, any task to be executed The first priority rating is: , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time.

7. The sampling accelerator according to claim 4, characterized in that, The scheduling control module is also used to calculate the second priority score of each task to be executed in the task sequence in real time during the operation of the accelerator, and to arrange the tasks to be executed in the task sequence in descending order according to their second priority scores, so as to update the task sequence in real time. Among them, any task to be executed The second priority rating is: , , , All are preset positive weights; Tasks to be performed The number of nodes in the corresponding node set; Preset degree; Tasks to be performed The preset number of neighbor nodes sampled; To execute pending tasks The estimated number of storage area blocks in the off-chip storage modules that need to be accessed at that time; Tasks to be performed The waiting time.

8. The sampling accelerator according to any one of claims 1-7, characterized in that, For each task to be executed, the sampling execution module calls the corresponding thread to obtain the corresponding node set from the cache unit corresponding to the task to be executed, and then performs the sampling operation in the following way: it calls the parallel random number generator to generate multiple sampling indices, and samples in parallel from the corresponding node set based on each sampling index.

9. The sampling accelerator according to any one of claims 1-7, characterized in that, The preset degree is the degree of the sequence of all nodes in the degree table corresponding to the graph data to be calculated, arranged in ascending order, at the quantile q; where q is 90–95%.

10. The sampling accelerator according to any one of claims 1-7, characterized in that, The preset degree is the degree of the sampled degree sequence at quantile p; wherein, the sampled degree sequence is the sequence of degrees obtained by randomly sampling all the node degrees in the degree table corresponding to the graph data to be calculated according to a ratio p and sorting each degree in ascending order; p is 1–5%.

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