OPC model training methods and equipment
By cutting and noise-processing the chip design layout file, a pattern generator is trained to generate diverse test patterns, solving the problem of low training accuracy of the OPC model and achieving more accurate and reliable lithography correction results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YIXIN TECH (HANGZHOU) CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-05-26
AI Technical Summary
In existing technologies, OPC model training methods suffer from low training accuracy due to the simple selection of basic graphics, making it difficult to generate rich graphics and effectively correct the graphic distortion on silicon wafers after lithography exposure.
By cutting the chip design layout file to generate multiple basic blocks and adding noise to them, a graphics generator is trained to generate diverse test graphics. The graphics generator and OPC model are then used for iterative training to optimize the noise vector and improve the model accuracy.
The generated OPC model is more accurate and reliable, and can effectively correct the pattern distortion after exposure by the lithography machine, thus improving the accuracy and reliability of the lithography process.
Smart Images
Figure CN121725085B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of model training technology, and more specifically, to an OPC model training method and an OPC model training device. Background Technology
[0002] In semiconductor integrated circuit manufacturing, as semiconductor process nodes continue to shrink, the increasingly severe optical proximity effect causes significant distortion of the patterns on the silicon wafer after lithography exposure relative to the design patterns. To address this problem, Optical Proximity Correction (OPC) technology has emerged.
[0003] In related technologies, engineers predefine a graphics library containing various typical topologies (such as line ends, corners, dense lines, isolated lines, etc.) based on experience. When generating test graphics, a base graphic is selected from this library, and its geometric parameters (such as line width, spacing, and angle) are systematically or randomly perturbed to produce a series of variants. An OPC model is then trained based on this test graphic.
[0004] However, in related technologies, the basic graphics selected from the library are relatively simple, making it difficult to generate rich graphics, resulting in low accuracy of the trained OPC model. Summary of the Invention
[0005] The purpose of this application is to provide an OPC model training method and an OPC model training device to address the shortcomings of the prior art and solve the aforementioned technical problems in the related art.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:
[0007] In a first aspect, embodiments of this application provide an OPC model training method, the method comprising:
[0008] The chip design layout file is cut into multiple basic blocks;
[0009] Add noise to multiple base blocks to obtain multiple noise-added blocks;
[0010] A graph generator is trained based on multiple noisy image patches and their corresponding real noise.
[0011] The aforementioned graphic generator is used to generate multiple test graphics based on multiple preset noise vectors;
[0012] The OPC model is obtained by training the model based on multiple test graphs.
[0013] Optionally, training the image generator based on multiple noisy image patches and corresponding real noise includes:
[0014] An initial graphic generator is used to predict noise based on the noisy graphics blocks, resulting in predicted noise.
[0015] The model parameters of the initial graphics generator are updated based on the predicted noise and the corresponding real noise to obtain the graphics generator.
[0016] Optionally, the step of adding noise to the multiple base tiles to obtain multiple noisy tiles includes:
[0017] Based on a preset random time step and a noise scheduling table, noise is added to multiple base blocks to obtain multiple noise-added blocks.
[0018] The process employs an initial graphics generator to predict noise based on the noisy graphics tiles, resulting in predicted noise, including:
[0019] Using the initial graphic generator, noise prediction is performed based on the preset random time step and the noise-added graphic block to obtain the predicted noise.
[0020] Optionally, the method further includes:
[0021] Optimize multiple preset noise vectors to obtain multiple target noise vectors;
[0022] Using the aforementioned image generator, multiple target images are generated based on multiple target noise vectors;
[0023] The OPC model is trained based on multiple target graphs to obtain the target OPC model.
[0024] Optionally, optimizing the plurality of preset noise vectors to obtain a plurality of target noise vectors includes:
[0025] The preset noise vector is optimized in multiple preset directions to obtain the optimized noise vector for each preset direction.
[0026] Using the aforementioned graphic generator, intermediate graphics in each of the preset directions are generated based on the optimized noise vectors of each preset direction;
[0027] Determine the target intermediate graphic from the intermediate graphics of each of the preset directions;
[0028] The target noise vector is determined based on the optimized noise vector corresponding to the target intermediate graphic.
[0029] Optionally, determining the target intermediate graphic from the intermediate graphics of each of the preset directions includes:
[0030] Using the OPC model, multiple first prediction graphics for each preset direction are obtained based on the intermediate graphics for each preset direction;
[0031] Based on multiple first prediction graphics for each preset direction, a geometric diversity assessment is performed on each preset direction to obtain value assessment parameters for each preset direction;
[0032] Based on the value assessment parameters of each preset direction, the intermediate graphic of the target direction is determined from the intermediate graphics of each preset direction as the target intermediate graphic.
[0033] Optionally, the step of evaluating the geometric diversity of each preset direction based on multiple first prediction graphs for each preset direction to obtain value evaluation parameters for each preset direction includes:
[0034] Calculate the variance among multiple first prediction patterns for each preset direction to obtain the variance corresponding to each preset direction;
[0035] Based on the variance corresponding to each preset direction, the value assessment parameters for each preset direction are obtained.
[0036] Optionally, training the OPC model based on multiple target graphs to obtain the target OPC model includes:
[0037] Obtain the target real silicon wafer image corresponding to the target image, wherein the target real silicon wafer image is acquired by the lithography machine after performing real exposure based on the target image;
[0038] The second predicted image is obtained by simulating exposure based on the target image using the OPC model.
[0039] The OPC model is trained based on the second predicted image and the target real silicon wafer image to obtain the target OPC model.
[0040] Optionally, the step of training the model based on multiple test graphs to obtain the OPC model includes:
[0041] Obtain the initial real silicon wafer pattern corresponding to the test pattern. The initial real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the test pattern.
[0042] A third predicted image is obtained by simulating exposure based on the test image using a preset OPC model.
[0043] The preset OPC model is trained based on the third predicted graph and the initial real silicon wafer graph to obtain the OPC model.
[0044] Secondly, embodiments of this application also provide an OPC model training device, including: a memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the OPC model training method described in any of the first aspects above.
[0045] Thirdly, embodiments of this application also provide an OPC model training apparatus, the apparatus comprising:
[0046] The cutting module is used to cut the chip design layout file into multiple basic blocks;
[0047] The processing module is used to add noise to multiple base blocks to obtain multiple noise-added blocks;
[0048] The first training module is used to train a graphics generator based on multiple noisy patches and corresponding real noise.
[0049] The generation module is used to generate multiple test graphics based on multiple preset noise vectors using the graphics generator.
[0050] The second training module is used to train the model based on multiple test graphs to obtain the OPC model.
[0051] Optionally, the first training module is specifically used to use an initial graphics generator to predict noise based on the noisy patches to obtain predicted noise; and to update the model parameters of the initial graphics generator based on the predicted noise and the corresponding real noise to obtain the graphics generator.
[0052] Optionally, the processing module is specifically used to add noise to multiple base tiles according to a preset random time step and a noise scheduling table to obtain multiple noise-added tiles;
[0053] The first training module is specifically used to use the initial graphics generator to perform noise prediction based on the preset random time step and the noise-added graphics patch, so as to obtain the predicted noise.
[0054] Optionally, the device further includes:
[0055] An optimization module is used to optimize multiple preset noise vectors to obtain multiple target noise vectors;
[0056] The first generation module has the ability to generate multiple target graphics based on multiple target noise vectors using the graphics generator.
[0057] The third training module is used to train the OPC model based on multiple target graphs to obtain the target OPC model.
[0058] Optionally, the optimization module is specifically used to optimize the preset noise vector in multiple preset directions to obtain optimized noise vectors for each preset direction; use the graphics generator to generate intermediate graphics for each preset direction based on the optimized noise vectors for each preset direction; determine a target intermediate graphic from the intermediate graphics for each preset direction; and determine the target noise vector based on the optimized noise vector corresponding to the target intermediate graphic.
[0059] Optionally, the optimization module is specifically used to employ the OPC model to obtain multiple first predicted graphics for each preset direction based on the intermediate graphics for each preset direction; to perform geometric diversity evaluation on each preset direction based on the multiple first predicted graphics for each preset direction to obtain value evaluation parameters for each preset direction; and to determine the intermediate graphics of the target direction from the intermediate graphics of each preset direction as the target intermediate graphics based on the value evaluation parameters for each preset direction.
[0060] Optionally, the optimization module is specifically used to calculate the variance among multiple first prediction patterns for each preset direction to obtain the variance corresponding to each preset direction; and to obtain the value evaluation parameters for each preset direction based on the variance corresponding to each preset direction.
[0061] Optionally, the third training module is specifically used to obtain the target real silicon wafer pattern corresponding to the target pattern, wherein the target real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the target pattern; to use the OPC model to perform simulated exposure based on the target pattern to obtain a second predicted pattern; and to train the OPC model based on the second predicted pattern and the target real silicon wafer pattern to obtain the target OPC model.
[0062] Optionally, the second training module is specifically used to obtain the initial real silicon wafer pattern corresponding to the test pattern, wherein the initial real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the test pattern; to obtain a third predicted pattern by simulating exposure based on the test pattern using a preset OPC model; and to train the preset OPC model based on the third predicted pattern and the initial real silicon wafer pattern to obtain the OPC model.
[0063] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when read and executed, implements the method described in any of the first aspects above.
[0064] The beneficial effects of this application are as follows: This application provides an OPC model training method, which may include: cutting a chip design layout file to obtain multiple basic blocks; adding noise to the multiple basic blocks to obtain multiple noisy blocks; training a graph generator based on the multiple noisy blocks and corresponding real noise; using the graph generator to generate multiple test graphs based on multiple preset noise vectors; and training the model based on the multiple test graphs to obtain an OPC model. By training the graph generator based on the multiple noisy blocks and corresponding real noise, the graph generator implicitly learns the data distribution of the graphs, that is, it learns the rules of chip design. Therefore, the multiple test graphs generated by the graph generator have more diverse forms and conform to the design rules. The OPC model trained based on these multiple test graphs is also more accurate and reliable. Attached Figure Description
[0065] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0066] Figure 1 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 1 ;
[0067] Figure 2 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 2 ;
[0068] Figure 3 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 3 ;
[0069] Figure 4 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 4 ;
[0070] Figure 5 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 5 ;
[0071] Figure 6A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 6 ;
[0072] Figure 7 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 7 ;
[0073] Figure 8 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 8 ;
[0074] Figure 9 A complete flowchart of an OPC model training method provided in this application embodiment is shown below;
[0075] Figure 10 This is a schematic diagram of the structure of an OPC model training device provided in an embodiment of this application;
[0076] Figure 11 This is a schematic diagram of the structure of an OPC model training device provided in an embodiment of this application. Detailed Implementation
[0077] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0078] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0079] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0080] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0081] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0082] This application provides an OPC model training method, which is applied to an OPC model training method device. The OPC model training method device can be a terminal device or a server, and this application does not impose specific limitations on it.
[0083] The following explains an OPC model training method provided in the embodiments of this application.
[0084] Figure 1 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method may include:
[0085] S101. Cut the chip design layout file to obtain multiple basic blocks.
[0086] Among them, the chip design layout file can be a real chip design layout file that covers a wide range of topologies.
[0087] In some implementations, a sliding window approach is used to divide the chip layout in the chip design layout file into multiple base tiles of preset sizes, ensuring that all local features in the chip design layout file are covered. For example, the preset size can be 1µm (micrometer) x 1µm. The number of base tiles can be in the millions.
[0088] It should be noted that multiple basic tiles can be converted into a binary image, using 0 to represent the background and 1 to represent the graphic.
[0089] S102. Add noise to multiple basic tiles to obtain multiple noise-added tiles.
[0090] In some implementations, multiple base tiles are divided into multiple batches, and a preset noise addition algorithm is used to add noise to each base tile in each batch, resulting in multiple noise-added tiles.
[0091] It should be noted that noise processing can be added to multiple basic blocks sequentially or simultaneously; this application does not impose specific limitations on this.
[0092] S103. Based on multiple noisy patches and their corresponding real noise, a graphics generator is trained.
[0093] Each noise-added image block has a pre-set corresponding real noise.
[0094] In some implementations, the model parameters of the initial graphics generator are updated based on multiple noisy patches and the corresponding real noise, thereby training the graphics generator.
[0095] Additionally, the initial graph generator can employ a diffusion model; for example, it could be a neural network with a U-Net structure (a deep convolutional neural network architecture). Of course, the initial graph generator can also be a generative adversarial network (GAN), a variational autoencoder (VAE), a diffusion model, or an autoregressive model; this application does not impose specific limitations on these aspects.
[0096] It is worth noting that during the training process of the graphics generator, the core objective is to repair (de-noise) all degrees of damage, and the graphics generator implicitly learns the data distribution of the graphics.
[0097] S104. Use a graph generator to generate multiple test graphs based on multiple preset noise vectors.
[0098] Among them, multiple preset noise vectors are different random noise vectors z.
[0099] In some implementations, a preset noise vector is input into a graph generator, which can generate a test graph, and so on, to obtain multiple test graphs.
[0100] In the embodiments of this application, the graphics generator can be considered as a graphics generation engine. The graphics generator implicitly learns the data distribution of the graphics, that is, it learns the basic syntax of chip design. Therefore, the graphics generator can generate test graphics with diverse shapes and in accordance with design rules.
[0101] S105. Train the model based on multiple test graphs to obtain the OPC model.
[0102] It should be noted that the test patterns generated by the pattern generator conform to chip design rules and are rich in variety. Based on multiple test patterns, the preset OPC model is trained, resulting in a more reliable and accurate OPC model.
[0103] In practical applications, the design pattern is input into the OPC model, which then performs simulated exposure based on the design pattern and outputs a target prediction pattern. The design pattern is continuously corrected using the target prediction pattern until the new target prediction pattern output by the OPC model is similar to the design pattern, resulting in a corrected pattern. The final corrected pattern is then subjected to actual exposure in a lithography machine, and the resulting silicon wafer pattern is similar to the design pattern.
[0104] In summary, this application provides an OPC model training method, which may include: cutting a chip design layout file to obtain multiple basic blocks; adding noise to the multiple basic blocks to obtain multiple noisy blocks; training a graph generator based on the multiple noisy blocks and corresponding real noise; using the graph generator to generate multiple test graphs based on multiple preset noise vectors; and training the model based on the multiple test graphs to obtain an OPC model. By training the graph generator based on the multiple noisy blocks and corresponding real noise, the graph generator implicitly learns the data distribution of the graphs, that is, it learns the rules of chip design. Therefore, the multiple test graphs generated by the graph generator have more diverse forms and conform to the design rules. The OPC model trained based on these multiple test graphs is also more accurate and reliable.
[0105] Optionally, Figure 2 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, the process of training the image generator based on multiple noisy image patches and corresponding real noise in S103 above may include:
[0106] S201. Using an initial graphic generator, noise prediction is performed based on the noise-added graphics to obtain the predicted noise.
[0107] S202. Based on the predicted noise and the corresponding real noise, update the model parameters of the initial graphics generator to obtain the graphics generator.
[0108] In some implementations, the noisy patch is input into the initial graphics generator, which performs noise prediction based on the noisy patch and outputs the predicted noise for the noisy patch. A preset loss function is used to calculate the loss value based on the predicted noise and the corresponding real noise. The model parameters of the initial graphics generator are updated by backpropagation based on the loss value, and the graphics generator G is trained.
[0109] The preset loss function can be the mean error (MSE) loss function.
[0110] Optionally, the process of adding noise to multiple base tiles to obtain multiple noisy tiles in step S102 above may include:
[0111] Based on a preset random time step and a noise scheduling table, noise is added to multiple basic blocks to obtain multiple noise-added blocks.
[0112] In some implementations, the base blocks are within a preset range. A random time step is sampled to obtain a preset random time step t for the base tile. Based on the preset random time step of the base tile, the noise scheduling table is consulted to obtain the cumulative noise level factor corresponding to the preset random time step of the base tile. Based on the cumulative noise level factor and standard Gaussian noise Noise is added to the base tiles to obtain the noisy tiles. The preset interval can be represented as (1,T), where T is the preset total number of diffusion steps, for example, 1000.
[0113] The above are the basic blocks Adding noise results in a noisy patch. The process can be represented as: .
[0114] The process described in S201 above, which uses an initial graphic generator to predict noise based on the noisy graphics, and obtains the predicted noise, may include:
[0115] An initial graphic generator is used to predict noise based on a preset random time step and noise-added graphics tiles, thus obtaining the predicted noise.
[0116] In some implementations, a preset random time step and a noisy patch are used. The initial image generator is input into the initial image generator, and the output of the initial image generator is the predicted noise. .
[0117] In addition, calculate the prediction noise. and real noise MSE loss between The model parameters of the initial graph generator are updated based on the backpropagation and gradient descent algorithm of the MSE loss, and the graph generator G is trained.
[0118] It is worth noting that a well-trained graph generator G can generate a completely new, realistic test graph that conforms to the design rules, starting from a random Gaussian noise vector z and undergoing a denoising process.
[0119] Optionally, Figure 3 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 3 ,like Figure 3 As shown, the method also includes:
[0120] S301. Optimize multiple preset noise vectors to obtain multiple target noise vectors.
[0121] In some implementations, multiple preset noise vectors are optimized in the latent space of the graphics generator to obtain multiple target noise vectors.
[0122] It should be noted that multiple preset noise vectors can be optimized sequentially or simultaneously, and this application embodiment does not impose specific limitations on this.
[0123] S302. Use a graphics generator to generate multiple target graphics based on multiple target noise vectors.
[0124] In this embodiment, a graphics generator is used to generate multiple target graphics based on multiple target noise vectors. This results in richer geometric diversity and higher training value for the OPC model, making the obtained OPC model more accurate and reliable.
[0125] S303. Train the OPC model based on multiple target graphs to obtain the target OPC model.
[0126] In this process, the model parameters of the OPC model are updated based on multiple target graphs to obtain the target OPC model.
[0127] Optionally, Figure 4 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 4 ,like Figure 4 As shown, the process of optimizing multiple preset noise vectors to obtain multiple target noise vectors in S301 above may include:
[0128] S401. Optimize the preset noise vectors in multiple preset directions to obtain the optimized noise vectors for each preset direction.
[0129] The preset noise vector can be represented as z.
[0130] In some implementations, a preset noise vector is optimized in multiple preset directions within the latent space of the graphics generator to obtain an optimized noise vector for each preset direction. The optimization of the preset noise vector in multiple preset directions can be performed simultaneously.
[0131] S402. Using a graphic generator, intermediate graphics in each preset direction are generated based on the optimized noise vectors in each preset direction.
[0132] In some implementations, the optimized noise vectors for each preset direction are input to the graphics generator, which can then output intermediate graphics for each preset direction.
[0133] S403. Determine the target intermediate graphic from the intermediate graphics of each preset direction.
[0134] In this embodiment of the application, based on the geometric diversity of the intermediate graphics in each preset direction, the intermediate graphic of the target direction with the best geometric diversity is selected from the intermediate graphics in each preset direction as the target intermediate graphic.
[0135] S404. Determine the target noise vector based on the optimized noise vector corresponding to the target intermediate graphic.
[0136] Specifically, from the optimized noise vectors of each preset direction, the optimized noise vector of the target direction corresponding to the target intermediate graphic is determined, that is, the optimized noise vector corresponding to the target intermediate graphic, wherein the target intermediate graphic is generated based on the optimized noise vector of the target direction.
[0137] In this embodiment, a similar optimization method is used to continuously optimize the optimized noise vector in the target direction to obtain the target noise vector. The graphic generated by the graphic generator based on the target noise vector is the graphic with the best geometric diversity in the target direction.
[0138] For example, the optimized noise vectors for each preset direction include: an optimized noise vector n1 for the first preset direction and an optimized noise vector n2 for the second preset direction; correspondingly, the intermediate patterns for each preset direction include: an intermediate pattern x1 for the first preset direction and an intermediate pattern x2 for the second preset direction. Among x1 and x2, x2 has the best geometric diversity and can be used as the target intermediate pattern. n2 is continuously optimized in the second preset direction until the target noise vector is obtained.
[0139] Optionally, Figure 5 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 5 ,like Figure 5 As shown, the process of determining the target intermediate graphic from the intermediate graphics in each preset direction in S403 above may include:
[0140] S501. Using the OPC model, multiple first prediction graphics for each preset direction are obtained based on the intermediate graphics for each preset direction.
[0141] In some implementations, the OPC model is used to perform multiple random forward propagations based on the intermediate patterns in each preset direction to obtain multiple first predicted patterns.
[0142] S502. Based on multiple first prediction graphics for each preset direction, perform geometric diversity assessment on each preset direction to obtain value assessment parameters for each preset direction.
[0143] In some implementations, a preset value assessment formula is used to assess the geometric diversity of each preset direction based on multiple first predicted patterns for each preset direction, thereby obtaining value assessment parameters for each preset direction. The larger the value assessment parameter for a preset direction, the richer the geometric diversity of the intermediate patterns in that preset direction.
[0144] S503. Based on the value assessment parameters of each preset direction, determine the intermediate graphic of the target direction from the intermediate graphics of each preset direction as the target intermediate graphic.
[0145] In this embodiment of the application, the highest value assessment parameter is determined from the value assessment parameters of each preset direction, and the highest value assessment parameter is the value assessment parameter of the target direction; the intermediate graphic of the target direction is determined from the intermediate graphics of each preset direction as the target intermediate graphic.
[0146] For example, the intermediate graphics in each preset direction include: the intermediate graphics x1 in the first preset direction and the intermediate graphics x2 in the second preset direction; correspondingly, the multiple first predicted graphics in each preset direction include: multiple first graphics x11, x12, and x13 in the first preset direction; and multiple first predicted graphics x21, x22, and x23 in the second preset direction.
[0147] Specifically, the value assessment parameter v1 for the first preset direction is calculated based on multiple first graphics x11, x12, and x13 in the first preset direction, and the value assessment parameter v2 for the second preset direction is calculated based on multiple first predicted graphics x21, x22, and x23 in the second preset direction. If v2 is greater than v1, then x2 is taken as the target intermediate graphic.
[0148] Optionally, Figure 6 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 6 ,like Figure 6 As shown, the process in S502 above, which evaluates the geometric diversity of each preset direction based on multiple first prediction graphics for each preset direction to obtain the value evaluation parameters for each preset direction, may include:
[0149] S601. Calculate the variance between multiple first prediction patterns in each preset direction to obtain the variance corresponding to each preset direction.
[0150] It should be noted that the variance between multiple first prediction patterns in each preset direction can be calculated simultaneously, thereby obtaining the variance corresponding to each preset direction simultaneously; or, the variance between multiple first prediction patterns in each preset direction can be calculated sequentially, thereby obtaining the variance corresponding to each preset direction sequentially.
[0151] S602. Based on the variance corresponding to each preset direction, obtain the value assessment parameters for each preset direction.
[0152] The variance corresponding to each preset direction is used as the value evaluation parameter for that preset direction. The larger the variance of a preset direction, the larger the value evaluation parameter for that preset direction, the richer the geometric diversity of the intermediate graphs in that preset direction, and the greater its value for OPC model training.
[0153] In summary, in this embodiment, the optimization of the preset noise vector z is achieved by calculating the gradient of the value function Vi(G(z)) with respect to z. Then, the gradient ascent method is used to optimize z (z := z +η). (...)), thereby continuously increasing the value Vi of the intermediate graph G(z) produced by the graph generator G based on the optimized z. Of course, in addition to gradient ascent, optimization in the latent space can also use derivative-free optimization algorithms, such as genetic algorithms and Bayesian optimization, to find high-value latent noise vectors z.
[0154] After obtaining the OPC model, the value criterion is transformed from geometric diversity to an OPC model-driven value criterion—maximizing OPC model uncertainty. For the i-th version of the OPC model Mi in the current iteration, we define its value function Vi(x). The key implementation is: Vi(x) = the prediction uncertainty of the OPC model Mi for the intermediate graph x. Specifically, this can be achieved through a Bayesian neural network or Monte Carlo Dropout technique: for the same input intermediate graph x, multiple random forward propagations are performed to obtain multiple first predicted graphs, and the variance among the multiple first predicted graphs is the uncertainty measure. The larger the variance, the larger the value assessment parameter, and the higher the value of the intermediate graph x.
[0155] It is worth noting that the value function can be, in addition to model uncertainty, the predicted edge placement error (EPE), process window sensitivity, or a weighted combination of these metrics. Any function that reflects the value of the graph to model calibration can be used as a substitute.
[0156] Furthermore, any network model for the initial graph generator that can map from the latent space to the graph space and supports gradient propagation is acceptable; this application does not impose any specific restrictions on this.
[0157] Optionally, Figure 7 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 7 ,like Figure 7 As shown, the process in S303 above, which trains the OPC model based on multiple target graphs to obtain the target OPC model, may include:
[0158] S701. Obtain the target real silicon wafer pattern corresponding to the target pattern.
[0159] The target real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the target pattern.
[0160] S702. The second predicted image is obtained by simulating exposure based on the target image using the OPC model.
[0161] S703. Based on the second predicted image and the target real silicon wafer image, train the OPC model to obtain the target OPC model.
[0162] The target OPC model can be represented as Mi+1.
[0163] In some implementations, a loss function value is calculated between the second predicted pattern and the target real silicon wafer pattern. The model parameters of the OPC model are updated based on this loss function value until a preset termination condition is met, thus obtaining the target OPC model. The preset termination condition is either that the loss function value converges or that the number of iterations reaches a preset number of iterations.
[0164] Optionally, Figure 8 A flowchart illustrating an OPC model training method provided in this application embodiment. Figure 8 ,like Figure 8 As shown, the process of training the model based on multiple test graphs to obtain the OPC model in S105 above may include:
[0165] S801. Obtain the initial real silicon wafer pattern corresponding to the test pattern.
[0166] The initial real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the test pattern.
[0167] S802. A third predicted image is obtained by simulating exposure based on the test image using a preset OPC model.
[0168] S803. Based on the third predicted graph and the initial real silicon wafer graph, train the preset OPC model to obtain the OPC model.
[0169] In some implementations, a loss function value is calculated between the third predicted pattern and the initial real silicon wafer pattern. The model parameters of a preset OPC model are then updated based on this loss function value until a preset termination condition is met, resulting in the OPC model. The preset termination condition is either that the loss function value converges or that the number of iterations reaches a preset number of iterations.
[0170] Figure 9 This is a complete flowchart illustrating an OPC model training method provided in an embodiment of this application, as shown below. Figure 9 As shown, the process includes: A) Start; B) Pre-training the graphics generation model; C) Generating multiple test graphics using the graphics generation model and performing real measurements to obtain multiple initial real silicon wafer graphics; D) Training the model based on the multiple test graphics and multiple initial real silicon wafer graphics to obtain the OPC model M0; E) Optimizing the iterative loop i=0, 1, 2, etc.; F) Calculating the value function Vi (e.g., model uncertainty) based on the current OPC model Mi; G) Optimizing in the latent space to make the graphics generator G produce multiple high-value target graphics; H) Performing real measurements on the multiple target graphics to obtain multiple target real silicon wafer graphics, and adding the multiple target graphics and multiple target real silicon wafer graphics to the training dataset; I) Training the OPC model M0 based on the training dataset to obtain the OPC model Mi+1; J) Determining whether the accuracy of the OPC model Mi+1 has converged; if not, i=i+1, and then executing process E for the next round of optimization iteration loop; if yes, then executing K, outputting the target OPC model and the training dataset.
[0171] In summary, in this embodiment, since the graphs generated in each iteration target the weakest and most uncertain aspects (steps F and G) of the current OPC model Mi, the data obtained from each measurement contributes the most to the correction of the OPC model parameters. This is equivalent to a master teacher creating practice questions specifically for students' knowledge gaps, which is far more efficient than the traditional method of aimlessly doing a large number of ordinary exercises. Therefore, a more accurate and robust OPC model can be calibrated with a much smaller number of graphs, greatly reducing measurement costs and time.
[0172] Furthermore, related technologies cannot create new graphics and struggle to cover all corner cases. The graphics generation model in this application possesses creativity, actively generating various complex and unusual graphics. More importantly, the value function Vi(x) (model uncertainty) automatically guides the generator to explore the "cognitive blind spots" (step G) of the current OPC model Mi. These blind spots often represent unpredictable corner cases. Through iteration, the OPC model is continuously strengthened in these weak points, and the final trained OPC model exhibits extremely strong generalization ability and robustness when facing various unknown complex designs (especially curved designs).
[0173] Furthermore, this application integrates deep learning into every step from graph generation and value assessment to optimal selection, forming a self-driven closed-loop optimization system. This reduces reliance on human experience, making the process of generating the optimal test graph set repeatable and optimizable, and capable of addressing more complex technological challenges in the future.
[0174] The following describes the OPC model training apparatus, device, and storage medium used to execute the OPC model training method provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the OPC model training method mentioned above, which will not be repeated below.
[0175] Figure 10 This is a schematic diagram of the structure of an OPC model training device provided in an embodiment of this application, as shown below. Figure 10 As shown, the device includes:
[0176] The cutting module 101 is used to cut the chip design layout file to obtain multiple basic blocks;
[0177] Processing module 102 is used to add noise to multiple base blocks to obtain multiple noise-added blocks;
[0178] The first training module 103 is used to train a graphics generator based on multiple noisy patches and corresponding real noise.
[0179] The generation module 104 is used to generate multiple test graphics based on multiple preset noise vectors using the graphics generator.
[0180] The second training module 105 is used to train the model based on multiple test graphs to obtain the OPC model.
[0181] Optionally, the first training module 103 is specifically used to use an initial graphics generator to predict noise based on the noisy patches to obtain predicted noise; and to update the model parameters of the initial graphics generator based on the predicted noise and the corresponding real noise to obtain the graphics generator.
[0182] Optionally, the processing module 102 is specifically used to add noise to a plurality of the basic blocks according to a preset random time step and a noise scheduling table to obtain a plurality of noise-added blocks;
[0183] The first training module 103 is specifically used to use the initial graphics generator to perform noise prediction based on the preset random time step and the noise-added graphics patch to obtain the predicted noise.
[0184] Optionally, the device further includes:
[0185] An optimization module is used to optimize multiple preset noise vectors to obtain multiple target noise vectors;
[0186] The first generation module has the ability to generate multiple target graphics based on multiple target noise vectors using the graphics generator.
[0187] The third training module is used to train the OPC model based on multiple target graphs to obtain the target OPC model.
[0188] Optionally, the optimization module is specifically used to optimize the preset noise vector in multiple preset directions to obtain optimized noise vectors for each preset direction; use the graphics generator to generate intermediate graphics for each preset direction based on the optimized noise vectors for each preset direction; determine a target intermediate graphic from the intermediate graphics for each preset direction; and determine the target noise vector based on the optimized noise vector corresponding to the target intermediate graphic.
[0189] Optionally, the optimization module is specifically used to employ the OPC model to obtain multiple first predicted graphics for each preset direction based on the intermediate graphics for each preset direction; to perform geometric diversity evaluation on each preset direction based on the multiple first predicted graphics for each preset direction to obtain value evaluation parameters for each preset direction; and to determine the intermediate graphics of the target direction from the intermediate graphics of each preset direction as the target intermediate graphics based on the value evaluation parameters for each preset direction.
[0190] Optionally, the optimization module is specifically used to calculate the variance among multiple first prediction patterns for each preset direction to obtain the variance corresponding to each preset direction; and to obtain the value evaluation parameters for each preset direction based on the variance corresponding to each preset direction.
[0191] Optionally, the third training module is specifically used to obtain the target real silicon wafer pattern corresponding to the target pattern, wherein the target real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the target pattern; to use the OPC model to perform simulated exposure based on the target pattern to obtain a second predicted pattern; and to train the OPC model based on the second predicted pattern and the target real silicon wafer pattern to obtain the target OPC model.
[0192] Optionally, the second training module is specifically used to obtain the initial real silicon wafer pattern corresponding to the test pattern, wherein the initial real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the test pattern; to obtain a third predicted pattern by simulating exposure based on the test pattern using a preset OPC model; and to train the preset OPC model based on the third predicted pattern and the initial real silicon wafer pattern to obtain the OPC model.
[0193] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0194] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0195] Figure 11 This is a schematic diagram of the structure of an OPC model training device provided in an embodiment of this application, as shown below. Figure 11 As shown, the OPC model training device includes: processor 201 and memory 202.
[0196] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiments. The specific implementation and technical effects are similar, and will not be described in detail here.
[0197] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.
[0198] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0199] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0200] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0201] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0202] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. An OPC model training method, characterized in that, The method includes: The chip design layout file is cut into multiple basic blocks; Add noise to multiple base blocks to obtain multiple noise-added blocks; A graph generator is trained based on multiple noisy image patches and their corresponding real noise. The aforementioned graphic generator is used to generate multiple test graphics based on multiple preset noise vectors; The OPC model is obtained by training the model based on multiple test graphs. The method further includes: Optimize multiple preset noise vectors to obtain multiple target noise vectors; Using the aforementioned image generator, multiple target images are generated based on multiple target noise vectors; The OPC model is trained based on multiple target graphs to obtain a target OPC model; The optimization of multiple preset noise vectors to obtain multiple target noise vectors includes: The preset noise vector is optimized in multiple preset directions to obtain the optimized noise vector for each preset direction. Using the aforementioned graphic generator, intermediate graphics in each of the preset directions are generated based on the optimized noise vectors of each preset direction; Determine the target intermediate graphic from the intermediate graphics of each of the preset directions; The target noise vector is determined based on the optimized noise vector corresponding to the target intermediate graphic.
2. The method according to claim 1, characterized in that, The step of training a graph generator based on multiple noisy image patches and corresponding real noise includes: An initial graphic generator is used to predict noise based on the noisy graphics blocks, resulting in predicted noise. The model parameters of the initial graphics generator are updated based on the predicted noise and the corresponding real noise to obtain the graphics generator.
3. The method according to claim 2, characterized in that, The step of adding noise to multiple base tiles to obtain multiple noisy tiles includes: Based on a preset random time step and a noise scheduling table, noise is added to multiple base blocks to obtain multiple noise-added blocks. The process employs an initial graphics generator to predict noise based on the noisy patches, resulting in predicted noise, including: Using the initial graphic generator, noise prediction is performed based on the preset random time step and the noise-added graphic block to obtain the predicted noise.
4. The method according to claim 1, characterized in that, Determining the target intermediate graphic from the intermediate graphics of each of the preset directions includes: Using the OPC model, multiple first prediction graphics for each preset direction are obtained based on the intermediate graphics for each preset direction; Based on multiple first prediction graphics for each preset direction, a geometric diversity assessment is performed on each preset direction to obtain value assessment parameters for each preset direction; Based on the value assessment parameters of each preset direction, the intermediate graphic of the target direction is determined from the intermediate graphics of each preset direction as the target intermediate graphic.
5. The method according to claim 4, characterized in that, The step of evaluating the geometric diversity of each preset direction based on multiple first prediction graphics for each preset direction to obtain value evaluation parameters for each preset direction includes: Calculate the variance among multiple first prediction patterns for each preset direction to obtain the variance corresponding to each preset direction; Based on the variance corresponding to each preset direction, the value assessment parameters for each preset direction are obtained.
6. The method according to claim 1, characterized in that, The step of training the OPC model based on multiple target graphs to obtain the target OPC model includes: Obtain the target real silicon wafer image corresponding to the target image, wherein the target real silicon wafer image is acquired by the lithography machine after performing real exposure based on the target image; The second predicted image is obtained by simulating exposure based on the target image using the OPC model. The OPC model is trained based on the second predicted image and the target real silicon wafer image to obtain the target OPC model.
7. The method according to any one of claims 1-6, characterized in that, The step of training the model based on multiple test graphs to obtain the OPC model includes: Obtain the initial real silicon wafer pattern corresponding to the test pattern. The initial real silicon wafer pattern is obtained by the lithography machine after performing real exposure based on the test pattern. A third predicted image is obtained by simulating exposure based on the test image using a preset OPC model. The preset OPC model is trained based on the third predicted graph and the initial real silicon wafer graph to obtain the OPC model.
8. An OPC model training device, characterized in that, include: A memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the OPC model training method according to any one of claims 1-7.