Static random access memory and manufacturing method thereof

Abstract

The invention provides a static random access memory and a manufacturing method thereof. The static random access memory at least comprises a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first read transistor (RPD) and a second read transistor (RPG). Wherein each of the first pull-down transistor (PD1) and the second access transistor (PG2) comprises a gate structure comprising a P-type work function metal layer, and an N-type work function metal layer on the P-type work function metal layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a static random access memory (SRAM), and more particularly to a structure of a static random access memory with balanced current. BACKGROUND

[0002] In an embedded static random access memory (embedded SRAM), there is a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a kind of volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The static random access memory stores data by using the conduction state of the transistor in the memory cell. The design of the static random access memory is based on the intercoupling transistor, there is no problem of capacitor discharge, it does not need to be charged constantly to keep the data from being lost, that is, it does not need to make memory update action, which is different from the dynamic random access memory (DRAM) which is also a kind of volatile memory, which stores data by using the charged state of the capacitor. The access speed of the static random access memory is quite fast, so it is used as cache memory and the like in computer systems. SUMMARY

[0003] This invention provides a static random access memory (SRAM) comprising at least a substrate, multiple fin structures located on the substrate, and multiple gate structures located on the substrate and spanning the multiple fin structures to form multiple transistors distributed on the substrate. Each transistor includes a portion of its gate structure spanning a portion of the fin structures. The multiple transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), and a second pull-down transistor (PD2), which together form a latch circuit. A first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit. A first read transistor (RPD) and a second read transistor (RPG) are connected in series. The gate structure of the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1). The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure, wherein each gate structure of the first pull-down transistor (PD1) and the second access transistor (PG2) includes a P-type work function metal layer and an N-type work function metal layer located on the P-type work function metal layer.

[0004] The present invention also provides a method for manufacturing a static random access memory (SRAM), comprising at least providing a substrate, forming multiple fin structures on the substrate, forming multiple gate structures on the substrate and spanning the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of its gate structure spanning a portion of the fin structures, wherein the multiple transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), and a second pull-down transistor (PD2), which together form a latch circuit, a first access transistor (PG1) and a second access transistor (PG2) connected to the latch circuit, and a first read transistor (RPD) and a second read transistor (RPG) connected in series, wherein the gate structure of the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1). The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure, wherein each gate structure of the first pull-down transistor (PD1) and the second access transistor (PG2) includes a P-type work function metal layer and an N-type work function metal layer located on the P-type work function metal layer.

[0005] The applicant discovered that the leakage current of current static random access memory (SRAM) still has room for improvement. Due to the layout pattern of the SRAM, some transistors have their finned structures cut off, resulting in differences in the current flowing through the two pull-down transistors and the two access transistors. This creates a current imbalance in the entire SRAM, thus affecting its performance. This invention reduces the P-type work function metal layer of some N-type transistors, thereby increasing the saturation current of some N-type transistors. By adjusting the saturation current of some N-type transistors, the overall current of the SRAM is balanced, thereby improving the stability and performance of the SRAM. Attached Figure Description

[0006] To facilitate understanding, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0007] Figure 1 This is a circuit diagram of a set of static random access memory cells in a static random access memory according to a first embodiment of the present invention.

[0008] Figure 2 This is a layout diagram of the static random access memory of the present invention.

[0009] Figure 3 A cross-sectional schematic diagram of a pull-up transistor, a pull-down transistor, an access transistor, and a read transistor according to a first embodiment of the present invention is shown.

[0010] Figure 4 A cross-sectional schematic diagram of the first / second pull-up transistor, the first pull-down transistor, the second access transistor, the access transistor / read transistor, the second pull-down transistor, and the first access transistor according to a second embodiment of the present invention is shown.

[0011] Figure 5 This is an example layout diagram of the static random access memory of the present invention after the formation of the masking layer.

[0012] [Symbol Explanation]

[0013] 10:8 TRF-SRAM memory cells

[0014] 12: Latch circuit

[0015] 20: Gate dielectric layer

[0016] 22: High dielectric constant layer

[0017] 24: Bottom Barrier Layer

[0018] 24A: Titanium nitride layer

[0019] 24B: Tantalum nitride layer

[0020] 25: P-type work function metal layer

[0021] 26: N-type work function metal layer

[0022] 27: Diffusion barrier layer

[0023] 28: Electrode layer

[0024] 30: Sidewall

[0025] A1: Area

[0026] A2: Area

[0027] B1: Area

[0028] B2: Area

[0029] S: Substrate

[0030] F: Fin-like structure

[0031] G: Gate structure

[0032] G1: Gate structure

[0033] G2: Gate structure

[0034] G3: Gate structure

[0035] G4: Gate structure

[0036] G5: Gate structure

[0037] HM: Mask

[0038] M0PY: Connection Structure

[0039] M0CT: Connection Structure

[0040] STI: Insulating Layer

[0041] V0: Contact element

[0042] RWL: Read character lines

[0043] RBL: Read Bit Line

[0044] PU1: First pull-up transistor

[0045] PU2: Second pull-up transistor

[0046] PD1: First pull-down transistor

[0047] PD2: Second pull-down transistor

[0048] PG1: First access transistor

[0049] PG2: Second access transistor

[0050] RPD: First Read Transistor

[0051] RPG: Second read transistor

[0052] BL1: The First Line

[0053] BL2: Second Line

[0054] WL1: Character Line

[0055] Vcc: Voltage source

[0056] Vss: Voltage source Detailed Implementation

[0057] Although specific configurations and arrangements are discussed herein, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that the disclosure of this application can also be used in a variety of other applications.

[0058] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0059] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context), as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or to describe multiple combinations of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey multiple usages, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0060] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosure of this application should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “on top of” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0061] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0062] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0063] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on top of and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0064] Please refer to Figure 1 and Figure 2 , Figure 1 This is a circuit diagram of a set of static random access memory cells in a static random access memory according to a first embodiment of the present invention. Figure 2 This is a layout diagram of a static random access memory according to the present invention.

[0065] In this embodiment, at least one 8-transistors register file SRAM (8TRF-SRAM) memory cell 10 is included. The 8TRF-SRAM memory cell 10 is preferably composed of a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1, a second access transistor PG2, a first read transistor RPD, and a second read transistor RPG, wherein the first read transistor RPD and the second read transistor RPG are connected in series. The first pull-up transistor PU1 and the second pull-up transistor PU2, the first pull-down transistor PD1 and the second pull-down transistor PD2 constitute a latch circuit 12, enabling data to be latched into a storage node. In this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and one drain region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0066] The gates of the first access transistor PG1 and the second access transistor PG2 are coupled to the word line WL1, and the sources S of the first access transistor PG1 and the second access transistor PG2 are coupled to the corresponding first bit line BL1 and the second bit line BL2, respectively. Additionally, the gate of the first read transistor RPD is connected to a read word line RWL, and the source of the first read transistor RPD is connected to a read bit line RBL. The gate of the second read transistor RPG is connected to the latch circuit 12, and the drain of the second read transistor RPG is connected to the voltage source Vss.

[0067] Figure 2 This is a layout diagram of a static random access memory (SRAM) according to the present invention. In this embodiment, as... Figure 2 As shown, the 8TRF-SRAM memory cell 10 is disposed on a substrate S, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate S can be a planar structure or have multiple fin structures F and multiple gate structures G located on the substrate S. In other embodiments of the present invention, it can also be applied to planar SRAM, meaning that it is not necessary to form fin structures on the substrate, but to form doped regions within the substrate, which is also within the scope of the present invention.

[0068] also Figure 2 The layout diagram also includes multiple metal layers. Here, the metal layer connecting the gates of each transistor is defined as MOPY, while the metal layer connecting the source / drain of each transistor is defined as MOCT. Figure 2 The MOSPY and MOST layers are represented by different meshes. However, the difference between MOSPY and MOST actually lies in the different connected components. Both are actually metal layers and can contain the same material, but are not limited to this. Figure 2 It also contains multiple contact posts (via) V0, which are used to connect the metal layers MOPY and MOCT to other conductive layers formed subsequently (such as M1, V1, M2, etc., commonly used in semiconductor manufacturing processes).

[0069] In the layout pattern of this invention, a three-dimensional SRAM is used as an example (that is, a fin-like structure F is formed to replace the planar doped region). Figure 2As shown, besides the locations of the fin structure F, gate structure G, connection structure MOPY, connection structure MOCT, and contact V0, the remaining portion of the substrate S is covered with an insulating layer, such as a shallow trench isolation (STI) structure, to isolate electronic components (e.g., transistors) and prevent short circuits. Furthermore, each gate structure G spans a portion of the fin structure F to form a transistor (e.g., the aforementioned first pull-up transistor PU1, second pull-up transistor PU2, first pull-down transistor PD1, second pull-down transistor PD2, first access transistor PG1, second access transistor PG2, first read transistor RPD, and second read transistor RPG). For clarity, the locations of the transistors are directly labeled. Figure 2 The above, especially the position marked at the junction of the gate structure G and the fin structure F.

[0070] In the first embodiment described above, each of the following transistors—the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, the second access transistor PG2, the first read transistor RPD, and the second read transistor RPG—each includes a gate structure G. The first pull-up transistor PU1 and the second pull-up transistor PU2 are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, the second access transistor PG2, the first read transistor RPD, and the second read transistor RPG are composed of N-type metal oxide semiconductor (PMOS) transistors. Therefore, from the cross-sectional view, the stacked material layers of each gate structure are different. A significant difference is that, typically, PMOS transistors have an additional P-type work function metal layer located in the gate stacked material layer compared to NMOS transistors.

[0071] For more details, please refer to Figure 3 , Figure 3 A cross-sectional schematic diagram illustrating the gate of the pull-up transistor, the gate of the pull-down transistor, the gate of the access transistor, and the gate of the read transistor according to a first embodiment of the present invention is shown. Wherein... Figure 3 In the text, "PU1 / PU2" represents the first pull-up transistor PU1 and / or the second pull-up transistor PU2. Figure 3 In the diagram, gate structure G1 represents the gate structure of the aforementioned transistor; "PD1 / PD2" represents the first pull-down transistor PD1 and the second pull-down transistor PD2, while "PG1 / PG2" represents the first access transistor PG1 and the second access transistor PG2. Figure 3In the diagram, gate structure G2 represents the gate structure of the aforementioned transistors (first pull-down transistor PD1, second pull-down transistor PD2, first access transistor PG1, and second access transistor PG2); "RPD / RPG" represents the first read transistor RPD and the second read transistor RPG. Figure 3 The gate structure of the transistor described above is represented by gate structure G3. For the sake of brevity, some components such as the substrate, dielectric layer, shallow trench isolation, source / drain, etc., are not shown in the figure, but those skilled in the art should recognize that these components exist in the semiconductor structure of the present invention.

[0072] like Figure 3 As shown, gate structures G1, G2, and G3 each include a gate dielectric layer 20, a high dielectric constant layer 22, a bottom barrier layer 24, an N-type work function metal layer 26, a diffusion barrier layer 27, and an electrode layer 28 stacked from bottom to top. If a gate recess (not shown) is first formed in the dielectric layer, and then the above material layers are sequentially formed in the gate recess, the cross-section of each material layer presents a "U" shape. Conversely, if the above material layers are stacked on a plane, the cross-section shows an "I" shape. Sidewalls 30 are also included on both sides of the stacked structure.

[0073] In this embodiment, the gate dielectric layer 20 is made of, for example, silicon oxide. The high dielectric constant layer 22 can be selected from dielectric materials with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicate oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide (SrTiO3). The diffusion barrier layer 24 may consist of the group consisting of bismuthtantalate (SrBi₂Ta₂O₉, SBT), lead zirconate titanate (PbZrₓTi₁ ... The electrode layer 28 is made of, for example, tungsten (W) or aluminum (Al). The sidewall 30 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., but the materials of the above-mentioned layers are only some examples of the present invention, and the present invention is not limited thereto.

[0074] It is worth noting that, in addition to the aforementioned gate dielectric layer 20, high dielectric constant layer 22, bottom barrier layer 24, N-type work function metal layer 26, and top electrode layer 28, the gate structure G1 (corresponding to the first pull-up transistor PU1 and / or the second pull-up transistor PU2) also includes a P-type work function metal layer 25 located between the bottom barrier layer 24 and the N-type work function metal layer 26. That is, from the cross-sectional view, the tantalum nitride (TaN) layer 24B of the bottom barrier layer 24 in the gate structure G1 directly contacts the P-type work function metal layer 25, and the N-type work function metal layer 26 also directly contacts the P-type work function metal layer 25.

[0075] In addition to the gate structure G1 (corresponding to the first pull-up transistor PU1 and / or the second pull-up transistor PU2) containing a P-type work function metal layer 25, the gate structure G2 (corresponding to the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2) also contains a P-type work function metal layer 25, while the gate structure G3 (corresponding to the first read transistor RPD and the second read transistor RPG) does not contain a P-type work function metal layer 25. Furthermore, the thickness of the P-type work function metal layer 25 in the gate structure G1 is approximately 16-32 angstroms, while the thickness of the P-type work function metal layer 25 in the gate structure G2 is approximately 8-16 angstroms. That is, the thickness of the P-type work function metal layer 25 in the gate structure G1 is greater than the thickness of the P-type work function metal layer 25 in the gate structure G2.

[0076] In contrast, the gate structure G3 in this embodiment (corresponding to the first read transistor RPD and the second read transistor RPG) does not include a P-type work function metal layer 25. That is, the tantalum nitride (TaN) layer 24B of the bottom barrier layer 24 in the gate structure G3 directly contacts the N-type work function metal layer 26.

[0077] The applicant found that in the first embodiment described above, there is still room for improvement in the leakage current of the 8TRF-SRAM memory cell 10. For example, because the fin structure spanned by each transistor has a different length, it affects the saturation drain current (Idsat) of each transistor, resulting in the first pull-down transistor PD1 and the second pull-down transistor PD2 of the 8TRF-SRAM memory cell 10 having different Idsats. Similarly, this also results in the first access transistor PG1 and the second access transistor PG2 having different Idsats.

[0078] More specifically, such as Figure 2 As shown, the fin structure F spanned by the first pull-down transistor PD1 is connected to the first read transistor RPD. Therefore, the fin structure F is a continuous structure between the first pull-down transistor PD1 and the first read transistor RPD (as shown). Figure 2As shown in region A1), however, the fin structure F spanned by the first pull-down transistor PD1 is not connected to the adjacent 8TRF-SRAM memory cell, therefore the fin structure F is disconnected between the second pull-down transistor PD2 and other 8TRF-SRAM memory cells (as shown in region A1). Figure 2 (As shown in region A2). Similarly, the fin structure spanned by the first access transistor PG1 is cut off between the first access transistor PG1 and the second read transistor RPG (as shown in region A2). Figure 2 As shown in region B1), the fin structure spanned by the second access transistor PG2 is a continuous structure between the second access transistor PG2 and its 8TRF-SRAM memory cell (as shown in region B1). Figure 2 (As shown in region B2). The varying lengths of the fin structures F traversed by the aforementioned transistors affect their saturation drain current. Specifically, according to the applicant's experiments, the saturation drain current of the first access transistor PG1 is approximately 10% lower than that of the second access transistor PG2, while the saturation drain current of the second pull-down transistor PD2 is approximately 10% lower than that of the first pull-down transistor PD1. This causes a current imbalance in the overall 8TRF-SRAM memory cell 10 and affects the quality of the 8TRF-SRAM memory cell 10.

[0079] To address the above issues, in other embodiments of the present invention, the applicant proposes a method to reduce the work function metal layer of some transistors to increase the saturation drain current of these transistors, thereby making the current of the overall 8TRF-SRAM memory cell 10 more balanced. See the following paragraphs for details.

[0080] The following description will focus on different embodiments of the static random access memory of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0081] Figure 4 A cross-sectional schematic diagram illustrating the first / second pull-up transistor, the first pull-down transistor / second access transistor, the access transistor / read transistor, the second pull-down transistor, and the first access transistor according to a second embodiment of the present invention is shown. Figure 4 As shown, this embodiment also proposes an 8TRF-SRAM memory cell, whose circuit diagram and layout pattern are the same as those of the first embodiment described above. Therefore, it can be referred to... Figure 1 and Figure 2 As shown, I will not repeat the details here.

[0082] This embodiment differs from the first embodiment described above in that, since the saturation drain currents of the first access transistor PG1 and the second pull-down transistor PD2 are low, the P-type work function metal layer 25 of the first access transistor PG1 and the second pull-down transistor PD2 is removed during fabrication to increase their saturation drain current, while the P-type work function metal layer 25 of the second access transistor PG2 and the first pull-down transistor PD1 is retained. Since both the first access transistor PG1 and the second pull-down transistor PD2 are N-type transistors, the P-type work function metal layer 25 suppresses their saturation drain current. Conversely, removing the P-type work function metal layer 25 increases the saturation drain current of the N-type transistors.

[0083] Therefore, as Figure 4 As shown, after removing the P-type work function metal layer 25 from the first access transistor PG1 and the second pull-down transistor PD2, the gate structure of the second pull-down transistor PD2 is defined as gate structure G4, and the gate structure of the first access transistor PG1 is defined as gate structure G5. Gate structures G3 (corresponding to the first read transistor RPD and the second read transistor RPG), G4 (corresponding to the second pull-down transistor PD2), and G5 (corresponding to the first access transistor PG1) have the same structure, meaning they all do not contain the P-type work function metal layer 25. Therefore, the tantalum nitride (TaN) layer 24B of the bottom barrier layer 24 directly contacts the N-type work function metal layer 26.

[0084] In actual manufacturing processes, Figure 5 This is an example layout diagram of the static random access memory (SRAM) of the present invention after the formation of the masking layer. For example... Figure 5 As shown, to remove the P-type work function metal layer 25 of gate structures G4 and G5, a P-type work function metal layer 25 can be formed in the gate of each transistor during the manufacturing process. Then, a mask HM is used to cover the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second access transistor PG2, exposing the first read transistor RPD, the second read transistor RPG, the first access transistor PG1, and the second pull-down transistor PD2. An etching process is then performed to remove the P-type work function metal layer 25 from the first read transistor RPD, the second read transistor RPG, the first access transistor PG1, and the second pull-down transistor PD2. In this embodiment, the pattern of the mask HM has multiple right-angled boundaries and exposes the first read transistor RPD, the second read transistor RPG, the first access transistor PG1, and the second pull-down transistor PD2. However, the present invention does not limit the pattern shape of the mask HM, and the specific shape of the mask can be adjusted according to requirements.

[0085] According to the applicant's experimental results, the above method can reduce the difference between the saturated drain current of the first access transistor PG1 and the saturated drain current of the second access transistor PG2, and also reduce the difference between the saturated drain current of the second pull-down transistor PD2 and the first pull-down transistor PD1. This improves the current balance of the overall 8TRF-SRAM memory cell 10. Furthermore, in other embodiments of the present invention, the saturated drain current of each transistor can be fine-tuned, thereby making the current of the overall 8TRF-SRAM memory cell 10 more balanced. For example, in the step of removing the P-type work function metal layer 25, the P-type work function metal layer 25 in the first access transistor PG1 and the second pull-down transistor PD2 can be partially removed during etching, leaving a smaller portion of the P-type work function metal layer 25. This variation also falls within the scope of the present invention.

[0086] Based on the above description and accompanying drawings, the present invention provides a static random access memory (Please refer to...). Figure 4 (An embodiment of the invention) includes at least a substrate S, multiple fin structures F located on the substrate S, and multiple gate structures G located on the substrate S and spanning the multiple fin structures F to form multiple transistors distributed on the substrate. Each transistor includes a portion of its gate structure G spanning a portion of the fin structures F. The multiple transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), and a second pull-down transistor (PD2), which together form a latch circuit. A first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit, and a first read transistor (RPD) and a second read transistor (RPG) are connected in series. The gate structure included in the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1). The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure (e.g., Figure 4 The gate structure G2 of the first pull-down transistor (PD1) and the second access transistor (PG2) each includes a P-type work function metal layer 25 and an N-type work function metal layer 26 on the P-type work function metal layer 25.

[0087] In some embodiments of the present invention, the gate structure G2 of the first pull-down transistor (PD1) and the second access transistor (PG2) respectively includes a P-type work function metal layer 25 made of titanium nitride and an N-type work function metal layer 26 made of titanium aluminide.

[0088] In some embodiments of the present invention, the P-type work function metal layer 25 is in direct contact with the N-type work function metal layer 26.

[0089] In some embodiments of the present invention, the gate structure G2 of the first pull-down transistor (PD1) and the second access transistor (PG2) further includes a bottom barrier layer 24 located below the P-type work function metal layer 25, a diffusion barrier layer 27 located on the N-type work function metal layer 26, and an electrode layer 28 located on the diffusion barrier layer 27.

[0090] In some embodiments of the present invention, the bottom barrier layer 24 includes a stacked structure of a titanium nitride layer 24A and a tantalum nitride layer 25B, wherein the tantalum nitride layer 24B is located above the titanium nitride layer 24A and directly contacts the p-type work function metal layer 25.

[0091] In some embodiments of the present invention, the diffusion barrier layer 27 comprises titanium nitride and the diffusion barrier layer 27 directly contacts the N-type work function metal layer 26.

[0092] In some embodiments of the present invention, the electrode layer 28 is made of tungsten or aluminum.

[0093] In some embodiments of the present invention, the first read transistor (RPD) and the second read transistor (RPG) each include a gate structure G3, the second pull-down transistor (PD2) includes a gate structure G4, the first access transistor (PG1) includes a gate structure G5, and the gate structures G4, G5, and G3 of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG) each include an N-type work function metal layer 26, and a bottom barrier layer 24 is located below the N-type work function metal layer 26.

[0094] In some embodiments of the present invention, in the gate structures G4, G5, and G3 of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG), the bottom barrier layer 24 includes a stacked structure of a titanium nitride layer 24A and a tantalum nitride layer 24B, wherein the tantalum nitride layer 24B is located above the titanium nitride layer 24A and directly contacts the N-type work function metal layer 26 (e.g., ...). Figure 4 In the embodiment shown, gate structures G3, G4, and G5 do not contain a P-type work function metal layer 25, therefore the N-type work function metal layer 26 directly contacts the tantalum nitride layer 24.

[0095] In some embodiments of the present invention, the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each include a gate structure G1, and the gate structure G1 of the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each includes an N-type work function metal layer 26 and a P-type work function metal layer 25.

[0096] In some embodiments of the present invention, the thickness of the P-type work function metal layer 25 in the gate structure G1 of the first pull-up transistor (PU1) is greater than the thickness of the P-type work function metal layer 25 in the gate structure G2 of the first pull-down transistor (PD1).

[0097] This invention also provides a method for manufacturing a static random access memory (SRAM) (please refer to...). Figures 2-4 (An embodiment of the invention) includes at least a substrate S, on which multiple fin structures F are formed, and multiple gate structures G are formed on the substrate S and span the multiple fin structures F to form multiple transistors distributed on the substrate. Each transistor includes a portion of the gate structure G spanning a portion of the fin structures F. The multiple transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), and a second pull-down transistor (PD2), which together form a latch circuit. A first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit, and a first read transistor (RPD) and a second read transistor (RPG) are connected in series. The gate structure included in the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1). The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure (e.g., Figure 4 The gate structure G2 of the first pull-down transistor (PD1) and the second access transistor (PG2) each includes a P-type work function metal layer 25 and an N-type work function metal layer 26 on the P-type work function metal layer 25.

[0098] The applicant discovered that the leakage current of current static random access memory (SRAM) still has room for improvement. Due to the layout pattern of the SRAM, some transistors have their finned structures cut off, resulting in differences in the current flowing through the two pull-down transistors and the two access transistors. This creates a current imbalance in the entire SRAM, thus affecting its performance. This invention reduces the P-type work function metal layer of some N-type transistors, thereby increasing the saturation current of some N-type transistors. By adjusting the saturation current of some N-type transistors, the overall current of the SRAM is balanced, thereby improving the stability and performance of the SRAM.

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A static random access memory, comprising at least: Base; Multiple fin-like structures are located on this substrate; Multiple gate structures are located on the substrate and span the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structures, and wherein the multiple transistors include: The first pull-up transistor (PU1), the first pull-down transistor (PD1), the second pull-up transistor (PU2), and the second pull-down transistor (PD2) together form a latch circuit. The first access transistor (PG1) and the second access transistor (PG2) are connected to the latch circuit; as well as A first read transistor (RPD) and a second read transistor (RPG) are connected in series, wherein the gate structure of the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1); The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure, wherein each of the gate structures of the first pull-down transistor (PD1) and the second access transistor (PG2) includes a P-type work function metal layer and an N-type work function metal layer located on the P-type work function metal layer.

2. The static random access memory according to claim 1, wherein in the gate structure of the first pull-down transistor (PD1) and the gate structure of the second access transistor (PG2), the material of the P-type work function metal layer comprises TiN (titanium nitride) and the material of the N-type work function metal layer comprises TiAl (titanium aluminum nitride).

3. The static random access memory according to claim 2, wherein the P-type work function metal layer is in direct contact with the N-type work function metal layer.

4. The static random access memory according to claim 1, wherein the gate structure of the first pull-down transistor (PD1) and the gate structure of the second access transistor (PG2) further include a bottom barrier layer located below the P-type work function metal layer, a diffusion barrier layer located on the N-type work function metal layer, and an electrode layer located on the diffusion barrier layer.

5. The static random access memory according to claim 4, wherein the bottom barrier layer comprises a stacked structure of a TiN layer and a TaN layer, the TaN layer being located above the TiN layer and the TaN layer directly contacting the P-type work function metal layer.

6. The static random access memory according to claim 4, wherein the diffusion barrier layer comprises TiN, the diffusion barrier layer directly contacts the N-type work function metal layer, and the electrode layer is made of W or Al.

7. The static random access memory according to claim 1, wherein the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG) each include a gate structure, and the gate structure of each of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG) includes an N-type work function metal layer and a bottom barrier layer located below the N-type work function metal layer.

8. The static random access memory according to claim 7, wherein in the gate structure of each of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG), the bottom barrier layer comprises a stacked structure of a TiN layer and a TaN layer, the TaN layer being located above the TiN layer and directly contacting the N-type work function metal layer.

9. The static random access memory according to claim 1, wherein the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each include a gate structure, and the gate structure of the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each includes an N-type work function metal layer and a P-type work function metal layer.

10. The static random access memory according to claim 9, wherein the thickness of the P-type work function metal layer in the gate structure of the first pull-up transistor (PU1) is greater than the thickness of the P-type work function metal layer in the gate structure of the first pull-down transistor (PD1).

11. A method for manufacturing a static random access memory, comprising at least: Provide a base; Multiple fin-like structures are formed on this substrate; Multiple gate structures are formed on the substrate and span the multiple fin structures to form multiple transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning a portion of the fin structures, and wherein the multiple transistors include: The first pull-up transistor (PU1), the first pull-down transistor (PD1), the second pull-up transistor (PU2), and the second pull-down transistor (PD2) together form a latch circuit. The first access transistor (PG1) and the second access transistor (PG2) are connected to the latch circuit; as well as A first read transistor (RPD) and a second read transistor (RPG) are connected in series, wherein the gate structure of the first read transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1); The first pull-down transistor (PD1) and the second access transistor (PG2) each include a gate structure, wherein each of the gate structures of the first pull-down transistor (PD1) and the second access transistor (PG2) includes a P-type work function metal layer and an N-type work function metal layer located on the P-type work function metal layer.

12. The method for manufacturing a static random access memory according to claim 11, wherein in the gate structure of the first pull-down transistor (PD1) and the gate structure of the second access transistor (PG2), the material of the P-type work function metal layer comprises TiN, and the material of the N-type work function metal layer comprises TiAl.

13. The method for manufacturing a static random access memory according to claim 12, wherein the P-type work function metal layer is in direct contact with the N-type work function metal layer.

14. The method for manufacturing a static random access memory according to claim 11, wherein the gate structure of the first pull-down transistor (PD1) and the gate structure of the second access transistor (PG2) further include a bottom barrier layer located below the P-type work function metal layer, a diffusion barrier layer located on the N-type work function metal layer, and an electrode layer located on the diffusion barrier layer.

15. The method for fabricating a static random access memory according to claim 14, wherein the bottom barrier layer comprises a stacked structure of a TiN layer and a TaN layer, the TaN layer being located above the TiN layer and the TaN layer directly contacting the P-type work function metal layer.

16. The method for fabricating a static random access memory according to claim 14, wherein the diffusion barrier layer comprises TiN, the diffusion barrier layer directly contacts the N-type work function metal layer, and the electrode layer is made of W or Al.

17. The method for manufacturing a static random access memory according to claim 11, wherein the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG) each include a gate structure, and the gate structure of each of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG) includes an N-type work function metal layer and a bottom barrier layer located below the N-type work function metal layer.

18. The method for manufacturing a static random access memory according to claim 17, wherein in the gate structure of each of the second pull-down transistor (PD2), the first access transistor (PG1), the first read transistor (RPD), and the second read transistor (RPG), the bottom barrier layer comprises a stacked structure of a TiN layer and a TaN layer, the TaN layer being located above the TiN layer and the TaN layer directly contacting the N-type work function metal layer.

19. The method for manufacturing a static random access memory according to claim 11, wherein the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each include a gate structure, and the gate structure of the first pull-up transistor (PU1) and the second pull-up transistor (PU2) each includes an N-type work function metal layer and a P-type work function metal layer.

20. The method for manufacturing a static random access memory according to claim 19, wherein the thickness of the P-type work function metal layer in the gate structure of the first pull-up transistor (PU1) is greater than the thickness of the P-type work function metal layer in the gate structure of the first pull-down transistor (PD1).

Images