Memory, reading method and electronic equipment

Abstract

The invention provides a memory, a reading method and electronic equipment, the memory comprises a first bit line, a second bit line and an induction amplifier which are connected with a memory unit, and when a reading voltage is applied to the first bit line, the memory unit outputs a reading current through the second bit line; the first input end of the induction amplifier receives the read current on the second bit line, the second input end of the induction amplifier receives the reference current, and a comparison result is output based on the read current and the reference current; the input end of the reading circuit is connected with the output end of the sense amplifier, the first output end is connected with the first bit line, and the reading voltage of the first bit line is adjusted according to the comparison result. By fixing the reference current and continuously adjusting the read voltage, the read current of the storage unit is continuously adjusted, so that the comparison result of the induction amplifier is continuously adjusted until the storage data of the storage unit can be determined according to the comparison result, the input common-mode current of the induction amplifier is controlled, the sensing precision of the induction amplifier is improved, and the power consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a memory, a reading method, and an electronic device. Background Technology

[0002] Data stored in memory is usually in the form of very weak voltage or current. Direct reading may lead to misreading or failure to read. These weak signals can be amplified by a sense amplifier (SA).

[0003] However, the sensing accuracy of the sensing amplifier is affected by a wide range of input common-mode currents. Summary of the Invention

[0004] This application provides a memory, a reading method, and an electronic device for improving the sensing accuracy of an induction amplifier.

[0005] In a first aspect, this application provides a memory, the memory comprising:

[0006] Storage unit;

[0007] The storage cell is connected to a first bit line and a second bit line. When a read voltage is applied to the first bit line, the storage cell outputs a read current through the second bit line.

[0008] An inductive amplifier, wherein a first input terminal of the inductive amplifier is connected to the second bit line and receives a read current on the second bit line, a second input terminal of the inductive amplifier receives a reference current, and the inductive amplifier outputs a comparison result based on the read current and the reference current;

[0009] A read circuit is provided, wherein the input terminal of the read circuit is connected to the output terminal of the inductive amplifier, and the first output terminal of the read circuit is connected to the first bit line. The read circuit adjusts the read voltage of the first bit line according to the comparison result, so as to adjust the comparison result output by the inductive amplifier, until the stored data of the memory cell is determined according to the comparison result.

[0010] Secondly, this application provides a method for reading a memory, the method being used in the aforementioned memory, the method comprising:

[0011] When a read voltage is applied to the first bit line, the memory cell is controlled to output a read current through the second bit line;

[0012] The sensor amplifier is controlled to output a comparison result based on the read current and the reference current;

[0013] The read circuit is controlled to adjust the read voltage according to the comparison result, so as to adjust the comparison result until the stored data of the memory cell is determined according to the comparison result.

[0014] Thirdly, this application provides an electronic device including the processor described in the above embodiments;

[0015] The memory, reading method, and electronic device provided in this application include a memory cell; a first bit line and a second bit line connected to the memory cell, wherein when a reading voltage is applied to the first bit line, the memory cell outputs a reading current through the second bit line; a sensing amplifier, wherein the first input terminal of the sensing amplifier is connected to the second bit line and receives the reading current on the second bit line, the second input terminal of the sensing amplifier receives a reference current, and the sensing amplifier outputs a comparison result based on the reading current and the reference current; the input terminal of a reading circuit is connected to the output terminal of the sensing amplifier, the first output terminal of the reading circuit is connected to the first bit line, and the reading circuit adjusts the reading voltage of the first bit line according to the comparison result to adjust the comparison result of the sensing amplifier until the stored data of the memory cell is determined according to the comparison result. The solution of this application fixes the reference current and continuously adjusts the reading voltage to continuously adjust the reading current of the memory cell, thereby continuously adjusting the comparison result of the sensing amplifier until the stored data of the memory cell can be determined according to the comparison result, thereby controlling the input common-mode current of the sensing amplifier, improving the sensing accuracy of the sensing amplifier, and reducing power consumption. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a 2T0C memory cell;

[0018] Figure 2 This is a schematic diagram of the structure of a 2T0C memory cell provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of another 2T0C memory cell provided in an embodiment of this application;

[0020] Figure 4 A schematic diagram of a reference current generation circuit provided in one embodiment of this application;

[0021] Figure 5 A schematic diagram showing the correspondence between a reference current and an amplification result provided in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the structure of a memory provided in one embodiment of this application;

[0023] Figure 7 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0024] Figure 8 A schematic diagram of the read current provided in one embodiment of this application;

[0025] Figure 9 A schematic diagram of the structure of a memory provided in another embodiment of this application;

[0026] Figure 10 This is a schematic diagram of the structure of another memory provided in an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the structure of an inductive amplifier provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] Figure 1 A schematic diagram of a 2T0C memory cell structure is shown, as follows: Figure 1 As shown, the 2T0C memory cell includes two transistors: a write transistor M and a read transistor M'. The gate of the write transistor M is connected to the write word line WWL, the first terminal of the write transistor M is connected to the write bit line WBL, and the second terminal of the write transistor M is coupled to the gate of the read transistor M' through the memory node SN. The first terminal of the read transistor M' is connected to the read word line RWL, and the second terminal of the read transistor M' is connected to the read bit line RBL.

[0030] During the writing process, a turn-on voltage is input to the gate of the write transistor M via the write word line WWL to turn on the write transistor M, and a write voltage is input via the write bit line WBL to store the write voltage in the memory node SN. For example, the write voltage may include the voltage corresponding to the stored data.

[0031] Storing data can be in multiple-bit formats, such as 2 bits, 3 bits, and 4 bits. Two bits correspond to four data types (00, 01, 10, 11), three bits to eight (000, 001, 010, 011, 100, 101, 110, 111), and four bits to sixteen (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111). Different data types can correspond to different currents and voltages. Specifically, different stored data types can correspond to different write voltages, and different write voltages control the read transistors to have different on / off states, thus resulting in different read currents.

[0032] During the reading process, a voltage is applied to the read word line RWL, and combined with the write voltage of the storage node SN, a corresponding read current is formed between the read word line RWL and the read bit line RBL.

[0033] However, in a storage array, if the voltage of the storage node SN of a storage cell is low and the voltage of the storage node SN of an adjacent storage cell is high, there will be crosstalk or current sharing problems between the read bit line and the read word line RWL of that storage cell, which will affect the reading results of that storage cell.

[0034] For example, for ease of description, a memory cell with a low voltage at memory node SN is called the first memory cell, and the three memory cells adjacent to the first memory cell are called the second, third, and fourth memory cells, respectively. The first and second memory cells share a read bit line, the second and third memory cells share a read word line, the third and fourth memory cells share a read bit line, and the fourth memory cell shares a read word line with the first memory cell. Furthermore, the voltages of the memory nodes of the second, third, and fourth memory cells are all high voltages.

[0035] When the read bit line of the first memory cell receives voltage, the following current path is formed: read bit line of the first memory cell — read transistor M' of the second memory cell — read word line RWL of the second and third memory cells — read transistor M' of the third memory cell — read bit line of the third and fourth memory cells — read transistor M' of the fourth memory cell — read word line RWL of the fourth and first memory cells. This causes the read transistor M' of the first memory cell to be turned on through the adjacent memory cell, resulting in crosstalk or current sharing between the read bit line and the read word line RWL of the first memory cell, which affects the reading result of the first memory cell.

[0036] Figure 2 This illustration shows a structural schematic diagram of another 2T0C memory cell provided in an embodiment of this application. Figure 2 The 2T0C storage structure shown can solve the current crosstalk and current sharing problems that exist in traditional 2T0C storage cells when reading data.

[0037] like Figure 2 As shown, the 2T0C memory cell includes two transistors, a write transistor M and a read transistor M', with the read transistor M' being a dual-gate transistor. The gate of the write transistor M is connected to the write word line WWL, the first terminal of the write transistor M is connected to the write bit line RBL, the second terminal of the write transistor M is coupled to the second gate of the read transistor M' through the memory node SN, the first gate of the read transistor M' is connected to the read word line RWL, the first terminal of the read transistor M' is connected to the read bit line, and the second terminal of the read transistor M' receives the reference voltage Vrefn.

[0038] For the memory cell that needs to be written, during the writing process, the write transistor M is turned on by inputting a turn-on voltage to the gate of the write transistor M through the write word line WWL, and the write voltage is input through the write bit line RBL to store the write voltage in the memory node SN, that is, to store the write voltage in the second gate of the read transistor M'.

[0039] In practical applications, for multiple memory cells connected to the same write bit line, when any one memory cell writes data through that write bit line, the other memory cells connected to the same write bit line need to be turned off to ensure that only that memory cell is written to. For example, a voltage different from the aforementioned turn-on voltage can be applied to the write word line WWL connected to other memory cells to turn on the write transistor M of that memory cell and turn off the write transistor M of the other memory cells.

[0040] For a memory cell to be read, during the reading process, a preset voltage is input through the read word line RWL, and a reference voltage Vrefn is input to the second terminal of the read transistor M'. If a change in the voltage at the first terminal of the read transistor M' is detected, the voltage stored at the second gate of the read transistor M' can be determined based on the change value, thus identifying the data stored in the memory cell. If no change in the voltage at the first terminal of the read transistor M' is detected, the data stored in the memory cell can also be determined.

[0041] It should be noted that when a preset voltage is input through the read word line RWL, due to the back-gate effect of the gate of the read transistor M', the threshold voltage of the first gate of the read transistor M' will shift when the second gate of the read transistor M' provides the write voltage for storage. The shift will vary depending on the voltage provided by the second gate. Taking an N-type transistor as an example, when the voltage of the second gate is high, the threshold voltage of the first gate of the read transistor M' shifts negatively; when the voltage of the second gate is low, the threshold voltage of the first gate of the read transistor M' shifts positively.

[0042] Therefore, when a preset voltage is applied to the first gate of the read transistor M' via the read word line RWL, the preset voltage can be determined based on the write voltage stored at the second gate of the read transistor M' to ensure that the read transistor M' is turned off. For example, the preset voltage can be located between a first threshold voltage and a second threshold voltage to supplement the voltage at the second gate, thereby turning off the read transistor M'. The first threshold voltage can be the threshold voltage at which the read transistor M' can be turned on when the voltage stored at the second gate of the read transistor M' is high, and the second threshold voltage is the threshold voltage at which the read transistor M' can be turned on when the voltage stored at the second gate of the read transistor M' is low.

[0043] For example, the reference voltage Vrefn may include, but is not limited to, 0V. The first threshold voltage and the second threshold voltage may be determined according to different requirements, and are not limited here.

[0044] In a dual-gate transistor, the main gate (i.e., the first gate of the read transistor M' in this application) is used to control the main current path, while the secondary gate (i.e., the second gate of the read transistor M' in this application) is used to regulate the current control of the main gate. For example, when a high voltage is applied to the main gate, a conducting current is formed between the source and drain, allowing current to flow. When a positive voltage is applied to the secondary gate, the electric field effect of the main gate is increased, increasing the degree of current flow. When a negative voltage is applied to the secondary gate, the electric field effect of the main gate is reduced, decreasing the degree of current flow.

[0045] therefore, Figure 2The 2TOC memory cell shown has a different preset voltage at the read word line RWL of the memory cell that does not need to read data compared to the preset voltage at the read word line RWL of the memory cell that needs to read data. This ensures that only the read transistor M' of the memory cell that needs to read data is controlled by the preset voltage to be turned on or off, while the read transistor M' of the memory cell that does not need to read data is turned off. This solves the current crosstalk and current sharing problems that exist in the traditional 2TOC memory cell during data reading. For example, the current sharing and crosstalk problems in the 2TOC memory cell can be solved by applying a low voltage to the read word line RWL of the memory cell that does not need to read data. Furthermore, the current between the source and drain of the read transistor M' can be controlled by the write voltage stored at the second gate of the read transistor M', so that the data stored in the memory cell can be determined by the voltage change at the first gate of the read transistor M'.

[0046] In some embodiments, the read bit line RBL and the write bit line WBL can be input with the same voltage or different voltages. When different voltages are required, the read bit line RBL and the write bit line WBL have no signal connection and can be connected to different bit lines in practical applications. When the same voltage is required, the read bit line RBL and the write bit line WBL can be electrically connected, that is, the read bit line RBL and the write bit line WBL can be a single bit line, thereby reducing the number of bit lines and achieving higher structural density.

[0047] Figure 3 This application provides a schematic diagram of the structure of another 2T0C memory cell according to an embodiment of the present application. Figure 3 As shown, the first electrode of the write transistor M and the first electrode of the read transistor M' are connected to the same bit line BL, which reduces the number of bit lines. In the layout design, only one via is needed to connect a bit line to the relevant electrodes of the two transistors, which helps to achieve high-density version design.

[0048] Specifically, the gate of the write transistor M is connected to the write word line WWL, the first terminal of the write transistor M is connected to the bit line BL, the second terminal of the write transistor M is coupled to the second gate of the read transistor M' through the storage node SN, the first gate of the read transistor M' is connected to the read word line RWL, the first terminal of the read transistor M' is connected to the bit line BL, and the second terminal of the read transistor M' receives the reference voltage Vrefn.

[0049] Figure 3 The read / write process of the 2T0C memory cell shown can be referenced. Figure 2 The read and write process of the 2T0C memory cell shown will not be described in detail here.

[0050] In practical applications, since the data in the storage unit is usually in the form of very weak voltage or current, direct reading may lead to misreading or failure to read. These weak signals can be amplified by a sense amplifier (SA) and then processed by subsequent circuits.

[0051] For example, an inductive amplifier can generate a voltage signal based on the current difference between a reference current Iref and the read current Icell of a memory cell, and amplify the voltage signal to enable reading of the state of the memory cell.

[0052] In some embodiments, considering that different memory cells have different storage bits, corresponding to different read currents Icell, and that the sensing amplifier has limitations on the input current difference, such as only being able to amplify differences greater than a certain value, the reference current Iref of the sensing amplifier can be adjusted. For example, the reference current Iref of the sensing amplifier can be dynamically changed according to the storage bits of the memory cell.

[0053] For example, such as Figure 4 As shown, when performing read operations on different memory cells, different reference currents Iref can be output by the successive approximation register 101, comparator 102, and digital-to-analog converter 103. The stored data of the memory cell is determined based on the relationship between the reference current Iref and the read current Icell. Specifically, the input of the digital-to-analog converter 103 is connected to the output of the successive approximation register 101, the output of the digital-to-analog converter 103 is connected to the first input of the comparator 102, the second input of the comparator 102 obtains the read current Icell of the memory cell, and the output of the comparator 102 is connected to the input of the successive approximation register 101. Comparator 102 compares the read current Icell with the current reference current. If the read current Icell is greater than or equal to the current reference current, it outputs a comparison result of 1; if the read current Icell is less than the current reference current, it outputs a comparison result of 0. Comparator 102 then outputs the comparison result to successive approximation register 101. Successive approximation register 101 adjusts its bits according to the current comparison result and determines the digital signal of the next reference current based on the current comparison result. Digital-to-analog converter 103 converts the received digital signal of the reference current into an analog signal and sends it to comparator 102.

[0054] For example, the reference current Iref for the current read operation can be determined based on the correspondence between the existing reference current Iref and the comparison result, so as to obtain the reference current Iref for the read operation more quickly.

[0055] like Figure 5As shown, when the first comparison result is "1", the second reference current Iref is determined to be I7.

[0056] When the second comparison result is "1", the third reference current Iref is determined to be I. 11 When the second comparison result is "0", the third reference current Iref is determined to be I3.

[0057] When the third reference current Iref is I 11 In the case where the third comparison result is "0", the fourth reference current Iref is determined to be I. 13 When the third comparison result is "1", the fourth reference current Iref is determined to be I9; when the third reference current Iref is I3, when the third comparison result is "0", the fourth reference current Iref is determined to be I5; when the third comparison result is "1", the fourth reference current Iref is determined to be I1.

[0058] When the fourth reference current Iref is I 13 In the case where the fourth comparison result is "0", the fifth reference current Iref is determined to be I. 14 When the fourth comparison result is "1", the fifth reference current Iref is determined to be I. 12 When the fourth reference current Iref is I9, and the fourth comparison result is "0", the fifth reference current Iref is determined to be I. 10 When the fourth comparison result is "1", the fifth reference current is determined to be I8; when the fourth reference current Iref is I5, when the fourth comparison result is "0", the fifth reference current Iref is determined to be I6; when the fourth comparison result is "1", the fifth reference current is determined to be I4; when the fourth reference current Iref is I1, when the fourth comparison result is "0", the fifth reference current Iref is determined to be I2; when the fourth comparison result is "1", the fifth reference current is determined to be I0.

[0059] Furthermore, considering that the sensing amplifier may be affected by a large range of input common-mode currents, increasing the sensing accuracy and power consumption, an embodiment of this application provides a memory that continuously adjusts the read voltage by fixing the reference current Iref, thereby continuously adjusting the read current of the memory cell, and thus continuously adjusting the comparison result of the sensing amplifier until the stored data of the memory cell can be determined based on the comparison result, thereby controlling the input common-mode current of the sensing amplifier, improving the sensing accuracy of the sensing amplifier, and reducing power consumption.

[0060] Figure 6 An embodiment of the memory provided in this application is shown, such as Figure 6 As shown, the memory provided in this application embodiment includes:

[0061] Storage unit 10;

[0062] The first bit line BL1 and the second bit line BL2 are connected to the storage cell 10. When a read voltage is applied to the first bit line BL1, the storage cell 10 outputs a read current Icell through the second bit line BL2.

[0063] The sensing amplifier 20 has a first input terminal connected to the second bit line BL2 and receives the read current Icell on the second bit line BL2. The second input terminal of the sensing amplifier 20 receives the reference current Iref. The sensing amplifier 20 outputs a comparison result based on the read current Icell and the reference current Iref.

[0064] The input terminal of the reading circuit 30 is connected to the output terminal of the inductive amplifier 20, and the first output terminal of the reading circuit 30 is connected to the first bit line BL1. The reading circuit 30 adjusts the reading voltage of the first bit line BL1 according to the comparison result, so as to adjust the comparison result output by the inductive amplifier 20, until the storage data of the storage unit 10 is determined according to the comparison result.

[0065] In this embodiment, the sensing amplifier 20 outputs a comparison result based on the read current Icell and the reference current Iref. The read circuit 30 adjusts the read voltage of the first bit line BL1 based on the comparison result, thereby adjusting the read current Icell of the storage cell 10. This allows the sensing amplifier 20 to adjust the comparison result. In this way, the read voltage and read current can be continuously adjusted, and thus the comparison result can be continuously adjusted until the stored data of the storage cell can be determined based on the comparison result. It can be understood that since the reference current Iref is fixed, by continuously adjusting the read voltage to continuously adjust the read current Icell, the stored data of the storage cell 10 can be ultimately determined. This allows control of the input common-mode current of the sensing amplifier 20, improving the sensing accuracy of the sensing amplifier 20.

[0066] The reading circuit 30 may include a second output terminal, which is used to output the stored data of the storage unit 10.

[0067] For example, when the storage bits for storing data are multiple, the storage unit can store any one of various types of data. Each voltage adjustment can filter out half of the possible stored data based on the corresponding comparison result. This process of adjustment and filtering is repeated to determine the stored data in storage unit 10. In some embodiments, when the Nth read voltage is applied to the first bit line BL1, storage unit 10 outputs the Nth read current Icell through the second bit line BL2. n N is an integer greater than 0; the inductive amplifier 20 can read the current Icell from the Nth current. nThe reference current Iref outputs the Nth comparison result; the read circuit 30 can adjust the read voltage of the first bit line BL1 to the (N+1)th voltage according to the Nth comparison result. When the (N+1)th voltage is applied to the first bit line BL1, the memory cell 10 outputs the (N+1)th read current Icell through the second bit line BL2. n+1 The Nth comparison result indicates the Nth read current Icell. n When the current is greater than the reference current Iref, the (N+1)th read current Icell n+1 Less than the Nth read current Icell n The Nth comparison result indicates the Nth read current Icell. n When the current is less than the reference current Iref, the (N+1)th read current Icell n+1 Greater than the Nth read current Icell n .

[0068] It is understandable that when the Nth comparison result indicates the Nth read current Icell n When the current exceeds the reference current Iref, decrease the next read current, i.e., the (N+1)th read current Icell. n+1 Less than the Nth read current Icell n When the Nth comparison result indicates the Nth read current Icell n When the current is less than the reference current Iref, increase the next read current, i.e., the (N+1)th read current Icell. n+1 Greater than the Nth read current Icell n .

[0069] One implementation approach is to determine the stored data of a storage unit based on the Sth comparison result, where S is the number of bits used to store the stored data in the storage unit, so that the stored data of the storage unit can be finally determined.

[0070] In some examples, when a first read voltage VBL1 is applied to the first bit line BL1, the memory cell 10 outputs a first read current Icell1 through the second bit line BL2; the sensing amplifier 20 outputs a first comparison result based on the first read current Icell1 and the reference current Iref.

[0071] When the first comparison result indicates that the first read current Icell1 is greater than the reference current Iref, the read circuit 30 outputs the second read voltage VBL2; when the second read voltage VBL2 is applied to the first bit line BL1, the memory cell 10 outputs the second read current Icell2 through the second bit line BL2, and the second read current Icell2 is less than the first read current Icell1; the sensing amplifier 20 outputs the second comparison result according to the second read current Icell2 and the reference current Iref.

[0072] When the second comparison result indicates that the second read current Icell2 is greater than the reference current Iref, the read circuit 30 outputs the third read voltage VBL3. When the third read voltage VBL3 is applied to the first bit line BL1, the storage cell 10 outputs the third read current Icell3 through the second bit line BL2. The sensing amplifier 20 outputs the third comparison result based on the third read current Icell3 and the reference current Iref. When the third comparison result indicates that the third read current Icell3 is greater than the reference current Iref, the stored data in the storage cell 10 is the first data. When the third comparison result indicates that the third read current Icell3 is less than the reference current Iref, the stored data in the storage cell 10 is the second data.

[0073] When the second comparison result indicates that the second read current Icell2 is less than the reference current Iref, the read circuit 30 outputs the fourth read voltage VBL4. When the fourth read voltage VBL4 is applied to the first bit line BL1, the storage cell 10 outputs the fourth read current Icell4 through the second bit line BL2. The fourth read current Icell4 is greater than the second read current Icell2. The sensing amplifier 20 outputs the fourth comparison result based on the fourth read current Icell4 and the reference current Iref. When the fourth comparison result indicates that the fourth read current Icell is greater than the reference current Iref, the stored data in the storage cell 10 is the third data. When the fourth comparison result indicates that the fourth read current Icell4 is less than the reference current Iref, the stored data in the storage cell 10 is the fourth data.

[0074] When the first comparison result indicates that the first read current Icell1 is less than the reference current Iref, the read circuit 30 outputs the fifth read voltage VBL1; when the fifth read voltage VBL5 is applied to the first bit line BL1, the memory cell 10 outputs the fifth read current Icell5 through the second bit line BL2, and the fifth read current Icell5 is greater than the first read current Icell1; the sensing amplifier 20 outputs the fifth comparison result based on the fifth read current Icell5 and the reference current Iref.

[0075] When the fifth comparison result indicates that the fifth read current Icell5 is greater than the reference current Iref, the read circuit 30 outputs the sixth read voltage VBL6; when the sixth read voltage VBL6 is applied to the first bit line BL1, the storage cell 10 outputs the sixth read current Icell6 through the second bit line BL2, and the sixth read current Icell6 is less than the fifth read current Icell5; the sensing amplifier 20 outputs the sixth comparison result based on the sixth read current Icell6 and the reference current Iref; when the sixth comparison result indicates that the sixth read current Icell6 is greater than the reference current Iref, the stored data in the storage cell 10 is the fifth data, and when the sixth comparison result indicates that the sixth read current Icell6 is less than the reference current Iref, the stored data in the storage cell 10 is the sixth data;

[0076] When the fifth comparison result indicates that the fifth read current Icell5 is less than the reference current Iref, the read circuit 30 outputs the seventh read voltage VBL7. When the seventh read voltage VBL7 is applied to the first bit line BL1, the storage cell 10 outputs the seventh read current Icell7 through the second bit line BL2. The seventh read current Icell7 is greater than the fifth read current Icell5. The sensing amplifier 20 outputs the seventh comparison result based on the seventh read current Icell7 and the reference current Iref. When the seventh comparison result indicates that the seventh read current Icell7 is greater than the reference current Iref, the stored data in the storage cell 10 is the seventh data. When the seventh comparison result indicates that the seventh read current Icell7 is less than the reference current Iref, the stored data in the storage cell 10 is the eighth data.

[0077] For example, if a storage unit has 3 storage bits, it can store any one of eight types of data: 111, 110, 101, 100, 011, 010, 001, and 000. Accordingly, the first data is 111, the second is 110, the third is 101, the fourth is 100, the fifth is 011, the sixth is 010, the seventh is 001, and the eighth is 000.

[0078] Specifically, such as Figure 8As shown, when a first read voltage VBL1 is applied to the first bit line BL1, the storage cell 10 outputs a first read current Icell1 through the second bit line BL2. The sensing amplifier 20 outputs a first comparison result based on the first read current Icell1 and the reference current Iref. Based on the first comparison result, the stored data can be determined to be one of 111-100 (inclusive of 111, 110, 101, 100) or one of 011-000 (inclusive of 011, 010, 001, 000). That is, half of the stored data that the storage cell 10 can store can be filtered out based on the first comparison result. When the first comparison result indicates that the first read current Icell1 is greater than the reference current Iref, the stored data is determined to be one of 111-100. When the first comparison result indicates that the first read current Icell1 is less than the reference current Iref, the stored data is determined to be one of 011-000.

[0079] When the stored data is one of 111-100, the read circuit 30 outputs a second read voltage VBL2, and the second read voltage VBL2 is applied to the first bit line BL1. When the second read voltage VBL2 is applied to the first bit line BL1, the storage cell 10 outputs a second read current Icell2 through the second bit line BL2. The second read current Icell2 is less than the first read current Icell1. The sensing amplifier 20 outputs a second comparison result based on the second read current Icell2 and the reference current Iref. Based on the second comparison result, it can be determined that the stored data is one of 111-110 (inclusive of 111 and 110) or one of 101-100 (inclusive of 101 and 100). That is, based on the second comparison result, half of the stored data selected by the first comparison result can be further filtered out. When the second comparison result indicates that the second read current Icell2 is greater than the reference current Iref, the stored data is determined to be one of 111-110. When the second comparison result indicates that Icell2 is less than the reference current Iref, the stored data is determined to be one of 101-100.

[0080] When the stored data is determined to be one of 111-110 according to the second comparison result, the read circuit 30 outputs a third read voltage VBL3. When the third read voltage VBL3 is applied to the first bit line BL1, the storage cell 10 outputs a third read current Icell3 through the second bit line BL2. The sensing amplifier 20 outputs a third comparison result according to the third read current Icell3 and the reference current Iref. The stored data can be determined to be 111 or 110 according to the third comparison result. That is, half of the stored data can be further filtered out from the half of the stored data filtered by the second comparison result according to the third comparison result. When the third comparison result indicates that the third read current Icell3 is greater than the reference current Iref, the stored data of the storage cell 10 is 111. When the third comparison result indicates that the third read current Icell3 is less than the reference current Iref, the stored data of the storage cell 10 is 110.

[0081] When the stored data is determined to be one of 101-100 based on the second comparison result, the read circuit 30 outputs a fourth read voltage VBL4. When the fourth read voltage VBL4 is applied to the first bit line BL1, the storage cell 10 outputs a fourth read current Icell4 through the second bit line BL2. The sensing amplifier 20 outputs a fourth comparison result based on the fourth read current Icell4 and the reference current Iref. The stored data can be determined to be 101 or 100 based on the fourth comparison result. When the fourth comparison result indicates that the fourth read current Icell is greater than the reference current Iref, the stored data of the storage cell 10 is 101. When the fourth comparison result indicates that the fourth read current Icell4 is less than the reference current Iref, the stored data of the storage cell 10 is 100.

[0082] When the stored data is one of 011-000, the read circuit 30 outputs the fifth read voltage VBL1; when the fifth read voltage VBL5 is applied to the first bit line BL1, the storage cell 10 outputs the fifth read current Icell5 through the second bit line BL2; the sensing amplifier 20 outputs the fifth comparison result according to the fifth read current Icell5 and the reference current Iref; the stored data can be determined to be one of 011-010 (inclusive of 011 and 010) or one of 001-000 (inclusive of 001 and 000) according to the fifth comparison result;

[0083] When the stored data is determined to be one of 011-010 based on the fifth comparison result, the read circuit 30 outputs a sixth read voltage VBL6; when the sixth read voltage VBL6 is applied to the first bit line BL1, the storage cell 10 outputs a sixth read current Icell6 through the second bit line BL2; the sensing amplifier 20 outputs a sixth comparison result based on the sixth read current Icell6 and the reference current Iref; the stored data can be determined to be one of 011 or 010 based on the sixth comparison result; when the sixth comparison result indicates that the sixth read current Icell6 is greater than the reference current Iref, the stored data of the storage cell 10 is 011; when the sixth comparison result indicates that the sixth read current Icell6 is less than the reference current Iref, the stored data of the storage cell 10 is 010.

[0084] When the stored data is determined to be one of 001-000 based on the fifth comparison result, the read circuit 30 outputs the seventh read voltage VBL7; when the seventh read voltage VBL7 is applied to the first bit line BL1, the storage cell 10 outputs the seventh read current Icell7 through the second bit line BL2; the sensing amplifier 20 outputs the seventh comparison result based on the seventh read current Icell7 and the reference current Iref; the stored data can be determined to be one of 001 or 000 based on the seventh comparison result; when the seventh comparison result indicates that the seventh read current Icell7 is greater than the reference current Iref, the stored data of the storage cell 10 is 001; when the seventh comparison result indicates that the seventh read current Icell7 is less than the reference current Iref, the stored data of the storage cell 10 is 000.

[0085] In practical applications, while a read voltage is applied to the first bit line BL1, a reference voltage is applied to the second bit line BL2 to ensure that the memory cell 10 can output the read current Icell. Each time a read voltage is applied to the first bit line BL1, a corresponding reference voltage is applied to the second bit line BL2. The reference voltage applied each time can be the same or approximately the same. For example, the difference between any two applied reference voltages is within a preset difference range, which can be determined according to the actual situation.

[0086] As one implementation method, the correspondence between stored data and stored current, as well as the correspondence between stored current and read voltage, can be preset. Thus, the first read voltage, the second read voltage, etc., can be determined based on the correspondence between stored data, stored current, and read voltage. This ensures that each adjustment of the read voltage makes the current corresponding to each stored data close to the reference current, thereby ensuring that each adjustment of the read voltage can filter out half of the stored data, and thus determine the stored data of the storage unit.

[0087] In some other examples, the storage unit has 4 storage bits, so the storage unit can store any one of sixteen types of data, namely 1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, and 0000.

[0088] Specifically, when a first read voltage VBL1 is applied to the first bit line BL1, the memory cell 10 outputs a first read current Icell1 through the second bit line BL2. The sensing amplifier 20 outputs a first comparison result based on the first read current Icell1 and the reference current Iref. Based on the first comparison result, the stored data can be determined to be one of 1111-1000 (inclusive of 1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000), or 0110-0000 (inclusive of 0). The data to be stored can be one of 1111-1000, i.e., half of the data that can be stored in storage unit 10 can be filtered out based on the first comparison result; when the first comparison result indicates that the first read current Icell1 is greater than the reference current Iref, the data to be stored is determined to be one of 1111-1000; when the first comparison result indicates that the first read current Icell1 is less than the reference current Iref, the data to be stored is determined to be one of 0111-0000.

[0089] When the stored data is one of 1111-1000, the read circuit 30 outputs a second read voltage VBL2, and the second read voltage VBL2 is applied to the first bit line BL1. When the second read voltage VBL2 is applied to the first bit line BL1, the storage cell 10 outputs a second read current Icell2 through the second bit line BL2, and the second read current Icell2 is less than the first read current Icell1. The sensing amplifier 20 outputs a second comparison result based on the second read current Icell2 and the reference current Iref. The stored data can be determined to be 1111-1100 based on the second comparison result. The data can be one of 1111, 1110, 1101, and 1100, or one of 1011-1000 (including 1011, 1010, 1001, and 1000). That is, based on the second comparison result, half of the stored data filtered by the first comparison result can be further filtered out. When the second comparison result indicates that the second reading current Icell2 is greater than the reference current Iref, the stored data is determined to be one of 1111-1100. When the second comparison result indicates that Icell2 is less than the reference current Iref, the stored data is determined to be one of 1011-1000.

[0090] When the stored data is determined to be one of 1111-1100 based on the second comparison result, the read circuit 30 outputs a third read voltage VBL3. When the third read voltage VBL3 is applied to the first bit line BL1, the storage cell 10 outputs a third read current Icell3 through the second bit line BL2. The third read current Icell3 is less than the second read current Icell2. The sensing amplifier 20 outputs a third comparison result based on the third read current Icell3 and the reference current Iref. The stored data can be determined to be 1111-1110 based on the third comparison result. The data stored in storage unit 10 can be one of 1111 and 1110, or one of 1101-1100 (including 1101 and 1100). That is, based on the third comparison result, half of the stored data can be further filtered out from the half of the stored data filtered by the second comparison result. When the third comparison result indicates that the third read current Icell3 is greater than the reference current Iref, the stored data in storage unit 10 is one of 1111-1110. When the third comparison result indicates that the third read current Icell3 is less than the reference current Iref, the stored data in storage unit 10 is 1101-1100.

[0091] When the stored data is determined to be one of 1111-1110 based on the third comparison result, the read circuit 30 outputs a fourth read voltage VBL4. When the fourth read voltage VBL4 is applied to the first bit line BL1, the storage cell 10 outputs a fourth read current Icell4 through the second bit line BL2. The fourth read current Icell4 is less than the third read current Icell3. The sensing amplifier 20 outputs a fourth comparison result based on the fourth read current Icell4 and the reference current Iref. The stored data can be determined to be 1111 or 1110 based on the fourth comparison result. That is, half of the stored data can be further filtered out from the half of the stored data filtered by the third comparison result based on the fourth comparison result. When the fourth comparison result indicates that the fourth read current Icell4 is greater than the reference current Iref, the stored data of the storage cell 10 is 1111. When the fourth comparison result indicates that the fourth read current Icell4 is less than the reference current Iref, the stored data of the storage cell 10 is 1110.

[0092] When the stored data is determined to be one of 1101-1100 based on the third comparison result, the read circuit 30 outputs a fifth read voltage VBL5. When the fifth read voltage VBL5 is applied to the first bit line BL1, the storage cell 10 outputs a fifth read current Icell5 through the second bit line BL2. The fifth read current Icell5 is greater than the third read current Icell3. The sensing amplifier 20 outputs a fifth comparison result based on the fifth read current Icell5 and the reference current Iref. When the fifth comparison result indicates that the fifth read current Icell5 is greater than the reference current Iref, the stored data of the storage cell 10 is 1101. When the fifth comparison result indicates that the fifth read current Icell5 is less than the reference current Iref, the stored data of the storage cell 10 is 1100.

[0093] When the stored data is determined to be one of 1011-1000 according to the second comparison result, the read circuit 30 outputs the sixth read voltage VBL6. When the sixth read voltage VBL6 is applied to the first bit line BL1, the storage cell 10 outputs the sixth read current Icell6 through the second bit line BL2. The sixth read current Icell6 is greater than the second read current Icell2. The sensing amplifier 20 outputs the sixth comparison result according to the sixth read current Icell6 and the reference current Iref. The stored data can be determined to be one of 1011-1010 (inclusive) or one of 1001-1000 (inclusive) according to the sixth comparison result. When the sixth comparison result indicates that the sixth read current Icell6 is greater than the reference current Iref, the stored data of the storage cell 10 is one of 1011-1010. When the sixth comparison result indicates that the sixth read current Icell6 is less than the reference current Iref, the stored data of the storage cell 10 is one of 1001-1000.

[0094] When the stored data is determined to be one of 1011-1010 based on the sixth comparison result, the read circuit 30 outputs a seventh read voltage VBL7. When the seventh read voltage VBL1 is applied to the first bit line BL1, the storage cell 10 outputs a seventh read current Icell7 through the second bit line BL2. The seventh read current Icell7 is less than the sixth read current Icell6. The sensing amplifier 20 outputs a seventh comparison result based on the sixth read current Icell6 and the reference current Iref. The stored data can be determined to be 1011 or 1010 based on the seventh comparison result. When the seventh comparison result indicates that the seventh read current Icell7 is greater than the reference current, the stored data of the storage cell 10 is 1011. When the seventh comparison result indicates that the seventh read current Icell7 is less than the reference current Iref, the stored data of the storage cell 10 is 1010.

[0095] When the stored data is determined to be one of 1001-1000 based on the sixth comparison result, the read circuit 30 outputs the eighth read voltage VBL8. When the eighth read voltage VBL8 is applied to the first bit line BL1, the storage cell 10 outputs the eighth read current Icell8 through the second bit line BL2. The eighth read current Icell8 is greater than the sixth read current Icell6. The sensing amplifier 20 outputs the eighth comparison result based on the eighth read current Icell8 and the reference current Iref. The stored data can be determined to be 1001 or 1000 based on the eighth comparison result. When the eighth comparison result indicates that the eighth read current Icell8 is greater than the reference current Iref, the stored data of the storage cell 10 is 1001. When the eighth comparison result indicates that the eighth read current Icell8 is less than the reference current Iref, the stored data of the storage cell 10 is 1000.

[0096] When the stored data is one of 0111-0000, the read circuit 30 outputs a ninth read voltage VBL9, and the ninth read voltage VBL9 is applied to the first bit line BL1; when the second read voltage VBL9 is applied to the first bit line BL1, the storage cell 10 outputs a ninth read current Icell9 through the second bit line BL2, and the ninth read current Icell9 is greater than the first read current Icell1; the sensing amplifier 20 outputs a ninth comparison result based on the ninth read current Icell9 and the reference current Iref; the result can be calculated based on the ninth comparison result. The comparison result determines that the stored data is one of 0111-0100 (inclusive of 0111, 0110, 0101, 0100) or one of 0011-0000 (inclusive of 0011, 0010, 0001, 0000); when the ninth comparison result indicates that the ninth read current Icell9 is greater than the reference current Iref, the stored data is determined to be one of 0111-0100; when the ninth comparison result indicates that Icell9 is less than the reference current Iref, the stored data is determined to be one of 0011-0000.

[0097] When the stored data is determined to be one of 0111-0100 based on the ninth comparison result, the read circuit 30 outputs the tenth read voltage VBL10. When the tenth read voltage VBL10 is applied to the first bit line BL1, the storage cell 10 outputs the tenth read current Icell through the second bit line BL2. 10 The tenth reading of the current Icell 10 Less than the ninth read current Icell9; the sensing amplifier 20 is based on the tenth read current Icell. 10The tenth comparison result is output with the reference current Iref; the stored data can be determined to be one of 0111-0110 (inclusive) or one of 0101-0100 (inclusive); the tenth comparison result indicates the tenth read current Icell. 10 When the current is greater than the reference current Iref, the stored data in storage cell 10 is one of 0111-0110, and the tenth comparison result indicates the tenth read current Icell. 10 When the current is less than the reference current Iref, the data stored in storage cell 10 is one of 0101-0100;

[0098] When the stored data is determined to be one of 0111-0110 based on the tenth comparison result, the read circuit 30 outputs the eleventh read voltage VBL11. When the eleventh read voltage VBL11 is applied to the first bit line BL1, the storage cell 10 outputs the eleventh read current Icell through the second bit line BL2. 11 Eleventh current reading Icell 11 Less than the ninth read current Icell9; the sensing amplifier 20 is based on the eleventh read current Icell. 11 The eleventh comparison result is output with the reference current Iref; the stored data (0111 or 0110) can be determined based on the eleventh comparison result; the eleventh comparison result indicates the eleventh read current Icell. 11 When the current is greater than the reference current Iref, the stored data in storage cell 10 is 0111, and the eleventh comparison result indicates the eleventh read current Icell. 11 When the current is less than the reference current Iref, the stored data in storage cell 10 is 0110;

[0099] When the stored data is determined to be one of 0101-0100 based on the tenth comparison result, the read circuit 30 outputs the twelfth read voltage VBL12. When the twelfth read voltage VBL12 is applied to the first bit line BL1, the storage cell 10 outputs the twelfth read current Icell through the second bit line BL2. 12 The twelfth read current Icell5 is greater than the tenth read current Icell. 10 The inductive amplifier 20 reads the twelfth current Icell. 12 The twelfth comparison result is output with the reference current Iref; the twelfth comparison result indicates the twelfth read current Icell. 12 When the current is greater than the reference current Iref, the stored data in storage cell 10 is 0101, and the twelfth comparison result indicates the twelfth read current Icell. 12 When the current is less than the reference current Iref, the stored data in storage cell 10 is 0100;

[0100] When the stored data is determined to be one of 0011-0000 based on the ninth comparison result, the read circuit 30 outputs the thirteenth read voltage VBL13. When the thirteenth read voltage VBL13 is applied to the first bit line BL1, the storage cell 10 outputs the thirteenth read current Icell through the second bit line BL2. 13 Thirteenth reading of current Icell 13 The reading current Icell9 is greater than the ninth read current; the sensing amplifier 20 is based on the thirteenth read current Icell. 13 The thirteenth comparison result is output along with the reference current Iref. Based on the thirteenth comparison result, the stored data can be determined to be one of 0011-0010 (inclusive) or one of 0001-0000 (inclusive). The thirteenth comparison result indicates the thirteenth read current Icell. 13 When the current is greater than the reference current Iref, the stored data in storage cell 10 is one of 0011-0010, and the thirteenth comparison result indicates the thirteenth read current Icell. 13 When the current is less than the reference current Iref, the data stored in the storage cell 10 is one of 0001-0000;

[0101] When the stored data is determined to be one of 0011-0010 based on the thirteenth comparison result, the read circuit 30 outputs the fourteenth read voltage VBL14. When the fourteenth read voltage VBL14 is applied to the first bit line BL1, the storage cell 10 outputs the fourteenth read current Icell through the second bit line BL2. 14 The fourteenth reading of the current Icell 14 Less than the thirteenth read current Icell 13 The inductive amplifier 20 reads the current Icell according to the fourteenth reading. 14 The fourteenth comparison result is output with the reference current Iref; the stored data (0011 or 0010) can be determined based on the fourteenth comparison result; the fourteenth comparison result indicates the fourteenth read current Icell. 14 When the current is greater than the reference current, the stored data in storage cell 10 is 0011, and the fourteenth comparison result indicates the fourteenth read current Icell. 14 When the current is less than the reference current Iref, the stored data of stored data 10 is 0010;

[0102] When the stored data is determined to be one of 0001-0000 based on the thirteenth comparison result, the read circuit 30 outputs the fifteenth read voltage VBL15. When the fifteenth read voltage VBL15 is applied to the first bit line BL1, the storage cell 10 outputs the fifteenth read current Icell through the second bit line BL2. 15 The fifteenth reading of the current Icell15 Greater than the thirteenth read current Icell 13 The inductive amplifier 20 reads the current Icell according to the fifteenth reading. 15 The fifteenth comparison result is output with the reference current Iref; the stored data can be determined to be 0001 or 0000 based on the fifteenth comparison result; the fifteenth comparison result indicates the fifteenth read current Icell. 15 When the current is greater than the reference current Iref, the stored data in storage cell 10 is 0001, and the fifteenth comparison result indicates the fifteenth read current Icell. 15 When the current is less than the reference current Iref, the stored data in storage cell 10 is 0000.

[0103] When the storage location for storing data is different, the above two cases can be used as a reference, which will not be elaborated here.

[0104] In some embodiments, such as Figure 7 As shown, the memory includes a read word line RWL, and the memory cell includes a read transistor M'. The read transistor M' is a dual-gate transistor, comprising a first gate, a second gate, a first electrode, and a second electrode. The first gate of the read transistor M' is connected to the read word line RWL, the second gate stores the write voltage, the first electrode of the read transistor M' is connected to the first bit line BL1, and the second electrode of the read transistor M' is connected to the second bit line BL2. Accordingly, when the read transistor M' is turned on, the current of the read transistor M', i.e., the read current Icell of the memory cell, can be controlled by the read voltage applied to the first bit line BL1.

[0105] In one implementation, if the read transistor is an NMOS transistor, the read current of the memory cell can be reduced by increasing the read voltage applied to the first bit line, and the read current of the memory cell can be increased by decreasing the read voltage applied to the first bit line.

[0106] Furthermore, the memory includes a write word line WWL, and the memory cell includes a write transistor M, which includes a gate, a first electrode, and a second electrode. The gate of the write transistor M is connected to the write word line WWL, the first electrode of the write transistor M is connected to either the first bit line BL1 or the second bit line BL2, and the second electrode of the write transistor M is connected to the second gate of the read transistor M'. Accordingly, when the write transistor M is turned on, the write voltage can be transmitted and stored in the second gate of the read transistor M', thereby realizing the writing of data.

[0107] In some examples, when the first terminal of the write transistor M is connected to the first bit line BL1, the first bit line BL1 is also used to receive the write voltage during the write operation. Specifically, when the write transistor M is turned on, the first bit line BL1 receives the write voltage and transmits and stores the write voltage at the second gate of the read transistor M'.

[0108] In other examples, when the first terminal of the write transistor M is connected to the second bit line BL2, the second bit line BL2 is also used to receive the write voltage. Specifically, when the write transistor M is turned on, the second bit line BL2 receives the write voltage and transmits and stores the write voltage at the second gate of the read transistor M'.

[0109] For example, the write transistor M can be either an N-type or a P-type transistor, and the read transistor M' can also be either an N-type or a P-type transistor. The first terminal of the write transistor M can be either the source or the drain. When the first terminal of the write transistor M is the source, the second terminal of the write transistor M is the drain; conversely, when the first terminal of the write transistor M is the drain, the second terminal of the write transistor M is the source. Similarly, the first terminal of the read transistor M' can be either the source or the drain. When the first terminal of the read transistor M' is the source, the second terminal of the read transistor M' is the drain; conversely, when the first terminal of the read transistor M' is the drain, the second terminal of the read transistor M' is the source.

[0110] In some embodiments, such as Figure 9 As shown, there are multiple memory cells 10 and multiple first bit lines BL1. At least two memory cells 10 are connected to the same first bit line BL1, so that a read voltage can be applied to multiple memory cells 10 through one first bit line BL1, which improves efficiency and reduces wiring.

[0111] Correspondingly, there can be multiple second bit lines BL2, with at least two memory cells 10 connected to the same second bit line BL2, so that the read current of multiple memory cells 10 can be output through one second bit line BL2.

[0112] In some examples, the number of inductive amplifiers 20 can be multiple or one. When there are multiple inductive amplifiers 20, the first input terminal of each inductive amplifier 20 is connected to at least one second bit line BL2, so that the read current of different memory cells can be compared with the reference current through different inductive amplifiers 20, thereby improving accuracy.

[0113] In some embodiments, such as Figure 9 As shown, there are multiple storage cells 10 and multiple read word lines (RWL). At least two storage cells 10 are connected to the same read word line (RWL), so that multiple storage cells 10 can be read through a single read word line (RWL), improving efficiency and reducing wiring.

[0114] Accordingly, there can be multiple write lines WWL, with at least two memory cells 10 connected to the same write line WWL, so that write voltage can be applied to multiple memory cells 10 through one write line WWL, thereby improving efficiency.

[0115] As one implementation method, such as Figure 10 As shown, the control circuit 30 includes a successive approximation register 301 and a digital-to-analog converter 302. The input terminal of the successive approximation register 301 serves as the input terminal of the read circuit 30, and the first output terminal of the successive approximation register 301 is connected to the input terminal of the digital-to-analog converter 302. The output terminal of the digital-to-analog converter 302 serves as the output terminal of the read circuit 302. The successive approximation register 301 outputs a digital signal corresponding to the adjusted read voltage based on the comparison result, and the digital-to-analog converter 302 outputs the adjusted read voltage based on the digital signal.

[0116] In some embodiments, the sensing amplifier 20 includes a sensing module and an amplification module. The sensing module includes a first terminal, a second terminal, a third terminal, and a fourth terminal, and the amplification module includes a first output line and a second output line. The first terminal of the sensing module is connected to either the first bit line BL1 or the second bit line BL2. The second terminal of the sensing module receives a reference current Iref. The first terminal of the first output line in the amplification module is connected to the third terminal of the sensing module, and the first terminal of the second output line of the amplification module is connected to the fourth terminal of the sensing module. The sensing module senses the current difference between the read current Icell of the memory cell and the reference current Iref. The amplification module acquires the current difference, generates a voltage signal based on the current difference, amplifies the voltage signal, and outputs the amplified result.

[0117] In some examples, such as Figure 11 As shown, the sensing module includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The gate of the first transistor M1 and the gate of the second transistor M2 are interconnected and receive the power supply voltage VDD. The first terminal of the first transistor M1 and the first terminal of the second transistor M2 are interconnected and receive the ground voltage VSS. The second terminal of the first transistor M1 is connected to the first terminal of the third transistor M3 and receives the read current Icell. The second terminal of the second transistor M2 is connected to the first terminal of the fourth transistor M4 and receives the reference current Iref. The gate of the third transistor M3, the first terminal of the sixth transistor M6, and the second terminal of the fourth transistor M4 are interconnected, serving as the fourth terminal of the sensing module. The second terminal of the third transistor M3, the gate of the fourth transistor M4, and the second terminal of the fifth transistor M5 are interconnected, serving as the third terminal of the sensing module. The gate of the fifth transistor M5 and the gate of the sixth transistor M6 are interconnected and receive the first enable signal V. SAEN The second terminals of the fifth transistor M5 and the sixth transistor M6 are connected to each other and receive the power supply voltage VDD.

[0118] The amplification module includes a first equalizer transistor M11, a second equalizer transistor M10, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The gate of the first equalizer transistor M11 receives a first control signal PEQ; its first terminal is connected to the first output line b, and its second terminal is connected to the second output line a. The gate of the second equalizer transistor M10 receives a second control signal PEQB; its first terminal is connected to the first output line b, and its second terminal is connected to the second output line a. The gate of the seventh transistor M7 is connected to the second output line a; its first terminal is connected to the first output line b; its second terminal is connected to the first terminals of both the eighth transistor M8 and the ninth transistor M9; the gate of the eighth transistor M8 is connected to the first output line b, and its second terminal is connected to the second output line a. The gate of the ninth transistor M9 receives a second enable signal V. SAENB The second terminal of the ninth transistor M9 receives the power supply voltage VDD.

[0119] Accordingly, the operation of the sensing amplifier 20 may include three stages: a voltage balancing stage, a current sensing stage, and a voltage sensing stage;

[0120] During the voltage balancing phase: the first equalizing transistor M11 and the second equalizing transistor 10 are turned on by the first control signal PEQ and the second control signal PEQB to balance the voltage V of the first output line b. SA Voltage V of the second output line a SAB .

[0121] During the current sensing phase: via the first enable signal V SAEN Second enable signal V SAENB The fifth transistor M5, the sixth transistor M6, and the ninth transistor M9 are turned on. During this period, the memory cell outputs a read current Icell via the first bit line BL1 or the second bit line BL2. The difference between the read current Icell and the reference current Iref is converted into a first induced current I. SA Second induced current I SB First induced current I SA It is the current in the branch containing the fifth transistor M5, the third transistor M3, and the first transistor M1, and the second induced current I. SAB This is the current in the branch containing the sixth transistor M6, the fourth transistor M4, and the second transistor M2. Furthermore, since the first output line b is connected to the third terminal of the sensing module, and the second output line a is connected to the fourth terminal of the sensing module, the first induced current I... SA Second induced current I SB That is, the voltage V of the first output line b SAVoltage V of the second output line a SAB The voltage difference between them.

[0122] During the voltage sensing phase: via the first enable signal V SAEN Second enable signal V SAENB The fifth transistor M5, the sixth transistor M6, and the ninth transistor M9 are turned on, and the cross-coupled inverter composed of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 amplifies the voltage difference between the first output line b and the second output line a. During this period, a high-level power supply can be provided through the ninth transistor M9, and a low-level power supply can be provided through the first transistor M1 and the second transistor M2.

[0123] Optionally, it may also include a tenth transistor M0, the gate of which receives a third enable signal C. SAENB The first terminal of the tenth transistor M0 is connected to the second terminals of the fifth transistor M5 and the sixth transistor M6. The second terminal of the tenth transistor M0 receives the power supply voltage VDD, thus allowing the tenth transistor M0 to control whether the induction amplifier operates. For example, the tenth transistor M0 is activated by the third enable signal C. SAENB When the transistor is turned on under the control of the signal, the inductive amplifier is in operation, and the tenth transistor M0 is activated by the third enable signal C. SAENB When the circuit is turned off under control, the inductive amplifier stops working.

[0124] For example, the first equalizing transistor, the second equalizing transistor, and the first transistor M1 to the tenth transistor M0 can be N-type transistors or P-type transistors.

[0125] The memory provided in this application has been described above. The memory provided in the embodiments of this application uses a fixed reference current and continuously adjusts the read voltage to continuously adjust the read current of the memory cell, thereby continuously adjusting the comparison result of the sensing amplifier until the stored data of the memory cell can be determined based on the comparison result. This controls the input common-mode current of the sensing amplifier, improves the sensing accuracy of the sensing amplifier, and reduces power consumption.

[0126] An embodiment of this application also provides a method for reading a memory. The memory reading method provided in this application embodiment can be used in the aforementioned memory, and the control method includes the following steps:

[0127] S10. When a read voltage is applied to the first bit line, the control memory cell outputs a read current through the second bit line.

[0128] S20, control the inductive amplifier to output the comparison result based on the read current and the reference current.

[0129] S30. The control reading circuit adjusts the reading voltage according to the comparison result, so as to adjust the comparison result until the storage data of the storage cell is determined according to the comparison result.

[0130] In some embodiments, when the Nth read voltage is applied to the first bit line, the control memory cell outputs the Nth read current through the second bit line, where N is an integer greater than 0;

[0131] The control inductive amplifier outputs the Nth comparison result based on the Nth read current and the reference current;

[0132] The control read circuit adjusts the read voltage of the first bit line to the (N+1)th voltage according to the Nth comparison result. When the (N+1)th voltage is applied to the first bit line, the control memory cell outputs the (N+1)th read current through the second bit line.

[0133] Among them, when the Nth comparison result indicates that the Nth read current is greater than the reference current, the (N+1)th read current is less than the Nth read current; when the Nth comparison result indicates that the Nth read current is less than the reference current, the (N+1)th read current is greater than the Nth read current.

[0134] Accordingly, the stored data of the storage cell can be determined based on the Sth comparison result, where S is the number of bits of the stored data in the storage cell.

[0135] In some examples, when a first read voltage is applied to the first bit line, the control memory cell outputs a first read current through the second bit line;

[0136] The control inductive amplifier outputs a first comparison result based on the first read current and the reference current;

[0137] When the first comparison result indicates that the first read current is greater than the reference current, the control circuit outputs the second read voltage.

[0138] When a second read voltage is applied to the first bit line, the control memory cell outputs a second read current through the second bit line. The second read current is less than the first read current.

[0139] The control induction amplifier outputs a second comparison result based on the second read current and the reference current;

[0140] When the second comparison result indicates that the second read current is greater than the reference current, the control read circuit outputs the third read voltage;

[0141] When the third read voltage is applied to the first bit line, the control memory cell outputs a third read current through the second bit line. The third read current is less than the second read current.

[0142] The control induction amplifier outputs a third comparison result based on the third read current and the reference current. When the third comparison result indicates that the third read current is greater than the reference current, the stored data in the storage unit is the first data. When the third comparison result indicates that the third read current is less than the reference current, the stored data in the storage unit is the second data.

[0143] When the second comparison result indicates that the second read current is less than the reference current, the control read circuit outputs the fourth read voltage.

[0144] When the fourth read voltage is applied to the first bit line, the control memory cell outputs the fourth read current through the second bit line. The fourth read current is greater than the second read current.

[0145] The control induction amplifier outputs a fourth comparison result based on the fourth read current and the reference current. When the fourth comparison result indicates that the fourth read current is greater than the reference current, the stored data in the storage unit is the third data. When the fourth comparison result indicates that the fourth read current is less than the reference current, the stored data in the storage unit is the fourth data.

[0146] In some examples, when the first comparison result indicates that the first read current is less than the reference current, the control circuit outputs a fifth read voltage;

[0147] When the fifth read voltage is applied to the first bit line, the control memory cell outputs the fifth read current through the second bit line. The fifth read current is greater than the first read current.

[0148] The control amplifier outputs the fifth comparison result based on the fifth read current and the reference current;

[0149] When the fifth comparison result indicates that the fifth read current is greater than the reference current, the control reading circuit outputs the sixth read voltage;

[0150] When the sixth read voltage is applied to the first bit line, the control memory cell outputs the sixth read current through the second bit line. The sixth read current is less than the fifth read current.

[0151] The control induction amplifier outputs a sixth comparison result based on the sixth read current and the reference current. When the sixth comparison result indicates that the sixth read current is greater than the reference current, the stored data in the storage unit is the fifth data. When the sixth comparison result indicates that the sixth read current is less than the reference current, the stored data in the storage unit is the sixth data.

[0152] When the fifth comparison result indicates that the fifth read current is less than the reference current, the control reading circuit outputs the seventh read voltage;

[0153] When the seventh read voltage is applied to the first bit line, the control memory cell outputs the seventh read current through the second bit line. The seventh read current is greater than the fifth read current.

[0154] The control induction amplifier outputs a seventh comparison result based on the seventh read current and the reference current. When the seventh comparison result indicates that the seventh read current is greater than the reference current, the stored data in the storage unit is the seventh data. When the seventh comparison result indicates that the seventh read current is less than the reference current, the stored data in the storage unit is the eighth data.

[0155] The specific implementation principle and technical effects of the memory reading method provided in this application embodiment can be found in the above-mentioned memory-related embodiments, and will not be repeated here.

[0156] An embodiment of this application also provides an electronic device, which includes the memory in the above embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc., and is not limited thereto.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory, characterized in that, The memory includes: Storage unit; The storage cell is connected to a first bit line and a second bit line. When a read voltage is applied to the first bit line, the storage cell outputs a read current through the second bit line. An inductive amplifier, wherein a first input terminal of the inductive amplifier is connected to the second bit line and receives a read current on the second bit line, a second input terminal of the inductive amplifier receives a reference current, and the inductive amplifier outputs a comparison result based on the read current and the reference current; A read circuit is provided, wherein the input terminal of the read circuit is connected to the output terminal of the inductive amplifier, and the first output terminal of the read circuit is connected to the first bit line. The read circuit adjusts the read voltage of the first bit line according to the comparison result, so as to adjust the comparison result output by the inductive amplifier, until the stored data of the memory cell is determined according to the comparison result.

2. The memory according to claim 1, characterized in that, The number of the storage units is multiple, and the number of the first bit lines is multiple; At least two of the memory cells are connected to the same first bit line.

3. The memory according to claim 2, characterized in that, The number of the second bit lines is multiple; At least two of the memory cells are connected to the same second bit line.

4. The memory according to claim 3, characterized in that, The number of the inductive amplifiers is multiple, and the first input terminal of each inductive amplifier is connected to at least one of the second bit lines.

5. The memory according to claim 1, characterized in that, The memory includes read word lines, and the memory cell includes a read transistor; The read transistor has a first gate connected to the read word line, a second gate storing the write voltage, a first electrode connected to the first bit line, and a second electrode connected to the second bit line.

6. The memory according to claim 5, characterized in that, The memory includes write word lines, and the memory cell includes a write transistor; The gate of the write transistor is connected to the write word line; The first terminal of the write transistor is connected to the first bit line or the second bit line, and the second terminal of the write transistor is connected to the second gate of the read transistor.

7. The memory according to claim 6, characterized in that, When the first terminal of the write transistor is connected to the first bit line, the first bit line is also used to receive the write voltage; when the first terminal of the write transistor is connected to the second bit line, the second bit line is also used to receive the write voltage.

8. The memory according to claim 7, characterized in that, The number of storage units is multiple, and the number of read lines is multiple; At least two of the storage units are connected to the same read word line.

9. The memory according to claim 8, characterized in that, The number of writing lines is multiple; At least two of the storage units are connected to the same write line.

10. The memory according to claim 2 or 8, characterized in that, The storage units are arranged in an array.

11. The memory according to any one of claims 1-9, characterized in that, The read circuit includes: a successive approximation register and a digital-to-analog converter; The input terminal of the successive approximation register serves as the input terminal of the read circuit, the first output terminal of the successive approximation register is connected to the input terminal of the digital-to-analog converter, and the output terminal of the digital-to-analog converter serves as the first output terminal of the read circuit. The successive approximation register outputs the digital signal corresponding to the adjusted read voltage based on the comparison result; The digital-to-analog converter outputs an adjusted read voltage based on the digital signal.

12. A method for reading a memory, characterized in that, The method is used in the memory according to any one of claims 1-11, the method comprising: When a read voltage is applied to the first bit line, the memory cell is controlled to output a read current through the second bit line; The sensor amplifier is controlled to output a comparison result based on the read current and the reference current; The read circuit is controlled to adjust the read voltage according to the comparison result, so as to adjust the comparison result until the stored data of the memory cell is determined according to the comparison result.

13. The reading method according to claim 12, characterized in that, When a read voltage is applied to the first bit line, controlling the memory cell to output a read current through the second bit line includes: When the Nth read voltage is applied to the first bit line, the memory cell is controlled to output the Nth read current through the second bit line, where N is an integer greater than 0; The control of the sensing amplifier based on the comparison result of the read current and the reference current includes: The inductive amplifier is controlled to output the Nth comparison result based on the Nth read current and the reference current; The control of the reading circuit to adjust the reading voltage according to the comparison result, thereby adjusting the comparison result, includes: The read circuit is controlled to adjust the read voltage of the first bit line to the (N+1)th voltage according to the Nth comparison result. When the (N+1)th voltage is applied to the first bit line, the memory cell is controlled to output the (N+1)th read current through the second bit line. Wherein, when the Nth comparison result indicates that the Nth read current is greater than the reference current, the (N+1)th read current is less than the Nth read current; when the Nth comparison result indicates that the Nth read current is less than the reference current, the (N+1)th read current is greater than the Nth read current.

14. The reading method according to claim 13, characterized in that, Determining the stored data of the storage unit based on the comparison result includes: The stored data of the storage unit is determined based on the Sth comparison result, where S is the number of bits of the stored data in the storage unit.

15. The reading method according to any one of claims 12-14, characterized in that, The method includes: When a first read voltage is applied to the first bit line, the memory cell is controlled to output a first read current through the second bit line; The inductive amplifier is controlled to output a first comparison result based on the first read current and the reference current; When the first comparison result indicates that the first read current is greater than the reference current, the reading circuit is controlled to output a second read voltage. When the second read voltage is applied to the first bit line, the memory cell is controlled to output a second read current through the second bit line, and the second read current is less than the first read current; The inductive amplifier is controlled to output a second comparison result based on the second read current and the reference current; When the second comparison result indicates that the second read current is greater than the reference current, the read circuit is controlled to output a third read voltage. When the third read voltage is applied to the first bit line, the memory cell is controlled to output a third read current through the second bit line, and the third read current is less than the second read current; The sensor amplifier is controlled to output a third comparison result based on the third read current and the reference current. When the third comparison result indicates that the third read current is greater than the reference current, the stored data in the storage unit is the first data. When the third comparison result indicates that the third read current is less than the reference current, the stored data in the storage unit is the second data. When the second comparison result indicates that the second read current is less than the reference current, the read circuit is controlled to output a fourth read voltage. When the fourth read voltage is applied to the first bit line, the memory cell is controlled to output a fourth read current through the second bit line, and the fourth read current is greater than the second read current. The sensor amplifier is controlled to output a fourth comparison result based on the fourth read current and the reference current. When the fourth comparison result indicates that the fourth read current is greater than the reference current, the stored data in the storage unit is the third data. When the fourth comparison result indicates that the fourth read current is less than the reference current, the stored data in the storage unit is the fourth data.

16. The reading method according to claim 15, characterized in that, The method includes: When the first comparison result indicates that the first read current is less than the reference current, the reading circuit is controlled to output a fifth read voltage. When the fifth read voltage is applied to the first bit line, the memory cell is controlled to output a fifth read current through the second bit line, and the fifth read current is greater than the first read current. The inductive amplifier is controlled to output a fifth comparison result based on the fifth read current and the reference current; When the fifth comparison result indicates that the fifth read current is greater than the reference current, the reading circuit is controlled to output a sixth read voltage. When the sixth read voltage is applied to the first bit line, the memory cell is controlled to output a sixth read current through the second bit line, and the sixth read current is less than the fifth read current; The sensor amplifier is controlled to output a sixth comparison result based on the sixth read current and the reference current. When the sixth comparison result indicates that the sixth read current is greater than the reference current, the stored data in the storage unit is the fifth data. When the sixth comparison result indicates that the sixth read current is less than the reference current, the stored data in the storage unit is the sixth data. When the fifth comparison result indicates that the fifth read current is less than the reference current, the reading circuit is controlled to output the seventh read voltage. When the seventh read voltage is applied to the first bit line, the memory cell is controlled to output a seventh read current through the second bit line, and the seventh read current is greater than the fifth read current; The sensor amplifier is controlled to output a seventh comparison result based on the seventh read current and the reference current. When the seventh comparison result indicates that the seventh read current is greater than the reference current, the stored data in the storage unit is the seventh data. When the seventh comparison result indicates that the seventh read current is less than the reference current, the stored data in the storage unit is the eighth data.

17. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 11.

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