Storage array and in-storage calculation method
By employing a source-line structure in the storage array where each column of storage cells is connected to different input, output, and intermediate result units, the problem of copying intermediate result data is solved, achieving efficient in-memory computation, reducing latency and power consumption, and improving storage density and computational efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-03-24
AI Technical Summary
Digital in-memory computing based on dual-source pole-line (2-SL) memory arrays suffers from the problem of copying intermediate result data during multi-step logical operations, leading to increased computational latency, increased power consumption, and reduced storage density.
It adopts a multi-column storage cell structure, with each column including an input cell, an intermediate result cell, and an output cell, which are connected to different source lines to avoid copying intermediate result data and directly perform subsequent calculations.
It significantly reduces in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage cell occupancy, increases storage density, and supports more complex multi-step computation logic.
Smart Images
Figure CN121725845A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and more particularly to a memory array and an in-memory computing method. Background Technology
[0002] The "Von Neumann bottleneck," caused by the separation of processor and memory in traditional computing architectures, has become a major obstacle to improving the energy efficiency and computing power of computing systems. In-memory computing is considered a disruptive technology to break this bottleneck. Its core idea is to integrate computing functions into the memory array and process the stored data directly, thereby minimizing the huge latency and power consumption caused by data transfer.
[0003] There are two main technical paths to achieving in-memory computing: analog in-memory computing and digital in-memory computing. Analog in-memory computing utilizes physical laws (such as Kirchhoff's current law) to perform multiplication and addition operations in the analog domain. While it has the potential for high parallelism, its accuracy is severely limited by device mismatch and noise. Its computational functions are fixed, its flexibility is poor, and it struggles to implement complex logic judgments and control functions, thus limiting its application in applications requiring high precision and complex control flows. Digital in-memory computing, on the other hand, utilizes the memory cells themselves to construct logic gates and perform Boolean logic operations. Digital in-memory computing offers advantages such as high precision, strong noise immunity, and good compatibility with existing digital design flows, making it an ideal choice for achieving general-purpose and complex computational tasks.
[0004] Currently, the main problem with in-memory computing based on dual-source pole line (2-SL) memory arrays is the "intermediate result dilemma" in multi-step logic operations. That is, in multi-step logic operations, after processing the input data to obtain intermediate result data, the intermediate result data must be copied to the memory cell connected to the same source pole line as the input data before the input data and intermediate result data can continue to be processed. These copying steps increase the computational latency and power consumption, reduce the computational efficiency, and require more memory cells to temporarily store the intermediate result data, resulting in a decrease in storage density. Summary of the Invention
[0005] This application provides a storage array and an in-memory computing method to reduce in-memory computing latency, improve computing efficiency, reduce power consumption, reduce storage unit occupancy, and increase storage density.
[0006] In a first aspect, embodiments of this application provide a storage array, including: multiple columns of storage units, each column of storage unit including an input unit, an intermediate result unit and an output unit;
[0007] The input unit is used to store input data for in-memory calculation, the intermediate result unit is used to store intermediate result data obtained by calculating the input data, and the output unit is used to store in-memory calculation result data obtained by calculating the input data and the intermediate result data.
[0008] The input unit, the intermediate result unit, and the output unit are each connected to different source lines.
[0009] In some embodiments, the source line includes a first source line, a second source line, and a third source line;
[0010] The input unit is connected to the first source line, the intermediate result unit is connected to the second source line, and the output unit is connected to the third source line.
[0011] In some implementations, every two adjacent columns of memory cells share the source line.
[0012] In some implementations, the input unit includes at least one storage unit, the intermediate result unit includes at least one storage unit, and the output unit includes at least one storage unit.
[0013] In some implementations, during the process of calculating the intermediate result data from the input data, the read line of the input unit is active, the write line of the intermediate result unit is active, the first source line is connected to a first logic level, and the second source line is grounded, so as to write the intermediate result data into the intermediate result unit.
[0014] In some implementations, during the process of calculating the in-memory calculation result data by calculating the input data and the intermediate result data, the read word line of the input unit is valid, the read word line of the intermediate result unit is valid, the write word line of the output unit is valid, the first source line is connected to the second logic level, the second source line is connected to the second logic level, and the third source line is grounded, so as to write the in-memory calculation result data into the output unit.
[0015] In some embodiments, the storage unit includes a magnetic storage device, which is a spin-orbit moment magnetic storage device or a spin-transfer moment magnetic storage device.
[0016] In some implementations, each column of memory cells is connected to multiple bit lines.
[0017] The storage array provided in this application embodiment, since the input unit, intermediate result unit, and output unit are connected to different source lines respectively, after calculating the intermediate result data from the input data, the input data and intermediate result data are distributed on different source lines. The intermediate result data and input data can be directly used for subsequent calculations without copying the intermediate result data. This completely eliminates the two copy operations required in the traditional dual-source 2-SL architecture, fundamentally reducing the number of steps and pulse cycles required for multi-step logic operations, significantly reducing in-memory computation latency, improving computational efficiency, reducing power consumption, reducing storage unit occupancy, and increasing storage density. At the same time, it also provides a hardware foundation for building more complex multi-step operation logic. Intermediate result data can be generated and temporarily stored on different source lines, and can be flexibly read and reused in subsequent operation steps as needed, improving computational parallelism and overall efficiency, and making the construction of complex operations simpler and more efficient.
[0018] Secondly, this application provides an in-memory computing method applied to the memory array as described in the first aspect, the method comprising:
[0019] The system controls the read line of the input unit to be valid, the write line of the intermediate result unit to be valid, and controls the source line connected to the input unit to be connected to the first logic level and the source line connected to the intermediate result unit to be grounded, so as to write the intermediate result data obtained by calculating the input data into the intermediate result unit.
[0020] The system controls the read line of the input unit to be active, the read line of the intermediate result unit to be active, and the write line of the output unit to be active. It also controls the source line connected to the input unit to be connected to the second logic level, the source line connected to the intermediate result unit to be connected to the second logic level, and the source line connected to the output unit to be grounded, so as to write the in-memory calculation result data obtained by calculating the input data and the intermediate result data into the output unit.
[0021] In some embodiments, a column of storage cells in the storage array performs the method described in the second aspect to implement any one of the following operations: XOR, XOR, or addition; and / or,
[0022] The multiple columns of storage cells in the storage array perform in-memory computation as described in the second aspect to achieve convolution operations.
[0023] The in-memory computation method provided in this application embodiment connects the input unit, intermediate result unit, and output unit to different source lines. After calculating the intermediate result data from the input data, the input data and intermediate result data are distributed on different source lines. Subsequent calculations can be performed directly on the intermediate result data and input data without copying the intermediate result data. This completely eliminates the two copy operations required in the traditional dual-source 2-SL architecture, fundamentally reducing the number of steps and pulse cycles required for multi-step logic operations. This significantly reduces in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage unit occupancy, and increases storage density. At the same time, it provides a hardware foundation for building more complex multi-step operation logic. Intermediate result data can be generated and temporarily stored on different source lines, and can be flexibly read and reused in subsequent operation steps as needed, improving computational parallelism and overall efficiency, making the construction of complex operations simpler and more efficient. Attached Figure Description
[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0025] Figure 1 This is a schematic diagram of the structure of a dual-source poleline (2-SL) memory array;
[0026] Figure 2 A schematic diagram of a storage array provided in this application embodiment. Figure 1 ;
[0027] Figure 3 A schematic diagram of a storage array provided in this application embodiment. Figure 2 ;
[0028] Figure 4 A schematic diagram of a storage array provided in this application embodiment. Figure 3 ;
[0029] Figure 5 A schematic diagram of a storage array provided in this application embodiment. Figure 4 ;
[0030] Figure 6 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 1 ;
[0031] Figure 7 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 1 ;
[0032] Figure 8 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application.Figure 2 ;
[0033] Figure 9 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 3 ;
[0034] Figure 10 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 4 ;
[0035] Figure 11 A schematic diagram of the structure of a column of storage cells provided in an embodiment of this application. Figure 2 ;
[0036] Figure 12 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 5 ;
[0037] Figure 13 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 6 ;
[0038] Figure 14 A schematic diagram of the calculation process in a column of storage units provided in an embodiment of this application. Figure 7 ;
[0039] Figure 15 A schematic diagram of the calculation process of convolution operation provided in the embodiments of this application. Figure 1 ;
[0040] Figure 16 A schematic diagram of the calculation process of convolution operation provided in the embodiments of this application. Figure 2 ;
[0041] Figure 17 A schematic diagram of the calculation process of convolution operation provided in the embodiments of this application. Figure 3 ;
[0042] Figure 18 This is a schematic diagram of the control unit provided in an embodiment of this application.
[0043] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation
[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0045] First, combine Figure 1 Examples of in-memory computing in related technologies are provided.
[0046] Figure 1 The diagram illustrates the structure of a dual-source-line (2-SL) memory array. In this array, each column of memory cells is connected to two source lines (SL00 and SL01). Memory cells A, B, C2, and C3 are connected to source line SL00, while memory cells C1 and R are connected to source line SL01. Figure 1 In the examples and other embodiments following this application, the data stored in storage unit A is represented by A, the data stored in storage unit B is represented by B, the data stored in storage unit C1 is represented by C1, and so on for other storage units. Furthermore, in Figure 1 In the examples and other embodiments of this application, the storage cell is in a high-resistance state, corresponding to stored data "0", and the storage cell is in a low-resistance state, corresponding to stored data "1".
[0047] based on Figure 1 The structure of the storage array shown requires performing an XNOR operation on A and B in the following four steps:
[0048] Step 11: C1 = A NOR B;
[0049] Step 12: C2 = COPY C1;
[0050] Step 13: C3 = COPY C1;
[0051] Step 14: R = TH4 (A, B, C2, C3).
[0052] In step 11, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, and the write word line WWL2 of memory cell C1 is enabled. A logic voltage Vlogic(NOR) is applied to the source line SL00, the source line SL01 is grounded, and the current on the bit line BL0 can cause the resistance state of memory cell C1 to flip or remain unchanged, thereby realizing the writing of the result of A NORB into memory cell C1.
[0053] The initial value of memory cell C1 is "1", meaning its initial resistance state is low. When both A and B are "0", the current on bit line BL0 is below the toggle threshold, preventing memory cell C1 from flipping, and C1 remains in the low-resistance state, still set to "1". When A and B are "0" and "1" respectively, or "1" and "0" respectively, or when both A and B are "1", the current on bit line BL0 exceeds the toggle threshold, causing memory cell C1 to flip from the low-resistance state to the high-resistance state, changing C1 from "1" to "0". This achieves the operation C1 = A NOR B.
[0054] In step 12, the read word line RWL2 of the control memory cell C1 is enabled, the write word line WWL3 of the control memory cell C2 is enabled, the logic voltage Vlogic(COPY) is applied to the source line SL01, the source line SL00 is grounded, and the current on the bit line BL0 can cause the resistance state of the memory cell C2 to flip or remain unchanged, thereby realizing the copying of C1 into the memory cell C1.
[0055] The initial value of memory cell C2 is "0", meaning its initial resistance state is high. When C1 is "0", the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell C2 from flipping, and C2 remains in a high-resistance state, still "0". When C1 is "1", the current on bit line BL0 is above the toggling threshold, causing memory cell C2 to flip from a high-resistance state to a low-resistance state, meaning C2 changes from "0" to "1". This achieves the operation C2 = COPY C1.
[0056] In step 13, the read word line RWL2 of memory cell C1 is enabled, the write word line WWL4 of memory cell C3 is enabled, a logic voltage Vlogic(COPY) is applied to the source line SL01, the source line SL00 is grounded, and the current on the bit line BL0 can cause the resistance state of memory cell C3 to flip or remain unchanged, thereby copying C1 into memory cell C3. The implementation process of step 13 is similar to that of step 12.
[0057] In step 14, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL3 of memory cell C2 is enabled, the read word line RWL4 of memory cell C3 is enabled, and the write word line WWL5 of memory cell R is enabled. A logic voltage Vlogic(TH4) is applied to the source line SL00, the source line SL01 is grounded, and the current on the bit line BL0 can cause the resistance state of memory cell R to flip or remain unchanged, thereby realizing the writing of the result of TH4(A,B,C2,C3) into memory cell R.
[0058] The initial value of memory cell R is "0", meaning its initial resistance state is high resistance. When A, B, C2, and C3 are "0", "1", "0", and "0" respectively, or when A, B, C2, and C3 are "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell R from flipping, and R remains in a high resistance state, meaning R is still "0". When A, B, C2, and C3 are "0", "0", "1", and "1" respectively, or when A, B, C2, and C3 are "1", "1", "0", and "0" respectively, the current on bit line BL0 is above the toggling threshold, causing memory cell R to flip from a high resistance state to a low resistance state, meaning R changes from "0" to "1". This achieves the operation R = TH4(A, B, C2, C3).
[0059] The truth table for the above XOR operation is shown in Table 1.
[0060] Table 1
[0061] A B C1 C2 C3 R 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1
[0062] based on Figure 1 The structure of the storage array shown requires the following four steps to perform an XOR operation on A and B:
[0063] Step 21: C1 = A NOR B;
[0064] Step 22: C2 = COPY C1;
[0065] Step 23: C3 = COPY C1;
[0066] Step 24: R= (A,B,C2,C3).
[0067] The implementation process of steps 21, 22, and 23 can be referred to the description of steps 11, 12, and 13 in the aforementioned XOR operation.
[0068] In step 24, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL3 of memory cell C2 is enabled, the read word line RWL4 of memory cell C3 is enabled, and the write word line WWL5 of memory cell R is enabled. A logic voltage Vlogic(TH4) is applied to the source line SL00, and the source line SL01 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell R to flip or remain unchanged, thereby realizing the switching of the read word line R. The result of (A,B,C2,C3) is written into storage unit R.
[0069] The initial value of memory cell R is "1", meaning its initial resistance state is low. When A, B, C2, and C3 are "0", "1", "0", and "0" respectively, or when A, B, C2, and C3 are "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell R from flipping, and R remains in the low-resistance state, meaning R is still "1". When A, B, C2, and C3 are "0", "0", "1", and "1" respectively, or when A, B, C2, and C3 are "1", "1", "0", and "0" respectively, the current on bit line BL0 is above the toggling threshold, causing memory cell R to flip from the low-resistance state to the high-resistance state, meaning R flips from "1" to "0". This achieves R = ... Operations on (A,B,C2,C3).
[0070] The truth table for the above XOR operation is shown in Table 2.
[0071] Table 2
[0072] A B C1 C2 C3 R 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0
[0073] As can be seen from the above-described computational process, in multi-step logical operations, due to the limitation on the number of source lines, if the intermediate result data output from the first step and the input data from the first step are to be used together for the calculation in the second step, the intermediate result data needs to be copied to another storage unit (i.e., two copy operations are required). This other storage unit is connected to the same source line as the storage unit where the input data from the first step is located. Copying the intermediate result data increases computational latency, power consumption, and computational efficiency, making it very difficult and inefficient to construct complex computations. Furthermore, copying the intermediate result requires more storage units, reducing storage density.
[0074] To address the aforementioned issues, this application proposes a storage array that avoids copying intermediate result data by adding source lines. The following description, in conjunction with embodiments, illustrates this approach.
[0075] Figure 2 A schematic diagram of a storage array provided in this application is shown below. Figure 2 As shown, the storage array 200 includes multiple columns of storage cells, each column of storage cell including an input cell 201, an intermediate result cell 202 and an output cell 203.
[0076] The input unit 201 is used to store the input data for in-memory calculation, the intermediate result unit 202 is used to store the intermediate result data obtained by calculating the input data, and the output unit 203 is used to store the in-memory calculation result data obtained by calculating the input data and the intermediate result data.
[0077] The input unit 201, intermediate result unit 202 and output unit 203 are connected to different source lines respectively.
[0078] Input unit 201, intermediate result unit 202, and output unit 203 are connected to bit line BL. Figure 2 The write and read lines connecting the storage units are not shown in the diagram.
[0079] The in-memory computation in this embodiment may include multi-step logical operations, which involve calculating intermediate result data from the input data. During the calculation of the input data to obtain intermediate result data, the read channel of the input unit is enabled, the write channel of the intermediate result unit is enabled, the source line SL00 connected to the input unit 201 is connected to the first logic level, and the source line SL01 connected to the intermediate result unit 202 is grounded. The intermediate result data is written to the intermediate result unit 202 through the current on the bit line BL.
[0080] During the process of calculating the in-memory calculation result data by processing the input data and intermediate result data, the read channels of the input unit 201 and the intermediate result unit 202 are turned on, the write channel of the output unit 203 is turned on, the source line SL00 connected to the input unit 201 is connected to the second logic level, the source line SL01 connected to the intermediate result unit 202 is connected to the second logic level, and the source line SL02 connected to the output unit 203 is grounded. The in-memory calculation result data is written to the output unit 203 through the current on the bit line BL.
[0081] Since the input unit 201, intermediate result unit 202, and output unit 203 are connected to different source lines, after calculating the intermediate result data from the input data in the first step, there is no need to copy the intermediate result data. In the second step, when calculating the in-memory calculation result data from the input data and the intermediate result data, it is only necessary to apply a second logic level to the source lines connected to the input unit 201 and the intermediate result unit 202, and ground the source line connected to the output unit 203. This allows the intermediate result data and the input data to be calculated together in the second step. Because there is no need to copy the intermediate result data, the memory array of this embodiment reduces in-memory calculation latency, improves calculation efficiency, reduces power consumption, reduces memory cell occupancy, increases storage density, and makes constructing complex calculations simpler and more efficient.
[0082] It should be noted that in this embodiment, only the input unit 201, intermediate result unit 202, and output unit 203 in each column of storage units need to be connected to different source lines, that is, the number of source lines is at least three, but there is no limitation on the specific number of source lines. The input unit 201 includes at least one storage unit, the intermediate result unit 202 includes at least one storage unit, and the output unit 203 includes at least one storage unit.
[0083] Provided that the input unit 201, intermediate result unit 202, and output unit 203 are connected to different source lines, when the input unit 201 includes multiple memory units, the source lines connected to different memory units in the input unit 201 can also be different. When the intermediate result unit 202 includes multiple memory units, the source lines connected to different memory units in the intermediate result unit 202 can also be different. When the output unit 203 includes multiple memory units, the source lines connected to different memory units in the output unit 203 can also be different.
[0084] Taking the source lines of each column of storage cells as including the first source line, the second source line and the third source line as an example, the input unit 201 is connected to the first source line, the intermediate result unit 202 is connected to the second source line, and the output unit 203 is connected to the third source line, thereby ensuring that the input unit 201, the intermediate result unit 202 and the output unit 203 are connected to different source lines respectively.
[0085] When the source lines of each column of memory cell include a first source line SL00, a second source line SL01, and a third source line SL02, during the process of calculating intermediate result data from the input data, the read word line of the input cell 201 is active, the write word line of the intermediate result cell 202 is active, the first source line SL00 is connected to the first logic level, and the second source line SL01 is grounded, so as to write the intermediate result data into the intermediate result cell 202.
[0086] During the process of calculating the in-memory calculation result data by processing the input data and intermediate result data, the read word line of the input unit 201 is valid, the read word line of the intermediate result unit 202 is valid, the write word line of the output unit 203 is valid, the first source line SL00 is connected to the second logic level, the second source line SL01 is connected to the second logic level, and the third source line SL02 is grounded, so as to write the in-memory calculation result data into the output unit 203.
[0087] It should be noted that the first and second logic levels applied during the calculation process may be different for different logical operations.
[0088] The storage unit in this application embodiment may include a magnetic storage device, which may be a spin-orbit moment magnetic storage device (SOT-MRAM) or a spin-transfer moment magnetic storage device (STT-MRAM). The spin-orbit moment magnetic storage device includes at least a spin-orbit moment layer and a magnetic tunnel junction disposed above the spin-orbit moment layer.
[0089] Furthermore, the spin-orbit moment layer is used to generate corresponding spin polarization currents with different writing currents, thereby generating spin torques in different directions. The spin-orbit moment layer can be a single layer or a stack, and its material includes conductive materials with strong spin-orbit coupling effects. For example, the material of the spin-orbit moment layer includes one or more of Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, FeMn, NiMn, Ta, W, Ir, IrMn, WOx, WN, WON, TaN, and TaB, as well as topological insulators. Topological insulators include Bi... x Se 1-x Bi x Sb 1-x , (Bi,Sb)2Te3, where x independently satisfies the value of 0.1-0.9.
[0090] A magnetic tunnel junction (MTJ) is the core structure of a magnetic storage device. MTJs can be cylindrical, elliptical, rectangular, or toroidal. A MTJ consists of a free layer, a barrier layer, and a fixed layer stacked from bottom to top. When the free and fixed layers are magnetized in the same direction (i.e., parallel, P-state), the MTJ is in a low-resistivity state, storing data "1". When the free and fixed layers are magnetized in opposite directions (i.e., antiparallel, AP-state), the MTJ is in a high-resistivity state, storing data "0".
[0091] In the structure illustrated in the embodiments of this application, a spin-orbit moment magnetic storage device is used as an example for illustration.
[0092] Reference Figure 3 As shown, the source lines connected to the storage cells in the 0th column of the memory array include a first source line SL00, a second source line SL01, and a third source line SL02. Specifically, the 0th and 3rd storage cells are connected to the first source line SL00, the 1st and 4th storage cells are connected to the second source line SL01, and the 2nd and 5th storage cells are connected to the third source line SL02. The 0th and 3rd storage cells are input cells, the 1st and 4th storage cells are intermediate result cells, and the 2nd and 5th storage cells are output cells. This achieves the goal of connecting the input cells, intermediate result cells, and output cells in the 0th column of the memory array to different source lines.
[0093] The source lines connected to the first column of memory cells include a first source line SL10, a second source line SL11, and a third source line SL12. Specifically, the 0th and 3rd memory cells are connected to the first source line SL10, the 1st and 4th memory cells are connected to the second source line SL11, and the 2nd and 5th memory cells are connected to the third source line SL12. The 0th and 3rd memory cells are input cells, the 1st and 4th memory cells are intermediate result cells, and the 2nd and 5th memory cells are output cells. This ensures that the input cells, intermediate result cells, and output cells in the first column of memory cells are connected to different source lines.
[0094] In some embodiments, every two adjacent columns of memory cells in the memory array share a source line.
[0095] Reference Figure 4 As shown, from left to right, the memory array is named column 0, column 1, column 2, and column 3, and so on. The source lines connecting the memory cells in columns 0 and 1 include a first source line SL00, a second source line SL01, and a third source line SL02. Within columns 0 and 1, the 0th and 3rd memory cells are connected to the first source line SL00, the 1st and 4th memory cells are connected to the second source line SL01, and the 2nd and 5th memory cells are connected to the third source line SL02. The 0th and 3rd storage units are input units, the 1st and 4th storage units are intermediate result units, and the 2nd and 5th storage units are output units. This ensures that the input, intermediate result, and output units in the 0th column of storage units are connected to different source lines, and the input, intermediate result, and output units in the 1st column of storage units are also connected to different source lines. Furthermore, adjacent columns (the 0th and 1st columns of storage units) share source lines, reducing the number of source lines per column and effectively mitigating wiring congestion and area overhead issues that may result from an increased number of source lines, thus achieving a balance between high performance and manufacturing cost.
[0096] The source lines connecting the second and third columns of memory cells include a first source line SL20, a second source line SL21, and a third source line SL22. Specifically, the 0th and 3rd memory cells are connected to the first source line SL20, the 1st and 4th memory cells are connected to the second source line SL21, and the 2nd and 5th memory cells are connected to the third source line SL22. The 0th and 3rd memory cells are input cells, the 1st and 4th memory cells are intermediate result cells, and the 2nd and 5th memory cells are output cells. This ensures that the input, intermediate result, and output cells in the second column of memory cells are connected to different source lines, and the same applies to the third column of memory cells. Meanwhile, adjacent columns (the second and third column memory cells) share source lines, reducing the number of source lines corresponding to a single column memory cell. This effectively alleviates the wiring congestion and area overhead problems that may result from the increase in the number of source lines, achieving a balance between high performance and manufacturing cost.
[0097] It should be noted that, Figure 3 and Figure 4 This is only used as an illustrative example of the connection between storage cells and source lines, and does not constitute a limitation on the number of storage cells and the order of arrangement of input cells, intermediate result cells and output cells in each column of storage cells.
[0098] exist Figure 3 and Figure 4 In the illustrated structure, each column of memory cells is connected to a bit line. For example, Figure 3 In the diagram, the 0th column memory cell is connected to bit line BL0, and the 1st column memory cell is connected to bit line BL1. Figure 4 In the diagram, the 0th column memory cell is connected to bit line BL0, the 1st column memory cell is connected to bit line BL1, the 2nd column memory cell is connected to bit line BL2, and the 3rd column memory cell is connected to bit line BL3.
[0099] In some embodiments, each column of memory can be connected to multiple bit lines. For example... Figure 5 As shown, in the 0th column of storage cells, some storage cells are connected to bit line BL00, and other storage cells are connected to bit line BL01. In the 1st column of storage cells, some storage cells are connected to bit line BL10, and other storage cells are connected to bit line BL11. With multiple bit lines connected to each column of storage cells, multiple calculations can be performed simultaneously in one column of storage cells, which can further improve computational efficiency.
[0100] The process of performing in-memory computation based on the storage array structure of this application embodiment will be described below with specific examples.
[0101] ReferenceFigure 6 As shown, Figure 6 The example uses a column of memory cells, where the source lines connected to this column of memory cells include a first source line SL00, a second source line SL01, and a third source line SL02. Input cells include memory cells A and B, which are connected to the first source line SL00. Intermediate result cells include memory cells C1 and C2, which are connected to the second source line SL01. Output cells include memory cell R, which is connected to the third source line SL02.
[0102] based on Figure 6 The structure shown requires performing an XNOR operation on A and B in the following three steps:
[0103] Step 31: C1 = A NOR B;
[0104] Step 32: C2 = A NOR B;
[0105] Step 33: C3 = TH4(A, B, C1, C2)
[0106] Among them, step 31 refers to Figure 7 As shown, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, and the write word line WWL2 of memory cell C1 is enabled. This means that the read channels of memory cells A and B are enabled, the write channel of memory cell C1 is enabled, and all other read or write channels are disabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the second source line SL01 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell C1 to flip or remain unchanged, thereby writing the result of A NOR B into memory cell C1.
[0107] The initial value of memory cell C1 is "1", meaning its initial resistance state is low. When both A and B are "0", the current on bit line BL0 is below the toggle threshold, preventing memory cell C1 from flipping, and C1 remains in the low-resistance state, still set to "1". When A and B are "0" and "1" respectively, or "1" and "0" respectively, or when both A and B are "1", the current on bit line BL0 exceeds the toggle threshold, causing memory cell C1 to flip from the low-resistance state to the high-resistance state, changing C1 from "1" to "0". This achieves the operation C1 = A NOR B.
[0108] Step 32 (refer to) Figure 8As shown, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, and the write word line WWL3 of memory cell C2 is enabled, which means that the read channels of memory cells A and B are enabled, and the write channel of memory cell C2 is enabled. A first logic level Vlogic(NOR) is applied to the first source line SL00, and the second source line SL01 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell C2 to flip or remain unchanged, thereby writing the result of A NOR B into memory cell C2.
[0109] The initial value of memory cell C2 is "1", meaning its initial resistance state is low. When both A and B are "0", the current on bit line BL0 is below the toggle threshold, preventing the resistance state of memory cell C2 from flipping, and C2 remains in the low-resistance state, meaning C2 is still "1". When A and B are "0" and "1" respectively, or "1" and "0" respectively, or when both A and B are "1", the current on bit line BL0 exceeds the toggle threshold, causing memory cell C2 to flip from the low-resistance state to the high-resistance state, meaning C2 flips from "1" to "0". This achieves the operation C2 = A NOR B.
[0110] Step 33 (refer to) Figure 9 As shown, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL2 of memory cell C1 is enabled, the read word line RWL3 of memory cell C2 is enabled, and the write word line WWL4 of memory cell R is enabled. The second logic level Vlogic(TH4) is applied to the first source line SL00 and the second source line SL01, and the third source line SL02 is grounded. The current on the bit line BL0 can cause the resistance state of memory cell R to flip or remain unchanged, thereby realizing the writing of the result of TH4(A,B,C1,C2) into memory cell R.
[0111] The initial value of memory cell R is "0", meaning its initial resistance state is high resistance. When A, B, C1, and C2 are "0", "1", "0", and "0" respectively, or when A, B, C1, and C2 are "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell R from flipping, and R remains in a high resistance state, meaning R is still "0". When A, B, C1, and C2 are "0", "0", "1", and "1" respectively, or when A, B, C1, and C2 are "1", "1", "0", and "0" respectively, the current on bit line BL0 is above the toggling threshold, causing memory cell R to flip from a high resistance state to a low resistance state, meaning R flips from "0" to "1". This achieves the operation R = TH4(A, B, C1, C2).
[0112] based on Figure 6 The truth table for the XOR operation of the structure shown is shown in Table 3.
[0113] Table 3
[0114] A B C1 C2 R 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1
[0115] based on Figure 6 The XOR operation of the structure shown requires only 3 calculation steps, which takes 3 pulse cycles and uses 6 storage units. This fundamentally reduces the number of steps and pulse cycles required for multi-step logic operations, significantly reduces in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage unit occupancy, and increases storage density.
[0116] based on Figure 6 The structure shown requires the following three steps to perform an XOR operation on A and B:
[0117] Step 41: C1 = A NOR B;
[0118] Step 42: C2 = A NOR B;
[0119] Step 43: C3 = (A, B, C1, C2)
[0120] Step 41 is described in the same way as step 31 above. Step 42 is described in the same way as step 32 above.
[0121] Step 43 (refer to) Figure 10 As shown, the read word line RWL0 of memory cell A is enabled, the read word line RWL1 of memory cell B is enabled, the read word line RWL2 of memory cell C1 is enabled, the read word line RWL3 of memory cell C2 is enabled, and the write word line WWL4 of memory cell R is enabled. A second logic level Vlogic is applied to the first source line SL00 and the second source line SL01. The third source line SL02 is grounded, and the current on the bit line BL0 can cause the resistance state of the memory cell R to flip or remain unchanged, thereby realizing the switching of the memory cell R. The result of (A,B,C1,C2) is written into storage unit R.
[0122] The initial value of memory cell R is "1", meaning its initial resistance state is low. When A, B, C1, and C2 are "0", "1", "0", and "0" respectively, or when A, B, C1, and C2 are "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell R from flipping, and R remains in a low-resistance state, meaning R is still "1". When A, B, C1, and C2 are "0", "0", "1", and "1" respectively, or when A, B, C1, and C2 are "1", "1", "0", and "0" respectively, the current on bit line BL0 is above the toggling threshold, causing memory cell R to flip from a low-resistance state to a high-resistance state, meaning R flips from "1" to "0". This achieves R = ... Operations on (A,B,C1,C2).
[0123] based on Figure 6 The truth table for the XOR operation of the structure shown is shown in Table 4.
[0124] Table 4
[0125] A B C1 C2 R 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0
[0126] based on Figure 6 The XOR operation of the structure shown requires only 3 calculation steps, which takes 3 pulse cycles and uses 6 storage units. This fundamentally reduces the number of steps and pulse cycles required for multi-step logic operations, significantly reduces in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage unit occupancy, and increases storage density.
[0127] Reference Figure 11 As shown, Figure 11 The example uses a column of memory cells, where the source lines connected to this column include a first source line SL00, a second source line SL01, and a third source line SL02. The input units include memory cells A, B, and C0, which are connected to the first source line SL00. The intermediate result units include memory cells... and storage unit storage unit and storage unit The second source line SL01 is connected, and the output unit includes a storage unit Sum, which is connected to the third source line SL02.
[0128] based on Figure 11 The structure shown implements a full adder, which means that to perform addition operations on A, B, and C0, it needs to be broken down into the following three steps:
[0129] Step 51: = (A,B,C0);
[0130] Step 52: = (A,B,C0);
[0131] Step 53: Sum=MAJ5(A,B,C0, , ).
[0132] Step 51 (refer to) Figure 12 As shown, the read word line RWL0 of memory cell A is active, the read word line RWL1 of memory cell B is active, the read word line WWL2 of memory cell C0 is active, and the memory cell... The write line WWL3 is active, which means that the read channels of memory cells A, B, and C0 are enabled, and the memory cells are activated. The write channel is enabled, while all other read or write channels are disabled. A first logic level, Vlogic, is applied to the first source line SL00. The second source line SL01 is grounded, and the current on the bit line BL0 can make the memory cell... The resistance state flips or remains unchanged, thereby achieving the reversal of the resistance state. The result of (A,B,C0) is written to the storage unit. .
[0133] storage unit The initial value is "1", which is the storage unit. The initial resistance state is a low-resistance state. When A, B, and C0 are "0", "0", and "0" respectively, or when A, B, and C0 are "0", "0", and "1" respectively, or when A, B, and C0 are "0", "1", and "0" respectively, or when A, B, and C0 are "1", "0", and "0" respectively, the current on the bit line BL0 is below the toggling threshold and cannot activate the memory cell. Resistance state flip, memory cell Maintaining a low-resistance state, that is It remains "1". When A, B, and C0 are "0", "1", and "1", or when A, B, and C0 are "1", "0", and "1", or when A, B, and C0 are "1", "1", and "0", or when A, B, and C0 are "1", "1", and "1", the current on bit line BL0 exceeds the toggle threshold, causing the memory cell to... The transition from a low-resistance state to a high-resistance state is... Flip the "1" to "0". This achieves the desired result. = Operations on (A,B,C0).
[0134] Step 52 (refer to)Figure 13 As shown, the read word line RWL0 of memory cell A is active, the read word line RWL1 of memory cell B is active, the read word line WWL2 of memory cell C0 is active, and the memory cell... The write line WWL4 is active, which means that the read channels of memory cells A, B, and C0 are enabled, and the memory cells are activated. The write channel is enabled, while all other read or write channels are disabled. A first logic level, Vlogic, is applied to the first source line SL00. The second source line SL01 is grounded, and the current on the bit line BL0 can make the memory cell... The resistance state flips or remains unchanged, thereby achieving the reversal of the resistance state. The result of (A,B,C0) is written to the storage unit. .
[0135] storage unit The initial value is "1", which is the storage unit. The initial resistance state is a low-resistance state. When A, B, and C0 are "0", "0", and "0" respectively, or when A, B, and C0 are "0", "0", and "1" respectively, or when A, B, and C0 are "0", "1", and "0" respectively, or when A, B, and C0 are "1", "0", and "0" respectively, the current on the bit line BL0 is below the toggling threshold and cannot activate the memory cell. Resistance state flip, memory cell Maintaining a low-resistance state, that is It remains "1". When A, B, and C0 are "0", "1", and "1" respectively, or when A, B, and C0 are "1", "0", and "1" respectively, or when A, B, and C0 are "1", "1", and "0" respectively, or when A, B, and C0 are "1", "1", and "1" respectively, the current on bit line BL0 exceeds the toggle threshold, causing the memory cell to... The transition from a low-resistance state to a high-resistance state is... Flip the "1" to "0". This achieves the desired result. = Operations on (A,B,C0).
[0136] Step 53 (refer to) Figure 14 As shown, the read word line RWL0 of memory cell A is active, the read word line RWL1 of memory cell B is active, the read word line WWL2 of memory cell C0 is active, and the memory cell... Read line RWL3 is valid, storage unit The read word line RWL4 is enabled, and the write word line WWL5 of the memory unit Sum is enabled, which means that memory units A, B, C0, and Sum are enabled. Storage unit The read channel is enabled, and the write channel of memory cell Sum is enabled; all other read and write channels are disabled. A second logic level Vlogic (MAJ5) is applied to the first source line SL00 and the second source line SL01, and the third source line SL02 is grounded. The current on bit line BL0 can cause the resistance state of memory cell Sum to flip or remain unchanged, thereby realizing the switching of MAJ5(A,B,C0,...)... , The result is written to storage unit R.
[0137] The initial value of the memory cell Sum is "0", meaning the initial resistive state of the memory cell Sum is a high-resistance state. At points A, B, C0, ... , They are respectively "0", "0", "0", "1", "1", or A, B, C0, , They are respectively "0", "1", "1", "0", "0", or A, B, C0, , They are respectively "1", "0", "1", "0", "0", or A, B, C, 0. , When the values are "1", "1", "0", "0", and "0" respectively, the current on bit line BL0 is below the toggling threshold, preventing the resistance state of memory cell Sum from toggling. Therefore, memory cell Sum remains in a high-resistance state, meaning Sum is still "0". In cases A, B, C0, ... , They are respectively "0", "0", "1", "1", "1", or A, B, C0, , They are respectively "0", "1", "0", "1", "1", or A, B, C0, , They are respectively "1", "0", "0", "1", "1", or A, B, C0, , When the values are "1", "1", "1", "0", "0", the current on bit line BL0 exceeds the toggling threshold, causing the memory cell Sum to flip from a high-resistance state to a low-resistance state, i.e., Sum flips from "0" to "1". This achieves Sum = MAJ5(A, B, C0, ... , Operations.
[0138] based on Figure 11 The truth table of the full adder with the structure shown is shown in Table 5.
[0139] Table 5
[0140] A B C0 Sum 0 0 0 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1
[0141] based on Figure 11 The addition operation shown requires only 3 calculation steps, which takes 3 pulse cycles and uses 6 storage units. This fundamentally reduces the number of steps and pulse cycles required for multi-step logic operations, significantly reduces in-memory computation latency, improves computational efficiency, reduces power consumption, reduces storage unit occupancy, and increases storage density.
[0142] In addition to the aforementioned operations in a single column of storage units, the storage array provided in this application embodiment can also perform more complex operations through multiple columns of storage units. The following explanation uses convolution operation as an example.
[0143] Reference Figures 15-17 The diagram illustrates a storage array in cell form, where one cell represents one storage unit, and a column of cells represents a column of storage units. Figures 15-17 The same storage unit in the diagram indicates the same storage unit. The input matrix... and convolution kernel The convolution operation can be broken down into the following steps:
[0144] Step 61: A1 = X1 XNOR W1; A4 = X4 XNOR W4; A7 = X7 XNOR W7.
[0145] A1, A4, and A7 are calculated simultaneously in three storage units. The calculation of A1, A4, and A7 is a multiplexed OR operation, and the specific calculation process can be referred to the description of the multiplexed OR operation in the previous embodiment. Storage units R1 / R2, R3 / R4, and R5 / R6 are used to store the intermediate result data of the multiplexed OR operation corresponding to A1, A4, and A7, respectively. Since the multiplexed OR operation requires 3 pulse cycles, step 61 takes a total of 3 pulse cycles.
[0146] Step 62: A2 = X2 XNOR W2; A5 = X5 XNOR W5; A8 = X8 XNOR W8.
[0147] A2, A5, and A8 are calculated simultaneously in three storage units. The calculation of A2, A5, and A8 is a multiplexed OR operation; the specific calculation process can be found in the description of the multiplexed OR operation in the previous embodiment. In step 62, storage units R1 / R2, R3 / R4, and R5 / R6 are still used to store the intermediate result data of the multiplexed OR operation corresponding to A2, A5, and A8. Step 62 takes a total of 3 pulse cycles.
[0148] Step 63: A3 = X3 XNOR W3; A6 = X6 XNOR W6; A9 = X9 XNOR W9.
[0149] A3, A6, and A9 are calculated simultaneously in three storage units. The calculation of A3, A6, and A9 is an XNOR operation, and the specific calculation process can be referred to the description of the XNOR operation in the previous embodiment. In step 63, storage units R1 / R2, R3 / R4, and R5 / R6 are still used to store the intermediate result data of the XNOR operation corresponding to A3, A6, and A9. Step 63 takes a total of 3 pulse cycles.
[0150] Step 64: S1=A1+ A2+ A3; S2=A4+ A5+ A6; S3=A7+ A8+ A9.
[0151] S1, S2, and S3 are calculated simultaneously in three column storage units. The calculations of S1, S2, and S3 are all addition operations; the specific calculation process can be found in the description of addition operations in the previous embodiments. Storage Unit / , / , / These are used to store the intermediate results of the addition operations corresponding to S1, S2, and S3, respectively. Since the addition operation requires 3 pulse cycles, step 61 takes a total of 3 pulse cycles.
[0152] Step 65: S22 = COPY S2; S33 = COPY S3.
[0153] S2 and S3 are copied sequentially to the memory cells in the same column as S1. Since copying takes one pulse cycle, step 65 takes a total of two pulse cycles.
[0154] Step 66: C1=INV C2=INV C3=INV .
[0155] right , , The numbers C1, C2, and C3 are obtained by inverting them sequentially. C1, C2, and C3 are stored in the 4th column. Since the inversion operation takes 1 pulse cycle, step 66 takes a total of 3 pulse cycles.
[0156] Step 67: S4 = S1 + S22 + S33; S5 = C1 + C2 + C3.
[0157] S4 and S5 are calculated simultaneously in two columns of storage units. The calculation of S4 and S5 is an addition operation. The specific calculation process can be found in the description of addition operations in the previous embodiment. Storage unit / , / These are used to store the intermediate results of the addition operations corresponding to S4 and S5, respectively. Since the addition operation requires 3 pulse cycles, step 67 takes a total of 3 pulse cycles.
[0158] Step 68: C4 = INV .
[0159] right The inverted value is obtained as C4, which is stored in the 4th column. Since the inverted operation takes 1 pulse cycle, step 68 takes a total of 1 pulse cycle.
[0160] Step 69: S6 = S5 + C4.
[0161] The calculation in S6 is an addition operation; the specific calculation process can be found in the description of addition operations in the previous embodiments. Storage unit / This is used to store the intermediate result data of the addition operation corresponding to S6. Since the addition operation takes 3 pulse cycles, step 69 takes a total of 3 pulse cycles.
[0162] Step 70: C5 = INV .
[0163] right The inverted value is obtained as C5, which is stored in column 4. Since the inverted operation takes 1 pulse cycle, step 70 takes a total of 1 pulse cycle.
[0164] Step 71: S7 = S6 + C5.
[0165] The calculation in S7 is an addition operation; the specific calculation process can be found in the description of addition operations in the previous embodiments. Storage unit / This is used to store the intermediate result data of the addition operation corresponding to S7. Since the addition operation takes 3 pulse cycles, step 71 takes a total of 3 pulse cycles.
[0166] Step 72: C7 = INV .
[0167] right The inverted value is obtained as C7, which is stored in column 4. Since the inverted operation takes 1 pulse cycle, step 72 takes a total of 1 pulse cycle.
[0168] Through steps 61-72 above, the convolution operation results are obtained: C7, S7, S6, and S4, taking a total of 29 pulse cycles. Compared with existing technologies, this reduces 7 pulse cycles, lowers in-memory computation latency, improves computational efficiency, and lowers power consumption.
[0169] This application provides an in-memory computing method applied to the memory array in the foregoing embodiments. The method includes:
[0170] The read line of the control input unit is enabled, the write line of the intermediate result unit is enabled, and the source line of the control input unit is connected to the first logic level and the source line of the control intermediate result unit is grounded, so as to write the intermediate result data obtained by calculating the input data into the intermediate result unit.
[0171] The system controls the read line of the input unit to be active, the read line of the intermediate result unit to be active, and the write line of the output unit to be active. It also controls the source line of the input unit to be connected to the second logic level, the source line of the intermediate result unit to be connected to the second logic level, and the source line of the output unit to be grounded, so as to write the in-memory calculation result data obtained by calculating the input data and the intermediate result data into the output unit.
[0172] The method can be executed by one column of storage cells in the storage array to perform any one of the following operations: XOR, XOR, or addition; and / or, the method can be executed by multiple columns of storage cells in the storage array to perform convolution. The implementation principle and technical effects of this method can be found in the descriptions of the foregoing embodiments, and will not be repeated here.
[0173] It should be noted that the storage array and the method described in this application embodiment can also implement other Boolean logic operations besides those listed above, or other complex operations composed of Boolean logic operations.
[0174] The methods described in this application embodiment can be executed by a control unit electrically connected to the storage array.
[0175] Figure 18 This is a schematic diagram of the control unit provided in this application. Figure 18 As shown, the control unit 180 provided in this embodiment includes at least one processor 1801 and a memory 1802. Optionally, the control unit 181 further includes a communication component 1803. The processor 1801, memory 1802, and communication component 1803 are connected via a bus.
[0176] In a specific implementation, at least one processor 1801 executes computer execution instructions stored in memory 1802, causing at least one processor 1801 to perform the above-described method.
[0177] The specific implementation process of processor 1801 can be found in the above method embodiments, and its implementation principle and technical effect are similar, so it will not be repeated here.
[0178] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microcontroller (MCU) or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0179] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0180] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0181] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0182] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0183] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0184] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0185] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0186] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0187] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0188] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0189] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0190] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A storage array, characterized in that, include: A multi-column storage unit, each column of which includes an input unit, an intermediate result unit, and an output unit; The input unit is used to store input data for in-memory calculation, the intermediate result unit is used to store intermediate result data obtained by calculating the input data, and the output unit is used to store in-memory calculation result data obtained by calculating the input data and the intermediate result data. The input unit, the intermediate result unit, and the output unit are each connected to different source lines.
2. The storage array according to claim 1, characterized in that, The source lines include a first source line, a second source line, and a third source line; The input unit is connected to the first source line, the intermediate result unit is connected to the second source line, and the output unit is connected to the third source line.
3. The storage array according to claim 1, characterized in that, Each pair of adjacent memory cells shares the source line.
4. The storage array according to any one of claims 1-3, characterized in that, The input unit includes at least one storage unit, the intermediate result unit includes at least one storage unit, and the output unit includes at least one storage unit.
5. The storage array according to claim 2, characterized in that, During the process of calculating the intermediate result data from the input data, the read line of the input unit is valid, the write line of the intermediate result unit is valid, the first source line is connected to the first logic level, and the second source line is grounded, so as to write the intermediate result data into the intermediate result unit.
6. The storage array according to claim 2, characterized in that, During the process of calculating the in-memory calculation result data by processing the input data and the intermediate result data, the read word line of the input unit is valid, the read word line of the intermediate result unit is valid, the write word line of the output unit is valid, the first source line is connected to the second logic level, the second source line is connected to the second logic level, and the third source line is grounded, so as to write the in-memory calculation result data into the output unit.
7. The storage array according to any one of claims 1-3, characterized in that, The storage unit includes a magnetic storage device, which is a spin-orbit moment magnetic storage device or a spin-transfer moment magnetic storage device.
8. The storage array according to any one of claims 1-3, characterized in that, Each column of storage cells is connected to multiple bit lines.
9. An in-memory computation method, characterized in that, Applied to the storage array as described in any one of claims 1-8, the method comprises: The system controls the read line of the input unit to be valid, the write line of the intermediate result unit to be valid, and controls the source line connected to the input unit to be connected to the first logic level and the source line connected to the intermediate result unit to be grounded, so as to write the intermediate result data obtained by calculating the input data into the intermediate result unit. The system controls the read line of the input unit to be active, the read line of the intermediate result unit to be active, and the write line of the output unit to be active. It also controls the source line connected to the input unit to be connected to the second logic level, the source line connected to the intermediate result unit to be connected to the second logic level, and the source line connected to the output unit to be grounded, so as to write the in-memory calculation result data obtained by calculating the input data and the intermediate result data into the output unit.
10. The in-memory calculation method according to claim 9, characterized in that, A column of storage cells in the storage array performs the method as described in claim 9 to implement any one of the following operations: XOR, XOR, and addition; and / or, The multiple columns of storage cells in the storage array perform the in-memory computation method as described in claim 9 to achieve convolution operations.