Semiconductor device

Abstract

A semiconductor device includes memory cell groups connected to a word line, a bit line, and a plate line, each memory cell group including first and second switching elements, and a capacitor connected to the first switching element and including a ferroelectric layer, the second switching element is connected between a first node between the first switching element and the capacitor and a second node supplying a predetermined voltage. In each of the memory cell groups, capacitors are connected to different board lines. A turn-on voltage is applied to a selected word line connected to the selected memory cell group, and a first switching element included in the selected memory cell group is turned on. When the selected memory cell groups are activated, a predetermined voltage is applied to unselected plate lines connected to the unselected memory cell groups, and second switching elements included in each of the unselected memory cell groups are turned on.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0128238, filed on September 23, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The present invention relates to semiconductor devices. Background Technology

[0004] Semiconductor devices provide the functionality to write data to and erase data from memory cells, or to read written data from memory cells, and memory cells can be written to in various ways. Recently, ferroelectric random access memory (FeRAM) including a ferroelectric layer has been proposed as a semiconductor device capable of writing data. Such FeRAM possesses the advantage of maintaining data non-volatility even when the power is off, while also operating at high speed. FeRAM writes data by changing the polarization state of the ferroelectric layer, and therefore, controlling the polarization state of the ferroelectric layer can significantly affect the performance of FeRAM. Summary of the Invention

[0005] The example embodiment provides a semiconductor device that has improved reliability and performance by blocking the coupling effect between selected and unselected board lines by applying the same voltage to the respective electrodes of a capacitor connected to an unselected word line.

[0006] According to an example embodiment, a semiconductor device includes: a cell region providing memory cell groups connected to word lines, bit lines, and board lines, each of the memory cell groups including a first switching element, a second switching element, and a capacitor connected to the first switching element and including a ferroelectric layer, the second switching element being connected between a first node between the first switching element and the capacitor and a second node supplying a predetermined voltage; and a peripheral circuit region controlling the control region via the word lines, bit lines, and board lines. In each of the memory cell groups, the capacitor is connected to different board lines. The peripheral circuit region applies an on-state voltage to a selected word line of a selected memory cell group connected to the selected memory cell group, and turns on the first switching element included in the selected memory cell group. When the selected memory cell group is activated, the peripheral circuit region applies the predetermined voltage to unselected board lines connected to unselected memory cell groups other than the selected memory cell group, and turns on the second switching element included in each of the unselected memory cell groups.

[0007] According to an example embodiment, a semiconductor device includes: a first region including a plurality of memory cell groups, each of the plurality of memory cell groups including a first switching element, a second switching element, and a plurality of capacitors including a ferroelectric layer; and a second region including a plurality of word line driving circuits, a plurality of sense amplifier circuits, and a plurality of board line drivers. The first region includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction perpendicular to the first direction, and a plurality of board lines. The plurality of board lines are disposed on the plurality of word lines, the plurality of bit lines, and the second switching element in a third direction perpendicular to the first and second directions, and are stacked in the third direction. In each of the memory cell groups, a plurality of capacitors penetrate the plurality of board lines in the third direction, and the capacitors are connected to the plurality of board lines that are different from each other. The second switching element is connected to a voltage source located between the first switching element and the plurality of capacitors and is set to a predetermined voltage.

[0008] According to an example embodiment, a semiconductor device includes: a plurality of word lines; a plurality of bit lines; a plurality of board lines; and a plurality of memory cell groups connected to the plurality of word lines, the plurality of board lines, and the plurality of bit lines. Each of the plurality of memory cell groups includes a first switching element, a second switching element, and a plurality of capacitors connected to the first switching element and including a ferroelectric layer. In each of the plurality of memory cell groups, the first switching element is connected to one of the word lines and one of the bit lines, the plurality of capacitors are connected to a plurality of board lines that are different from each other, and the second switching element is connected between the first switching element and the plurality of capacitors. Attached Figure Description

[0009] The above and other aspects, features and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is simply a block diagram illustrating a semiconductor device according to an example embodiment;

[0011] Figure 2 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment;

[0012] Figure 3 This is simply a circuit diagram illustrating memory cells included in an array of memory cells according to an example embodiment;

[0013] Figure 4 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment;

[0014] Figure 5 It is shown Figure 4 A diagram illustrating the operation of the memory cell array in the example embodiment shown;

[0015] Figure 6 This is a diagram illustrating the characteristics of a memory cell included in a semiconductor device according to an example embodiment;

[0016] Figure 7 and Figure 8 This is a diagram illustrating programming operations of a semiconductor device according to an example embodiment;

[0017] Figure 9 This is a diagram illustrating a read operation of a semiconductor device according to an example embodiment;

[0018] Figure 10 This is simply a diagram illustrating an array of memory cells included in a semiconductor device according to an example embodiment;

[0019] Figure 11 It is shown Figure 10 A diagram illustrating the operation of the memory cell array in the example embodiment shown;

[0020] Figure 12 This is a diagram illustrating an array of memory cells included in a semiconductor device according to an example embodiment;

[0021] Figure 13 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0022] Figure 14 It is shown Figure 13 A cross-sectional view of the semiconductor device along the I-I' direction; and

[0023] Figure 15 It is shown Figure 13 The cross-sectional view of the semiconductor device in the II-II' direction is shown in the figure. Detailed Implementation

[0024] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. The same reference numerals throughout refer to the same elements.

[0025] Figure 1 This is a simple block diagram illustrating a semiconductor device according to an example embodiment.

[0026] Reference Figure 1The semiconductor device 10 according to the example embodiment can be a storage device based on semiconductor elements. The semiconductor device 10 can be a random access memory (RAM) device and can be used as main memory in electronic devices such as desktop computers, laptop computers, tablet PCs, and smartphones. The semiconductor device 10 can store data received as a data signal (DQ) in response to address signals and control command signals received from an external host (e.g., a central processing unit (CPU), application processor (AP), system-on-a-chip (SoC), etc.), or it can read the stored data and output the read data as a data signal (DQ).

[0027] The semiconductor device 10 may also include a cell region 20, a peripheral circuit region 30, etc. The cell region 20 includes multiple memory cells, and the multiple memory cells can form a memory cell array. The peripheral circuit region 30 may include a word line driving circuit 31, a board line driving circuit 32, a sense amplifier circuit 33, a data input / output circuit 34, control logic 35, etc., and can control the control unit region 20.

[0028] Multiple memory cells included in cell region 20 can be connected to word lines WL, bit lines BL, and board lines PL to form a memory cell array. These memory cells can be connected to word line driver circuit 31 via word line WL and to board line driver circuit 32 via board line PL. Simultaneously, the multiple memory cells are connected to sense amplifier circuit 33 via bit line BL, and sense amplifier circuit 33 can perform programming operations, read operations, etc., via bit line BL. The multiple memory cells can be located at the intersection points of word line WL and bit line BL.

[0029] Each of the plurality of memory cells may include a first switching element and a capacitor connected to the first switching element, and the capacitor may include electrodes and a ferroelectric layer. In an example embodiment, the plurality of memory cells may respectively form a plurality of memory cell groups. Each of the plurality of memory cell groups may include a first switching element, a capacitor, and a second switching element connected between the first switching element and the capacitor. The capacitor may share the first switching element. Among the electrodes included in the capacitor, the first electrode may be connected to the first switching element and the second switching element, and the second electrode may be connected to a plate line (PL).

[0030] Simultaneously, each of the first and second switching elements can be implemented as a transistor. The gate of the first switching element can be connected to the word line WL, one of the source / drain regions of the first switching element can be connected to the first electrode of a capacitor, and the other of the source / drain regions of the first switching element can be connected to the bit line BL. The gate of the second switching element can be connected to the second switching control line, one of the source / drain regions of the second switching element can be connected to a voltage source set to a predetermined voltage, and the other of the source / drain regions of the second switching element can be connected to the first electrode of a capacitor. The peripheral circuit region 30 can record data by changing the polarization state and polarization degree of the ferroelectric layer included in the capacitor included in the memory cell group.

[0031] Control logic 35 can receive address signals and control command signals from an external host. The address signals may include row addresses indicating rows in the memory cell array of cell region 20 and column addresses indicating columns in the memory cell array. For example, word line driver circuit 31 can determine the selected word line among multiple word lines WL by referring to the row address, and board line driver circuit 32 and sense amplifier circuit 33 can determine the selected board line and selected bit line by referring to the column address.

[0032] The sense amplifier circuit 33 may include multiple sense amplifiers connected to the cell region 20 via multiple bit lines BL. For example, when performing a read operation, a sense amplifier connected to a selected bit line can read data from a selected capacitor connected to the selected bit line. The data input / output circuit 34 can output the data read by the sense amplifier as a data signal (DQ).

[0033] Simultaneously, during programming, a predetermined programming voltage can be applied to selected bit lines and selected board lines connected to selected memory cells, while simultaneously turning on a first switching element included in the selected memory cell group and turning off a second switching element. Specifically, the predetermined programming voltage can be applied to selected bit lines and selected board lines connected to selected capacitors. In an example embodiment, the programming voltage is determined by the difference between the voltage applied to the selected board line and the voltage applied to the selected bit line, and the polarization of the ferroelectric layer included in the selected capacitor can be changed by the programming voltage. Polarization can be a concept encompassing the polarization direction and polarization degree of the ferroelectric layer.

[0034] In this way, the polarization of the ferroelectric layer included in the capacitor can be changed by the voltage applied to the capacitor. The polarization of the ferroelectric layer and the voltage applied to the capacitor can have a relationship defined by a hysteresis curve. When a specific voltage is continuously applied to the capacitor, the relationship between the voltage and the polarization expressed by the hysteresis curve can change, which can lead to a degrade in the characteristics of the memory cell and the performance of the semiconductor device 10.

[0035] A typical semiconductor device may not include a second switching element. In a typical semiconductor device, when the first switching element included in the selected memory cell group is turned on, a predetermined programming voltage can be applied to the selected bit line and selected board line connected to the selected memory cell, and the selected memory cell is connected to the selected capacitor. At this time, when the first switching element included in the unselected memory cell group is turned off, the unselected bit line and / or unselected board line can be floated.

[0036] In typical semiconductor devices, electrical interference can occur due to coupling effects between selected board lines and adjacent unselected board lines. Specifically, this coupling effect can lead to unexpected voltage differences between the electrodes of unselected capacitors connected to unselected board lines. Consequently, data stored in the unselected capacitors may be corrupted or altered, and leakage current may occur within the unselected capacitors, potentially degrading the performance and reliability of the semiconductor device.

[0037] The semiconductor device 10 of the example embodiment can reduce the coupling effect between selected board lines and adjacent unselected board lines by including a second switching element. Specifically, the first switching element can be turned off and the second switching element can be turned on to apply a predetermined voltage from a voltage source to the first electrode of the unselected capacitor. By applying the predetermined voltage equally to the unselected board lines, the predetermined voltage can also be applied to the second electrode of the unselected capacitor, thereby achieving control to prevent a voltage difference between the electrodes of the unselected capacitor.

[0038] The semiconductor device 10 in the example embodiment can prevent data stored in unselected capacitors from being corrupted or altered. Furthermore, by preventing leakage current in unselected capacitors, performance degradation of the semiconductor device 10 can be minimized, thereby improving reliability.

[0039] Figure 2 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment. Figure 3 This is simply a circuit diagram illustrating memory cells included in a memory cell array according to an example embodiment.

[0040] First, refer to Figure 2The memory cell array 40 according to the example embodiment may include a plurality of memory cells MC connected to a plurality of word lines (WL1-WLm: WL), a plurality of board lines (PL1-PLm: PL), and a plurality of bit lines (BL1-BLn: BL). The number of the plurality of word lines WL, the plurality of board lines PL, the plurality of bit lines BL, and the plurality of memory cells MC may vary depending on the example embodiment. The plurality of memory cells MC may be located at the intersection of the plurality of word lines WL, the plurality of board lines PL, and the plurality of bit lines BL.

[0041] As referenced above Figure 1 As described, multiple word lines WL can be connected to word line driver circuits (e.g., word line driver circuit 31), multiple board lines PL can be connected to board line driver circuits (e.g., board line driver circuit 32), and multiple bit lines BL can be connected to sense amplifier circuits (e.g., sense amplifier circuit 33). When the selected word line selected by the word line driver circuit and the selected board line selected by the board line driver circuit are determined, programming operations, read operations, restore operations, etc., can be performed on the selected memory cells connected to the selected word line and the selected board line. The multiple bit lines BL are respectively connected to different sense amplifiers included in the sense amplifier circuit, and therefore, the selected memory cells can be controlled individually.

[0042] Reference Figure 3 The memory cell MC included in the semiconductor device according to the example embodiment may include a first switching element SW1, a second switching element SW2, and a capacitor CC.

[0043] The first switching element SW1 can be implemented as a transistor, and its gate can be connected to the word line WL. Simultaneously, one of the source / drain regions of the first switching element SW1 can be connected to the bit line BL, and the other can be connected to the capacitor CC. The capacitor CC may include a ferroelectric layer and can be connected to the board line PL.

[0044] The second switching element SW2 can be implemented as a transistor. The gate of the second switching element can be connected to the second switching control line SG2, one of the source / drain regions of the second switching element can be connected to a voltage source set to a predetermined voltage VS, and the other of the source / drain regions of the second switching element can be connected to a capacitor CC.

[0045] When a memory cell MC of a semiconductor device is selected via an address signal received from an external host or similar source, the first switching element SW1 can be turned on by applying a voltage to the word line WL, and the second switching element SW2 can be turned off by applying a voltage to the second switch control line SG2. For example, the voltage applied to the second switch control line SG2 may have a phase opposite to that applied to the word line WL. Specifically, the second switching element SW2 may be turned off or on simultaneously with turning the first switching element SW1 on / off. However, the phase of the voltage is not limited to this.

[0046] Then, programming operations can be performed to change the polarization of capacitor CC by applying voltage to each of bit lines BL and PL, and read operations can be performed to read and write data to memory cell MC by determining the polarization of capacitor CC. Programming and read operations will be described later.

[0047] In the example embodiment, multiple memory cells MC can be formed into memory cell groups. Hereinafter, reference will be made to... Figure 4 and Figure 5 The memory cell group and its operation are described in detail.

[0048] Figure 4 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment. Figure 5 It is shown Figure 4 A diagram illustrating the operation of the memory cell array of the example embodiment shown.

[0049] First, refer to Figure 4 The memory cell array 100 according to the example embodiment may include a plurality of memory cell groups (MCGs) connected to a plurality of word lines WL1 to WL2, a plurality of board lines PL1 to PLm and a plurality of bit lines BL1 to BL2.

[0050] exist Figure 4 In the example embodiment shown, the memory cell group (MCG) may include a first switching element SW1, a second switching element SW2, and a plurality of capacitors CC. Each of the plurality of capacitors CC may include a ferroelectric layer and may be connected to the first switching element SW1. Specifically, the plurality of capacitors CC may share the first switching element SW1. Therefore, each of the plurality of capacitors CC, the first switching element SW1, and the second switching element SW2 can perform the above-described... Figure 3 The role of a single memory unit (MC) as described in the text.

[0051] The second switching element SW2 can be connected between a first node N1 (between the first switching element SW1 and multiple capacitors CC) and a second node N2 (supplying a predetermined voltage VS). The second switching element SW2 can be connected to a second switching control line SG2. For example, each memory cell group (MCG) can be connected to a different second switching control line SG2. The second node N2 can be connected to a voltage source set with the predetermined voltage VS. When the second switching element SW2 is turned on by the second switching control line SG2, the predetermined voltage VS can be applied to the second node N2.

[0052] As Figure 4 In the illustrated example embodiment, m capacitors CC can be connected to a first switching element SW1, which is connected to the first bit line BL1 and the first word line WL1. The m capacitors CC can be connected to different board lines PL1 to PLm. For example, the m capacitors CC connected to the first switching element SW1 can be matched one-to-one with multiple board lines PL1 to PLm. Therefore, the polarization of multiple corresponding capacitors CC sharing a single first switching element SW1 can be controlled individually.

[0053] refer to Figure 5 , will describe Figure 4 The operation of the memory cell array 100 in the example embodiment shown is illustrated. Selected memory cells may correspond to memory cells targeted as either programming operations for recording data in a semiconductor device or reading operations for retrieving recorded data. Selected memory cells may include selected capacitors.

[0054] exist Figure 5 In the example embodiment shown, the selected capacitors can be the 21st and 22nd capacitors CC21_m and CC22_m, and the selected memory cell groups can be the 21st and 22nd memory cell groups MCG21 and MCG22, respectively, including the selected capacitors CC21_m and CC22_m. The second word line WL2 connected to the selected memory cell groups MCG21 and MCG22 can be a selected word line, and the plurality of bit lines BL1 to BL2 connected to the selected memory cell groups MCG21 and MCG22 can be selected bit lines. Among the plurality of board lines PL1-PLm, the selected board line connected to the selected capacitors CC21_m and CC22_m can be a single line as the m-th board line PLm.

[0055] For example, the first switching element SW1 of the selected memory cell groups MCG21 and MCG22 connected to the selected word line WL2 can be turned on by applying a voltage to the selected word line WL2. The second switching element SW2 of the selected memory cell groups MCG21 and MCG22 can be turned off by applying a voltage to the second switch control line SG2. In the state where the first switching element SW1 of the selected memory cell groups MCG21 and MCG22 is turned on and the second switching element SW2 is turned off, the polarization of the selected capacitors CC21_m and CC22_m connected only to the selected board line (PLm) is changed by the voltage applied to the selected bit lines BL1 to BL2 and the selected board line (PLm), so that the selected capacitors CC21_m and CC22_m can be activated.

[0056] To selectively change the polarization of the selected capacitors CC21_m and CC22_m connected to the selected board line (PLm), a selection voltage can be applied to the m-th board line PLm connected to the selected memory cell group MCG21 and MCG22, and the first board lines PL1 to the (m-1)-th board lines PLm-1 connected to the selected memory cell group MCG21 and MCG22 can be floated. In this case, the selection voltage applied to the m-th board line PLm can be the same as or different from the voltage applied to the selected bit lines BL1 to BL2.

[0057] Besides the selected memory cell groups MCG21 and MCG22, the 11th and 12th memory cell groups MCG11 and MCG12 can be unselected memory cell groups, and the capacitors included in the unselected memory cell groups MCG11 and MCG12 can be unselected capacitors. The first word line WL1 connected to the unselected memory cell groups MCG11 and MCG12 can be an unselected word line, and the first board lines PL1 to the m-th board line PLm connected to the unselected memory cell groups MCG11 and MCG12 can correspond to unselected board lines.

[0058] While activating the selected capacitors CC21_m and CC22_m, the first switching element SW1 of the unselected memory cell groups MCG11 and MCG12 can be turned off because no voltage is applied to the unselected word line WL1. The second switching element SW2 of the selected memory cell groups MCG21 and MCG22 can be turned on by applying a voltage to the second switch control line SG2. Accordingly, since a predetermined voltage VS is applied to the second node N2, the predetermined voltage VS can be applied to one of the electrodes of the unselected capacitor. Additionally, by applying the predetermined voltage VS to the unselected board lines PL1 to PLm connected to the unselected memory cell groups MCG11 and MCG12, the predetermined voltage VS can also be applied to the other electrode of the unselected capacitor.

[0059] For example, the predetermined voltage VS can be lower than the voltage applied to the selected word line WL2. Specifically, the predetermined voltage VS can be 0V, but the magnitude of the predetermined voltage VS is not limited to this.

[0060] According to an example embodiment, a predetermined voltage VS can be applied to each of the electrodes of the unselected capacitor, such that no voltage difference occurs between the electrodes of the unselected capacitor. Therefore, the coupling effect between the selected plate line (PLm) and the adjacent unselected plate lines PL1 to PLm can be reduced, thereby preventing data stored in the unselected capacitor from being corrupted or altered and preventing leakage current from occurring in the unselected capacitor.

[0061] The polarization of the ferroelectric layer changes depending on the voltage applied to the capacitor, and, for example, the relationship between voltage and polarization can be represented as a hysteresis curve. This will be referenced below. Figure 6 To describe in more detail.

[0062] Figure 6 This is a diagram illustrating the characteristics of a memory cell included in a semiconductor device according to an example embodiment.

[0063] Figure 6 This could be a graph showing the relationship between the voltage applied to a memory cell and the polarization of the ferroelectric layer included in the memory cell. For example... Figure 6 As shown, the relationship between the voltage applied to the memory cell and the polarization of the ferroelectric layer included in the memory cell can be expressed as a hysteresis curve.

[0064] refer to Figure 6 The graph shown illustrates that, under the condition that a positive voltage is applied to the memory cell, the polarization of the ferroelectric layer can increase in a specific direction along the first curve CV1. At this time, the positive voltage at which the polarization of the ferroelectric layer saturates can be the first programming voltage VPGM1. For example, a positive voltage can be applied to the memory cell by setting the voltage of the board line connected to the memory cell to be higher than the voltage of the bit line connected to the memory cell. The polarization of the ferroelectric layer can be changed by the positive voltage applied to the memory cell. Afterwards, even if the voltage applied to the memory cell is blocked, the polarization of the ferroelectric layer can be maintained as positive polarization (P+).

[0065] On the other hand, when a negative voltage is applied to the memory cell, the polarization of the ferroelectric layer can change from positive polarization (P+) to different directions along the second curve CV2. At this time, the negative voltage that saturates the polarization of the ferroelectric layer can be the second programming voltage VPGM2. A negative voltage can be applied to the memory cell by setting the voltage of the board line connected to the memory cell to be lower than the voltage of the bit line connected to the memory cell. The polarization of the ferroelectric layer included in the memory cell is reduced to negative polarization (P-) by the negative voltage, and the negative polarization (P-) can be maintained as is even if the voltage applied to the memory cell is blocked.

[0066] In this way, data can be written to a memory cell by changing the polarization of the ferroelectric layer to either the negative or positive direction. For example, the state of changing the polarization of the ferroelectric layer to the negative direction can be defined as the state of writing the first data to the memory cell, and the state of changing the polarization of the ferroelectric layer to the positive direction can be defined as the state of writing the second data to the memory cell. Assuming that 1 bit of data is written to the memory cell, one of the first data and the second data can correspond to "0", and the other can correspond to "1".

[0067] In an example embodiment, a read operation on a memory cell can be performed by applying a read voltage, which is a positive voltage, to the memory cell while simultaneously turning on a first switching element included in the memory cell. For example, in the case of writing first data to a memory cell, since the ferroelectric layer has positive polarization (P+), the polarization of the ferroelectric layer is hardly changed by the read voltage, which is a positive voltage. Therefore, the voltage of the capacitor including the ferroelectric layer may be detected as relatively small.

[0068] On the other hand, in the case of a memory cell that records second data, since the ferroelectric layer has negative polarization (P-), the polarization of the ferroelectric layer changes relatively significantly by means of a read voltage that is a positive voltage, and the voltage of the capacitor can be detected relatively significantly during the read operation.

[0069] During a read operation, the voltage of a capacitor is detected from the bit line connected to the memory cell, and the capacitor voltage can be determined based on the difference between the polarization of the ferroelectric layer of the memory cell before the read operation and the polarization of the ferroelectric layer by the read voltage applied to the memory cell.

[0070] To perform the programming and reading operations on the selected memory cell, a voltage can be applied to the selected board line to activate it. The voltage applied to the selected board line can cause a coupling effect between the selected board line and an adjacent unselected board line. This coupling effect may cause abnormal voltages in the unselected memory cell, potentially affecting the data in that cell.

[0071] For example, a positive voltage can be applied to an unselected memory cell that maintains negative polarization (P-) through coupling effects. The polarization of the ferroelectric layer included in the unselected memory cell can increase to positive polarization (P+), thereby altering the recorded data. As another example, a negative voltage can be applied to an unselected memory cell that maintains positive polarization (P+) through coupling effects. The polarization of the ferroelectric layer included in the unselected memory cell may decrease, leading to charge leakage.

[0072] In an example embodiment, when a selected memory cell is activated, the voltage applied to an unselected memory cell can be maintained within the unselected range (USRG). Figure 6 In the example embodiment shown, the maximum value of the unselected range (USRG) is a first threshold voltage VC1, and the first threshold voltage VC1 can be a positive voltage. The minimum value of the unselected range (USRG) is a second threshold voltage VC2, and the second threshold voltage VC2 can be a negative voltage.

[0073] For example, the magnitudes of the first programming voltage VPGM1 and the second programming voltage VPGM2 can be the same, and they can be opposite in polarity only. The first threshold voltage VC1 can correspond to half of the first programming voltage VPGM1, and the second threshold voltage VC2 can correspond to half of the second programming voltage VPGM2. Specifically, the magnitudes of the first threshold voltage VC1 and the second threshold voltage VC2 can be the same, and they can be opposite in polarity only.

[0074] Figure 7 and Figure 8 This is a diagram illustrating the programming operation of a semiconductor device according to an example embodiment.

[0075] First, refer to Figure 7 , Figure 7 This could be a diagram illustrating a programming operation for writing first data into a memory cell MC. In the programming operation for recording the first data, a first switching element SW1 can be turned on by applying a voltage to the word line WL, and a second switching element SW2 can be turned off by applying a voltage to the second switch control line SG2. With the first switching element SW1 on, a first bias voltage VBIAS1 can be applied to the bit line BL, and a second bias voltage VBIAS2 can be applied to the board line PL. The second bias voltage VBIAS2 is greater than the first bias voltage VBIAS1, and the first bias voltage VBIAS1 can be a reference voltage such as ground.

[0076] The difference between the first bias voltage VBIAS1 and the second bias voltage VBIAS2 is defined as the first programming voltage VPGM1, and the first programming voltage VPGM1 can be a positive voltage. (Reference) Figure 6 The diagram shows the hysteresis curve of the memory cell MC, including the polarization of the ferroelectric layer in the capacitor CC, which can be changed to positive polarization (P+) by a first programming voltage VPGM1. Even after the voltage supply to each of the board line PL and bit line BL is cut off, the polarization of the ferroelectric layer remains positive (P+), and the first data written to the memory cell MC can be maintained.

[0077] refer to Figure 8 , Figure 8 This could be a diagram illustrating a programming operation for writing second data into a memory cell MC. In the programming operation for writing the second data, the first switching element SW1 can be turned on by applying a voltage to the word line WL, and the second switching element SW2 can be turned off by applying a voltage to the second switch control line SG2. A first bias voltage VBIAS1 can be applied to the board line PL, and a second bias voltage VBIAS2 can be applied to the bit line BL. (Refer to reference...) Figure 7 As in the example described, the second bias voltage VBIAS2 is greater than the first bias voltage VBIAS1, and the first bias voltage VBIAS1 can be a reference voltage such as ground voltage.

[0078] The difference between the first bias voltage VBIAS1 and the second bias voltage VBIAS2 is defined as the second programming voltage VPGM2, and the second programming voltage VPGM2 can be a negative voltage. For example, the first programming voltage VPGM1 and the second programming voltage VPGM2 can have the same amplitude, but their polarities can be opposite to each other.

[0079] Refer to the hysteresis curve of the memory cell MC. Figure 6 The polarization of the ferroelectric layer, including in capacitor CC, can be changed from positive polarization (P+) to negative polarization (P-) by a second programming voltage VPGM2. Even after the voltage supply to each of the board line PL and bit line BL is cut off, the polarization of the ferroelectric layer remains negative polarization (P-), and the second data written to the memory cell MC can be maintained.

[0080] Figure 9 This is a diagram illustrating a read operation of a semiconductor device according to an example embodiment.

[0081] Specific embodiments of semiconductor devices can be similar to those described above. Figures 1 to 8 Those described in [the text]. See [the text]. Figure 9 The read operation may include the activation period ACT, the charge sharing period CS, the sensing period RD, the write period RW, and the precharge period PRECH.

[0082] First, during the activation period ACT, an on-state voltage VPP can be input to the selected word line WL connected to the selected memory cell group, causing the first switching element included in the selected memory cell group to be turned on. The second switching element can be turned off by applying a voltage to the second switch control line connected to the selected memory cell group. Therefore, the selected memory cell group can be activated. For example, when the on-state voltage VPP is applied to the selected word line WL, the voltage applied to the second switch control line can have a voltage corresponding to a logic low, thereby turning off the second switching element.

[0083] Subsequently, during the charge-sharing period CS, a second voltage VINTA can be input to the selected board line PL connected to the selected memory cell. The selected bit line BL connected to the selected group of memory cells can be floated during a portion of the sharing period CS. At this time, the selected memory cell can correspond to the selected capacitor among the first switching element, the second switching element, and the capacitor, and the selected board line PL can be a line connected to the selected capacitor.

[0084] In an example embodiment, the first voltage VSS can be ground voltage, and the second voltage VinTA can be greater than the first voltage VSS and less than the turn-on voltage VPP. A positive voltage is applied to the selected memory cell through the first voltage VSS and the second voltage VinTA, and the polarization of the selected capacitor can be set to positive polarization.

[0085] During the sensing period RD, the voltage of the selected capacitor, to which the first voltage VSS and the second voltage VINTA are applied, can be detected by the sensing amplifier from the selected bit line BL. For example, assuming that the first data D0 is written to the selected memory cell before the start of the read operation, the polarization of the selected capacitor hardly changes during the charge sharing period CS, and therefore, the voltage of the selected bit line BL may hardly change from the first voltage VSS.

[0086] On the other hand, assuming that the second data D1 is written to the selected memory cell before the read operation begins, during the charge sharing period CS, the polarization of the selected capacitor changes from negative to positive, so the voltage of the selected bit line BL may rise relatively significantly. The sensing amplifier can amplify the voltage of the selected bit line BL during the sensing period RD and compare the amplified voltage with a reference voltage.

[0087] exist Figure 9In the example embodiment shown, the reference voltage compared to the voltage of the selected bit line BL can be an intermediate voltage VMID. If the voltage of the selected bit line BL is lower than the reference voltage, the data of the selected memory cell can be read as first data D0, and if the voltage of the selected bit line BL is higher than the reference voltage, the data of the selected memory cell can be read as second data D1.

[0088] When reading data from a selected memory cell, the voltage of the selected board line PL can be reduced to a first voltage VSS. Subsequently, a write operation to recover the data of the selected memory cell changed during the charge-sharing period CS can be performed during the write period RW. The data of the selected memory cell can be changed to the first data D0 by applying a positive voltage to the selected memory cell during the charge-sharing period CS.

[0089] Therefore, as Figure 9 As shown, if the data of the selected memory cell is read as first data D0, a separate write operation is not required. On the other hand, if the data of the selected memory cell is read as second data D1, the second data D1 can be written again to the selected memory cell where the first data D0 was written during the charge-sharing period CS by maintaining the voltage of the selected bit line BL at the second voltage VINTA during the write period RW. When the write period RW ends, the operation of reducing the voltage of the selected bit line BL to the first voltage VSS can be performed during the precharge period PRECH.

[0090] Figure 10 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment. Figure 11 It is shown Figure 10 A diagram illustrating the operation of the memory cell array in the example embodiment.

[0091] First, refer to Figure 10 The memory cell array 200 according to the example embodiment may include a plurality of memory cell groups connected to a plurality of word lines WL1 to WL2, a plurality of board lines PL1 to PLm and a plurality of bit lines BL1 to BL2.

[0092] The memory cell group (MCG) may include a first switching element SW1, a second switching element SW2, and multiple capacitors CC, each including a ferroelectric layer. The second switching element SW2 may be connected between a first node N1 (between the first switching element SW1 and the multiple capacitors CC) and a second node N2 (supplying a predetermined voltage VS). The second switching element SW2 may be connected to a second switching control line SG2 to which the predetermined voltage VS is applied.

[0093] Specific embodiments of the memory cell array 200 can be similar to those described above. Figure 4 and Figure 5 The embodiments described herein.

[0094] Compare Figure 4 and Figure 10 The arrangement of multiple board lines PL1~PLm, multiple word lines WL1~WL2, and multiple bit lines BL1~BL2 can be different. Figure 4 In the memory cell array 100 of the illustrated example embodiment, multiple board lines PL1 to PLm can be parallel to multiple word lines WL1 to WL2 and perpendicular to multiple bit lines BL1 to BL2. On the other hand, in Figure 10 In the memory cell array 200 of the example embodiment shown, multiple board lines PL1 to PLm can be parallel to multiple bit lines BL1 to BL2 and perpendicular to multiple word lines WL1 to WL2.

[0095] refer to Figure 11 , will describe Figure 10 The operation of the memory cell array 200 in the example embodiment shown. Figure 11 In the example embodiment shown, the selected capacitors may be the 21st and 22nd capacitors CC21_m and CC22_m, and the selected memory cell groups may be the 21st and 22nd memory cell groups MCG21 and MCG22, which include the selected capacitors CC21_m and CC22_m. The second word line WL2 connected to the selected memory cell groups MCG21 and MCG22 is the selected word line, and the plurality of bit lines BL1 to BL2 connected to the selected memory cell groups MCG21 and MCG22 may be selected bit lines.

[0096] Compare Figure 5 and Figure 11 The number of board wires connected to the selected capacitors CC21_m and CC22_m may differ. Figure 5 In the example embodiment shown, the selected capacitors CC21_m and CC22_m can be connected to the same m-th board line PLm. Specifically, the selected board line can be a single line. On the other hand, in Figure 11 In the example embodiment shown, the selected capacitors CC21_m and CC22_m can be connected to different m-th board lines PLm. More specifically, there can be multiple board lines selected.

[0097] Besides the selected memory cell groups MCG21 and MCG22, the 11th and 12th memory cell groups MCG11 and MCG12 can be unselected memory cell groups, and the capacitors included in the unselected memory cell groups MCG11 and MCG12 can be unselected capacitors. The first word line WL1 connected to the unselected memory cell groups MCG11 and MCG12 can be an unselected word line.

[0098] Compare Figure 5 and Figure 11 Whether an unselected memory cell group is connected to a selected board line can differ. (See reference...) Figure 5 Unselected memory cell groups MCG21 and MCG22 may not be connected to the selected board line PLm. On the other hand, reference... Figure 11 Unselected memory cell groups MCG21 and MCG22 can be connected to different selected board lines PLm.

[0099] refer to Figure 5 and Figure 11 While activating the selected capacitors CC21_m and CC22_m, the second switching element SW2 of the unselected memory cell groups MCG11 and MCG12 can be turned on, allowing a predetermined voltage VS to be applied to one of the electrodes of the unselected capacitors. Therefore, no voltage difference may appear between the electrodes of the unselected capacitors. For example, the second switching element SW2 included in the unselected memory cell groups MCG21 and MCG22 can... Figure 9 It remains in the on state during the charge sharing period CS to the pre-charge period PRECH.

[0100] However, due to Figure 11 The unselected memory cell groups MCG21 and MCG22 are connected to different selected board lines PLm, so the amplitude of the predetermined voltage VS can be... Figure 5 The examples differ from those in the implementation examples.

[0101] first, Figure 5 The predetermined voltage VS in an example embodiment may be Figure 9 The first voltage VSS. Specifically, the predetermined voltage VS can be the ground voltage (0V). Included in... Figure 5 The second switching element SW2 in the unselected memory cell groups MCG21 and MCG22 can remain on while the selected capacitor is activated.

[0102] on the other hand, Figure 11In an example embodiment, the predetermined voltage VS can be a positive voltage, and more specifically, it can be equal to or less than the second voltage VINTA applied to the selected word line WL2. For example, the magnitude of the predetermined voltage VS can be half of the second voltage VINTA. However, the magnitude of the predetermined voltage VS is not limited to this.

[0103] Figure 12 This is a simple illustration of a memory cell array included in a semiconductor device according to an example embodiment.

[0104] First, refer to Figure 12 The memory cell array 300 according to the example embodiment may include a plurality of memory cell groups connected to a plurality of word lines WL1 to WL2, a plurality of board lines PL1 to PLm and a plurality of bit lines BL1 to BL2.

[0105] The memory cell group (MCG) may include a first switching element SW1, a second switching element SW2, and multiple capacitors CC, each including a ferroelectric layer. The second switching element SW2 may be connected between a first node N1 (between the first switching element SW1 and the multiple capacitors CC) and a second node N2 (supplying a predetermined voltage VS). The second switching element SW2 may be connected to a second switching control line SG2 to which the predetermined voltage VS is applied.

[0106] Will Figure 10 and Figure 12 Comparison, Figure 12 The memory cell array 300 of the illustrated example embodiment may further include a third switching element SW3. The third switching element SW3 may be implemented as a transistor. The third switching element SW3 may be connected between the first switching element SW1 and a plurality of capacitors. Specifically, the gate of the third switching element SW3 may be connected to one of the electrodes of the capacitor CC. One of the source / drain regions of the third switching element SW3 may be connected to ground, and another of the source / drain regions of the third switching element SW3 may be connected to a third switch control line SG3. For example, each memory cell group MCG may be connected to a different third switch control line SG3.

[0107] exist Figure 12 In the example embodiment shown, the third switch control line SG3 can correspond to the read bit line, and the bit line BL can correspond to the program bit line. The third switch control line SG3 is connected to the above... Figure 1 The sensing amplifier circuit 33 described herein, and Figure 1 The sensing amplifier circuit 33 can perform a read operation on the selected memory cell through the third switch control line SG3.

[0108] While performing a programming operation on the selected memory cell, the third switching element SW3 can be turned off by applying a voltage to the third switching control line SG3. At this time, the voltage applied to the third switching control line SG3 can be either low or high. While performing a read operation on the selected memory cell, a high-level voltage is applied to the third switching control line SG3, and the bit line BL can remain in a floating state. At this time, the sense amplifier circuit can detect the change in the voltage applied to the third switching control line SG3 and read the data written to the selected memory cell.

[0109] Figure 12 The operation of the first switching element SW1 and the second switching element SW2 in the example embodiment shown above can be the same as that described above. Figure 11 The operation described in the text is similar.

[0110] Figure 13 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 14 It is shown Figure 13 A cross-sectional view of the semiconductor device shown in the I-I' direction. Figure 15 It is shown Figure 13 The cross-sectional view of the semiconductor device in the II-II' direction is shown.

[0111] exist Figures 13 to 15 In the example embodiment shown, the semiconductor device 400 according to the example embodiment may include region A 400A and region B 400B.

[0112] Reference Figures 13 to 15 Region A 400A can correspond to a memory cell layer in which multiple memory cells are formed, and the memory cell layer can correspond to the above... Figure 5 and Figure 6 The memory cell array 100 described herein. Region B 400B may correspond to a core peripheral layer in which multiple sub-word line drivers, multiple sense amplifiers, etc., are formed in addition to multiple memory cells. For example, region B 400B may correspond to the above-described memory cell array 100. Figure 1 The peripheral circuit area 30 described herein may include word line driving circuit 31, board line driving circuit 32, sense amplifier circuit 33, data input / output circuit 34, control logic 35, etc., and may control the memory cell layer of area A 400A.

[0113] In region A 400A, an active region 403A, a gate structure 410A providing word lines, a bit line structure 420A connected to the active region 403A, a capacitor structure 440A, a plate line structure 450A, a second switching element SW2, etc., can be formed. The gate structure 410A may intersect with the active region 403A and the bit line structure 420A, and may be buried in the substrate 401A.

[0114] The gate structure 410A may include a gate electrode layer 411A, a capping layer 412A, etc. The gate electrode layer 411A may be formed of a conductive material such as a metal or a metal compound. The capping layer 412A may be formed of an insulating material such as silicon nitride. A gate insulating layer 405A may be disposed between the gate electrode layer 411A and the substrate 401A, and the gate insulating layer 405A may be formed of silicon oxide or the like.

[0115] The active region 403A may be doped with impurities and may provide source and drain regions for switching elements included in the memory cell. The active region 403A may be connected to the capacitor structure 440A via multiple interconnect patterns 493A and 494A.

[0116] A second switching element SW2 may be formed adjacent to the gate structure 410A. One of the source / drain regions of the second switching element SW2 may be connected to a second switching control line (not shown) via multiple interconnect patterns 493A and 494A. The other of the source / drain regions of the second switching element SW2 may be connected to the capacitor structure 440A and the active region 403A via multiple interconnect patterns 493A and 494A.

[0117] The bit line structure 420A can be buried in the intermediate insulating layer 430A and the insulating layer 470A. The bit line structure 420A may include a bit line conductive layer 421A, a bit line cover layer 422A and a spacer layer (not shown).

[0118] The board-line structure 450A may include a board-line conductive layer 452A, a board-line cover layer 454A, etc. The board-line conductive layer 452A may be formed of a conductive material such as a metal or a metal compound. The board-line cover layer 454A may be formed of an insulating material such as silicon nitride.

[0119] Region A 400A may include multiple board line structures 450A. Multiple board line structures 450A may be stacked in a third direction (Z-axis direction). Figure 14 and Figure 15 In the example embodiment shown, region A 400A may include four board line structures 450A stacked upwards on a third side. (Refer to...) Figure 13The four board line structures 450A stacked upwards on the third side can be arranged in the second direction (Y-axis direction). For example, the four board line structures 450A stacked upwards on the third side can be connected to the same memory cell group, and the board line structures 450A arranged in the second direction can be connected to different memory cell groups respectively.

[0120] The capacitor structure 440A can be connected to the active region 403A via multiple interconnect patterns 493A and 494A. The capacitor structure 440A may include a ferroelectric layer 442A, a dielectric layer 444A, etc. The capacitor structure 440A may extend upward on a third side perpendicular to the upper surfaces of the substrates 401A and 401B.

[0121] The ferroelectric layer 442A may include a ferroelectric material and may include at least one of hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), titanium (Ti), scandium (Sc), and their oxides. The dielectric layer 444A may include an insulating material and may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), high-k materials, or combinations thereof.

[0122] In region B 400B, a substrate 401B, multiple semiconductor elements TR formed on the substrate 401B, a B insulating layer 470B, and multiple interconnect patterns 493B and 494B formed in the B insulating layer 470B and connected to the multiple semiconductor elements TR can be formed. The multiple interconnect patterns 493B and 494B may include device contacts 493B and lower wiring 494B. The semiconductor elements TR can be configured with word line driving circuits, sense amplifier circuits, board line driving circuits, etc.

[0123] Reference Figures 13 to 15 Region A 400A and Region B 400B can be stacked on top of each other. Region A 400A can be stacked on top of Region B 400B. Therefore, Figure 13 The plan view of the semiconductor device 400 in the example embodiment shown may correspond to the plane of region A 400A. The semiconductor device 400 may have a chip-on-package (CoP) structure, but is not limited thereto.

[0124] In region A 400A, a board line structure 450A can be formed on the gate structure 410A, bit line structure 420A, and second switching element SW2 in a third-party orientation. At this time, a capacitor structure 440A can be formed in a third-party orientation to penetrate the board line structure 450A.

[0125] exist Figures 13 to 15In the illustrated example embodiment, the board line structure 450A and the gate structure 410A may extend in a first direction (X-axis direction). Specifically, the board line structure 450A and the gate structure 410A may overlap in a third direction. The bit line structure 420A may extend in a second direction.

[0126] In Figures 13 to 15 In another example, different from the illustrated embodiment, the board line structure and bit line structure may extend in a first direction, and the gate structure may extend in a second direction. Specifically, the board line structure and bit line structure may overlap in a third direction. This corresponds to the above example... Figure 10 and Figure 11 The memory cell array 200 described herein.

[0127] As described above, according to the example embodiment, by applying the same voltage to the corresponding electrode of the unselected capacitor connected to the unselected word line, the polarization of the unselected capacitor can be maintained within a predetermined range, thereby improving the reliability and performance of semiconductor devices such as those recording data.

[0128] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The cell region provides memory cell groups connected to word lines, bit lines and board lines. Each memory cell group includes a first switching element, a second switching element and a capacitor connected to the first switching element and including a ferroelectric layer. The second switching element is connected between a first node between the first switching element and the capacitor and a second node supplying a predetermined voltage. and The peripheral circuit area controls the cell area via the word lines, bit lines, and board lines. In each of the memory cell groups, the capacitor is connected to different plate lines. The peripheral circuit region applies a conduction voltage to the word line, which is connected to the selected word line of the selected memory cell group within the memory cell group, and activates the first switching element included in the selected memory cell group. When the selected memory cell group is activated, the peripheral circuit region applies the predetermined voltage to the unselected board lines connected to the unselected memory cell groups other than the selected memory cell group, and turns on the second switching element included in each of the unselected memory cell groups.

2. The semiconductor device according to claim 1, wherein, In the board line, the selected board line connected to the selected capacitor included in the selected memory cell group is a single line.

3. The semiconductor device according to claim 2, wherein, In each of the memory cell groups, the first switching element is connected to one of the word lines and one of the bit lines.

4. The semiconductor device according to claim 3, wherein, In the peripheral circuit region, when the selected memory cell group is activated, a first voltage is applied to the selected board line and the selected bit line among the word lines connected to the selected memory cell group, and a second voltage greater than the first voltage is applied to the selected board line, the second voltage is applied to the selected board line and the selected bit line, the first voltage is applied to the selected board line, and the second voltage is applied to the selected bit line.

5. The semiconductor device according to claim 1, wherein, In each of the memory cell groups, the second node is connected to a voltage source set to the predetermined voltage.

6. The semiconductor device according to claim 5, wherein, The predetermined voltage is a first voltage, and the first voltage is lower than the turn-on voltage.

7. The semiconductor device according to claim 6, wherein, The first voltage is 0V.

8. The semiconductor device according to claim 1, wherein, Each of the first and second switching elements is implemented as a transistor.

9. The semiconductor device according to claim 1, wherein, The peripheral circuit area includes a word line driving circuit, a sense amplifier circuit, and a board line driving circuit. The word line driving circuit includes a word line driver connected to the word line, the sense amplifier circuit includes a sense amplifier connected to the bit line, and the board line driving circuit includes a board line driver connected to the board line.

10. A semiconductor device, comprising: The first region includes multiple memory cell groups, each of which includes a first switching element, a second switching element, and multiple capacitors including ferroelectric layers; and The second region includes multiple word line driver circuits, multiple sense amplifier circuits, and multiple board line drivers. The first region includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction perpendicular to the first direction, and a plurality of board lines. The first switching element is connected to one of the plurality of word lines and one of the plurality of bit lines. The plurality of board lines are arranged on the plurality of word lines, the plurality of bit lines, and the second switching element in a third direction perpendicular to the first direction and the second direction, and are stacked in the third direction. In each of the plurality of memory cell groups, the plurality of capacitors extend through the plurality of board lines in a third-order direction, and the plurality of capacitors are connected to the plurality of board lines that are different from each other. The second switching element is connected to a voltage source located between the first switching element and the plurality of capacitors and is set to a predetermined voltage.

11. The semiconductor device according to claim 10, wherein, The plurality of plate lines extend in the first direction.

12. The semiconductor device according to claim 11, wherein, The plurality of board lines overlap with the plurality of letter lines in the third direction.

13. The semiconductor device according to claim 11, wherein, The predetermined voltage is 0V.

14. The semiconductor device according to claim 10, wherein, The plurality of plate lines extend in the second direction.

15. The semiconductor device according to claim 14, wherein, The plurality of board lines overlap with the plurality of bit lines in the third direction.

16. The semiconductor device according to claim 14, wherein, The predetermined voltage is a positive voltage.

17. A semiconductor device, comprising: Multiple character lines; Multiple bit lines; Multiple board lines; and Multiple memory cell groups are connected to the multiple word lines, the multiple board lines, and the multiple bit lines. Each of the plurality of memory cell groups includes a first switching element, a second switching element, and a plurality of capacitors connected to the first switching element and including ferroelectric layers. In each of the plurality of memory cell groups, the first switching element is connected to one of the plurality of word lines and one of the plurality of bit lines, the plurality of capacitors are connected to the plurality of board lines that are different from each other, and the second switching element is connected between the first switching element and the plurality of capacitors.

18. The semiconductor device according to claim 17, wherein, In each of the plurality of memory cell groups, the second switching element is connected to a voltage source set to a predetermined voltage.

19. The semiconductor device according to claim 17, wherein, Each of the plurality of memory cell groups further includes a third switching element connected between the first switching element and the plurality of capacitors.

20. The semiconductor device according to claim 19, wherein, In each of the plurality of memory cell groups, the third switching element is connected to ground voltage.

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