Memory device, memory control circuit, and read method
By introducing an auxiliary circuit into the memory control circuit to adjust the voltage drop signal to delay the pull-down time of the virtual bit line signal, the noise interference problem in the low-voltage operating range is solved, ensuring the accuracy of memory reads.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2026-03-24
AI Technical Summary
In the low-voltage operating range, memory devices are susceptible to noise interference, which can lead to operational errors, and existing technologies are unable to effectively address this issue.
By introducing auxiliary circuitry into the memory control circuitry, adjusting the voltage and pulse width of the voltage drop signal, and delaying the pull-down time of the virtual bit line signal, the enable signal switching time of the sense amplifier is enhanced, ensuring that the voltage difference between the bit line signal and the complementary bit line signal is sufficiently large.
It effectively reduces noise interference in the low-voltage operating range, ensures the accuracy of memory cell read operations, and avoids read errors caused by insufficient voltage difference.
Smart Images
Figure CN121725849A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to memory-related technologies, and in particular to a memory device with auxiliary circuitry, a memory control circuit, and a reading method. Background Technology
[0002] With the development of technology, various memory devices have been developed. Due to the application of dynamic voltage and frequency scaling (DVFS), the voltage operating range of memory devices has increased. However, in the low-voltage operating range, operational errors caused by noise interference are prone to occur. Summary of the Invention
[0003] Some embodiments of the present invention relate to a memory device. The memory device includes a memory cell array and a memory control circuit. The memory cell array is coupled to multiple bit lines and multiple complementary bit lines. The memory control circuit is coupled to the memory cell array. The memory control circuit includes a drive circuit, a tracking circuit, and a sensing circuit. The drive circuit is used to transmit a word line signal to the memory cell array. The drive circuit includes an auxiliary circuit. The tracking circuit is used to control a virtual bit line signal based on a voltage drop signal. The sensing circuit is coupled to the bit lines and the complementary bit lines and is used to read a memory cell in the memory cell array based on the virtual bit line signal. When the auxiliary circuit is off, the voltage drop signal has a first voltage. When the auxiliary circuit is on, the voltage drop signal has a second voltage. The second voltage is lower than the first voltage.
[0004] Some embodiments of the present invention relate to a memory control circuit. The memory control circuit includes a driving circuit, a tracking circuit, and a sensing circuit. The driving circuit transmits a word line signal to a memory cell array. The driving circuit includes an auxiliary circuit. The tracking circuit controls a virtual bit line signal based on a voltage drop signal. The sensing circuit is coupled to multiple bit lines and multiple complementary bit lines and reads a memory cell from the memory cell array based on the virtual bit line signal. When the auxiliary circuit is off, the voltage drop signal has a first voltage. When the auxiliary circuit is on, the voltage drop signal has a second voltage. The second voltage is lower than the first voltage.
[0005] Some embodiments of the present invention relate to a method for reading a memory device. The reading method includes the following operations: transmitting a word line signal to a memory cell array via a driving circuit in a memory control circuit, wherein the driving circuit includes an auxiliary circuit; controlling a virtual bit line signal based on a voltage drop signal via a tracking circuit in the memory control circuit, wherein the voltage drop signal has a first voltage when the auxiliary circuit is turned off, and has a second voltage when the auxiliary circuit is turned on, wherein the second voltage is lower than the first voltage; and reading a memory cell in the memory cell array based on the virtual bit line signal via a sensing circuit in the memory control circuit. Attached Figure Description
[0006] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention.
[0007] Figure 2 This is a waveform diagram of a multi-signal according to an embodiment of the present invention.
[0008] Figure 3 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0009] Figure 4 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0010] Figure 5 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0011] Figure 6 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0012] Figure 7 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0013] Figure 8 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0014] Figure 9 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0015] Figure 10 This is a schematic diagram of a tracking circuit according to an embodiment of the present invention.
[0016] Figure 11 This is a flowchart illustrating a reading method according to an embodiment of the present invention.
[0017] Explanation of reference numerals in the attached figures:
[0018] 100: Memory device; 110: Memory cell array; 1100: Reading method
[0019] 111: Memory cell; 112: Bit line; 113: Complementary bit line
[0020] 114: Word line; 120: Memory control circuit; 121: Main control circuit
[0021] 122: Drive circuit 1221: Auxiliary circuit 123: Auxiliary circuit
[0022] 124: Drive circuit; 125: Register circuit; 1261: Virtual bit line
[0023] 126, 300, 400, 500, 600, 700, 800, 900, 1000: Tracking circuit
[0024] 127: Load circuit; 128: Sensing circuit; 1281: Inverter
[0025] IUDE: Internal voltage drop enable signal UDE: Voltage drop enable signal 1282: Sensing amplifier
[0026] 310, 320, 330, 410, 420, 430, 510, 520, 530, 610, 620, 630, 710, 720, 730, 810, 820, 830, 910, 920, 930, 1010, 1020, 1030: Selection Circuit
[0027] S1110, S1120, S1130: Operations M1, M2, M3: Selection switches CLK: Clock signal
[0028] ICLK: Internal clock signal; WL: Word line signal; UD: Voltage drop signal
[0029] DWL: Virtual word line signals; OPT, OPT1, OPT2, OPT3: Selection signals
[0030] DBL: Virtual Bit Line Signal; SAE: Enable Signal; BL: Bit Line Signal
[0031] BLB: Complementary bit line signal; OUT: Output signal; TP1, TP2: Time points.
[0032] V1, V2, V3, V4, V5: Voltage; DV: Voltage Difference; S1: Pull-up Switch
[0033] S2: Pull-down switch VDD: Voltage source GND: Ground
[0034] T1, T2, T3, T4, T5: Transistors Detailed Implementation
[0035] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction between two or more components.
[0036] refer to Figure 1 . Figure 1 This is a schematic diagram of a memory device 100 according to some embodiments of the present invention. In some embodiments, the memory device 100 may be static random-access memory (SRAM), but the present invention is not limited thereto.
[0037] by Figure 1 For example, memory device 100 includes memory cell array 110 and memory control circuitry 120. Memory control circuitry 120 is coupled to memory cell array 110 and is used to control (write to or read from) memory cell array 110.
[0038] The memory cell array 110 includes multiple memory cells 111. These memory cells 111 are arranged in an array. These memory cells 111 are coupled to multiple bit lines, multiple complementary bit lines, and multiple word lines. For example, the memory cells 111 in the first column are coupled to bit lines 112 and complementary bit lines 113. The memory cells 111 in the first row are coupled to word lines 114. Other columns and other rows have a similar architecture.
[0039] The memory control circuit 120 includes a main control circuit 121, a drive circuit 122, an auxiliary circuit 123, a drive circuit 124, a register circuit 125, a tracking circuit 126, a multi-load circuit 127, and a sensing circuit 128.
[0040] The main control circuit 121 generates an internal voltage drop enable signal IUDE based on the voltage drop enable signal UDE, and generates an internal clock signal ICLK based on the clock signal CLK.
[0041] The driving circuit 122 generates a word line signal WL based on the internal voltage drop enable signal IUDE and the internal clock signal ICLK, and transmits the word line signal WL to these memory cells 111. For example, the driving circuit 122 can transmit the word line signal WL to these memory cells 111 in the first row via word line 114.
[0042] The drive circuit 122 includes an auxiliary circuit 1221. In some embodiments, a dropout enable signal UDE can be used to turn the auxiliary circuit 1221 on or off. Specifically, due to the application of dynamic voltage and frequency scaling (DVFS), the voltage operating range of the memory device 100 is increased. When the memory device 100 operates in the low-voltage operating range, the dropout enable signal UDE may have a high logic level. The main control circuit 121 may generate an internal dropout enable signal IUDE with a high logic level based on the dropout enable signal UDE with a high logic level. The auxiliary circuit 1221 may be turned on based on the internal dropout enable signal IUDE with a high logic level. When the auxiliary circuit 1221 is turned on, the voltage of the word line signal WL is reduced to reduce noise interference to the memory cell 111. Conversely, when the memory device 100 is not operating in the low-voltage operating range, the dropout enable signal UDE may have a low logic level. The main control circuit 121 can generate an internal voltage drop enable signal IUDE with a low logic level based on the voltage drop enable signal UDE with a low logic level. The auxiliary circuit 1221 can be turned off based on the internal voltage drop enable signal IUDE with a low logic level. In some embodiments, the auxiliary circuit 1221 is a read / write assist circuit. The read / write assist circuit can be implemented using a voltage drop circuit in conjunction with a buffer with an under-drive circuit.
[0043] The auxiliary circuit 123 generates an under-drive signal UD based on the internal voltage drop enable signal IUDE and the internal clock signal ICLK, and transmits the under-drive signal UD to the tracking circuit 126. In some embodiments, the auxiliary circuit 123 may also be implemented using a voltage drop circuit in conjunction with a buffer.
[0044] The driving circuit 124 generates a virtual word line signal DWL based on the internal clock signal ICLK and transmits the virtual word line signal DWL to the tracking circuit 126.
[0045] Register circuit 125 generates one or more select signals OPT and transmits the select signals OPT to tracking circuit 126. In some embodiments, register circuit 125 may be implemented using one or more registers.
[0046] The tracking circuit 126 controls the dummy bit line signal DBL on the dummy bit line 1261 based on the voltage drop signal UD, the dummy word line signal DWL, and the selection signal OPT. The dummy bit line signal DBL can be transmitted to the sensing circuit 128 through the dummy bit line 1261.
[0047] These load circuits 127 are coupled to virtual bit lines 1261. In some embodiments, the circuit architecture of each load circuit 127 may be the same as or similar to the circuit architecture of each memory cell 111, and the number of these load circuits 127 may be the same as the number of one column of memory cells 111 to mimic the capacitive and resistive environment of each column of memory cells 111.
[0048] Sensing circuit 128 includes an inverter 1281 and multiple sense amplifiers 1282. Inverter 1281 is coupled between the virtual bit line 1261 and the sense amplifiers 1282. The sense amplifiers 1282 are coupled to the bit line and the complementary bit line. Inverter 1281 inverts the virtual bit line signal DBL to generate an enable signal SAE. The enable signal SAE is sent to the sense amplifiers 1282 to enable them. For example, when the first sense amplifier 1282 is enabled, it senses the bit line signal BL on bit line 112 and the complementary bit line signal BLB on complementary bit line 113, and amplifies the voltage difference between the bit line signal BL and the complementary bit line signal BLB to generate an output signal OUT, thereby completing the corresponding readout operation.
[0049] Also refer to Figure 1 as well as Figure 2 . Figure 2 These are waveform diagrams of multiple signals shown according to some embodiments of the present invention.
[0050] It should be noted that, in Figure 2 In the diagram, the dashed line indicates that the auxiliary circuit 1221 is off, while the solid line indicates that the auxiliary circuit 1221 is on. Additionally, Figure 2 This illustrates the case where the bit line signal BL is pulled down by memory cell 111. In other embodiments, the complementary bit line signal BLB may also be pulled down by memory cell 111.
[0051] refer to Figure 2These are the dashed lines in the diagram. When the memory device 100 is not operating in the low-voltage operating range, the auxiliary circuit 1221 is turned off. The drive circuit 122 outputs a word line signal WL with voltage V1 and a short pulse width. The auxiliary circuit 123 outputs a voltage drop signal UD with voltage V2 and a short pulse width. The drive circuit 124 outputs a virtual word line signal DWL with voltage V3 and a short pulse width. The word line signal WL can turn on the memory cell 111, causing the bit line signal BL to be pulled down by the memory cell 111. The virtual bit line signal DBL is pulled down by the tracking circuit 126. At time TP1, the virtual bit line signal DBL is pulled down to a predetermined voltage, causing the enable signal SAE to go high to enable these sense amplifiers 1282. Meanwhile, since the voltage difference between the bit line signal BL and the complementary bit line signal BLB is large enough, the corresponding sensing amplifier 1282 can correctly amplify and read out this voltage difference.
[0052] refer to Figure 2 These are the solid lines in the diagram. When the memory device 100 operates in the low-voltage operating range, the auxiliary circuit 1221 is activated. The drive circuit 122 outputs a word line signal WL with a voltage V4 (lower than voltage V1) and a longer pulse width. The auxiliary circuit 123 outputs a voltage drop signal UD with a voltage V5 (lower than voltage V2) and a longer pulse width. The drive circuit 124 outputs a virtual word line signal DWL with a voltage V3 and a longer pulse width. It should be noted that the main control circuit 121 adjusts the internal clock signal ICLK according to the virtual bit line signal DBL, and the drive circuit 124 adjusts the pulse width of the virtual word line signal DWL according to the internal clock signal ICLK.
[0053] In some embodiments, when voltage V2 is 0.8 volts, voltage V5 may be 0.72 volts. In this example, the voltage difference between voltage V5 and voltage V2 is 10% of voltage V2. However, the invention is not limited to these voltage values and voltage differences. In other embodiments, the voltage difference between voltage V5 and voltage V2 may be more than 10% of voltage V2.
[0054] As mentioned earlier, in some related technologies, when the memory device 100 operates in the low-voltage operating range, the voltage of the word line signal WL is reduced, thereby reducing noise interference to the memory cell 111. However, this also weakens the pull-down capability of the memory cell 111 to the bit line signal BL or the complementary bit line signal BLB, resulting in a voltage difference between the bit line signal BL and the complementary bit line signal BLB that is too small to be read correctly.
[0055] Compared to the aforementioned related technologies, in this invention, when the memory device 100 operates in the low-voltage operating range, the pull-down capability of the tracking circuit 126 to the virtual bit line signal DBL is weakened by the voltage drop signal UD having a lower voltage V5 (details will be described in later paragraphs). As a result, the virtual bit line signal DBL will drop to the predetermined voltage at time point TP2, causing the enable signal SAE to turn high at time point TP2 to enable the sense amplifiers 1282. At time point TP2, the voltage difference DV between the bit line signal BL and the complementary bit line signal BLB is also large enough that the sense amplifier 1282 can correctly amplify and read out the voltage difference DV.
[0056] refer to Figure 1 , Figure 2 as well as Figure 3 . Figure 3 This is a schematic diagram of a tracking circuit 300 according to some embodiments of the present invention.
[0057] by Figure 3 For example, the tracking circuit 300 includes a pull-up switch S1, a pull-down switch S2, a selection circuit 310, a selection circuit 320, and a selection circuit 330. In this example, the pull-up switch S1 is implemented using a P-type transistor, and the pull-down switch S2 is implemented using an N-type transistor, but the invention is not limited thereto.
[0058] Pull-up switch S1 is coupled to voltage source VDD. Pull-up switch S1 and pull-down switch S2 are connected in series and coupled to an intermediate node, which is coupled to virtual bit line 1261. Pull-up switch S1 and pull-down switch S2 are controlled (on or off) by virtual word line signal DWL.
[0059] Selection circuits 310, 320, and 330 are connected in parallel and coupled between the pull-down switch S2 and ground GND. Figure 3 In this example, selection circuit 310 includes transistors T1 and T2. Transistors T1 and T2 are connected in series between the pull-down switch S2 and ground GND, and are controlled (on or off) by the combined signal of selection signal OPT1 and voltage drop signal UD. Selection circuit 320 includes transistor T3. Transistor T3 is connected in parallel between the pull-down switch S2 and ground GND, and is controlled (on or off) by the combined signal of selection signal OPT2 and voltage drop signal UD. Selection circuit 330 includes transistors T4 and T5. Transistors T4 and T5 are connected in parallel between the pull-down switch S2 and ground GND, and are controlled (on or off) by the combined signal of selection signal OPT3 and voltage drop signal UD. In this example, transistors T1-T5 are implemented using N-type transistors, but the invention is not limited thereto.
[0060] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the selection signal OPT1 and the voltage drop signal UD to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0061] Because the circuit architectures of selection circuits 310, 320 and 330 are different from each other, their pull-down capabilities for the virtual bit line signal DBL are also different. Figure 3 The implementations of selection circuits 310, 320, and 330 shown are merely examples. Other implementations of selection circuits 310, 320, and 330 are also within the scope of this invention.
[0062] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 310, 320, and 330, and the logic level of the selection signals OPT1-OPT3 can be determined according to actual needs to selectively turn on one or more of the selection circuits 310, 320, and 330, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0063] refer to Figure 1 , Figure 2 as well as Figure 4 . Figure 4 This is a schematic diagram of a tracking circuit 400 according to some embodiments of the present invention.
[0064] by Figure 4 For example, the tracking circuit 400 includes a pull-up switch S1, a pull-down switch S2, a selection circuit 410, a selection circuit 420, a selection circuit 430, a selection switch M1, a selection switch M2, and a selection switch M3.
[0065] Pull-up switch S1 is coupled to voltage source VDD. Pull-up switch S1 and pull-down switch S2 are connected in series and coupled to an intermediate node, which is coupled to virtual bit line 1261. Pull-up switch S1 and pull-down switch S2 are controlled by virtual word line signal DWL.
[0066] Selection circuits 410, 420, and 430 are coupled to pull-down switch S2 and controlled by the voltage drop signal UD. In some embodiments, selection circuits 410, 420, and 430 may respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0067] Selector switch M1 is coupled between selection circuit 410 and ground GND and is controlled by selection signal OPT1. Selector switch M2 is coupled between selection circuit 420 and ground GND and is controlled by selection signal OPT2. Selector switch M3 is coupled between selection circuit 430 and ground GND and is controlled by selection signal OPT3. In this example, selector switches M1-M3 are implemented using N-type transistors, but the invention is not limited thereto.
[0068] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 410, 420, and 430, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0069] refer to Figure 1 , Figure 2 as well as Figure 5 . Figure 5 This is a schematic diagram of a tracking circuit 500 according to some embodiments of the present invention.
[0070] by Figure 5 For example, the tracking circuit 500 includes a pull-up switch S1, a pull-down switch S2, a selector switch M1, a selector switch M2, a selector switch M3, a selector circuit 510, a selector circuit 520, and a selector circuit 530.
[0071] Pull-up switch S1 is coupled to voltage source VDD. Pull-up switch S1 and pull-down switch S2 are connected in series and coupled to an intermediate node, which is coupled to virtual bit line 1261. Pull-up switch S1 and pull-down switch S2 are controlled by virtual word line signal DWL.
[0072] Selection circuits 510, 520, and 530 are coupled to ground terminal GND and controlled by a voltage drop signal UD. In some embodiments, selection circuits 510, 520, and 530 can respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0073] Selector switch M1 is coupled between pull-down switch S2 and selection circuit 510 and is controlled by selection signal OPT1. Selector switch M2 is coupled between pull-down switch S2 and selection circuit 520 and is controlled by selection signal OPT2. Selector switch M3 is coupled between pull-down switch S2 and selection circuit 530 and is controlled by selection signal OPT3.
[0074] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 510, 520, and 530, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0075] refer to Figure 1 , Figure 2 as well as Figure 6 . Figure 6 This is a schematic diagram of a tracking circuit 600 according to some embodiments of the present invention.
[0076] by Figure 6 For example, the tracking circuit 600 includes a pull-up switch S1, a selection circuit 610, a selection circuit 620, and a selection circuit 630.
[0077] The pull-up switch S1 is coupled between the voltage source VDD and the virtual bit line 1261 and is controlled by the virtual word line signal DWL.
[0078] Selection circuits 610, 620, and 630 are connected in parallel and coupled between the virtual bit line 1261 and the ground terminal GND. In some embodiments, selection circuits 610, 620, and 630 can respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0079] Selection circuit 610 is controlled by a combination of selection signal OPT1, virtual word line signal DWL, and voltage drop signal UD. Selection circuit 620 is controlled by a combination of selection signal OPT2, virtual word line signal DWL, and voltage drop signal UD. Selection circuit 630 is controlled by a combination of selection signal OPT3, virtual word line signal DWL, and voltage drop signal UD.
[0080] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the selection signal OPT1, the virtual word line signal DWL, and the voltage drop signal UD to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0081] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 610, 620, and 630, and the logic level of the selection signals OPT1-OPT3 can be determined according to actual needs to selectively turn on one or more of the selection circuits 610, 620, and 630, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0082] Additionally, in some other embodiments, selection circuits 610, 620, and 630 may not utilize... Figure 3 The selection circuits 310, 320, and 330 are implemented in the above. Taking selection circuit 610 as an example, selection circuit 610 may include multiple transistors, some of which are controlled by selection signal OPT1, some of which are controlled by virtual word line signal DWL, and other transistors are controlled by voltage drop signal UD. Alternatively, selection circuit 610 may include multiple transistors, some of which are controlled by a combination of selection signal OPT1, virtual word line signal DWL, and voltage drop signal UD, and other transistors are controlled by the remaining one.
[0083] refer to Figure 1 , Figure 2 as well as Figure 7 . Figure 7 This is a schematic diagram of a tracking circuit 700 according to some embodiments of the present invention.
[0084] by Figure 7 For example, the tracking circuit 700 includes a pull-up switch S1, a selection circuit 710, a selection circuit 720, a selection circuit 730, a selection switch M1, a selection switch M2, and a selection switch M3.
[0085] The pull-up switch S1 is coupled between the voltage source VDD and the virtual bit line 1261 and is controlled by the virtual word line signal DWL.
[0086] Selection circuits 710, 720, and 730 are coupled to virtual bit line 1261 and controlled by a voltage drop signal UD. In some embodiments, selection circuits 710, 720, and 730 may respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0087] Selector switch M1 is coupled between selector circuit 710 and ground (GND) and is controlled by the combined signal of selector signal OPT1 and virtual word line signal DWL. Selector switch M2 is coupled between selector circuit 720 and ground (GND) and is controlled by the combined signal of selector signal OPT2 and virtual word line signal DWL. Selector switch M3 is coupled between selector circuit 730 and ground (GND) and is controlled by the combined signal of selector signal OPT3 and virtual word line signal DWL.
[0088] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the selection signal OPT1 and the virtual word line signal DWL to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0089] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 710, 720, and 730, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0090] refer to Figure 1 , Figure 2 as well as Figure 8 . Figure 8 This is a schematic diagram of a tracking circuit 800 according to some embodiments of the present invention.
[0091] by Figure 8 For example, the tracking circuit 800 includes a pull-up switch S1, a selection switch M1, a selection switch M2, a selection switch M3, a selection circuit 810, a selection circuit 820, and a selection circuit 830.
[0092] The pull-up switch S1 is coupled between the voltage source VDD and the virtual bit line 1261 and is controlled by the virtual word line signal DWL.
[0093] Selector switches M1, M2, and M3 are coupled to virtual bit line 1261. Selector switch M1 is controlled by the combined signal of select signal OPT1 and virtual word line signal DWL. Selector switch M2 is controlled by the combined signal of select signal OPT2 and virtual word line signal DWL. Selector switch M3 is controlled by the combined signal of select signal OPT3 and virtual word line signal DWL.
[0094] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the selection signal OPT1 and the virtual word line signal DWL to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0095] Selection circuit 810 is coupled between selection switch M1 and ground GND and controlled by voltage drop signal UD. Selection circuit 820 is coupled between selection switch M2 and ground GND and controlled by voltage drop signal UD. Selection circuit 830 is coupled between selection switch M3 and ground GND and controlled by voltage drop signal UD. In some embodiments, selection circuits 810, 820, and 830 can respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0096] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 810, 820, and 830, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0097] refer to Figure 1 , Figure 2 as well as Figure 9 . Figure 9 This is a schematic diagram of a tracking circuit 900 according to some embodiments of the present invention.
[0098] by Figure 9 For example, the tracking circuit 900 includes a pull-up switch S1, a selection circuit 910, a selection circuit 920, a selection circuit 930, a selection switch M1, a selection switch M2, and a selection switch M3.
[0099] The pull-up switch S1 is coupled between the voltage source VDD and the virtual bit line 1261 and is controlled by the virtual word line signal DWL.
[0100] Selection circuits 910, 920, and 930 are coupled to virtual bit line 1261 and controlled by a combined signal of the voltage drop signal UD and the virtual word line signal DWL. In some embodiments, selection circuits 910, 920, and 930 may respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0101] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the voltage drop signal UD and the virtual word line signal DWL to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0102] Selector switch M1 is coupled between selection circuit 910 and ground GND and is controlled by selection signal OPT1. Selector switch M2 is coupled between selection circuit 920 and ground GND and is controlled by selection signal OPT2. Selector switch M3 is coupled between selection circuit 930 and ground GND and is controlled by selection signal OPT3.
[0103] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 910, 920, and 930, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0104] Additionally, in some other embodiments, selection circuits 910, 920, and 930 may not utilize... Figure 3 The selection circuits 310, 320, and 330 are implemented in the above. In these other embodiments, taking selection circuit 910 as an example, selection circuit 910 may include multiple transistors, some of which are controlled by a voltage drop signal UD, and others are controlled by a virtual word line signal DWL.
[0105] refer to Figure 1 , Figure 2 as well as Figure 10 . Figure 10 This is a schematic diagram of a tracking circuit 1000 according to some embodiments of the present invention.
[0106] by Figure 10 For example, the tracking circuit 1000 includes a pull-up switch S1, a selection switch M1, a selection switch M2, a selection switch M3, a selection circuit 1010, a selection circuit 1020, and a selection circuit 1030.
[0107] The pull-up switch S1 is coupled between the voltage source VDD and the virtual bit line 1261 and is controlled by the virtual word line signal DWL.
[0108] Selector switches M1, M2, and M3 are coupled to virtual bit line 1261. Selector switch M1 is controlled by selection signal OPT1. Selector switch M2 is controlled by selection signal OPT2. Selector switch M3 is controlled by selection signal OPT3.
[0109] Selection circuit 1010 is coupled between selection switch M1 and ground GND and controlled by the combined signal of voltage drop signal UD and virtual word line signal DWL. Selection circuit 1020 is coupled between selection switch M2 and ground GND and controlled by the combined signal of voltage drop signal UD and virtual word line signal DWL. Selection circuit 1030 is coupled between selection switch M3 and ground GND and controlled by the combined signal of voltage drop signal UD and virtual word line signal DWL. In some embodiments, selection circuits 1010, 1020, and 1030 may respectively utilize... Figure 3 The selection circuits 310, 320 and 330 in the present invention are used to implement this invention, but the invention is not limited thereto.
[0110] The aforementioned combined signal can be a signal generated by an AND gate. For example, an AND gate can be used to perform an AND operation on the voltage drop signal UD and the virtual word line signal DWL to generate a combined signal of the two. Other combined signals are similar and will not be described in detail here.
[0111] In practical applications, the voltage drop signal UD, which has a lower voltage V5 when the auxiliary circuit 1221 is turned on, can be used to determine (e.g., weaken) the pull-down capability of the selection circuits 1010, 1020, and 1030, and determine the logic level of the selection signals OPT1-OPT3 according to actual needs to selectively turn on one or more of the selection switches M1, M2, and M3, thereby determining (e.g., delaying) the time when the virtual bit line signal DBL is pulled down to a predetermined voltage (e.g., determining the time point TP2).
[0112] Additionally, in some other embodiments, selection circuits 1010, 1020, and 1030 may not utilize... Figure 3 The selection circuits 310, 320, and 330 are implemented in the above. In these other embodiments, taking selection circuit 1010 as an example, selection circuit 1010 may include multiple transistors, some of which are controlled by a voltage drop signal UD, and others are controlled by a virtual word line signal DWL.
[0113] refer to Figure 11 . Figure 11 This is a flowchart of a reading method 1100 according to some embodiments of the present invention.
[0114] by Figure 11For example, the reading method 1100 includes operations S1110, S1120, and S1130. In some embodiments, the reading method 1100 is applied to... Figure 1 The present invention includes a memory device 100, but is not limited thereto. For ease of understanding, the following will describe the accompanying memory device 100. Figure 1 The memory device 100 and Figure 2 The waveform in the text is used to explain the reading method 1100.
[0115] In operation S1110, the word line signal WL is transmitted to the memory cell array 110 via the drive circuit 122 in the memory control circuit 120, wherein the drive circuit 122 includes an auxiliary circuit 1221. In operation S1120, the tracking circuit 126 in the memory control circuit 120 controls the virtual bit line signal DBL according to the voltage drop signal UD. When the auxiliary circuit 1221 is turned off, the voltage drop signal UD has a higher voltage V2. When the auxiliary circuit 1221 is turned on, the voltage drop signal UD has a lower voltage V5. In operation S1130, the sensing circuit 128 in the memory control circuit 120 reads the memory cell 111 in the memory cell array 110 according to the virtual bit line signal DBL.
[0116] The details of these operations have been described in the previous embodiments, and therefore will not be repeated here.
[0117] In summary, this invention, with the aid of an auxiliary circuit, utilizes a voltage drop signal to adjust (e.g., weaken) the pull-down capability of the tracking circuit to control (e.g., delay) the time it takes for the virtual bit line signal to be pulled down to a predetermined voltage. This extended time allows the voltage difference between the bit line signal and the complementary bit line signal to be large enough to be read correctly.
[0118] Although the present invention has been described above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the claims of the present invention.
Claims
1. A memory device, comprising: A memory cell array coupled to multiple bit lines and multiple complementary bit lines; as well as A memory control circuit is coupled to the memory cell array, the memory control circuit comprising: A driving circuit is used to transmit a word line signal to the memory cell array, and the driving circuit includes an auxiliary circuit. A tracking circuit for controlling a virtual bit line signal based on a voltage drop signal; and A sensing circuit, coupled to the plurality of bit lines and the plurality of complementary bit lines, is used to read a memory cell in the memory cell array based on the virtual bit line signal. When the auxiliary circuit is turned off, the voltage drop signal has a first voltage; when the auxiliary circuit is turned on, the voltage drop signal has a second voltage, wherein the second voltage is lower than the first voltage.
2. The memory device according to claim 1, characterized in that, When the auxiliary circuit is turned off, the word line signal has a third voltage, and when the auxiliary circuit is turned on, the word line signal has a fourth voltage, wherein the fourth voltage is lower than the third voltage.
3. The memory device according to claim 1, characterized in that, When the auxiliary circuit is turned off, the voltage drop signal has a first pulse width, and when the auxiliary circuit is turned on, the voltage drop signal has a second pulse width, wherein the second pulse width is longer than the first pulse width.
4. The memory device according to claim 1, characterized in that, When the auxiliary circuit is turned off, the word line signal has a first pulse width, and when the auxiliary circuit is turned on, the word line signal has a second pulse width, wherein the second pulse width is longer than the first pulse width.
5. The memory device according to claim 1, characterized in that, The tracking circuit is used to pull down the virtual bit line signal based on the voltage drop signal, a virtual word line signal, and multiple selection signals.
6. The memory device according to claim 5, characterized in that, When the auxiliary circuit is turned off, the virtual word line signal has a first pulse width, and when the auxiliary circuit is turned on, the virtual word line signal has a second pulse width, wherein the second pulse width is longer than the first pulse width.
7. The memory device according to claim 5, characterized in that, The tracking circuit includes: Multiple selection circuits are coupled between a virtual bit line and a ground terminal, and are controlled by the voltage drop signal to pull down the virtual bit line signal on the virtual bit line.
8. The memory device according to claim 7, characterized in that, These selection circuits have different pull-down capabilities for the virtual bit line signal.
9. A memory control circuit, comprising: A driving circuit for transmitting a word line signal to a memory cell array, the driving circuit including an auxiliary circuit; A tracking circuit for controlling a virtual bit line signal based on a voltage drop signal; and A sensing circuit, coupled to multiple bit lines and multiple complementary bit lines, is used to read a memory cell in the memory cell array based on the virtual bit line signals. When the auxiliary circuit is turned off, the voltage drop signal has a first voltage; when the auxiliary circuit is turned on, the voltage drop signal has a second voltage, wherein the second voltage is lower than the first voltage.
10. A method for reading a memory device, comprising: A word line signal is transmitted to a memory cell array via a driving circuit in a memory control circuit, wherein the driving circuit includes an auxiliary circuit. A tracking circuit in the memory control circuit controls a virtual bit line signal based on a voltage drop signal, wherein when the auxiliary circuit is turned off, the voltage drop signal has a first voltage, and when the auxiliary circuit is turned on, the voltage drop signal has a second voltage, wherein the second voltage is lower than the first voltage. as well as A sensing circuit in the memory control circuit reads a memory cell from the memory cell array based on the virtual bit line signal.