Three-valued reconfigurable logic circuit based on memristor
By designing a memristor-based ternary reconfigurable logic circuit and utilizing a 1T1M unit composed of memristors and transistors, various ternary logic operations are realized, solving the problem of insufficient construction of ternary logic circuits in the existing technology, and providing a ternary logic solution with high flexibility and large-scale computing power.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-03-24
AI Technical Summary
In the current technology, research on ternary logic based on memristors is in its initial stage, and a lot of research and accumulation is needed in the construction of ternary logic circuits.
Design a memristor-based ternary reconfigurable logic circuit. Utilize a 1T1M unit composed of two memristors and transistors to implement various ternary logic operations through different operating signals. The logic output is represented by the resistance state of the memristor, and the operation result is directly stored in the memristor.
It implements ternary logic operations with simple circuit structure and high flexibility. It can reconstruct different logic operations by changing the operation signals, adapt to sudden situations, is suitable for large-scale parallel computing, and supports in-memory computing architecture.
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Figure CN121725852A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing technology, and in particular to a ternary reconfigurable logic circuit based on memristors. Background Technology
[0002] As the miniaturization of complementary metal-oxide-semiconductor (CMOS) devices driven by Moore's Law gradually approaches its physical limits, traditional binary computing architectures face severe challenges in interconnect latency, noise margin, and dynamic power consumption during further development. Against this backdrop, multi-valued logic systems have attracted widespread attention due to their higher information density and potential for system complexity optimization. Among them, ternary logic, as the smallest integer base with a base greater than binary, exhibits unique advantages. Theoretical research shows that base 3 is closest to the base e of the natural logarithm, enabling the achievement of high information density while maintaining low system implementation complexity, thus demonstrating superior information efficiency.
[0003] Ternary logic exhibits significant advantages in multiple dimensions: In information encoding, its information density is approximately 1.58 times that of binary, reducing the number of bits in data representation by about 58.5%, thus significantly reducing interconnect complexity and chip area; in arithmetic operations, balanced ternary logic naturally supports signed number representation, its multiplication structure is simplified, and it generates almost no carry propagation; at the device implementation level, ternary logic is highly compatible with emerging nanodevices, such as carbon nanotube field-effect transistors and memristors, especially the multi-resistivity characteristics of memristors, which provide an ideal physical carrier for realizing in-memory computing architectures; in terms of circuit design methodology, in addition to basic logic gates, diverse implementation methods such as multiplexer-based design strategies and decoder-encoder structures can be adopted to effectively optimize the power consumption-delay product and system integration. Furthermore, ternary systems maintain backward compatibility with binary logic and demonstrate accuracy advantages in applications such as analog-to-digital conversion.
[0004] Therefore, ternary logic, with its comprehensive advantages in information efficiency, computational performance, device compatibility, and design flexibility, provides a valuable technical path for the innovative development of high-performance computing, low-power embedded systems, and novel non-von Neumann architectures in the post-Moore's Law era. Currently, research on memristor-based ternary logic is in its initial stage, and much research and accumulation is still needed in the construction of ternary logic circuits. Ternary logic computation can be divided into symmetric ternary logic computation {-1, 0, 1} and asymmetric ternary logic computation {0, 1, 2}. Considering the performance of memristor devices, the focus will be on asymmetric ternary computation.
[0005] Disadvantages of existing technology: At present, research on ternary logic based on memristors is in its initial stage, and a lot of research and accumulation is still needed in the construction of ternary logic circuits. Summary of the Invention
[0006] The present invention provides a ternary reconfigurable logic circuit based on memristors, which offers a new approach to realizing ternary logic operations.
[0007] To achieve the above objectives, the present invention provides a ternary reconfigurable logic circuit based on a memristor, the key of which includes the following steps: a first memristor is provided. Second memristor The first memristor The top is the X terminal, the second memristor The top end is the Y-terminal, the first memristor Second memristor The bottom ends are connected together to form the Z end;
[0008] First memristor Second memristor The resistance states include a high resistance state H, an intermediate resistance state I, and a low resistance state L, the first memristor Second memristor The initial state is the low-resistivity state L;
[0009] First memristor Second memristor The resistive state represents the logic output value of the logic circuit. .
[0010] Through the above design, this invention uses two memristors to form a ternary logic circuit, resulting in a simple circuit structure. This scheme uses the non-volatile resistive states of the two memristors to represent the output of the logic circuit. By using this method to represent the logic circuit output, the output result is directly stored in the memristors, preventing data loss due to power failure. This gives the circuit better anti-interference capabilities and adaptability to sudden situations.
[0011] Furthermore, the logic circuit of this invention is highly flexible; different ternary logic operations can be implemented using the same circuit by simply changing the operating signals. This provides a new approach to implementing ternary logic operations.
[0012] As a preferred option: the first memristor Second memristor The constructed logic circuit includes the following states:
[0013] when At that time, the states of the logic circuit include HH, HI, IH, HL, and LH; where HH represents and Both are in a high-resistivity state; HI indicates In a high-resistivity state, In the intermediate resistive state; IH represents In the intermediate resistive state, In a high-resistivity state; HL indicates In a high-resistivity state, In a low-resistivity state; LH indicates In a low-resistivity state, It is in a high-resistivity state;
[0014] when At that time, the states of the logic circuit include II, IL, and LI; where II represents and Both are in the intermediate resistive state; IL represents In the intermediate resistive state, In a low-resistivity state; LI indicates In a low-resistivity state, It is in an intermediate resistive state;
[0015] when At that time, the state of the logic circuit is LL, that is and Both are in a low-resistivity state.
[0016] As a preferred option: the first memristor Second memristor The constructed logic circuit includes the following states:
[0017] when At that time, the states of the logic circuit include HH, HI, IH, HL, and LH; where HH represents and Both are in a high-resistivity state; HI indicates In a high-resistivity state, In the intermediate resistive state; IH represents In the intermediate resistive state, In a high-resistivity state; HL indicates In a high-resistivity state, In a low-resistivity state; LH indicates In a low-resistivity state, It is in a high-resistivity state;
[0018] when At that time, the states of the logic circuit include II, IL, and LI; where II represents and Both are in the intermediate resistive state; IL represents In the intermediate resistive state, In a low-resistivity state; LI indicates In a low-resistivity state, It is in an intermediate resistive state;
[0019] when At that time, the state of the logic circuit is LL, that is and Both are in a low-resistivity state.
[0020] Operators can define the relationship between resistance state and logic value according to the specific usage. When the definition of resistance state and logic value changes, the corresponding operating voltage also changes.
[0021] Preferably, the logic circuit also includes transistors. and transistors The transistor The drain D is connected to the first memristor. At the bottom, the transistor The drain D is connected to the second memristor. At the bottom, the transistor and transistors The source S of the transistor is connected together as the Z terminal. and transistors The gate G is connected to the gate voltage. ;
[0022] The logic circuit contains two sets of 1T1M units, each consisting of a transistor and a memristor. One of the 1T1M units consists of the bottom of a memristor connected to the drain (D) of a transistor.
[0023] Preferably, m×n groups of 1T1M cells form a 1T1M cross array, in which transistors in all 1T1M cells of the i-th row of the 1T1M cross array... The source pole S is connected to the i-th word line. Connected, transistors in all 1T1M cells of column j The gate G is connected to the j-th gate line. Connected, memristors in all 1T1M cells of column j. The top of each bit line is connected to the j-th bit line. Connect them, 1≤i≤m, 1≤j≤n.
[0024] In a memristor crossbar array, the absence of transistors can lead to leakage current issues and potentially inaccurate calculations. Therefore, memristors and transistors are combined to form 1T1M cells, and multiple 1T1M cells are then used to construct a 1T1M crossbar array. This 1T1M crossbar array not only enables parallel and large-scale computations but also ensures the accuracy of ternary logic operations.
[0025] Preferably, the logic circuit can perform the following operations: TNOR (three-valued logic OR), TTRUE (three-valued logic true), TFALSE (three-valued logic false), TUNKNOWN (three-valued logic unknown), TCOPY p (three-valued logic copy p), TCOPY q (three-valued logic copy q), STI p (positive three-valued logic NOT p), STI q (positive three-valued logic NOT q), TAND (three-valued logic AND), TNIMP (three-valued logic implied NOT), TRNIMP (three-valued logic inverse implied NOT), TNAND (three-valued logic AND), TOR (three-valued logic OR), TIMP (three-valued logic implied), TRIMP (three-valued logic inverse implied), TXNOR (three-valued logic XOR), and TXOR (three-valued logic XOR).
[0026] The logic circuit of this invention can implement at least 17 kinds of ternary logic operations, not just single-variable logic; it is simple to operate and highly flexible. Different ternary logic operations can be implemented by reconstructing the same circuit simply by changing the operation signal.
[0027] Preferably, the logic circuit performs a ternary logic AND-NOT operation (TNAND) as follows:
[0028] First, apply a logic voltage signal to terminal X. , The Y and Z terminals are grounded, i.e., Y=Z=0;
[0029] when When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL;
[0030] when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL;
[0031] when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL; note that the logic circuit state obtained in this step will be used as the initial resistor state for the next logic operation.
[0032] Then, a logic voltage signal is applied to the X terminal. , Apply logic voltage signals to the Y and Z terminals. , ;
[0033] when When XZ = 02 and YZ = 22, regardless of , still The states of the logic circuits are all converted to LL;
[0034] when When XZ = 12 and YZ = 22, if If the logic circuit remains in state LL; If the state of the logic circuit remains at IL; Then the state of the logic circuit switches from HL to IL;
[0035] when When XZ = 22 and YZ = 22, if If the logic circuit remains in state LL; If the state of the logic circuit remains at IL; Then the state of the logic circuit remains at HL;
[0036] Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ;
[0037] In logical input At that time, the state of the logic circuit is IL, that is, the logic output. ;
[0038] In logical input At that time, the state of the logic circuit is HL, that is, the logic output is... This indicates that, under the control of the input signal, the three-valued logic NAND operation was implemented.
[0039] Preferably, the logic circuit performs a ternary OR operation (TNOR) as follows:
[0040] For transistors and transistors A gate voltage is applied to the gate G. Apply a logic voltage signal to terminal X. , Apply a logic voltage signal to the Y terminal. , The Z terminal is grounded, i.e., Z=0;
[0041] when Right now , When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL;
[0042] when When XZ = 00 and YZ = 10, the state of the logic circuit changes from LL to LI;
[0043] when When XZ = 00 and YZ = 20, the state of the logic circuit changes from LL to LH;
[0044] when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL;
[0045] when When XZ = 10 and YZ = 10, the state of the logic circuit changes from LL to II;
[0046] when When XZ = 10 and YZ = 20, the state of the logic circuit changes from LL to IH;
[0047] when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL;
[0048] when When XZ = 20 and YZ = 10, the state of the logic circuit changes from LL to HI;
[0049] when When XZ = 20 and YZ = 20, the state of the logic circuit changes from LL to HH;
[0050] Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ; in logical input At that time, the state of the logic circuit is LI, IL, II, that is, the logic output. ; in logical input At that time, the state of the logic circuit is LH, IH, HL, HI, HH, which is the logic output. This indicates that the TNOR logic operation was achieved under the control of the input signal.
[0051] Preferably, the logic circuit, when performing ternary logic operations including TNOR, TTRUE, TFALSE, TUNKNOWN, TCOPY p, TCOPY q, STI p, STI q, TAND, TNIMP, and TRNIMP, outputs the following logic values: With logical input variables , , , , , The relational expression is as follows:
[0052] ;
[0053] The logic circuit, in performing ternary logic operations (TNAND, TOR, TIMP, and TRIMP), outputs the following logic values: With logical input variables , , , , , The relational expression is as follows:
[0054] ;
[0055] The logic circuit, in performing the three-valued logic operations TXNOR and TXOR, outputs the following logic values: With logical input variables , , , , , , , , , , , The relationship between and is expressed as follows:
[0056] ;
[0057] in, , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the first step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the second step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the third step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the fourth step of the operation, respectively; (symbols) Represents logical OR, symbol The symbol ￣ represents logical AND, and the symbol ￣ represents logical NOT.
[0058] The beneficial effects of the present invention are: the memristor-based ternary logic circuit provided by the present invention provides a new way to realize ternary logic operations. It has the advantages of simple circuit structure and high flexibility. Different ternary logic operations can be realized by simply changing the operation signal using the same circuit reconstruction.
[0059] The proposed logic structure can be mapped to a cross array, facilitating large-scale ternary logic computation. The logic output is represented by the resistance state of a memristor, and the computation result is directly stored in the memristor, realizing the integration of logic operation and storage, which is of great significance to the development of in-memory computing architecture. Attached Figure Description
[0060] Figure 1 This is a ternary logic circuit diagram based on memristors;
[0061] Figure 2 A diagram representing the logical input and output variables;
[0062] Figure 3 This is a diagram showing the symbol for a memristor and the state transitions of its resistor.
[0063] Figure 4 memristor State transition diagram;
[0064] Figure 5 Implement a ternary logic AND-NOT operation diagram for a memristor-based ternary logic circuit;
[0065] Figure 6 The circuit diagram is a ternary reconfigurable logic circuit based on transistors and memristors 1T1M.
[0066] Figure 7 A diagram illustrating the implementation of TNOR logic operations for a 1T1M ternary logic circuit;
[0067] Figure 8 This is a ternary logic operation diagram based on a 1T1M cross array. Detailed Implementation
[0068] The present invention will be further described in detail below with reference to the accompanying drawings and specific examples. The following embodiments or drawings are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0069] Figure 3The diagram shows the symbol of a memristor and its resistance state transitions. The top of the memristor is labeled A, and the bottom is labeled B. This device has three resistance states: high resistance (H), intermediate resistance (I), and low resistance (L). When the memristor is in the low resistance state (L), the voltage difference between terminals A and B, i.e., the voltage at terminal A, is... Reduce B-terminal voltage Greater than the absolute value of the reset voltage When the memristor switches from a low-resistance state L to a high-resistance state H; when the memristor is in a low-resistance state L, and the voltage difference between memristor A and B is greater than the absolute value of the reset voltage. And less than the absolute value of the reset voltage When the memristor switches from low resistance state L to intermediate resistance state I; when the memristor is in intermediate resistance state I, and the voltage difference between memristor A and B is greater than the absolute value of the reset voltage. When the memristor switches from the intermediate resistance state I to the high resistance state H; when the memristor is in the high resistance state H, and the voltage difference between the memristor's B and A terminals is equal to the voltage at memristor B... Reduce terminal A voltage Greater than the set voltage When the memristor switches from a high-resistance state H to a low-resistance state L; when the memristor is in a high-resistance state H, and the voltage difference between memristor B and A is greater than the set voltage. And less than the set voltage When the memristor switches from the high-resistance state H to the intermediate-resistance state I; when the memristor is in the intermediate-resistance state I, and the voltage difference between the memristor's B and A terminals is greater than the set voltage. When the memristor switches from its intermediate resistance state I to its low resistance state L, it does so; otherwise, it remains in its current resistance state. The relationship between the memristor set voltage and the set voltage is as follows: The relationship between the magnitudes of the memristor reset voltages is as follows: .
[0070] Figure 1 The diagram shown illustrates a logic circuit for implementing ternary logic operations, comprising two memristors as described above. and Connect the B terminals of two memristors together, denoted as Z terminal. Denote the A terminal of one memristor as X terminal, and the A terminal of the other memristor as Y terminal. To enable ternary logic operations in this circuit, voltage-represented logic inputs (p, q) are applied to the three terminals X, Y, and Z. , GND (0 V) represents logic 2, 1, and 0 respectively, where voltage... and The following relationship must be satisfied:
[0071] ;
[0072] ;
[0073] ;
[0074] ;
[0075] ;
[0076] ;
[0077] like Figure 2 As shown, the logic output value of the logic circuit Memristor and The resistance state is represented as follows:
[0078] when At that time, the states of the logic circuit include HH, HI, IH, HL, and LH; where HH represents and Both are in a high-resistivity state; HI indicates In a high-resistivity state, In the intermediate resistive state; IH represents In the intermediate resistive state, In a high-resistivity state; HL indicates In a high-resistivity state, In a low-resistivity state; LH indicates In a low-resistivity state, It is in a high-resistivity state;
[0079] when At that time, the states of the logic circuit include II, IL, and LI; where II represents and Both are in the intermediate resistive state; IL represents In the intermediate resistive state, In a low-resistivity state; LI indicates In a low-resistivity state, It is in an intermediate resistive state;
[0080] when At that time, the state of the logic circuit is LL, that is and Both are in a low-resistivity state.
[0081] for Figure 1 The logic circuit shown includes a memristor. and The state transition logic is the same, such as Figure 4 As shown. Using a memristor For example, the specific state transition logic is as follows:
[0082] (1) When the memristor When in high impedance state H, if the X and Z terminals are set to logic 0 and 1 or 1 and 2 respectively, i.e., XZ = (01, 12), then the memristor... Voltage difference between the two ends make memristor Switching from high-resistance state H to intermediate-resistance state I; if the X and Z terminals are set to 0 and 2 respectively, i.e., XZ = 02, then the memristor... Voltage difference between the two ends make memristor The memristor switches from a high-resistance state (H) to a low-resistance state (L). If the X and Z terminals are set to 0, 0 or 1, 0 or 1, 1 or 2, 0 or 2, 1 or 2, 2 respectively, i.e., XZ = (00, 10, 11, 20, 21, 22), then the memristor... Voltage difference between the two ends memristor Maintain high impedance state H. Note that the operation signals logic 0, 1, and 2 applied to the X, Y, and Z terminals of the logic circuit here refer to their corresponding voltage signals GND, Y, and Z, respectively. , .
[0083] (2) When the memristor When in the intermediate resistive state, if the X and Z terminals are set to logic 0 and 2 respectively, i.e., XZ = 02, then the memristor... Voltage difference between the two ends make memristor The memristor switches from the intermediate resistance state I to the low resistance state L; if the X and Z terminals are set to 2 and 0 respectively, i.e., XZ = 20, then the memristor... Voltage difference between the two ends make memristor Switching from intermediate resistance state I to high resistance state H; if the X and Z terminals are set to 0, 0 or 0, 1 or 1, 0 or 1, 1 or 1, 2 or 2, 1 or 2, 2 respectively, i.e., XZ = (00, 01, 10, 11, 12, 21, 22), then the memristor Voltage difference between the two ends memristor Remain in the intermediate resistance state I.
[0084] (3) When the memristor When in low-impedance state, if the X and Z terminals are set to 2 and 0 respectively, i.e., XZ = 20, then the memristor... Voltage difference between the two ends make memristor The memristor switches from a low-resistance state (L) to a high-resistance state (H). If the X and Z terminals are set to 1 and 0 or 2 and 1 respectively, i.e., XZ = (10, 21), then the memristor... Voltage difference between the two ends make memristor Switching from low-resistance state L to intermediate-resistance state I; if the X and Z terminals are set to 0, 0 or 0, 1 or 0, 2 or 1, 1 or 1, 2 or 2, 2 respectively, i.e., XZ = (00, 01, 02, 11, 12, 22), then the memristor... Voltage difference between the two ends memristor Maintain in a low-resistivity state L.
[0085] Before logic operations, memristor and The initial resistance state is set to the low resistance state L. Based on Figure 1 The logic structure shown can implement different ternary logic operations by applying appropriate operation signals to the X, Y, and Z terminals. Five operation signals can be applied to the X, Y, and Z terminals: input signals p, q, 0, 1, and 2. Inputs p and q each have three possible values: logic 0, 1, and 2. The specific operation process is illustrated here using the ternary logic NAND operation as an example:
[0086] Step 1: Apply a logic voltage signal to terminal X. , The Y and Z terminals are grounded, i.e., Y=Z=0;
[0087] when When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL;
[0088] when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL;
[0089] when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL; note that the logic circuit state obtained in this step will be used as the initial resistor state for the next logic operation.
[0090] Step 2: Apply a logic voltage signal to terminal X. , Apply logic voltage signals to the Y and Z terminals. , ;
[0091] when When XZ = 02 and YZ = 22, regardless of the previous operation... , still The states of the logic circuits are all converted to LL;
[0092] when If then XZ = 12 and YZ = 22, then in the previous operation... If the logic circuit remains in state LL in the previous operation... Then the state of the logic circuit remains at IL; if in the previous operation Then the state of the logic circuit switches from HL to IL;
[0093] when When XZ = 22 and YZ = 22, if in the previous operation... If the logic circuit remains in state LL in the previous operation... Then the state of the logic circuit remains at IL; if in the previous operation Then the state of the logic circuit remains at HL;
[0094] Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ;
[0095] In logical input At that time, the state of the logic circuit is IL, that is, the logic output. ;
[0096] In logical input At that time, the state of the logic circuit is HL, that is, the logic output is... ,like Figure 5 As shown, this demonstrates that the three-valued logic AND and NOT operations are implemented under the control of the input signal.
[0097] Figure 1 The ternary logic circuit shown can be used as a reconfigurable logic gate, meaning that by simply changing the voltages applied to the X, Y, and Z terminals, this logic circuit can implement different ternary logic operations. Table 1 lists 17 ternary logic operations and their corresponding applied operation signals. The 17 ternary logic operations are: TNOR, TTRUE, TFALSE, TUNKNOWN, TCOPY p, TCOPY q, STI p, STI q, TAND, TNIMP, TRNIMP, TNAND, TOR, TIMP, TRIMP, TXNOR, and TXOR.
[0098] For example, when the X, Y, and Z terminals of a ternary logic circuit are set to p, q, and 0 respectively, the ternary logic OR operation TNOR can be implemented in one step. Conversely, when the X, Y, and Z terminals of a ternary logic circuit are set to 2, 2, and p respectively, the ternary logic copy operation TCOPY p can be implemented in one step.
[0099] As shown in Table 1, for the three-valued logic operations numbered 1-11, regardless of whether it's the first or second step of the logic operation, if the memristor's resistance state changes, the memristor will only perform a RESET operation, i.e., switching from low resistance state L to intermediate resistance state I, from low resistance state L to high resistance state H, or from intermediate resistance state I to high resistance state H. When XZ = 10 and YZ = 10, the memristor... and The memristor switches from the low-resistance state L to the intermediate-resistance state I; at XZ = 20 and YZ = 20, the memristor... and The memristor switches from a low-resistance state L to a high-resistance state H, or from an intermediate-resistance state I to a high-resistance state H; in other cases, the memristor... and The resistor state remains unchanged. Furthermore, when the logic circuit state is HH, HI, IH, HL, or LH, the logic output is 0; when the logic circuit state is II, IL, or LI, the logic output is 1; and when the logic circuit state is LL, the logic output is 2. Therefore, for the three-valued logic operations numbered 1-11, the logic output... With logical input variables , , , , , The relational expression is as follows:
[0100] ;
[0101] in, , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the first step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the second step of the operation, respectively; (symbols) Represents logical OR, symbol The symbol ￣ represents logical AND, and the symbol ￣ represents logical NOT.
[0102] For a three-valued logical operation implemented in one step, not executing the second step is equivalent to... , , The signal is 0. Taking the TNOR logic operation as an example, , , , , , Given p, q, 0, 0, 0, and 0 respectively, we get... .
[0103] For the three-valued logic operations numbered 12-15, in the first logic operation, if the resistance state of the memristor changes, the memristor will only perform a RESET operation, that is, switch from the low resistance state L to the intermediate resistance state I or the high resistance state H, and in and At that time, the memristor switches from the low-resistance state L to the intermediate-resistance state I; and When the resistance state changes, the memristor switches from low resistance state L to high resistance state H; otherwise, it remains in low resistance state L. In the second logic operation, if the memristor's resistance state changes, it will only perform a set operation, i.e., switch from high resistance state H to intermediate resistance state I, from high resistance state H to low resistance state L, or from intermediate resistance state I to low resistance state L. and At that time, the memristor switches from the high-resistance state H to the intermediate-resistance state I; and When switching from a high-resistance state H to a low-resistance state L, or from an intermediate-resistance state I to a low-resistance state L, the memristor remains in its current resistance state, i.e., low-resistance state L, intermediate-resistance state I, or high-resistance state H. Therefore, for the three-valued logic operations numbered 12-15, the logic output... With logical input variables , , , , , The relational expression is as follows:
[0104] .
[0105] For the three-valued logic operations numbered 16-17, in the first / third logic operation, if the resistance state of the memristor changes, the memristor will only perform a RESET operation, that is, switch from the low resistance state L to the intermediate resistance state I or the high resistance state H, and in and At that time, the memristor switches from the low-resistance state L to the intermediate-resistance state I; and When the memristor switches from a low-resistance state L to a high-resistance state H, it remains in the low-resistance state L. In the second / fourth logic operation, if the memristor's resistance state changes, it will only perform a SET operation, i.e., switch from high-resistance state H to intermediate-resistance state I, from high-resistance state H to low-resistance state L, or from intermediate-resistance state I to low-resistance state L. and At that time, the memristor switches from the high-resistance state H to the intermediate-resistance state I; and When the resistance changes, the memristor switches from a high-resistance state H to a low-resistance state L, or from an intermediate-resistance state I to a low-resistance state L; otherwise, the memristor remains unchanged in its current resistance state. Therefore, for the ternary logic operations numbered 16-17, the logic output... With logical input variables , , , , , , , , , , , The relationship between and is expressed as follows:
[0106] ;
[0107] in, , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the first step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the second step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the third step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the fourth step of the operation, respectively; (symbols) Represents logical OR, symbol The symbol ￣ represents logical AND, and the symbol ￣ represents logical NOT.
[0108] For the three-step implementation of the three-valued logic XOR operation TXNOR, the fourth step is not executed, which is equivalent to... , , The signal is 0.
[0109] Table 1. Relationship between 17 ternary logic operations and their corresponding signal allocation, logic input, and logic output.
[0110]
[0111]
[0112]
[0113]
[0114] The aforementioned ternary logic structure and operation method can be extended to circuits based on transistors and memristors, such as... Figure 6 As shown, the ternary reconfigurable logic circuit based on transistors and memristors contains two one-transistor-one-memristor units 1T1M, one of which consists of a memristor. / The B terminal and an NMOS transistor / The drains D are connected to form a circuit. In a ternary logic circuit based on 1T1M, the memristor is used. Terminal A is marked as X, memristor The A terminal is marked as Y, transistor and transistors The common node of the source S is labeled Z. To implement ternary logic operations in a 1T1M ternary reconfigurable logic circuit, a gate voltage is applied. To transistor and transistors Gate G of the transistor and transistors Voltage difference between gate G and source S Greater than the threshold voltage of transistors T1 and T2 , making transistors and transistors Conducting is equivalent to a closed switch. ,in This represents the voltage applied to the Z terminal of the 1T1M ternary logic circuit. Simultaneously, according to Table 1, appropriate operating signals are applied to the three terminals of the circuit to implement a ternary logic operation.
[0115] Taking the TNOR (Negative-Negative) operation of a 1T1M ternary logic circuit as an example, the specific operation process is as follows:
[0116] Gate voltage Applied to transistor and transistors The gate G, the X, Y and Z terminals of the 1T1M ternary logic circuit are respectively set as , And 0, that is The corresponding voltage signal is applied to terminal X. The corresponding voltage signal is applied to the Y terminal, while the Z terminal is grounded, thus implementing the TNOR logic operation. , Z=0.
[0117] when Right now , When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL;
[0118] when When XZ = 00 and YZ = 10, the state of the logic circuit changes from LL to LI;
[0119] when When XZ = 00 and YZ = 20, the state of the logic circuit changes from LL to LH;
[0120] when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL;
[0121] when When XZ = 10 and YZ = 10, the state of the logic circuit changes from LL to II;
[0122] when When XZ = 10 and YZ = 20, the state of the logic circuit changes from LL to IH;
[0123] when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL;
[0124] when When XZ = 20 and YZ = 10, the state of the logic circuit changes from LL to HI;
[0125] when When XZ = 20 and YZ = 20, the state of the logic circuit changes from LL to HH;
[0126] Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ; in logical input At that time, the state of the logic circuit is LI, IL, II, that is, the logic output. ; in logical input At that time, the state of the logic circuit is LH, IH, HL, HI, HH, which is the logic output. ,like Figure 7 As shown, this demonstrates that the TNOR logic operation was achieved under the control of the input signal.
[0127] Figure 8 The diagram illustrates a 1T1M crossover array constructed using transistors and memristors, where an NMOS transistor and a memristor are connected in series at each crossover point. The top of the memristor in the same column is connected to the bit line BL, the source of the transistor in the same row is connected to the word line WL, and the gate of the transistor in the same column is connected to the gate line GL. To implement logic operations in the 1T1M array, the gate voltage is... When an operating signal is applied to the selected gate line GL, the corresponding transistor is turned on, equivalent to a closed switch. Conversely, when the unselected gate line GLs is grounded, the corresponding transistor is not turned on, equivalent to an open switch. Simultaneously, according to Table 1, appropriate operating signals are applied to the selected BL and selected WL, while the unselected BL is left floating, and the voltage is... Apply WL to the unselected rows to isolate the unselected rows so as not to change the resistance state of the memristors that are not involved in the calculation. .
[0128] Figure 8 The green box indicates a 1T1M ternary logic unit constructed on an array row. It contains two 1T1M units on the same row of a 1T1M cross-array. These two 1T1M units can be arbitrarily selected on the same row. Their equivalent circuit is as follows: Figure 8 As shown in the red box.
[0129] The memristor-based ternary logic circuit proposed in this invention provides a new approach to implementing ternary logic operations. The circuit structure is simple and highly flexible; different ternary logic operations can be achieved by reconfiguring the same circuit simply by changing the operating signals. The proposed logic structure can be mapped to a crossbar array, facilitating large-scale ternary logic computation. The logic output is represented by the resistance state of the memristor, and the operation results are directly stored in the memristor, achieving a fusion of logic operation and storage, which is of great significance to the development of in-memory computing architectures.
[0130] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A ternary reconfigurable logic circuit based on memristors, characterized in that: A first memristor is provided. Second memristor The first memristor The top is the X terminal, the second memristor The top end is the Y-terminal, the first memristor Second memristor The bottom ends are connected together to form the Z end; First memristor Second memristor The resistance states include a high resistance state H, an intermediate resistance state I, and a low resistance state L, the first memristor Second memristor The initial state is a low-resistivity state L; First memristor Second memristor The resistive state represents the logic output value of the logic circuit. .
2. The memristor-based ternary reconfigurable logic circuit according to claim 1, characterized in that: From the first memristor Second memristor The constructed logic circuit includes the following states: when At that time, the states of the logic circuit include HH, HI, IH, HL, and LH; where HH represents and Both are in a high-resistivity state; HI indicates In a high-resistivity state, In the intermediate resistive state; IH represents In the intermediate resistive state, In a high-resistivity state; HL indicates In a high-resistivity state, In a low-resistivity state; LH indicates In a low-resistivity state, It is in a high-resistivity state; when At that time, the states of the logic circuit include II, IL, and LI; where II represents and Both are in the intermediate resistive state; IL represents In the intermediate resistive state, In a low-resistivity state; LI indicates In a low-resistivity state, It is in an intermediate resistive state; when At that time, the state of the logic circuit is LL, that is and Both are in a low-resistivity state.
3. The memristor-based ternary reconfigurable logic circuit according to claim 1, characterized in that: From the first memristor Second memristor The constructed logic circuit includes the following states: when At that time, the states of the logic circuit include HH, HI, IH, HL, and LH; where HH represents and Both are in a high-resistivity state; HI indicates In a high-resistivity state, In the intermediate resistive state; IH represents In the intermediate resistive state, In a high-resistivity state; HL indicates In a high-resistivity state, In a low-resistivity state; LH indicates In a low-resistivity state, It is in a high-resistivity state; when At that time, the states of the logic circuit include II, IL, and LI; where II represents and Both are in the intermediate resistive state; IL represents In the intermediate resistive state, In a low-resistivity state; LI indicates In a low-resistivity state, It is in an intermediate resistive state; when At that time, the state of the logic circuit is LL, that is and Both are in a low-resistivity state.
4. The memristor-based ternary reconfigurable logic circuit according to claim 1 or 2, characterized in that: The logic circuit also includes transistors. and transistors The transistor The drain D is connected to the first memristor. At the bottom, the transistor The drain D is connected to the second memristor. At the bottom, the transistor and transistors The source S of the transistor is connected together as the Z terminal. and transistors The gate G is connected to the gate voltage. ; The logic circuit contains two sets of 1T1M units, one of which consists of the bottom of a memristor connected to the drain D of a transistor.
5. The memristor-based ternary reconfigurable logic circuit according to claim 4, characterized in that: m×n groups of 1T1M cells form a 1T1M cross array. In the 1T1M cross array, the transistors in all 1T1M cells in the i-th row... The source pole S is connected to the i-th word line. Connected, transistors in all 1T1M cells of column j The gate G is connected to the j-th gate line. Connected, memristors in all 1T1M cells of column j. The top of each bit line is connected to the j-th bit line. Connect them, 1≤i≤m, 1≤j≤n.
6. The memristor-based ternary reconfigurable logic circuit according to claim 2 or 4, characterized in that: The three-valued logic operations performed by the logic circuit include, but are not limited to: three-valued logic NOR (TNOR), three-valued logic TRUE (TRUE), three-valued logic TFALSE (TFALSE), three-valued logic TUNKNOWN (TUNKNOWN), three-valued logic copy p (TCOPY p), three-valued logic copy q (TCOPY q), positive three-valued logic NOT (STI p), positive three-valued logic NOT (STI q), three-valued logic AND (TAND), three-valued logic implied NOT (TNIMP), three-valued logic inverse implied NOT (TRNIMP), three-valued logic NAND (TNAND), three-valued logic OR (TOR), three-valued logic implied operation (TIMP), three-valued logic inverse implied operation (TRIMP), three-valued logic XNOR (TXNOR), and three-valued logic XOR (TXOR).
7. The memristor-based ternary reconfigurable logic circuit according to claim 6, characterized in that: The logic circuit performs a ternary logic AND-NOT operation (TNAND) as follows: First, apply a logic voltage signal to terminal X. , The Y and Z terminals are grounded, i.e., Y=Z=0; when When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL; when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL; when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL; Then, a logic voltage signal is applied to the X terminal. , Apply logic voltage signals to the Y and Z terminals. , ; when When XZ = 02 and YZ = 22, regardless of , still The states of the logic circuits are all converted to LL; when When XZ = 12 and YZ = 22, if If the logic circuit remains in state LL; If the state of the logic circuit remains at IL; Then the state of the logic circuit switches from HL to IL; when When XZ = 22 and YZ = 22, if If the logic circuit remains in state LL; If the state of the logic circuit remains at IL; Then the state of the logic circuit remains at HL; Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ; In logical input At that time, the state of the logic circuit is IL, that is, the logic output. ; In logical input At that time, the state of the logic circuit is HL, that is, the logic output is... .
8. The memristor-based ternary reconfigurable logic circuit according to claim 6, characterized in that: The logic circuit performs a ternary OR operation (TNOR) as follows: For transistors and transistors A gate voltage is applied to the gate G. Apply a logic voltage signal to terminal X. , Apply a logic voltage signal to the Y terminal. , The Z terminal is grounded, i.e., Z=0; when Right now , When XZ = 00 and YZ = 00, the state of the logic circuit remains at LL; when When XZ = 00 and YZ = 10, the state of the logic circuit changes from LL to LI; when When XZ = 00 and YZ = 20, the state of the logic circuit changes from LL to LH; when When XZ = 10 and YZ = 00, the state of the logic circuit changes from LL to IL; when When XZ = 10 and YZ = 10, the state of the logic circuit changes from LL to II; when When XZ = 10 and YZ = 20, the state of the logic circuit changes from LL to IH; when When XZ = 20 and YZ = 00, the state of the logic circuit changes from LL to HL; when When XZ = 20 and YZ = 10, the state of the logic circuit changes from LL to HI; when When XZ = 20 and YZ = 20, the state of the logic circuit changes from LL to HH; Therefore, in the logical input At that time, the state of the logic circuit is LL, that is, the logic output is... ; in logical input At that time, the state of the logic circuit is LI, IL, II, that is, the logic output. ; in logical input At that time, the state of the logic circuit is LH, IH, HL, HI, HH, which is the logic output. .
9. The memristor-based ternary reconfigurable logic circuit according to claim 6, characterized in that: The logic circuit performs the following ternary logic operations: TNOR, TTRUE, TFALSE, TUNKNOWN, TCOPY p, TCOPY q, STI p, STI q, TAND, TNIMP, and TRNIMP. The logic output is... With logical input variables , , , , , The relational expression is as follows: ； The logic circuit, in performing ternary logic operations (TNAND, TOR, TIMP, and TRIMP), outputs the following logic values: With logical input variables , , , , , The relational expression is as follows: ； The logic circuit, in performing the three-valued logic operations TXNOR and TXOR, outputs the following logic values: With logical input variables , , , , , , , , , , , The relationship between and is expressed as follows: ； in, , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the first step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the second step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the third step of the operation, respectively. , , These represent the signals applied to the X, Y, and Z terminals of the logic circuit in the fourth step of the operation, respectively; (symbols) The symbol represents logical OR. The symbol ￣ represents logical AND, and the symbol ￣ represents logical NOT.