Storage controller, storage system, and electronic device

Abstract

The invention provides a storage controller, a storage system and electronic equipment, and belongs to the technical field of electronic equipment. The storage controller comprises an error positioning unit, a data processing unit and an error correction unit, the error positioning unit is connected with the processor, the storage and the data processing unit, the processor outputs a first read instruction, first data is read from the storage to perform error byte positioning, and if error bytes exist, the error correction unit performs error correction; sending the error byte address to a processor and a data processing unit; the data processing unit is connected with the processor and the error correction unit, receives a first write instruction output by the processor to the error byte address, and sends a correct byte corresponding to the error byte address included in the first write instruction and the error byte address to the error correction unit; the error correction unit is connected with the processor and the memory, performs ECC coding on correct bytes and writes correction codes into the memory; receiving a second read instruction output by the processor; and the data processing unit receives the second read instruction, obtains correct bytes and outputs the correct bytes to the processor.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and more particularly to a storage controller, storage system, and electronic device. Background Technology

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. With the development of chip technology, SRAM is mainly used to store high-speed cache inside the Central Processing Unit (CPU), acting as a high-speed temporary working area between the processor and slow main memory to compensate for their speed difference.

[0003] To ensure the correctness of data transmission and storage, SRAM reads currently have a verification mechanism. When the CPU writes data to the SRAM via the bus, it generates a checksum corresponding to the written data and simultaneously writes this checksum into the SRAM. This allows the CPU to first read the data and its corresponding checksum when it needs to read data from the SRAM, and then generate its own actual checksum for the read data. If the actual checksum does not match the checksum stored in the SRAM, it determines that the read data has failed verification and initiates an error interrupt to the CPU.

[0004] However, compared to the CPU directly writing data to SRAM for later reading, the SRAM verification mechanism requires reading back the data after it has been retrieved for verification. Clearly, this additional read-back operation increases the time spent on SRAM data reading, reduces SRAM access speed, and makes SRAM response slower. Summary of the Invention

[0005] This application provides a storage controller, storage system, and electronic device to improve SRAM access speed and enhance SRAM response speed.

[0006] To achieve the above objectives, the technical solutions provided in this application are as follows: A first aspect of this application provides a storage controller, the storage controller comprising: an error location unit, a data processing unit, and an error correction unit; The error location unit is connected to the processor, the memory and the data processing unit respectively. When the processor outputs a first read instruction, it reads the first data to be read from the memory as indicated by the first read instruction, performs error byte location on the first data to obtain a location result, and sends the error byte address of the error byte to the processor and the data processing unit when the location result indicates that there is an error byte in the first data. The data processing unit is connected to the processor and the error correction unit, and is used to receive a first write instruction output by the processor for the erroneous byte address, and send the correct byte corresponding to the erroneous byte address and the erroneous byte address included in the first write instruction to the error correction unit; The error correction unit is connected to the processor and the memory respectively, and is used to perform ECC encoding on the correct byte, obtain and write the correction code to the memory; and to receive a second read instruction output by the processor, and when the second read instruction includes the address of the error byte, read the error byte corresponding to the error byte address and the correction code from the memory, and correct the error byte according to the correction code to obtain the correct byte; The data processing unit is further configured to receive the second read instruction, and if the read address included in the second read instruction contains the erroneous byte address, obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit, and output the correct byte to the processor.

[0007] Optionally, the error location unit is further configured to receive a second write instruction output by the processor, perform error detection and verification encoding on each byte of the data to be written included in the second write instruction to obtain an error detection code for each byte, and write the data to be written and the error detection code for each byte into the memory. The first data is at least one byte in the data to be written; the error location unit is further configured to read the error detection code corresponding to the first data from the memory, and perform error detection verification and decoding on the first data according to the error detection code to obtain the location result.

[0008] Optionally, the error location unit is further configured to perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain an error detection code for each byte; The error location unit is further configured to perform parity check decoding on the first data according to the error detection code to obtain the location result.

[0009] Optionally, the error location unit includes a first encoding module and a first decoding module; The first encoding module is connected to the processor and the memory, and is used to receive the second write instruction output by the processor, perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code of each byte, and write the data to be written and the error detection code of each byte into the memory. The first decoding module is connected to the memory and the data processing unit, and is used to read the first data to be read as indicated by the first read instruction and the error detection code corresponding to the first data from the memory in response to the first read instruction output by the processor, and to perform parity check decoding on the first data according to the error detection code to obtain the positioning result. If the positioning result indicates that there is an error byte in the first data, the module sends the error byte address of the error byte to the processor and the data processing unit.

[0010] Optionally, the data processing unit receives the first read instruction and, if it determines that the read address included in the first read instruction does not contain an erroneous byte address, outputs the read address included in the first read instruction to the error location unit. The error location unit is used to read the first data corresponding to the read address included in the first read instruction from the memory, and to perform error byte verification on the first data to obtain a location result. If the location result indicates that there is an error byte in the first data, the unit sends the error byte address of the error byte to the processor and the data processing unit.

[0011] Optionally, the error location unit is further configured to send the first data to the data processing unit when the location result indicates that the first data does not contain any error bytes; The data processing unit is also used to output the first data corresponding to the first read instruction to the processor.

[0012] Optionally, the second read instruction is used to read at least two bytes, including the erroneous byte; The data processing unit is further configured to, upon receiving the second read instruction, output the target read address of the second read instruction to the error location unit, wherein the target read address is the byte address excluding the error byte address among the read addresses included in the second read instruction; The error location unit is further configured to read the second data corresponding to the target read address from the memory, perform error byte verification on the second data to obtain a location result, and send the second data to the data processing unit if the location result indicates that there are no error bytes in the second data; The data processing unit is also used to output the correct byte and the second data to the processor.

[0013] Optionally, the data processing unit includes: an address selection unit and a data selection unit; The address selection unit is connected to the processor, the misalignment location unit, and the error correction unit, and is used to receive the error byte address sent by the error location unit; and to receive the first write instruction output by the processor, and send the correct byte corresponding to the error byte address included in the first write instruction and the error byte address to the error correction unit; The data selection unit is connected to the processor, the misalignment location unit, and the error correction unit, and is used to receive the erroneous byte address sent by the error location unit; and to receive the second read instruction, and if it is determined that the read address included in the second read instruction contains the erroneous byte address, to obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit, and to output the correct byte to the processor.

[0014] Optionally, the error correction unit includes: a second encoding module and a second decoding module; The second encoding module is connected to the address selection unit and the memory, and is used to receive the correct byte corresponding to the erroneous byte address sent by the address selection unit, perform ECC encoding on the correct byte, and obtain and write the correction code to the memory; The second decoding module is connected to the processor, the memory, and the data selection unit. It is used to receive a second read instruction output by the processor. If the second read instruction includes the error byte address, it reads the error byte corresponding to the error byte address and the correction code from the memory, corrects the error byte according to the correction code to obtain the correct byte, and sends the correct byte to the data selection unit.

[0015] A second aspect of this application provides a storage system, characterized in that the storage system includes a processor, a memory, and a storage controller as described in any of the first aspects.

[0016] Optionally, the storage system further includes an AHB bus, through which the processor is connected to the storage controller.

[0017] A third aspect of this application provides an electronic device, the electronic device including any of the storage systems described in the second aspect.

[0018] In this embodiment, the error location unit in the storage controller is connected to the processor, the memory, and the data processing unit. The error location unit, when the processor outputs a first read instruction, reads the first data to be read as indicated by the first read instruction from the memory, performs error byte verification on the first data to obtain a location result, and then, if the location result indicates that the first data contains an error byte, sends the error byte address to the processor and the data processing unit. The data processing unit receives a first write instruction output by the processor for the error byte address, and sends the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit, so that the error correction unit can perform ECC encoding on the correct byte, obtain and write a correction code to the memory, thereby generating a correction code for a single byte. Furthermore, the error correction unit also receives a second read instruction output by the processor, and, if the second read instruction includes an error byte address, reads the error byte corresponding to the error byte address and the correction code from the memory, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit and output the correct byte to the processor.

[0019] In this technical solution, an error location unit performs error byte location on the read first data to quickly locate erroneous bytes and determine their addresses. Correspondingly, an error correction unit performs ECC encoding on the correct byte corresponding to the received error byte address to obtain a correction code. Therefore, when the processor needs to read data at the error byte address, the error correction unit can correct only the error byte at that address using the correction code to obtain the correct byte. This allows the data processing unit, upon receiving a read instruction from the processor including the error byte address, to directly obtain the correct byte corresponding to the error byte address corrected by the error correction unit and return the correct byte to the processor. This effectively ensures the accuracy of data reads by the processor, significantly improves memory access speed, and addresses the issue of slow memory response speed. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1This is a schematic diagram of the structure of a storage controller provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an error location unit of a storage controller provided in an embodiment of this application; Figure 3 This is a connection diagram of a storage controller provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a data processing unit of a storage controller provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an error correction unit of a storage controller provided in an embodiment of this application; Figure 6 This is a schematic diagram of the data flow of a processor write operation of a storage controller provided in an embodiment of this application; Figure 7 This is a schematic diagram of the data flow of a processor read operation of a storage controller according to an embodiment of this application; Figure 8 This is a schematic diagram of the data flow of the processor's first write instruction in a memory controller according to an embodiment of this application; Figure 9 This is a schematic diagram of the data flow of the processor's second read instruction in a memory controller provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0027] Please refer to Figure 1 This illustrates a schematic diagram of the structure of a storage controller provided in an embodiment of this application. Figure 1 As shown, the storage controller includes: an error location unit 1, a data processing unit 2, and an error correction unit 3.

[0028] Error location unit 1 is connected to processor 4, memory 5, and data processing unit 2. When processor 4 outputs a first read instruction, error location unit 1 reads the first data to be read as indicated by the first read instruction from memory 5, performs error byte location on the first data to obtain a location result, and sends the error byte address of the error byte to processor 4 and data processing unit 2 if the location result indicates that the first data contains an error byte. The first read instruction is used to read the first data.

[0029] Data processing unit 2 is connected to processor 4 and error correction unit 3. Data processing unit 2 receives a first write instruction output by processor 4 for an erroneous byte address, and sends the correct byte corresponding to the erroneous byte address and the erroneous byte address included in the first write instruction to error correction unit 3. The first write instruction is used to write correct data, including the correct byte corresponding to the erroneous byte address.

[0030] Error correction unit 3 is connected to processor 4 and memory 5 respectively. Error correction unit 3 is used to perform ECC encoding on correct bytes, obtain and write correction codes to memory 5. Error correction unit 3 is also used to receive a second read instruction output by processor 4. If the second read instruction includes the address of an erroneous byte, it reads the erroneous byte corresponding to the erroneous byte address and the correction code from memory 5, and corrects the erroneous byte according to the correction code to obtain the correct byte. The second read instruction is used to read data.

[0031] The data processing unit 2 is also used to receive a second read instruction, and if the read address included in the second read instruction contains an erroneous byte address, to obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit 3, and to output the correct byte to the processor 4.

[0032] In an optional embodiment of this application, when the processor 4 outputs a first read instruction to read first data, the error location unit 1 can read the first data corresponding to the read address included in the first read instruction from the memory 5, and perform error byte location on the first data to obtain a location result. The location result indicates whether the data of each byte included in the first data is error-free, so that if a certain byte of data is determined to be erroneous, that byte is determined to be an erroneous byte. That is, the location result indicates whether the first data includes an erroneous byte, and an erroneous byte refers to a byte of data with errors.

[0033] Error location unit 1 is used to send the address of the erroneous byte in the first data to processor 4 and data processing unit 2 when the location result indicates that there is an erroneous byte in the first data. The erroneous byte address indicates the storage location of the erroneous byte in memory 5. Optionally, error location unit 1 is also used to return the first data to processor 4 when the location result indicates that there is no erroneous byte in the first data, that is, all bytes of the first data are correct bytes. A correct byte refers to a byte that is error-free.

[0034] Upon receiving one or more erroneous byte addresses, processor 4 can trigger interrupt handling to generate a first write instruction and send it to the data processing unit 2 of the memory controller. The first write instruction includes at least the correct byte corresponding to the erroneous byte address, and the erroneous byte address itself. It should be noted that the data read / write instructions (including read and write instructions) between processor 4 and the memory controller can include word (32-bit), byte (8-bit), or half-word (16-bit) data read / write instructions. Therefore, the data bit width between processor 4 and the memory controller can be 32-bit, 8-bit, or 16-bit. The first write instruction includes the correct byte corresponding to the erroneous byte address, so that the data at the erroneous byte address is rewritten.

[0035] Upon receiving the first write instruction from the processor 4 for the erroneous byte address, the data processing unit 2 sends the correct byte corresponding to the erroneous byte address and the erroneous byte address included in the first write instruction to the error correction unit 3. This allows the error correction unit 3 to perform ECC encoding on the correct byte and obtain and write the correction code to the memory 5.

[0036] When processor 4 triggers a read data again, processor 4 can simultaneously output a second read instruction to data processing unit 2 and error correction unit 3. The second read instruction includes the second data to be read and the address of the second data.

[0037] Upon receiving a second read instruction from the processor 4, the error correction unit 3 can match the read address included in the second read instruction with the address of the erroneous byte received from the data processing unit 2. If it is determined that the second read instruction includes an erroneous byte address, the error byte corresponding to the erroneous byte address and the correction code are read from the memory 5, and the erroneous byte is corrected according to the correction code to obtain the correct byte. Optionally, the correction code may include Hamming code, BCH code, or convolutional code, etc.

[0038] When data processing unit 2 receives the second read instruction from processor 4, it matches the read address included in the second read instruction with the erroneous byte address received from error location unit 1. If the read address included in the second read instruction contains the erroneous byte address, it retrieves the correct byte corresponding to the erroneous byte address corrected by error correction unit 3 and outputs the correct byte to processor 4. It is easy to understand that processor 4 takes two cycles to access memory 5. In the first cycle, processor 4 simultaneously outputs the second read instruction to data processing unit 2 and error correction unit 3. In the second cycle, if error correction unit 3 determines that the second read instruction includes the erroneous byte address, it reads the erroneous byte corresponding to the erroneous byte address and the correction code from memory 5, and corrects the erroneous byte to obtain the correct byte based on the correction code. If data processing unit 2 determines that the second read instruction includes the erroneous byte address, it can directly retrieve the correct byte corresponding to the erroneous byte address corrected by error correction unit 3 and output the correct byte to processor 4.

[0039] Obviously, in the storage controller provided in this application embodiment, after receiving a read instruction from the processor 4 to the memory 5, the data processor 4 can complete the data read operation in two clock cycles, enabling the processor 4 to receive accurate read data. Compared with related technologies, this significantly improves the access speed of the memory 5 and reduces the slow response speed of the memory 5.

[0040] In this embodiment, the error location unit 1 in the storage controller is connected to the processor 4, the memory 5, and the data processing unit 2. The error location unit 1 is used to read the first data to be read from the memory 5 when the processor 4 outputs a first read instruction, and to perform error byte verification on the first data to obtain a location result; then, if the location result indicates that the first data contains an error byte, it sends the error byte address of the error byte to the processor 4 and the data processing unit 2. The data processing unit 2 is used to receive the first write instruction output by the processor 4 for the error byte address, and send the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit 3, so that the error correction unit 3 can perform ECC encoding on the correct byte, obtain and write a correction code to the memory 5, thereby realizing the generation of a correction code for a single byte. Furthermore, the error correction unit 3 is also used to receive the second read instruction output by the processor 4, and if the second read instruction includes an error byte address, to read the error byte corresponding to the error byte address and the correction code from the memory 5, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit 2 to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit 3 and output the correct byte to the processor 4.

[0041] In this technical solution, the error location unit 1 locates the erroneous bytes in the first data being read, quickly identifying the erroneous bytes and determining their addresses. Correspondingly, the error correction unit 3 performs ECC encoding on the correct byte corresponding to the received erroneous byte address to obtain a correction code. Therefore, when the processor 4 needs to read data from the erroneous byte address, the error correction unit 3 can correct only the erroneous byte at that address using the correction code to obtain the correct byte. This allows the data processing unit 2, upon receiving a read instruction from the processor 4 including the erroneous byte address, to directly obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit 3 and return the correct byte to the processor 4. This effectively ensures the accuracy of data read by the processor 4, significantly improves the access speed of the memory 5, and addresses the relatively slow response speed of the memory 5.

[0042] Optionally, the error location unit 1 is further configured to receive the second write instruction output by the processor 4, perform error detection and verification encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code of each byte, and write the data to be written and the error detection code of each byte into the memory 5.

[0043] When processor 4 needs to read the first data stored in memory 5, processor 4 outputs a first read instruction. The first data is at least one byte of the data to be written to memory 5 by error location unit 1. Error location unit 1 is also used to read the first data to be read as indicated by the first read instruction from memory 5 when processor 4 outputs the first read instruction, and to read the error detection code corresponding to the first data from memory 5, and to perform error detection verification and decoding on the first data according to the error detection code to obtain the location result.

[0044] In an optional embodiment, the error location unit 1 can be used to perform error detection and verification encoding on each byte of the data to be written included in the second write instruction, generating a corresponding error detection code for each byte of the data to be written, and then writing the data to be written and the error detection code corresponding to each byte into the memory 5. Since the error location unit 1 can generate an independent error detection code for each byte, when reading data, the error detection code corresponding to each byte can be used to independently verify whether the data of the byte is error-free, thereby enabling the rapid location of erroneous bytes in the read data, improving the efficiency of erroneous byte location, effectively identifying erroneous data in the memory 5, and reducing the risk of erroneous data being transmitted to the processor 4. In some embodiments, the error detection and verification encoding can be parity check encoding, XOR check encoding, or redundancy check encoding, etc. Correspondingly, the error detection and verification decoding can be parity check decoding, XOR check decoding, or redundancy check decoding, etc.

[0045] In an optional configuration, the error location unit 1 is further configured to receive a second write instruction output by the processor 4, perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain an error detection code for each byte, and write the data to be written and the error detection code for each byte into the memory 5.

[0046] Optionally, the error location unit 1 is further configured to read the first data to be read as indicated by the first read instruction from the memory 5 when the processor 4 outputs the first read instruction, and read the error detection code corresponding to the first data from the memory 5, and perform parity check decoding on the first data according to the error detection code to obtain the location result, so as to send the error byte address of the error byte to the processor 4 and the data processing unit 2 when the location result indicates that there is an error byte in the first data.

[0047] Since parity checking is 1-bit, error location unit 1 performs parity checking on each byte of data to be written in the second write instruction, obtaining a 1-bit error detection code for each byte. This code is used to check if the byte data is erroneous, thus locating the erroneous byte. Because each byte has a 1-bit error correction code under parity checking, the 32-bit data in memory 5 only has a 4-bit error correction code. This effectively reduces the amount of error correction code data in memory 5, decreases the memory required to store the error correction code, and saves storage space. Furthermore, since the error data for 32-bit data in memory 5 is typically 1 bit, meaning there is usually only one erroneous byte in the 32-bit data, and the minimum width of the correction code obtained from ECC encoding is 4 bits, the minimum check code (a collective term for error correction code and correction code) for 32-bit data in memory 5 can be 4+4 bits. Obviously, compared with the scheme of using ECC encoding for data verification of each byte, this application can significantly reduce the amount of data of the check code, reduce the memory required to store the error correction code in memory 5, and save the storage area in memory 5 used to store the error correction code.

[0048] In some embodiments, such as Figure 2 As shown, the error location unit 1 includes a first encoding module 11 and a first decoding module 12. The first encoding module 11 is connected to the processor 4 and the memory 5, and is used to receive a second write instruction output by the processor 4, perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain an error detection code for each byte, and write the data to be written and the error detection codes for each byte into the memory 5. The first decoding module 12 is connected to the memory 5 and the data processing unit 2, and is used to respond to a first read instruction output by the processor 4, read the first data to be read as indicated by the first read instruction from the memory 5, and the error detection code corresponding to the first data, and perform parity check decoding on the first data according to the error detection code to obtain a location result. If the location result indicates that there is an error byte in the first data, it sends the error byte address of the error byte to the processor 4 and the data processing unit 2.

[0049] The first encoding module 11 and the first decoding module 12 work together to locate erroneous bytes in the read first data, quickly identifying erroneous bytes and determining their addresses. This allows subsequent error correction of the first data to focus solely on correcting erroneous bytes, improving the speed of error correction and consequently increasing the access speed of the memory 5.

[0050] In an optional embodiment, upon receiving a second write instruction output by the processor, the first encoding module 11 performs parity check encoding on each byte of the data to be written included in the second write instruction to obtain an error detection code for each byte, and stores the data to be written and the error detection codes for each byte. The first decoding module 12 reads the first data corresponding to the first read instruction and the corresponding error detection code from the data SRAM, and performs parity check decoding on the first data corresponding to the target read address based on the error detection code to obtain a location result. If the location result indicates that there is an error byte in the first data corresponding to the first read instruction, the first decoding module 12 sends the error byte address of the error byte to the processor 4 and the data processing unit 2.

[0051] In some embodiments of this application, the data processing unit 2 is used to receive a first read instruction and, if it is determined that the read address included in the first read instruction does not contain an error byte address, output the read address included in the first read instruction to the error location unit 1.

[0052] Error location unit 1 is used to read the first data corresponding to the read address included in the first read instruction from memory 5, and to perform error byte verification on the first data to obtain the location result. If the location result indicates that there is an error byte in the first data, it sends the error byte address of the error byte to processor 4 and data processing unit 2.

[0053] When processor 4 needs to read the first data stored in memory 5, processor 4 outputs a first read instruction. Data processing unit 2 receives the first read instruction from processor 4 and judges the read address included in the first read instruction based on the stored error byte address to determine whether the first read instruction includes an error byte address. If the first read instruction includes a read address but does not include an error byte address, data processing unit 2 outputs the read address included in the first read instruction to error location unit 1. This excludes known error byte addresses and prevents repeated reading and correction of error bytes. When error location unit 1 reads the first data from memory 5 according to the read address included in the first read instruction, it can use the error detection code corresponding to each byte to independently verify whether the data of each byte is error-free, thereby enabling rapid location of error bytes in the read data, improving the efficiency of error byte location, effectively identifying erroneous data in memory 5, and reducing the risk of erroneous data being transmitted to the processor. After error byte verification, the location result is obtained, and error location unit 1 finds the error byte address based on the error byte. Error location unit 1 sends the error byte address of the error byte to processor 4 and data processing unit 2. This precise location of the error byte provides the error byte address for subsequent error correction.

[0054] In an optional embodiment, the data processing unit 2 receives a first read instruction from the processor 4. The data processing unit 2 determines that the first read instruction does not include the error byte address based on the stored error byte address. The data processing unit 2 outputs the first read instruction to the error location unit 1. The error location unit 1 reads the first data corresponding to the first read instruction from the memory 5 according to the received first read instruction from the data processing unit 2, and reads the error detection code corresponding to the first data from the memory 5. Based on the error detection code corresponding to each byte, it independently verifies whether the data of each byte is error-free, thereby enabling rapid location of error bytes in the read data, improving the efficiency of error byte location, and effectively identifying erroneous data in the memory 5. The error location unit 1 performs error byte verification on the first data to obtain the location result. The error location unit 1 finds the error byte address based on the error byte and sends the error byte address of the error byte in the first data to the processor 4 and the data processing unit 2. The error byte address indicates the storage location of the error byte in the memory 5. This process locates possible error bytes in the first data, providing error byte addresses for subsequent error correction.

[0055] Optionally, the error location unit 1 is further configured to send the first data to the data processing unit 2 if the location result indicates that the first data does not contain an error byte. The data processing unit 2 is further configured to output the first data corresponding to the first read instruction to the processor 4.

[0056] If the error location unit 1 indicates that there are no erroneous bytes in the first data, it means that the first data is correct and does not need to be corrected by the error correction unit 3 to read the first data normally. Therefore, the error location unit 1 can send the first data to the processor 4 through the data processing unit 2 to achieve effective reading of the first data.

[0057] In an optional embodiment, after receiving the first read instruction from the processor 4, the data processing unit 2 outputs the first read instruction to the error location unit 1. The error location unit 1 reads the first data corresponding to the first read instruction from the memory 5 according to the first read instruction, performs error byte verification on the first data to obtain a location result. If the location result indicates that there are no error bytes after verification, it means that the first data is correct and does not need to be corrected by the error correction unit 3. The first data in the memory 5 is then read normally. The first data is then sent to the processor 4 through the data processing unit 2.

[0058] Optionally, the second read instruction is used to read at least two bytes, including the erroneous byte. The data processing unit 2 is further configured to, upon receiving the second read instruction and if the read address included in the second read instruction contains the address of the erroneous byte, obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit 3, and output the correct byte to the processor; and output the target read address of the second read instruction to the error location unit 1, wherein the target read address is the address of the byte in the read address included in the second read instruction excluding the address of the erroneous byte.

[0059] Error location unit 1 is also used to read the second data corresponding to the target read address from memory 5, and perform error byte verification on the second data to obtain a byte verification result. If the byte verification result indicates that there are no error bytes in the second data, the second data is sent to data processing unit 2.

[0060] The data processing unit 2 is also used to output the correct byte and the second data to the processor 4 to return all the bytes to be read as indicated by the second read instruction to the processor 4.

[0061] In an optional embodiment, when the data processing unit 2 receives a second read instruction from the processor 4, it matches the read address included in the second read instruction with the error byte address received from the error location unit 1 to determine whether the read address includes the error byte address.

[0062] If the read address included in the second read instruction only includes the address of the erroneous byte, the data processing unit 2 obtains the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit 3, and outputs the correct byte to the processor.

[0063] If the second read instruction includes only the target read address, the data processing unit 2 outputs the target read address of the second read instruction to the error location unit 1. The error location unit 1 reads the second data corresponding to the target read address from the memory 5 and performs error byte verification on the second data to obtain a byte verification result. If the byte verification result indicates that there are no error bytes in the second data, the second data is sent to the data processing unit 2. The data processing unit 2 is also used to output the second data to the processor 4.

[0064] When the read address included in the second read instruction includes both the erroneous byte address and the target read address, the data processing unit 2 obtains the correct byte corresponding to the erroneous byte address corrected by the error correction unit 3 and outputs the correct byte to the processor; and outputs the target read address of the second read instruction to the error location unit 1. The error location unit 1 reads the second data corresponding to the target read address from the memory 5 and performs error byte verification on the second data to obtain a byte verification result. If the byte verification result indicates that the second data does not contain an erroneous byte, the second data is sent to the data processing unit 2. The data processing unit 2 is also used to output the correct byte and the second data to the processor 4. The error correction unit 3 corrects the erroneous byte address according to the correction code to obtain the correct byte, so that when the data processing unit 2 receives a read instruction from the processor 4 including the erroneous byte address, it can directly obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit 33 and return the correct byte to the processor 4.

[0065] Optionally, such as Figure 4 As shown, the data processing unit 2 includes an address selection unit 21 and a data selection unit 22. The address selection unit 21 is connected to the processor 4, the misalignment location unit, and the error correction unit 33, and is used to receive the erroneous byte address sent by the error location unit 1. It also receives the first write instruction output by the processor 4 and sends the correct byte and the erroneous byte address corresponding to the erroneous byte address included in the first write instruction to the error correction unit 33.

[0066] The data selection unit 22 is connected to the processor 4, the misalignment location unit, and the error correction unit 33. It is used to receive the erroneous byte address sent by the error location unit 1. It is also used to receive a second read instruction, and if it is determined that the read address included in the second read instruction contains the erroneous byte address, to obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit 33, and output the correct byte to the processor 4.

[0067] In an optional embodiment, when the processor outputs a first write instruction for an erroneous byte address, the address selection unit 21 sends the correct byte and the erroneous byte address corresponding to the erroneous byte address included in the first write instruction to the error correction unit 33. Upon receiving the correct byte and the erroneous byte address, the error correction unit 33 performs ECC encoding on the correct byte to obtain the correction code corresponding to the erroneous byte address and writes the correction code to the ECC verification SRAM. When the processor 4 outputs a second read instruction to the error correction unit 33 and the data selection unit 22 via the AHB bus, the error correction unit 33 receives the second read instruction output by the processor 4. It matches the read address included in the second read instruction with the erroneous byte address. If the read address included in the second read instruction contains the erroneous byte address, the error correction unit 33 reads the erroneous byte and the correction code corresponding to the erroneous byte address from the memory 5 and corrects the erroneous byte according to the correction code to obtain the correct byte. After receiving the second read instruction output by the processor 4, the data selection unit 22 matches the read address included in the second read instruction with the address of the erroneous byte. If the read address included in the second read instruction contains an erroneous byte, the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit 33 is obtained, and the correct byte is output to the processor 4.

[0068] In this way, the address selection unit 21 is connected to the processor 4, the misalignment location unit, and the error correction unit 33. The address selection unit 21 receives the erroneous byte address sent by the error location unit 1 and the first write instruction output by the processor 4. After receiving the first write instruction, the address selection unit 21 sends the first write instruction and the erroneous byte address to the error correction unit 33. The first write instruction includes the correct byte corresponding to the erroneous byte address. Data reception and transmission are performed through the address selection unit 21, enabling data transmission between the processor 4, the misalignment location unit, and the error correction unit 33, thereby improving processing speed. The data selection unit 22 is connected to the processor 4, the misalignment location unit, and the error correction unit 33. The data selection unit 22 receives the erroneous byte address sent by the error location unit 1 and stores the erroneous byte address. After receiving the second read instruction output by the processor 4, the data selection unit 22 matches the read address included in the second read instruction with the erroneous byte address. If the read address included in the second read instruction contains an erroneous byte, the data selection unit 22 obtains the correct byte corresponding to the erroneous byte address corrected by the error correction unit 33 and outputs the correct byte to the processor 4. After the data selection unit 22 obtains the corrected data from the error correction unit 33, it transmits it to the processor 4, ensuring that the processor 4 can finally receive the corrected data, thus enhancing the system reliability.

[0069] In some embodiments, such as Figure 5As shown, the error correction unit 33 includes a second encoding module 31 and a second decoding module 32. The second encoding module 31 is connected to the address selection unit 21 and the memory 5, and is used to receive the correct byte corresponding to the erroneous byte address sent by the address selection unit 21, perform ECC encoding on the correct byte, and write a correction code to the memory 5. The second decoding module 32 is connected to the processor 4, the memory 5, and the data selection unit 22, and is used to receive a second read instruction output by the processor 4. If the second read instruction includes an erroneous byte address, it reads the erroneous byte corresponding to the erroneous byte address and the correction code from the memory 5, corrects the erroneous byte according to the correction code to obtain the correct byte, and sends the correct byte to the data selection unit 22.

[0070] The second encoding module 31 is connected to the address selection unit 21 and the memory 5. The second encoding module 31 receives the correct byte corresponding to the erroneous byte address sent by the address selection unit 21. The second encoding module 31 performs ECC encoding on the correct byte and writes the correction code generated by the ECC encoding of the correct byte into the memory 5. At this time, only the correction code is generated by the second encoding module 31; the erroneous byte is not corrected. When the second read instruction output by the processor 4 contains the erroneous byte address, the second decoding module 32 corrects the erroneous byte according to the correction code to obtain the correct byte and sends the correct byte to the data selection unit 22. Correcting the erroneous byte address only when the second read instruction contains it avoids correcting the erroneous byte address when it is not present, thus improving the response speed of the memory controller.

[0071] In an optional embodiment, upon receiving a first write instruction from the processor 4, the address selection unit 21 sends the correct byte corresponding to the erroneous byte address included in the first write instruction to the second encoding module 31, and sends the erroneous byte address to the second decoding module 32. The second encoding module 31 receives the correct byte corresponding to the erroneous byte address sent by the address selection unit 21, performs ECC encoding on the correct byte, and obtains a 5-bit correction code corresponding to the correct byte. The 5-bit correction code of the correct byte corresponding to the erroneous byte address is written into the ECC check SRAM. The processor 4 synchronously outputs a second read instruction to the data selection unit 22 and the second decoding module 32 of the memory controller via the AHB bus. The second decoding module 32 receives the second read instruction from the processor 4, matches the read address included in the second read instruction with the erroneous byte address, and if the second read instruction contains an erroneous byte address, reads the erroneous byte corresponding to the erroneous byte address from the memory 5 and reads the correction code from the ECC check memory 5. The correct byte is obtained by correcting the erroneous byte according to the correction code and sent to the data selection unit 22.

[0072] In this embodiment, the error location unit in the storage controller is connected to the processor, the memory, and the data processing unit. The error location unit, when the processor outputs a first read instruction, reads the first data to be read as indicated by the first read instruction from the memory, performs error byte verification on the first data to obtain a location result, and then, if the location result indicates that the first data contains an error byte, sends the error byte address of the error byte to the processor and the data processing unit. The data processing unit receives a first write instruction output by the processor for the error byte address, and sends the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit, so that the error correction unit can perform ECC encoding on the correct byte, obtain and write a correction code to the memory, thereby achieving correction code generation for a single byte. Furthermore, the error correction unit also receives a second read instruction output by the processor, and, if the second read instruction includes an error byte address, reads the error byte corresponding to the error byte address and the correction code from the memory, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit and output the correct byte to the processor.

[0073] In this technical solution, an error location unit performs error byte location on the read first data to quickly locate erroneous bytes and determine their addresses. Correspondingly, an error correction unit performs ECC encoding on the correct byte corresponding to the received error byte address to obtain a correction code. Therefore, when the processor needs to read data at the error byte address, the error correction unit can correct only the error byte at that address using the correction code to obtain the correct byte. This allows the data processing unit, upon receiving a read instruction from the processor including the error byte address, to directly obtain the correct byte corresponding to the error byte address corrected by the error correction unit and return the correct byte to the processor. This effectively ensures the accuracy of data reads by the processor, significantly improves memory access speed, and addresses the issue of slow memory response speed.

[0074] To facilitate a further understanding of the technical solution of this application, the following example further illustrates the memory controller provided in the embodiments of this application. For example, assume that memory 5 is SRAM. Figure 3As shown, the storage system includes a processor 4, an AHB bus, a storage controller, and a memory 5. Memory 5 includes two storage areas: a data SRAM and an ECC check SRAM. The AHB bus has a 32-bit read / write data width; the data SRAM has a 36-bit read / write data width; and the ECC check SRAM has a 5-bit read / write data width, meaning the correction code has a 5-bit width.

[0075] The storage controller includes an error location unit 1, a data processing unit 2, and an error correction unit 3. The error location unit 1 includes a first encoding module 11 and a first decoding module 12; for example... Figure 4 As shown, the data processing unit 2 includes an address selection unit 21 and a data selection unit 22; as Figure 5 As shown, the error correction unit 3 includes a second encoding module 31 and a second decoding module 32.

[0076] When processor 4 needs to write to memory 5, such as Figure 6 As shown, a second write instruction (AHB write data) is generated and output to the first encoding module 11 of the storage controller via the AHB bus. The second write instruction includes 32 bits of data to be written.

[0077] In the storage controller, upon receiving the second write instruction output by the processor 4, the first encoding module 11 performs parity check encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code for each byte, and writes the data to be written and the error detection codes of each byte (data SRAM write data) into the data SRAM. The total bit width of the data to be written and the error detection codes of each byte is 8+1+8+1+8+1+8+1 (36) bits.

[0078] When processor 4 needs to perform a read operation on memory 5, such as Figure 7 As shown, a first read instruction is generated and output to the data selection unit 22 of the storage controller via the AHB bus (AHB write data). The first read instruction includes the read address of the first data to be read.

[0079] In the storage controller, the data selection unit 22 matches the read address included in the first read instruction with the error byte address to determine that the read address included in the first read instruction does not contain the error byte address. The data selection unit 22 outputs the read address included in the first read instruction to the first decoding module 12, so that the first decoding module 12 reads the first data to be read as indicated by the first read instruction from the data SRAM, as well as the error detection code corresponding to the first data (data SRAM read data), and performs parity check decoding on the first data according to the error detection code to obtain the positioning result.

[0080] If the positioning result indicates that there is no erroneous byte in the first data, the data selection unit 22 outputs the first data to the processor 4, so that the data selection unit 22 outputs the first data (AHB read data). If the positioning result indicates that there is an erroneous byte in the first data, the data selection unit 22 sends the erroneous byte address and parity error flag to the processor 4 and the address selection unit 21.

[0081] like Figure 8 As shown, after receiving one or more erroneous byte addresses, processor 4 can trigger interrupt processing to generate a first write instruction and send the first write instruction to the address selection unit 21 of the memory controller. The first write instruction includes at least the correct byte corresponding to the erroneous byte address and the erroneous byte address.

[0082] In the memory controller, upon receiving a first write instruction from the processor 4, the address selection unit 21 sends the correct byte corresponding to the erroneous byte address included in the first write instruction to the second encoding module 31, and sends the erroneous byte address to the second decoding module 32. After receiving the correct byte corresponding to the erroneous byte address sent by the address selection unit 21, the second encoding module 31 performs ECC encoding on the correct byte to obtain the correction code corresponding to the erroneous byte address, and writes the correction code corresponding to the erroneous byte address into the ECC check SRAM.

[0083] If processor 4 performs another read operation, such as Figure 9 As shown, a second read instruction is generated and synchronously output to the data selection unit 22 of the storage controller and the second decoding module 32 via the AHB bus. The second read instruction includes the read address of the 32 bits of second data to be read.

[0084] In the storage controller, upon receiving a second read instruction, the second decoding module 32 matches the read address included in the second read instruction with the address of the erroneous byte. If the read address included in the second read instruction contains the address of the erroneous byte, it reads the correction code corresponding to the erroneous byte address from the ECC check SRAM and the erroneous byte corresponding to the erroneous byte address from the data SRAM. Then, the second encoding module 31 corrects the read erroneous byte according to the correction code to obtain the correct byte and sends the correct byte to the data selection unit 22.

[0085] Upon receiving the second read instruction, the data selection unit 22 matches the read address included in the second read instruction with the erroneous byte address. If the read address included in the second read instruction contains the erroneous byte address, it directly obtains the correct byte (8 bits) corresponding to the erroneous byte address transmitted by the second decoding module 32. Furthermore, it outputs the target read address of the second read instruction to the first decoding module 12. This target read address is the byte address in the read address included in the second read instruction, excluding the erroneous byte address.

[0086] The first decoding module 12 reads the second data (24 bits) corresponding to the target read address and the corresponding error detection code from the data SRAM, and performs parity check decoding on the second data corresponding to the target read address according to the error detection code to obtain the positioning result.

[0087] If the positioning result indicates that the second data corresponding to the target read address does not contain an error byte, the first decoding module 12 outputs the second data corresponding to the target read address to the data selection unit 22, so that the data selection unit 22 outputs the second data corresponding to the target read address and the correct byte corresponding to the error byte address to the processor 4. If the positioning result indicates that the second data corresponding to the target read address contains an error byte, the first decoding module 12 sends the error byte address of the error byte to the processor 4 and the address selection unit 21, and repeats the aforementioned steps.

[0088] It is easy to understand that the processor 4 takes a total of two cycles to access the memory 5. In the first cycle, if a read operation is performed again, the processor 4 generates a second read instruction and synchronously outputs the second read instruction to the data selection unit 22 of the memory controller and the second decoding module 32 via the AHB bus. The second read instruction includes the read address of the 32 bits of second data to be read.

[0089] During the second cycle, in the storage controller, upon receiving a second read instruction, the second decoding module 32 matches the read address included in the second read instruction with the erroneous byte address. If it determines that the read address included in the second read instruction contains the erroneous byte address, it reads the correction code corresponding to the erroneous byte address from the ECC check SRAM and reads the erroneous byte corresponding to the erroneous byte address from the data SRAM. Then, the second encoding module 31 corrects the read erroneous byte according to the correction code to obtain the correct byte and sends the correct byte to the data selection unit 22.

[0090] Upon receiving a second read instruction, the data selection unit 22 matches the read address included in the second read instruction with the error byte address. If the read address included in the second read instruction contains an error byte address, it directly obtains the correct byte corresponding to the error byte address transmitted by the second decoding module 32. Furthermore, it outputs the target read address of the second read instruction to the first decoding module 12. This target read address is the byte address in the read address included in the second read instruction, excluding the error byte address. The first decoding module 12 reads the second data corresponding to the target read address and the corresponding error detection code from the data SRAM, and performs parity check decoding on the second data corresponding to the target read address based on the error detection code to obtain the location result. If the location result indicates that the second data corresponding to the target read address does not contain an error byte, the first decoding module 12 outputs the second data corresponding to the target read address to the data selection unit 22, so that the data selection unit 22 outputs the second data corresponding to the target read address and the correct byte corresponding to the error byte address to the processor 4.

[0091] In this embodiment, the error location unit in the storage controller is connected to the processor, the memory, and the data processing unit. The error location unit, when the processor outputs a first read instruction, reads the first data to be read as indicated by the first read instruction from the memory, performs error byte verification on the first data to obtain a location result, and then, if the location result indicates that the first data contains an error byte, sends the error byte address to the processor and the data processing unit. The data processing unit receives a first write instruction output by the processor for the error byte address, and sends the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit, so that the error correction unit can perform ECC encoding on the correct byte, obtain and write a correction code to the memory, thereby generating a correction code for a single byte. Furthermore, the error correction unit also receives a second read instruction output by the processor, and, if the second read instruction includes an error byte address, reads the error byte corresponding to the error byte address and the correction code from the memory, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit and output the correct byte to the processor.

[0092] In this technical solution, an error location unit performs error byte location on the read first data to quickly locate erroneous bytes and determine their addresses. Correspondingly, an error correction unit performs ECC encoding on the correct byte corresponding to the received error byte address to obtain a correction code. Therefore, when the processor needs to read data at the error byte address, the error correction unit can correct only the error byte at that address using the correction code to obtain the correct byte. This allows the data processing unit, upon receiving a read instruction from the processor including the error byte address, to directly obtain the correct byte corresponding to the error byte address corrected by the error correction unit and return the correct byte to the processor. This effectively ensures the accuracy of data reads by the processor, significantly improves memory access speed, and addresses the issue of slow memory response speed.

[0093] This application also provides a storage system including a processor, a memory, and a storage controller provided in this application embodiment. In this application embodiment, an error location unit in the storage controller is connected to the processor, the memory, and a data processing unit. The error location unit is used to read the first data to be read as indicated by the first read instruction from the memory when the processor outputs a first read instruction, and to perform error byte verification on the first data to obtain a location result; then, if the location result indicates that there is an error byte in the first data, it sends the error byte address of the error byte to the processor and the data processing unit. The data processing unit is used to receive a first write instruction output by the processor for the error byte address, and send the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit, so that the error correction unit can perform ECC encoding on the correct byte, obtain and write a correction code to the memory, thereby realizing the generation of a correction code for a single byte. Furthermore, the error correction unit is also used to receive a second read instruction output by the processor, and if the second read instruction includes an error byte address, to read the error byte corresponding to the error byte address and the correction code from the memory, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit and output the correct byte to the processor.

[0094] In this technical solution, an error location unit performs error byte location on the read first data to quickly locate erroneous bytes and determine their addresses. Correspondingly, an error correction unit performs ECC encoding on the correct byte corresponding to the received error byte address to obtain a correction code. Therefore, when the processor needs to read data at the error byte address, the error correction unit can correct only the error byte at that address using the correction code to obtain the correct byte. This allows the data processing unit, upon receiving a read instruction from the processor including the error byte address, to directly obtain the correct byte corresponding to the error byte address corrected by the error correction unit and return the correct byte to the processor. This effectively ensures the accuracy of data reads by the processor, significantly improves memory access speed, and addresses the issue of slow memory response speed.

[0095] This application also provides an electronic device including the energy storage system provided in this application embodiment. In this application embodiment, an error location unit in the storage controller is connected to the processor, the memory, and the data processing unit. The error location unit is used to read the first data to be read as indicated by the first read instruction from the memory when the processor outputs a first read instruction, and to perform error byte verification on the first data to obtain a location result; then, if the location result indicates that there is an error byte in the first data, it sends the error byte address of the error byte to the processor and the data processing unit. The data processing unit is used to receive a first write instruction output by the processor for the error byte address, and send the correct byte corresponding to the error byte address and the error byte address included in the first write instruction to the error correction unit, so that the error correction unit can perform ECC encoding on the correct byte, obtain and write a correction code to the memory, thereby realizing the generation of a correction code for a single byte. Furthermore, the error correction unit is also used to receive a second read instruction output by the processor, and if the second read instruction includes an error byte address, to read the error byte corresponding to the error byte address and the correction code from the memory, so as to correct the error byte according to the correction code to obtain the correct byte. This enables the data processing unit to receive the second read instruction. If the read address included in the second read instruction contains the address of the erroneous byte, it can directly obtain the correct byte corresponding to the address of the erroneous byte corrected by the error correction unit and output the correct byte to the processor.

[0096] In this technical solution, an error location unit performs error byte location on the read first data to quickly locate erroneous bytes and determine their addresses. Correspondingly, an error correction unit performs ECC encoding on the correct byte corresponding to the received error byte address to obtain a correction code. Therefore, when the processor needs to read data at the error byte address, the error correction unit can correct only the error byte at that address using the correction code to obtain the correct byte. This allows the data processing unit, upon receiving a read instruction from the processor including the error byte address, to directly obtain the correct byte corresponding to the error byte address corrected by the error correction unit and return the correct byte to the processor. This effectively ensures the accuracy of data reads by the processor, significantly improves memory access speed, and addresses the issue of slow memory response speed.

[0097] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0098] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage controller, characterized in that, The storage controller includes: an error location unit, a data processing unit, and an error correction unit; The error location unit is connected to the processor, the memory and the data processing unit respectively. When the processor outputs a first read instruction, it reads the first data to be read from the memory as indicated by the first read instruction, performs error byte location on the first data to obtain a location result, and sends the error byte address of the error byte to the processor and the data processing unit when the location result indicates that there is an error byte in the first data. The data processing unit is connected to the processor and the error correction unit, and is used to receive a first write instruction output by the processor for the erroneous byte address, and send the correct byte corresponding to the erroneous byte address and the erroneous byte address included in the first write instruction to the error correction unit; The error correction unit is connected to the processor and the memory respectively, and is used to perform ECC encoding on the correct byte, obtain and write the correction code to the memory; and to receive a second read instruction output by the processor, and when the second read instruction includes the address of the error byte, read the error byte corresponding to the error byte address and the correction code from the memory, and correct the error byte according to the correction code to obtain the correct byte; The data processing unit is further configured to receive the second read instruction, and if the read address included in the second read instruction contains the erroneous byte address, obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit, and output the correct byte to the processor.

2. The storage controller according to claim 1, characterized in that, The error location unit is also used to receive the second write instruction output by the processor, perform error detection and verification encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code of each byte, and write the data to be written and the error detection code of each byte into the memory. The first data is at least one byte in the data to be written; the error location unit is further configured to read the error detection code corresponding to the first data from the memory, and perform error detection verification and decoding on the first data according to the error detection code to obtain the location result.

3. The storage controller according to claim 2, characterized in that, The error location unit is also used to perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code of each byte; The error location unit is further configured to perform parity check decoding on the first data according to the error detection code to obtain the location result.

4. The storage controller according to claim 3, characterized in that, The error location unit includes a first encoding module and a first decoding module; The first encoding module is connected to the processor and the memory, and is used to receive the second write instruction output by the processor, perform parity check encoding on each byte of the data to be written included in the second write instruction to obtain the error detection code of each byte, and write the data to be written and the error detection code of each byte into the memory. The first decoding module is connected to the memory and the data processing unit, and is used to read the first data to be read as indicated by the first read instruction and the error detection code corresponding to the first data from the memory in response to the first read instruction output by the processor, and to perform parity check decoding on the first data according to the error detection code to obtain the positioning result. If the positioning result indicates that there is an error byte in the first data, the module sends the error byte address of the error byte to the processor and the data processing unit.

5. The storage controller according to claim 1, characterized in that, The data processing unit is used to receive the first read instruction, and if it is determined that the read address included in the first read instruction does not contain the address of the erroneous byte, it outputs the read address included in the first read instruction to the error location unit. The error location unit is used to read the first data corresponding to the read address included in the first read instruction from the memory, and to perform error byte verification on the first data to obtain a location result. If the location result indicates that there is an error byte in the first data, the unit sends the error byte address of the error byte to the processor and the data processing unit.

6. The storage controller according to claim 5, characterized in that, The error location unit is further configured to send the first data to the data processing unit when the location result indicates that the first data does not contain any error bytes; The data processing unit is also used to output the first data corresponding to the first read instruction to the processor.

7. The storage controller according to claim 1, characterized in that, The second read instruction is used to read at least two bytes, including the erroneous byte; The data processing unit is further configured to, upon receiving the second read instruction, output the target read address of the second read instruction to the error location unit, wherein the target read address is the byte address excluding the error byte address among the read addresses included in the second read instruction; The error location unit is further configured to read the second data corresponding to the target read address from the memory, perform error byte verification on the second data to obtain a location result, and send the second data to the data processing unit if the location result indicates that there are no error bytes in the second data; The data processing unit is also used to output the correct byte and the second data to the processor.

8. The storage controller according to claim 1, characterized in that, The data processing unit includes: an address selection unit and a data selection unit; The address selection unit is connected to the processor, the misalignment location unit, and the error correction unit, and is used to receive the error byte address sent by the error location unit; and to receive the first write instruction output by the processor, and send the correct byte corresponding to the error byte address included in the first write instruction and the error byte address to the error correction unit; The data selection unit is connected to the processor, the misalignment location unit, and the error correction unit, and is used to receive the erroneous byte address sent by the error location unit; and to receive the second read instruction, and if it is determined that the read address included in the second read instruction contains the erroneous byte address, to obtain the correct byte corresponding to the erroneous byte address corrected by the error correction unit, and to output the correct byte to the processor.

9. The storage controller according to claim 8, characterized in that, The error correction unit includes: a second encoding unit and a second decoding unit; The second encoding unit is connected to the address selection unit and the memory, and is used to receive the correct byte corresponding to the erroneous byte address sent by the address selection unit, perform ECC encoding on the correct byte, and obtain and write the correction code to the memory; The second decoding unit is connected to the processor, the memory, and the data selection unit, and is used to receive a second read instruction output by the processor. If the second read instruction includes the error byte address, the unit reads the error byte corresponding to the error byte address and the correction code from the memory, corrects the error byte according to the correction code to obtain the correct byte, and sends the correct byte to the data selection unit.

10. A storage system, characterized in that, The storage system includes a processor, a memory, and a storage controller as described in any one of claims 1 to 9.

11. The storage system according to claim 10, characterized in that, The storage system also includes an AHB bus, through which the processor is connected to the storage controller.

12. An electronic device, characterized in that, The electronic device includes the storage system as described in claim 10 or 11.

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