PCB (printed circuit board) material impedance Dk reverse model method
By using TDR testing, slicing, and impedance simulation techniques, a model relating impedance Dk to material RC% was established. This solved the problem of impedance control deviation in high-frequency communication PCBs, enabling closed-loop control of precise design and manufacturing, and reducing costs and time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-03-24
AI Technical Summary
In the design and manufacturing of high-frequency communication PCBs, the systematic deviation between the material equivalent Dk and the supplier specification Dk makes it difficult to guarantee the accuracy of impedance control. The existing process lacks an effective modeling mechanism, resulting in an increase in the number of prototyping, a longer cycle, and higher costs.
By employing TDR testing, slice fabrication, data analysis, and impedance simulation techniques, and through multi-position vertical slicing and CCD measurement, outlier data is eliminated, Er values are iteratively adjusted, a relationship model between impedance Dk and material RC% is established, and an impedance Dk database is constructed to achieve precise design.
Significantly improve impedance accuracy, reduce trial and error prototyping, shorten the R&D cycle, reduce costs, and ensure closed-loop control of design and manufacturing.
Smart Images
Figure CN121725941A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PCB material technology, specifically to a method for inversely calculating the impedance Dk model of PCB materials. Background Technology
[0002] In the design and manufacturing process of high-frequency communication PCBs, engineers typically rely on impedance simulation software to determine the key parameter combinations that meet the target impedance at the design front end. These parameters include dielectric constant Dk, dielectric layer thickness, copper thickness, line width, and line spacing. The standard practice is that dielectric thickness, copper thickness, line width, and line spacing can be controlled and verified through material selection, layout design, and process control. Material Dk is often directly taken from the supplier's specifications at a specific frequency (e.g., 1 GHz) as the simulation input. During mass production, the average impedance is obtained by measuring the coupon using TDR within the 30% to 70% stable range. This is supplemented by local slice verification of physical factors such as copper thickness, dielectric thickness, and line width, thereby retrospectively verifying the consistency between design and process control to achieve closed-loop control between design and manufacturing.
[0003] However, the aforementioned reliance on supplier specifications (Dk) often leads to significant deviations in actual mass production. Even if the slicing confirms that the copper thickness, dielectric thickness, and linewidth / spacing all match the design specifications, the measured impedance still deviates significantly from the target value. The core reason is that there are systematic differences between the specification Dk and the actual stack-up, frequency, resin content, asymmetry of the upper and lower dielectrics, lamination density, and copper surface roughness, resulting in the Dk input to the front-end simulation not being the "process-equivalent Dk". This deviation makes it difficult to guarantee the accuracy of impedance parameters during the design stage, requiring multiple rounds of trial and error adjustments, which increases the number of prototyping, lengthens the cycle, and raises costs. At the same time, the existing process lacks a modeling mechanism that links measured impedance, fine slicing data, and simulation iterations to deduce the "equivalent Dk that meets impedance requirements," and it also lacks a regressible database for the RC% dimension, making it difficult to conduct predictable and transferable impedance design and rapid decision-making under different materials and different RC% conditions. Summary of the Invention
[0004] The purpose of this invention is to solve the impedance control problem caused by the systematic deviation between the material equivalent Dk and the supplier specification Dk in the design and manufacturing of high-frequency communication PCBs, and to propose a PCB material impedance Dk back-calculation model method.
[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A method for inversely calculating the impedance Dk of PCB materials includes the following steps: S10. Use TDR testing technology to measure the impedance of PCB products, obtain the mean value of the impedance coupon in the 30%-70% measurement range, and obtain the actual impedance data characteristics. S20. Using slicing technology, vertical slices are made at 25%, 50%, and 75% of the coupon line length. Using CCD measurement technology, the thickness of the upper dielectric layer, the thickness of the lower dielectric layer, the upper and lower line widths, the copper thickness, and the differential mode line width spacing are accurately measured in micrometers to obtain the physical parameter characteristics of the impedance line. S30. Data analysis techniques are used to remove outlier data with abnormally amplified linewidth, copper thickness, and dielectric layer thickness, and to verify the consistency between the differential mode slice LW+LS and the design center distance pitch value, so as to obtain an effective slice dataset. S40. Using impedance simulation technology, select the corresponding impedance model in Polar Si9000 software, substitute the average value of the slice data, and set the initial Er value according to the PP material type of the upper and lower dielectric layers. By iteratively adjusting the Er value, the difference between the simulated value and the measured value is less than 0.2 ohms, and the accurate impedance Dk value is obtained. S50. A linear regression analysis technique is used to establish a model relating impedance Dk to material RC%, and the impedance Dk value corresponding to different RC% is calculated by interpolation to construct a complete impedance Dk database.
[0006] Based on the above technical solution, the present invention can be further improved as follows.
[0007] Furthermore, the TDR testing technology in S10 specifically includes: The inner layer impedance was measured using a time-domain reflectometer. A stable measurement range of 30%-70% was selected to avoid the influence of end effects. The mean impedance value was recorded as the reference data. The impedance measurement must cover both single-ended impedance and differential impedance. For differential impedance, the impedance values of both the positive and negative lines must be recorded simultaneously to ensure that complete impedance characteristic data is obtained for subsequent back-calculation of the Dk value.
[0008] Furthermore, the slicing technique in step S20 includes the following steps: S201. Prepare slice samples perpendicular to the line at three positions: 25%, 50%, and 75% of the coupon line length. Record various parameters with an accuracy of 0.1 μm using a CCD optical measurement system. S202. For differential line structures, additional measurements of the line width and lower span parameters are required. S203. Take the average value of the slice data at the three locations to eliminate the influence of local process deviations.
[0009] Furthermore, the data analysis technology in step S30 includes two sub-steps: outlier detection and differential mode verification. First, check whether there are any abnormal amplifications in the line width, copper thickness, and dielectric layer thickness that exceed the design specifications by 25μm. If so, they are determined to be measurement or slicing errors and need to be eliminated. Second, verify the consistency between the LW+LS sum of the differential line slices and the design center distance pitch value. Data groups with differences exceeding 25μm need to be remeasured or excluded.
[0010] Furthermore, the specific method for setting the Er value according to the dielectric layer material type in step S40 is as follows: when the same PP material is used above and below the line, the same Er value is substituted into the upper and lower dielectric layers for simulation; when different PP materials are used, if there is an impedance Dk database, the difference in Dk between the two PP materials in the database is referenced; if there is no database, the difference is calculated by referring to the 1GHz Dk specification value provided by the manufacturer. The Er value of the upper and lower dielectric layers is adjusted simultaneously with this difference for iterative simulation until the difference between the simulated value and the measured value is less than 0.2 ohms.
[0011] Furthermore, the method for establishing the impedance Dk database in step S50 includes: S501 is a dedicated impedance Dk reverse calculation test board. It adopts a linear gradient design to gradually change the line width at the design median of ±0.5mil, ±1mil, and ±2mil to obtain an impedance distribution range of 15-20 ohms. S502. The same RC% PP material must be used on the upper and lower parts of the circuit of the test board to avoid misjudgment of the equivalent RC% value due to the difference in RC% and thickness of different PP materials. S503. Establish a relationship model of y=nx through linear regression analysis, and adjust the Er value to make the slope n approach 1.
[0012] Furthermore, the impedance data processing method for the test board includes: Substitute the sliced data into Polar SiExcel software, initially substituting the same assumed values for Er1 and Er2; Plot a scatter plot of impedance simulation data and measurement data, add a linear trend line and set the intercept to 0; Simultaneously adjust Er1 and Er2 to gradually bring the slope of the trend line closer to 1, and exclude abnormal groups whose simulated values and measured values differ by more than 3 ohms during the approximation process. When y=1x and R 2 When the value is greater than 0.98, Er1 and Er2 are the impedance Dk values of the material under a specific stack structure.
[0013] Furthermore, the specific steps for the linear analysis of impedance Dk and material RC% are as follows: Obtain the impedance Dk values at the two endpoints (high RC% and low RC%) of the same material through testing; plot the Dk-RC% scatter plot in Excel and add a linear trend line to obtain a regression formula of the form y=ax+b; based on this regression formula, calculate the impedance Dk values corresponding to each intermediate RC% using interpolation, where the RC% range covers the 50%-75% interval; the established database contains three key parameters: material type, RC% value, and corresponding impedance Dk value.
[0014] Furthermore, it also includes a dynamic update mechanism for the impedance Dk database: impedance Dk is back-calculated for each batch of new materials, and the database is updated when the measured Dk value deviates from the database prediction value by more than 2%.
[0015] Furthermore, when updating the database, at least three test boards need to be remade for verification to ensure data reliability. The database is classified and managed according to material supplier, material model, and RC% range, and supports fast query and retrieval.
[0016] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: This invention uses the impedance mean value measured by TDR as the core input for reverse calculation, ensuring that the initial data closely matches actual mass production and avoiding deviations caused by insufficient data representativeness. Through multi-position vertical slicing and CCD micron-level measurements, key parameters such as the thickness of the upper and lower dielectric layers and the upper and lower linewidths are supplemented, solving the problems of single slicing position, incomplete parameters, and insufficient accuracy in the background technology. This makes the physical parameters more closely match the actual stack-up, eliminates outlier data, and verifies the consistency between differential mode slicing and the design pitch, ensuring data quality and avoiding outlier interference. Through iterative simulation with Polar Si9000, the difference between simulated and measured values is less than 0.2 ohms, leading to the derivation of the "process equivalent Dk," completely solving the impedance deviation problem caused by inaccurate supplier Dk. An RC%-Dk relationship model and database are established, and Dk values under different RC% are quickly obtained through interpolation, achieving transferable and accurate design. The overall method significantly improves impedance accuracy, reduces trial-and-error prototyping, shortens the R&D cycle, and reduces costs. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the test board layout for this invention; Figure 2 This is a snapshot diagram of the simulation input / output data table of the present invention; Figure 3 This is a scatter regression plot of Zsim against Zmeas in this invention; Figure 4 This is the RC% endpoint data table of the present invention; Figure 5 This is the RC%—Dk regression trend chart of the present invention. Detailed Implementation
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] The present invention provides a method for inversely calculating the impedance Dk of PCB materials, comprising the following steps: S10. Use TDR testing technology to measure the impedance of PCB products, obtain the mean value of the impedance coupon in the 30%-70% measurement range, and obtain the actual impedance data characteristics. S20. Using slicing technology, vertical slices are made at 25%, 50%, and 75% of the coupon line length. Using CCD measurement technology, the thickness of the upper dielectric layer, the thickness of the lower dielectric layer, the upper and lower line widths, the copper thickness, and the differential mode line width spacing are accurately measured in micrometers to obtain the physical parameter characteristics of the impedance line. S30. Data analysis techniques are used to remove outlier data with abnormally amplified linewidth, copper thickness, and dielectric layer thickness, and to verify the consistency between the differential mode slice LW+LS and the design center distance pitch value, so as to obtain an effective slice dataset. S40. Using impedance simulation technology, select the corresponding impedance model in Polar Si9000 software, substitute the average value of the slice data, and set the initial Er value according to the PP material type of the upper and lower dielectric layers. By iteratively adjusting the Er value, the difference between the simulated value and the measured value is less than 0.2 ohms, and the accurate impedance Dk value is obtained. S50. A linear regression analysis technique is used to establish a model relating impedance Dk to material RC%, and the impedance Dk value corresponding to different RC% is calculated by interpolation to construct a complete impedance Dk database.
[0020] S10: Measure the inner layer impedance coupon of the target using a TDR within the 30%–70% stable range, and use the mean value of the instrument's original trace after automatic noise reduction as the measured impedance benchmark. S20: Prepare perpendicular slices orthogonal to the coupon line length at 25%, 50%, and 75%, respectively. Use a CCD optical measurement system to record the upper dielectric layer thickness, lower dielectric layer thickness, upper linewidth, lower linewidth, copper thickness, and the lower spacing of the differential structure at a resolution of 0.1 μm. Average the three data points to characterize the geometric reality of the coupon. S30: Perform data quality control: detect anomalies in key factors such as linewidth, copper thickness, and dielectric thickness (threshold 25 μm), and verify whether LW+LS of the differential structure is approximately equal to the design center distance pitch. If not (deviation > 25 μm), the data is considered erroneous and discarded. S40: [The text abruptly ends here, likely due to an incomplete sentence or missing information.] In Si9000, select a single-ended or differential model that matches the stacked structure, import the mean-processed slice geometry parameters, and set the initial Er according to the upper and lower PP types. Use a step-by-step iterative method to synchronously adjust the Er of the upper and lower dielectric layers until the absolute value of the difference between the simulated impedance and the TDR mean is less than 0.2 Ω. Use this Er as the equivalent impedance Dk for the stacked structure. In S50, for different RC% samples of the same material, collect the equivalent Dk results. Establish a linear regression model y=ax+b between RC% (independent variable) and Dk (dependent variable) in Excel, and generate standardized entries within the 50%~75% RC% range using interpolation. This forms an impedance Dk database managed hierarchically by material / RC% to support rapid selection and accurate simulation in subsequent designs. The above process can be used for batch product verification and can also serve the database construction of dedicated test boards.
[0021] like Figure 1 As shown, the TDR testing technology in S10 specifically includes: The inner layer impedance was measured using a time-domain reflectometer. A stable measurement range of 30%-70% was selected to avoid the influence of end effects. The mean impedance value was recorded as the reference data. Impedance measurements must cover both single-ended and differential impedance. For differential impedance, the impedance values of both positive and negative lines must be recorded simultaneously to ensure complete impedance characteristic data for subsequent Dk value calculation. For S10, a time-domain reflectometer with time gating and impedance mean calculation functions is preferred. Appropriate probes and fixtures should be set for both single-ended and differential coupons. Differential measurements require simultaneous recording of the impedance traces of both positive and negative lines and calculation of the differential impedance. During measurement, the time window should be precisely limited to the 30% to 70% range to avoid the influence of termination and transition discontinuities. Averaging and bandpass filtering should be enabled to reduce noise. The final interval mean output by the software should be used as the representative impedance value for that coupon. At least three coupons should be measured for each level and each linewidth specification to obtain statistical stability. Ambient temperature and humidity, test frequency band, and sampling rate should be recorded to ensure data traceability.
[0022] The slicing technique in step S20 includes the following steps: S201. Prepare slice samples perpendicular to the line at three positions: 25%, 50%, and 75% of the coupon line length. Record various parameters with an accuracy of 0.1 μm using a CCD optical measurement system. S202. For differential line structures, additional measurements of the line width and lower span parameters are required. S203. Average the slice data from the three locations to eliminate the influence of local process deviations and improve the accuracy and reliability of impedance Dk back-calculation. In S20, the slice preparation adopts a standard grinding and polishing process to ensure that the cut surface is perpendicular and the edge is free of chipping. Prepare a cross-section at three equidistant locations: 25%, 50%, and 75%. Use a calibrated CCD measurement system to repeatedly measure the upper / lower dielectric layer thickness, upper / lower linewidth, copper thickness, and differential line spacing at the same magnification. Each parameter should be read at least 3 times and the average value should be recorded to 0.1 μm. For differential structures, pay attention to the symmetry of the two lines and mark the geometric center distance. Perform a weighted average of the three data points as the geometric input of the coupon to reduce the influence of local process fluctuations on back-calculation of Dk.
[0023] The data analysis techniques in step S30 include two sub-steps: outlier detection and differential mode verification. First, check whether there are any abnormal amplifications in linewidth, copper thickness, and dielectric layer thickness exceeding the design specifications by 25 μm. If so, they are judged as measurement or slicing errors and need to be removed. Second, verify the consistency between the LW+LS sum of the differential circuit slices and the design center distance pitch value. Data groups with differences exceeding 25 μm need to be remeasured or excluded to ensure the data quality used for Dk back-calculation. S30 includes two types of quality control: one is outlier detection, which uses a combination of absolute threshold method and box plot method. If any of the linewidth, copper thickness, or dielectric thickness deviates from the design nominal value or the average value of the same batch by more than 25 μm, or falls into the statistical outlier interval (such as outside the IQR method), it is judged as an anomaly and removed. The second is differential geometric consistency verification, which calculates the difference between the measured LW+LS of the slice and the design center distance pitch. If the absolute deviation is >25 μm, it is determined that there is a slicing or measurement error, and retesting or sample replacement is required. The dataset can only proceed to the S40 simulation iteration if both types of quality control are passed.
[0024] like Figure 2 As shown, the specific method for setting the Er value according to the dielectric layer material type in step S40 is as follows: When the same PP material is used above and below the line, the same Er value is substituted into the upper and lower dielectric layers for simulation; when different PP materials are used, if there is an impedance Dk database, the difference in Dk between the two PP materials in the database is referenced; if there is no database, the difference is calculated by referring to the 1GHz Dk specification value provided by the manufacturer. The Er value of the upper and lower dielectric layers is adjusted simultaneously with this difference for iterative simulation until the difference between the simulated value and the measured value is less than 0.2 ohms. In S40, the appropriate single-ended microstrip, differential microstrip, stripline or differential stripline model is selected in Polar Si9000 according to the stack-up structure, and the geometric mean obtained in S20 is input with an accuracy of 0.1 μm. For cases where the upper and lower PPs are the same, the same Er is initially assigned, and an iterative strategy combining binary search and fine-tuning is used to approximate the difference until |Zsim−Zmeas|<0.2 Ω. For cases where the upper and lower PPs are different, if the database already has the equivalent Dk difference between the two PPs, this difference is used as a constraint for synchronous parameter tuning to keep the difference between the upper and lower Er constant and shift the overall value. If the database is not available, the iteration is carried out with the supplier's 1 GHz Dk difference as the initial assumption. If necessary, the second-order effect of copper surface roughness or surface treatment on the effective dielectric is added to the simulation as a sensitivity check until the error threshold is met, and the equivalent impedance Dk under this stack is output.
[0025] like Figure 5 As shown, the method for establishing the impedance Dk database in step S50 includes: S501 is a dedicated impedance Dk reverse calculation test board. It adopts a linear gradient design to gradually change the line width at the design median of ±0.5mil, ±1mil, and ±2mil to obtain an impedance distribution range of 15-20 ohms. S502. The same RC% PP material must be used on the upper and lower parts of the circuit of the test board to avoid misjudgment of the equivalent RC% value due to the difference in RC% and thickness of different PP materials. S503. A linear regression model y=nx is established, and the Er value is adjusted to make the slope n approach 1. To construct a transferable Dk database across RC%, a dedicated impedance regression test board is designed: under the condition of symmetrical laying of the same stacked structure and PP in the same RC%, multiple sets of linear gradient linewidth coupons are arranged. The linewidth gradually changes around the design median at ±0.5, ±1, and ±2 mil, so that the obtained impedance covers a distribution bandwidth of approximately 15~20 Ω, which is conducive to robust fitting of linear regression. After the test board is completed, TDR measurement and three-point slice measurement are performed, and outlier data are removed. After each RC% completes one round of S40 simulation iteration to obtain the equivalent Dk, it enters S50 linear regression modeling to form the "material-RC%-Dk" entry.
[0026] If an impedance Dk database is to be established, an impedance Dk regression test board should be fabricated. The top and bottom of the circuit should be made of the same RC% PP material. This avoids the situation where different PP materials have different RC% and thicknesses, which affect the impedance to varying degrees and lead to misjudgments of the equivalent RC% value. The reference stack is shown in the table below; like Figure 3 ,and Figure 4 As shown, the impedance data processing method for the test board includes: Substitute the sliced data into Polar SiExcel software, initially substituting the same assumed values for Er1 and Er2; Plot a scatter plot of impedance simulation data and measurement data, add a linear trend line and set the intercept to 0; Simultaneously adjust Er1 and Er2 to gradually bring the slope of the trend line closer to 1, and exclude abnormal groups whose simulated values and measured values differ by more than 3 ohms during the approximation process. When y=1x and R 2When the value is greater than 0.98, Er1 and Er2 represent the impedance Dk values of the material under a specific stack. Import the geometric parameters of each slice into Polar SiExcel or an equivalent tool, setting the initial values of Er1 and Er2 to be the same to ensure the neutrality of the regression starting point. Plot a scatter plot of the simulated impedance and corresponding TDR mean of each coupon, add a linear trend line, and fix the intercept to 0 to eliminate the interference of systematic bias. Simultaneously adjust Er1 and Er2 so that the slope n of the trend line gradually approaches 1, while removing point pairs where |Zsim−Zmeas|>3 Ω (judged as measurement / slicing error). When y=1x and R 2 When the value is ≥0.98, Er1 and Er2 are denoted as the equivalent impedance Dk under the RC% condition. The results, along with the stack identification, frequency band, temperature measurement, and sample size, are archived together.
[0027] The specific steps for linear analysis of impedance Dk and material RC% are as follows: Obtain the impedance Dk values at the two endpoints (high RC% and low RC%) of the same material through testing. Plot a Dk-RC% scatter plot in Excel and add a linear trend line to obtain a regression formula of the form y=ax+b. Based on this regression formula, calculate the impedance Dk values corresponding to each intermediate RC% using interpolation, where the RC% range covers 50%-75%. The established database contains three key parameters: material type, RC% value, and corresponding impedance Dk value, providing accurate reference for impedance design of materials with different RC% values. For the same material, prioritize collecting samples from the two endpoints (high RC% and low RC%) and obtain the equivalent Dk at each endpoint through the above process. Establish a linear fit in Excel with RC% as the independent variable and Dk as the dependent variable, output the regression equation y=ax+b, and record R. 2 When R 2 When a preset threshold is met (e.g., ≥0.95), an interpolation method is used to generate a standardized equivalent Dk table for RC% in the 50% to 75% range; for R... 2 In cases where the RC% is too low, intermediate RC% samples can be added or piecewise linearity can be introduced to improve the fit. The final database entries include material type, RC%, equivalent Dk, stack / layer, frequency point, and temperature measurement information, meeting the engineering requirements of the design end for searchability and reusability.
[0028] It also includes a dynamic update mechanism for the impedance Dk database: impedance Dk is back-calculated and verified for each batch of new materials. When the deviation between the measured Dk value and the database prediction exceeds 2%, the database is updated. During the update, at least three test boards must be remade for verification to ensure data reliability. The database is categorized and managed by material supplier, material model, and RC% range, supporting quick query and retrieval. Through continuous data accumulation and optimization, the first-time success rate of PCB impedance design is improved to over 95%, establishing a continuous verification and update mechanism for the database: when a new batch of materials is introduced into production, a representative stack-up and linewidth coupon are randomly selected for a quick back-calculation. If the deviation between the measured equivalent Dk and the database prediction exceeds 2%, the update process is triggered, and at least three regression test boards are remade for verification. After the update, version management is implemented using supplier / material model / RC% as indexes, and historical backtracking is retained. Through rolling updates, the database gradually covers major materials and RC% ranges, aiming to increase the first-time design success rate to approximately 95%.
[0029] This method is applied to the manufacturing process of high-frequency communication PCBs. By obtaining the actual Dk value that meets impedance requirements, it solves the problem of inaccurate impedance control and prediction caused by the inaccuracy of the Dk specifications provided by suppliers. Designers can perform impedance simulation based on the accurate Dk value obtained by reverse engineering, which can provide more accurate design parameters, including optimized combinations of dielectric thickness, copper thickness, line width, and spacing. This method reduces the impedance deviation in the design stage from ±10% to within ±3%, reduces trial and error costs by more than 60%, and improves product production efficiency and yield. This method is preferably applied to the mass production process of high-frequency communication, multilayer differential backplanes, and high-speed interconnect PCBs: In the design stage, the equivalent Dk in the database is used to replace the supplier's nominal Dk as the simulation input. Combined with the joint optimization of stack-up, copper thickness, line width / spacing, and dielectric thickness, the trial and error cycle is significantly shortened. In the pilot production stage, the equivalent Dk is confirmed by S10-S40 closed-loop and deviation samples are quickly corrected. In the mass production stage, the database is the primary basis for material and RC% selection. Through this process, the impedance deviation in the design phase has been reduced from ±10% to within approximately ±3%, significantly reducing trial production iteration and scrap costs, improving production cycle time and yield, and providing a data foundation for subsequent cross-model reuse.
[0030] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0031] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A PCB material impedance Dk back-calculation model method, characterized in that, The method comprises the following steps: S10, using TDR test technology to measure the impedance of the PCB product, obtaining the mean value of the impedance coupon in the 30%-70% measurement interval, and obtaining the actual data characteristics of the impedance; S20, using slicing technology to make vertical slices at the positions of 25%, 50%, and 75% of the length of the coupon line, and using CCD measurement technology to accurately measure the thickness of the upper dielectric layer, the thickness of the lower dielectric layer, the line width upper amplitude, the lower amplitude, the copper thickness, and the difference mode line width lower amplitude spacing in units of microns, and obtaining the physical parameter characteristics of the impedance line; S30, using data analysis technology to remove outlier data of abnormal amplification of line width, copper thickness, and dielectric layer thickness, verify the consistency of the difference mode slice LW+LS and the design center distance pitch value, and obtain the effective slice data set; S40, using impedance simulation technology to select the corresponding impedance model in the Polar Si9000 software, substitute the average value of the slice data, and set the initial Er value according to the PP material type of the upper and lower dielectric layers, and adjust the Er value through iteration to make the difference between the simulation value and the measured value less than 0.2 ohm, and obtain the accurate impedance Dk value; S50, using linear regression analysis technology to establish a relationship model between impedance Dk and material RC%, and calculating the impedance Dk value corresponding to different RC% through interpolation method, and constructing a complete impedance Dk database.
2. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The TDR test technology in S10 specifically comprises: Using a time domain reflectometer to measure the inner layer impedance, selecting a stable measurement interval of 30%-70% to avoid the influence of end effect, and recording the impedance mean value as the reference data; The impedance measurement needs to cover single-ended impedance and differential impedance, and the impedance values of the positive and negative lines of the differential impedance need to be recorded at the same time to ensure that complete impedance characteristic data is obtained for subsequent Dk value back calculation.
3. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The slicing technology in step S20 comprises the following steps: S201, making slice samples perpendicular to the line at the positions of 25%, 50%, and 75% of the length of the coupon line, and using a CCD optical measurement system to record various parameters with an accuracy of 0.1 μm; S202, for the differential line structure, the line width lower amplitude spacing parameter needs to be additionally measured; S203, taking the average value of the slice data at the three positions to eliminate the influence of local process deviation.
4. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The data analysis technology in step S30 comprises two sub-steps of outlier detection and differential mode verification: first, check whether the line width, copper thickness, and dielectric layer thickness have abnormal amplification exceeding the design specification of 25 μm, if yes, it is determined that the measurement or slicing error needs to be removed; second, verify the consistency of the sum of the slice LW+LS and the design center distance pitch value for the differential line, and the data group with a difference exceeding 25 μm needs to be re-measured or excluded.
5. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The specific method of setting the Er value in step S40 according to the type of dielectric layer material is: when the same PP material is used above and below the line, the same Er value is substituted into the upper and lower dielectric layers for simulation; when different PP materials are used, if there is an impedance Dk database, the Dk difference between the two PP materials in the database is referred to, if there is no database, the difference is calculated according to the 1GHz Dk specification value provided by the manufacturer, and the Er value of the upper and lower dielectric layers is adjusted by the difference to perform iterative simulation until the difference between the simulation value and the measured value is less than 0.2 ohm.
6. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The method of establishing the impedance Dk database in step S50 includes: S501, design a dedicated impedance Dk back-propagation test board, use linear gradient design to make the line width gradually change at the design center value ±0.5mil, ±1mil, ±2mil, and obtain an impedance distribution range of 15-20 ohm; S502, the same RC% PP material must be used above and below the line of the test board to avoid misjudgment of the equivalent RC% value caused by the difference in RC% and thickness of different PP; S503, establish a relationship model of y=nx by linear regression analysis, and adjust the Er value to make the slope n tend to 1.
7. The PCB material impedance Dk back-calculation model method of claim 6, wherein, The impedance data processing method of the test board includes: Substitute the slice data into the Polar SiExcel software, and assume the same initial value for Er1 and Er2; Draw a scatter plot of the impedance simulation data and the measured data, add a linear trend line and set the intercept to 0; Adjust Er1 and Er2 at the same time to make the slope of the trend line gradually tend to 1, and exclude abnormal groups with a difference between the simulation value and the measured value greater than 3 ohm in the approximation process; When y = 1x and R 2 When y = 1x and R 2 When y = 1x and R 2 When y = 1x and R 2 When y = 1x and R 2 When y = 1x and R 2 When y = 1x 8. The PCB material impedance Dk back-calculation model method of claim 1, wherein, The specific operation steps of linear analysis of impedance Dk and material RC% are: obtain the impedance Dk values of two endpoints of high RC% and low RC% of the same material by testing, draw a Dk-RC% scatter plot in Excel and add a linear trend line to obtain a regression formula like y=ax+b; based on the regression formula, use interpolation method to calculate the impedance Dk values corresponding to each RC% in the middle, where the RC% range covers the 50%-75% interval; the established database contains three key parameters of material type, RC% value and corresponding impedance Dk value.
9. The PCB material impedance Dk back-calculation model method of claim 1, wherein, It also includes a dynamic updating mechanism of the impedance Dk database: for each batch of new materials, impedance Dk back-propagation verification is performed, and when the measured Dk value deviates from the predicted value in the database by more than 2%, the database is updated.
10. The PCB material impedance Dk back-calculation model method of claim 9, wherein, When updating the database, at least 3 test boards need to be re-made for verification to ensure data reliability, the database is classified and managed according to the material supplier, material model and RC% range, and supports fast query and call.