Semiconductor device and method of manufacturing semiconductor device
By employing a silicon carbide epitaxial layer structure in power metal-oxide-semiconductor transistors and utilizing a combination of island oxide and gate oxide layers, the problem of switching energy loss caused by gate and drain capacitance is solved, achieving a balance between low capacitance and low on-resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2026-03-24
AI Technical Summary
In traditional power metal-oxide-semiconductor transistors, the gate and drain capacitances affect the switching energy loss of the device, and the thickness of the oxide between the gate and drain cannot be effectively controlled to reduce the capacitance.
The silicon carbide epitaxial layer structure includes a p-type well region, a heavily doped n-type region, a heavily doped p-type region, an island oxide layer, and a gate oxide layer. The island oxide layer and the gate oxide layer are formed by patterning process, and the spacing between the flip-chip silicon layer and the junction field-effect region is maintained or increased to reduce the gate and drain capacitance.
While reducing the drain-to-source on-resistance, the gate-to-drain capacitance is maintained or reduced to improve switching energy loss.
Smart Images
Figure CN121728808A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor device, and more particularly to a power MOSFET. BACKGROUND
[0002] In a conventional power MOSFET, gate-drain capacitance (Cgd) affects the switching energy loss of the device, but the oxide thickness between the gate and the drain cannot be effectively controlled individually to reduce the gate-drain capacitance. Therefore, a new semiconductor device and a method for manufacturing a semiconductor device are needed to overcome these problems. SUMMARY
[0003] Therefore, the present invention provides a semiconductor device, which includes a silicon carbide epitaxial layer, comprising: a p-type well region; a junction field effect region adjacent to the p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region under the heavily doped n-type region and within the p-type well region. The semiconductor device further includes: an island oxide on the junction field effect region; a gate oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide; and a polysilicon layer on the gate oxide layer and not in contact with the island oxide.
[0004] The present invention also provides a method for manufacturing a semiconductor device, comprising: providing a silicon carbide epitaxial layer, wherein a p-type well region, a heavily doped n-type region on a surface of the p-type well region, a heavily doped p-type region under the heavily doped n-type region and within the p-type well region, and a junction field effect region adjacent to the p-type well region are predefined on the silicon carbide epitaxial layer; depositing an oxide layer; subjecting the oxide layer to a patterning process to form an island oxide, wherein the island oxide is on the junction field effect region; depositing a gate oxide layer to cover the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide; and depositing a polysilicon layer on the gate oxide layer.
[0005] In summary, when the width of the junction field effect region is reduced to reduce the drain-to-source on-resistance (Rdson) by reducing the overall cell pitch, the low gate-drain capacitance can be maintained by forming the island oxide and depositing the gate oxide layer to maintain the distance between the polysilicon layer and the junction field effect region, or even reduced by forming the island oxide and depositing the gate oxide layer to increase the distance between the polysilicon layer and the junction field effect region, further improving the switching energy loss. BRIEF DESCRIPTION OF DRAWINGS
[0006] In order to make the above objectives, features and advantages of the present invention more clear and comprehensible, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, in which:
[0007] Figures 1 to 5 is a cross-sectional view of a semiconductor device manufacturing process at different manufacturing stages, according to certain embodiments of the present invention;
[0008] Figure 6 is a flowchart of a semiconductor device manufacturing method, according to certain embodiments of the present invention;
[0009] Figures 7 to 11 is a cross-sectional view of a semiconductor device manufacturing process at different manufacturing stages, according to certain embodiments of the present invention; and
[0010] Figure 12 is a flowchart of a semiconductor device manufacturing method, according to certain embodiments of the present invention.
[0011] Reference Signs:
[0012] 101: silicon carbide epitaxial layer
[0013] 102A: gate oxide layer
[0014] 102B: gate oxide layer
[0015] 103: polysilicon layer
[0016] 105: heavily doped p region
[0017] 107: heavily doped n region
[0018] 108: oxide layer
[0019] 108A: island oxide
[0020] 109: oxide layer
[0021] 109A: island oxide
[0022] PW: p-well region
[0023] JF1: junction field effect region
[0024] JF2: junction field effect region
[0025] W1: width
[0026] W2: width
[0027] T1: thickness
[0028] T2: thickness
[0029] T3: thickness
[0030] T4: thickness
[0031] DA1: region
[0032] DA2: region
[0033] 600: method
[0034] 601: step
[0035] 602: step
[0036] 603: step
[0037] 604: step
[0038] 605: step
[0039] 606: step
[0040] 1200: method
[0041] 1201: step
[0042] 1202: step
[0043] 1203: step
[0044] 1204: step
[0045] 1205: step
[0046] 1206: step DETAILED DESCRIPTION
[0047] Figures 1 to 5 are cross-sectional views of a semiconductor device of the present application at different manufacturing stages, according to Figure 6 method 600. In step 601, a silicon carbide epitaxial layer 101 is provided, wherein p-well regions PW are predefined on the silicon carbide epitaxial layer 101, a heavily doped n-type region 107 is on the surface of the p-well regions PW, a heavily doped p-type region 105 is under the heavily doped n-type region 107 and within the p-well regions, and a junction field effect region JFl is between two adjacent p-well regions PW and adjacent to the p-well regions PW, as shown in Figure 1 The width Wl of the junction field effect region JFl can be 1.2 μm. In step 602, an oxide layer 108 is deposited, as shown in Figure 2 In step 603, a patterning process is performed on the oxide layer 108 to form island-shaped oxides 108A, as shown in Figure 3 The patterning process can include a photolithography process and an etching process. In some embodiments, the etching process can include a wet etching process and a photoresist removal process. The island-shaped oxides 108A are on the junction field effect region JFl, and the thickness Tl of the island-shaped oxides 108A can be about and the width of the island-shaped oxides 108A is less than the width Wl of the junction field effect region JFl.
[0048] In step 604, a thermal oxidation process is performed to produce the gate oxide layer 102A. For example... Figure 4 As shown, the gate oxide layer 102A is on and contacts the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, and the junction field-effect region JF1. The gate oxide layer 102A only contacts a portion of the side edge of the island oxide 108A and does not cover the upper surface of the island oxide 108A. The thickness T2 of the gate oxide layer 102A can be approximately The thickness of the oxide in the region DA1 above the drain is approximately still In step 605, a polycrystalline silicon layer 103 is deposited on the gate oxide layer 102A and the island oxide layer 108A. For example... Figure 5 As shown, a polysilicon layer 103 is on and in contact with the gate oxide layer 102A and the island oxide layer 108A. The polysilicon layer 103, after being patterned, can be formed as the gate of a transistor. Additionally, a first metal layer (not shown) is formed at the source and gate ends, which can be patterned to form source and gate contacts. The source contact contacts the heavily doped p-type region 105 and the heavily doped n-type region 107 through a metal silicide, while the gate contact contacts the polysilicon layer 103. At the drain end, a silicon carbide substrate (not shown) can be formed below the silicon carbide epitaxial layer 101, and a second metal layer (not shown) can be formed below the silicon carbide substrate as a drain contact.
[0049] In silicon carbide planar MOSFETs, the gate and drain capacitances (Cgd) affect the switching energy loss of the device, such as... Figure 5 The gate and drain capacitances of the metal-oxide-semiconductor field-effect transistor shown depend on the thickness of the gate oxide (e.g., island oxide 108A). The thicker the gate oxide, the lower the gate and drain capacitances. Lower gate and drain capacitances can improve the energy loss of the device during switching. Figure 5 The thickness T1 of the island oxide 108A in the middle is approximately This results in lower gate and drain capacitances. To reduce the drain-to-source on-resistance (Rdson), the cell pitch can be reduced. Common methods for reducing cell pitch include reducing the width W1 of the junction field-effect region JF1. Although Figure 5The metal-oxide-semiconductor field-effect transistor (MOSFET) with this architecture can achieve low gate and drain capacitances. However, if the junction field-effect region JF1 is miniaturized, in order to generate island oxides 108A with a width narrower than that of the junction field-effect region JF1, photoresist peeling on the oxide layer 108 may occur. Moreover, the thermal oxidation process does not easily increase the oxide layer thickness at the drain oxide (e.g., island oxide 108A). Therefore... Figure 7 to 11 Maintaining low gate-drain capacitance or reducing gate-drain capacitance while lowering the drain-to-source on-resistance (Rdson) is quite challenging in this architecture.
[0050] Figure 12 These are cross-sectional views of the semiconductor manufacturing apparatus of the present invention at different manufacturing stages, according to Figure 7 Method 1200 is shown. Figure 1 and Figure 8 Similarly, in step 1201, a silicon carbide epitaxial layer 101 is provided, wherein a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, a heavily doped p-type region 105 below the heavily doped n-type region 107 and within the p-type well region, and a junction field-effect region JF2 between and adjacent to the p-type well regions PW are predefined on the silicon carbide epitaxial layer 101. The junction field-effect region JF2 differs from the junction field-effect region JF1 in that the junction field-effect region JF2 is narrower than the junction field-effect region JF1, and the width W2 of the junction field-effect region JF2 can be miniaturized to 0.8 μm. In step 1202, an oxide layer 109 is deposited, such as... Figure 8 As shown. It should be noted that, Figure 2 The thickness of the oxide layer 109 is greater than that of the oxide layer 109. Figure 9 The oxide layer 108 is thinner. In step 1203, a patterning process is applied to the oxide layer 109 to form island-shaped oxides 109A, such as... Figure 10 As shown. The patterning process described above may include photolithography and etching processes. In some embodiments, the etching process may include wet etching and photoresist removal. The island oxide 109A is on the junction field-effect region JF2, and the thickness T3 of the island oxide 109A may be approximately The width of the island oxide 109A is smaller than the width W2 of the junction field-effect region JF2.
[0051] In step 1204, a gate oxide layer 102B is deposited to cover the p-type well region PW, the junction field-effect region JF2, the heavily doped n-type region 107, the heavily doped p-type region 105, and the island oxide 109A. For example... Figure 11As shown, the gate oxide layer 102B is on and in contact with the p-type well region PW, the heavily doped n-type region 107, the heavily doped p-type region 105, the junction field-effect region JF2, and the island oxide 109A. The thickness T4 of the gate oxide layer 102B can be approximately Therefore, the thickness of the oxide in the region DA2 above the drain is In step 1205, a polycrystalline silicon layer 103 is deposited on the gate oxide layer 102B. For example... Figure 11 As shown, the polysilicon layer 103 is on and in contact with the gate oxide layer 102B, but not with the island oxide 109A. The polysilicon layer 103, after being patterned, can be formed as the gate of a transistor. Similarly, a first metal layer (not shown) is formed with respect to the source and gate terminals. This first metal layer can be patterned to form source and gate contacts. The source contacts are in contact with the heavily doped p-type region 105 and the heavily doped n-type region 107 through metal silicide, while the gate contacts can be in contact with the polysilicon layer 103. With respect to the drain terminal, a silicon carbide substrate (not shown) can be formed below the silicon carbide epitaxial layer 101, and a second metal layer (not shown) can be formed below the silicon carbide substrate as a drain contact.
[0052] exist Figure 5 In the architecture shown, the gate oxide layers are all deposited oxide layers, not generated by a thermal oxidation process. Therefore, when the width W2 of the junction field-effect region JF2 is reduced to decrease the oxide thickness (e.g., island oxide 109A) at the drain end (e.g., region DA2), the thickness of the drain oxide can be compensated by the gate oxide layer 102B. In terms of the ratio of the drain oxide thickness to the width of the junction field-effect region, in... Figure 11 In the middle, the maximum spacing between the polycrystalline silicon layer 103 and the junction field-effect region JF1 (approximately The ratio of the thickness T1 of the island oxide 108A to the width W1 (approximately 1.2 μm) of the junction field-effect region JF1 is 0.075. Figure 11 In the middle, the maximum spacing between the polycrystalline silicon layer 103 and the junction field-effect region JF2 (approximately The ratio of the thickness T3 of the island oxide 109A plus the thickness T4 of the gate oxide layer 102B to the width W2 (approximately 0.8 μm) of the junction field-effect region JF2 is 0.1125, which is greater than 0.075. In some embodiments, the maximum spacing between the polysilicon layer 103 and the junction field-effect region JF2 (approximately...) can be maintained. ) to reduce the width W2 of the junction field effect region JF2, or to increase the maximum spacing between the polysilicon layer 103 and the junction field effect region JF2 (approximately ) to maintain the width W2 of the junction field effect region JF2 (approximately 0.8 μm), so that the ratio of the maximum spacing to the width W2 of the junction field effect region JF2 can be greater than 0.1125, such as even greater than 0.2 or 0.3, etc. In summary, The architecture of the above embodiments can maintain or reduce the gate-to-drain capacitance (increase the maximum spacing between the polysilicon layer 103 and the junction field effect region JF2) while reducing the width of the junction field effect region to reduce the overall cell pitch and reduce the drain-to-source on-resistance (Rdson), further improving the switching energy loss.
[0053] The above description of the features of many embodiments enables those skilled in the art to clearly understand the form of the present disclosure. Those skilled in the art can understand that they can use the disclosure to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the above embodiments. Those skilled in the art can also understand that equivalent structures that do not deviate from the spirit and scope of the present disclosure can be arbitrarily modified, replaced and modified without deviating from the spirit and scope of the present disclosure.
Claims
1. A semiconductor device, comprising: The silicon carbide epitaxial layer includes: p-type well region; The junction field-effect region is adjacent to the p-type well region; A heavily doped n-type region, on the surface of the p-type well region; and A heavily doped p-type region, which is below the heavily doped n-type region and within the p-type well region; Island-shaped oxides, located in the field-effect region of the junction; A gate oxide layer covering the p-type well region, the junction field-effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide; and A polycrystalline silicon layer is located on the gate oxide layer and is not in contact with the island oxide.
2. The semiconductor device as claimed in claim 1, characterized in that, The width of the island oxide is smaller than the width of the junction field-effect region.
3. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the maximum spacing between the polycrystalline silicon layer and the junction field-effect region to the width of the junction field-effect region is greater than 0.
075.
4. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The first metal layer contacts the heavily doped p-type region and the heavily doped n-type region through the metal silicide.
5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A silicon carbide substrate, located beneath the silicon carbide epitaxial layer; as well as A second metal layer is located beneath the silicon carbide substrate.
6. A method for manufacturing a semiconductor device, comprising: A silicon carbide epitaxial layer is provided, wherein a p-type well region, a heavily doped n-type region on the surface of the p-type well region, a heavily doped p-type region below the heavily doped n-type region and within the p-type well region, and a junction field-effect region adjacent to the p-type well region are predefined on the silicon carbide epitaxial layer. Deposited oxide layer; A patterning process is applied to the oxide layer to form island-shaped oxides, wherein the island-shaped oxides are located on the junction field-effect region; A gate oxide layer is deposited to cover the p-type well region, the junction field-effect region, the heavily doped n-type region, the heavily doped p-type region, and the island oxide; and A polycrystalline silicon layer is deposited on the gate oxide layer.
7. The method of claim 6, characterized in that, The width of the island oxide is smaller than the width of the junction field-effect region.
8. The method of claim 6, characterized in that, The ratio of the maximum spacing between the polycrystalline silicon layer and the junction field-effect region to the width of the junction field-effect region is greater than 0.
075.
9. The method of claim 6, characterized in that, Also includes: Form the first metal layer; as well as The first metal layer is patterned to form the source and gate contacts.
10. The method of claim 6, characterized in that, Also includes: A silicon carbide substrate is formed beneath the silicon carbide epitaxial layer; as well as A second metal layer is formed beneath the silicon carbide substrate.