Electronic component separated from wafer by backside recess and recess extension
By combining back-side grooves and groove extensions on the wafer, the problem of low separation efficiency and material waste in the prior art is solved, realizing efficient and fast wafer separation and material utilization, and is applicable to wafer separation of various thicknesses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2026-03-24
AI Technical Summary
Existing technologies are inefficient and underutilize materials when separating electronic components from wafers, especially for small electronic components, which can lead to significant waste.
By forming back-side grooves and groove extensions on the wafer, through-holes are formed using a combination of mechanical cutting and plasma cutting to separate electronic components. The back-side grooves are wider and the groove extensions are narrower, which reduces the amount of material removed from the front side and improves the separation efficiency.
It enables efficient and rapid separation of wafers into individual electronic components, reduces material loss, increases the yield of electronic components per wafer, and is suitable for wafer separation of various thicknesses.
Smart Images
Figure CN121728992A_ABST
Abstract
Description
Technical Field
[0001] Various embodiments relate to a method for separating electronic components from a wafer and an electronic component. Background Technology
[0002] Packages can be represented, for example, as encapsulated electronic chips that have electrical connections and are mounted onto electronic peripherals, such as printed circuit boards. Prior to packaging, a semiconductor wafer is separated into multiple electronic chips. After the wafer is separated into individual electronic chips, the chips can then be used for further processing.
[0003] Separation can be achieved by mechanically or by laser cutting the wafer. However, the separation process can be slow and may result in the loss of a significant portion of the wafer that could be used to manufacture electronic components, especially in the case of smaller electronic components. Summary of the Invention
[0004] It may be necessary to make efficient use of wafer area and to separate electronic components from the wafer in a rapid manner.
[0005] According to an exemplary embodiment, a method for separating electronic components from a wafer is provided, wherein the method includes: providing a semiconductor substrate for the wafer, the semiconductor substrate having a front side with an active region and a back side covered by a functional layer, the wafer including a plurality of integrally connected electronic components arranged side by side; forming a back side recess extending through the functional layer into the semiconductor substrate between adjacent electronic components; and forming a recess extension connected to the back side recess, thereby forming a through-hole extending through the front side to separate adjacent electronic components from each other, wherein the back side recess is formed with a maximum horizontal width greater than the maximum horizontal width of the recess extension.
[0006] According to another exemplary embodiment, an electronic component is provided, comprising a semiconductor substrate, an active region on the front side of the semiconductor substrate, and a functional layer on the back side of the semiconductor substrate, wherein the sidewall of the electronic component has a notch extending laterally into the functional layer and into a connection portion of the semiconductor substrate.
[0007] According to an exemplary embodiment, an efficient and rapid method is provided for separating a wafer having an active region on a front side and a functional layer on a back side into individual electronic components. The corresponding separation method can form a back-side recess that extends through the functional layer and into a portion of the semiconductor substrate. Subsequently, the separation method can form a recess extension such that the back-side recess and the recess extension are connected to each other to form a via that facilitates the separation of the wafer into individual electronic components. Advantageously, the recess extension has a smaller maximum horizontal width than the back-side recess. Advantageously, this separation method can remove only a smaller width of material from the front side adjacent to the active region, which allows for a large number of electronic components per unit wafer area with minimal loss in the dicing path (e.g., by plasma dicing). Simultaneously, the described manufacturing method allows for the rapid formation of wider back-side recesses (e.g., by mechanical dicing) that have already separated the functional layer and extend additionally into a portion of the semiconductor substrate thickness, wherein the absence of an active region on the back side makes the removal of a larger amount of material locally confined to the back-side region unimportant in terms of efficient wafer volume utilization. The resulting electronic component may have, for example, a sidewall characteristic of the described manufacturing process, having a notch in the functional layer and in the connection portion of the semiconductor substrate. The notch may be located at a position where a back-side groove has already been formed during the manufacturing process.
[0008] Description of other exemplary embodiments
[0009] Further exemplary embodiments of the method and electronic components will be explained below.
[0010] In the context of this application, the term "wafer" may specifically refer to a semiconductor-based plate or disk that has been processed to form multiple integrated circuit elements in the active areas of the wafer and can be diced into multiple individual electronic components or chips. For example, a wafer may have a matrix arrangement of electronic components in rows and columns. It is possible that a wafer has a circular geometry or a polygonal geometry (e.g., a rectangular geometry or a triangular geometry).
[0011] In the context of this application, the term "electronic component" can specifically encompass semiconductor chips (specifically, power semiconductor chips), active electronic devices (e.g., transistors), passive electronic devices (e.g., capacitors or inductors or ohmic resistors), sensors (e.g., pressure sensors, light sensors, or gas sensors), actuators (e.g., loudspeakers), and microelectromechanical systems (MEMS, such as loudspeakers, components including mechanical springs, etc.). However, in other embodiments, the electronic component can also be of different types, such as electromechanical components, particularly mechanical switches, etc.
[0012] In the context of this application, the term "semiconductor substrate" may specifically refer to a body comprising semiconductor material. The semiconductor body may initially be part of a semiconductor wafer and may be separable from the wafer composite during the manufacturing process. For example, the semiconductor body comprises silicon or silicon carbide. The semiconductor body may be made primarily of semiconductor material. For example, the semiconductor body may be a plate-like structure, a cubic structure, or a disk-like structure.
[0013] In the context of this application, the term "active region" may specifically refer to a surface region of a semiconductor substrate of a wafer or electronic component, on which at least one monolithic integrated circuit element (e.g., transistor, diode, capacitor, resistor, etc.) is formed. Specifically, such an active region may be a surface region of a wafer or electronic component formed on its positive side.
[0014] In the context of this application, the term "functional layer" may specifically refer to a layer that can be disposed on (e.g., attached to) the back side of a wafer or electronic component to provide a specified function during the use of an easily manufactured electronic component and / or during the manufacture of the electronic component. For example, a functional layer may be a dark band. However, many different functions can be implemented by a functional layer, such as electrical and / or thermal insulation functions, electrical and / or thermal conductivity functions, mechanical functions, protective functions against chemical and / or physical effects, and / or optical functions (e.g., shielding or absorbing light or enhancing contrast).
[0015] In the context of this application, the term "backside recess" may specifically refer to a long, narrow channel or recess extending into the back side of a semiconductor substrate. A backside recess may extend along multiple juxtaposed electronic components of a wafer. Thus, a backside recess may be an elongated blind via extending through a portion of a functional layer and a semiconductor substrate. A backside recess may be straight and / or curved. Multiple backside recesses may be formed along rows and columns to facilitate the separation of a two-dimensional wafer into individual electronic components. Each separated electronic component may be surrounded by four backside recesses along the four sidewalls of the electronic component.
[0016] In the context of this application, the term "groove extension" may specifically refer to a void region extending from the front side of a semiconductor substrate to a back side groove. Thus, the groove extension and the back side groove can together form a via extending through the entire wafer. Specifically, a groove extension without a connected back side groove can be a front side groove, i.e., a long, narrow groove or recess extending into the front side of the semiconductor substrate. The groove extension may have a single continuous width along its entire vertical extension, or it may consist of two or more vertical segments with different widths. The groove extension may be straight and / or curved. Multiple groove extensions may be formed along rows and columns to facilitate the separation of a two-dimensional wafer into individual electronic components. Each separated electronic component may be surrounded by four groove extensions along the four sidewalls of the electronic component.
[0017] In the context of this application, the term "via" may specifically refer to a void region extending across the entire passageway between the front and back sides of a semiconductor substrate including a functional layer thereon. The via may be elongated. The via may have a straight and / or curved shape. Multiple vias may be formed along rows and columns for separating a two-dimensional wafer into individual electronic components.
[0018] In the context of this application, the term "maximum horizontal width" may specifically refer to the maximum horizontal width of the entire vertical extension of a groove, recess, hole, or void structure (e.g., a back groove or groove extension or a portion thereof) that extends through at least a portion of a semiconductor substrate and / or functional layer.
[0019] In the context of this application, the term "notch" may specifically refer to a sidewall recess. A notch may be defined in a portion of a semiconductor substrate and in a functional layer thereon. Alternatively, another notch may be defined in another portion of a semiconductor substrate and in a back-end process structure thereon. For example, such a notch may be a blind via in a sidewall. Such a notch may be defined solely by the material of the semiconductor substrate and the material of the functional layer, or by the material of the semiconductor substrate and the material of the back-end process structure. Such a notch may be closed around the periphery of an electronic component, for example, in a ring-like manner.
[0020] In one embodiment, the method includes forming a back-side groove by mechanical cutting or by laser cutting. Specifically, mechanical cutting enables rapid individualization while the relatively wide scribe lines produced on the back side do not negatively impact the number of electronic components obtainable per wafer.
[0021] In one embodiment, the method includes forming a groove extension by machining from the front side until the groove extension connects with the back side groove. Machining the back side groove and the groove extension from the front side allows for a simple separation process.
[0022] However, in another embodiment, the groove extension can also be formed by processing from the back side.
[0023] In one embodiment, the method includes forming at least a portion of the groove extension by plasma cutting. Advantageously, plasma cutting can achieve very narrow scribe lines, which can have a positive impact on the number of electronic components available per wafer.
[0024] In one embodiment, the method includes forming a groove extension through two processing stages (particularly through two dicing stages). For example, the first stage may be specifically tuned to open up the back-end process structure, while the second stage may be specifically tuned to obtain narrow scribing lines for obtaining a large number of electronic components per wafer.
[0025] In one embodiment, the method includes forming an extension of the groove to the outer portion of the front side by laser grooving. Advantageously, laser grooving can cut through the back-end process structure.
[0026] In one embodiment, the method includes forming an inner portion of the groove extension vertically between the back-side groove and the outer portion by plasma cutting. Plasma cutting is an excellent choice for obtaining narrow scribe lines within a semiconductor body, allowing for the production of a large number of electronic components per wafer.
[0027] In one embodiment, the method includes: providing a back-end process (BEOL) structure for a semiconductor substrate on an active region, and forming a recessed extension that extends through the back-end process structure. Such a back-end process structure may include a metallization pattern that can be cut, for example, by laser grooving.
[0028] In one embodiment, the method includes forming a back-side recess with a maximum horizontal width ranging from 20 μm to 50 μm, particularly from 25 μm to 35 μm. Although relatively large, given the absence of active regions on the back side, scribe lines on the back side do not negatively impact the number of electronic components per wafer. However, this can advantageously enable a rapid first part of the individualization process.
[0029] In one embodiment, the method includes forming the outer portion of the groove extension to have a maximum horizontal width in the range of 10 μm to 35 μm, particularly in the range of 15 μm to 25 μm. Corresponding scribing lines can be formed by laser grooving. The moderate width of the scribing lines in this process is compatible with the efficient use of wafer area, while simultaneously enabling the opening of the BEOL structure.
[0030] In one embodiment, the method includes forming the inner portion of the groove extension to have a maximum horizontal width in the range of 5 μm to 30 μm, particularly in the range of 10 μm to 20 μm. Such extremely small scribing, obtainable through plasma cutting, can advantageously realize a very large number of electronic components per wafer.
[0031] In an embodiment, the method includes: forming a back-side groove wider than the outer portion of the groove extension (specifically, having a larger maximum horizontal width), wherein, specifically, the inner portion of the groove extension is formed narrower than the outer portion of the groove extension (specifically, having a smaller maximum horizontal width). This configuration can be obtained by mechanically cutting the back-side groove, forming the outer portion of the groove extension by laser grooving, and forming the inner portion of the groove extension by plasma cutting.
[0032] In one embodiment, the method includes forming the inner portion of the groove extension with substantially vertical sidewalls. Such geometry can be obtained by plasma cutting.
[0033] In one embodiment, the method includes forming a concave tapering section at the interface between an outer portion of the groove extension and an inner portion of the groove extension. Such a concave tapering section may be a feature of laser grooving used to form the outer portion.
[0034] In one embodiment, the method includes forming a concave tapering section at the interface between the back side groove and the inner portion of the groove extension. Such a concave tapering section may be a feature of a mechanical cut used to form the back side groove.
[0035] In an embodiment, the method includes: forming a conductive connection structure on the front side and embedding the conductive connection structure in a temporary protective carrier; subsequently, thinning a semiconductor substrate on the back side; subsequently, forming the functional layer on the back side of the thinned semiconductor substrate before forming the back side groove; and removing the temporary protective carrier used to form the back side groove. For example, the conductive connection structure can be a solder structure, particularly solder bumps or solder balls. Other conductive connection structures are also possible, such as sintered structures or conductive adhesives. By temporarily covering the conductive connection structure with a protective carrier, the conductive connection structure can be protected from impacts during the thinning of the semiconductor substrate by grinding (particularly from slurry or debris). The latter can be removed after thinning the semiconductor substrate and after forming and cutting the functional layer.
[0036] In an embodiment, the method includes: forming a conductive connection structure on the positive side and coating the conductive connection structure with an anti-plasma coating; subsequently forming the groove extension, the groove extension being in the semiconductor substrate and extending through the anti-plasma coating; and subsequently removing the anti-plasma coating. Advantageously, the conductive connection structure (e.g., solder bumps) can be temporarily protected from plasma cutting. Further advantageously, the corresponding temporary anti-plasma coating can also be compatible with the laser process that can be used when forming the groove extension.
[0037] In this embodiment, the transition at the notch between the functional layer and the semiconductor substrate is continuous and stepless. Specifically, the functional layer and the semiconductor substrate may define vertical, inclined, and / or curved notch surfaces without any discontinuity therebetween. This can be the result of forming the notch through mechanical cutting.
[0038] In one embodiment, the sidewall has a step between the notch and another connection portion of the semiconductor substrate. Such geometric features at the sidewall of the electronic component can be obtained when the notch is formed by mechanical cutting.
[0039] In one embodiment, another connecting portion has a vertical segment adjacent to the step, wherein, in particular, the other connecting portion has another notch adjacent to the vertical segment, wherein, more specifically, the notch extends laterally into the semiconductor substrate deeper than the other notch. The vertical segment can be obtained by forming the corresponding sidewall portion through plasma cutting. The other notch can be the result of forming the corresponding sidewall portion by laser grooving. A notch formed by laser grooving may not be as pronounced as a notch formed by mechanical cutting.
[0040] In an alternative embodiment, the vertical segment of the other connection portion extends from the step all the way to the front side. Therefore, it is possible that further steps are omitted (e.g., if the material does not contain a low dielectric in the back-end process stack). The slot forming the other notch can then be replaced by plasma etching, allowing further steps to be omitted, and the groove already has the width of the vertical segment.
[0041] In embodiments, the functional layer includes at least one of a protective layer, an insulating layer, a metallization layer, a plastic layer, a die attachment layer, an opaque layer, and a light contrast enhancement layer. The functional layer can be a permanent functional layer that forms part of an easily manufactured electronic component. For example, the function of the functional layer can be protection, isolation, facilitating die attachment, providing darkness so that the light detection of the electronic component is not affected by light refraction, marking functionality, or providing interference from metal reservoirs for improved attachment or improved shielding. The functional layer can be electrically insulating, conductive, light-absorbing, contrast-enhancing, and / or prevent mechanical and / or chemical effects.
[0042] In this embodiment, the electronic component is a power semiconductor chip. Such a power semiconductor chip may integrate one or more integrated circuit elements, such as transistors (e.g., field-effect transistors, such as metal-oxide-semiconductor field-effect transistors and / or bipolar transistors, such as insulated-gate bipolar transistors) and / or diodes. An exemplary application that can be provided by such integrated circuit elements is for switching purposes. For example, such integrated circuit elements of a power semiconductor device may be integrated in a half-bridge or full-bridge. An exemplary application is automotive applications.
[0043] Electronic components (particularly semiconductor chips) may include at least one of the group consisting of diodes and transistors (more specifically, insulated-gate bipolar transistors). For example, electronic chips can be used as semiconductor chips for power applications, such as in the automotive field. In embodiments, at least one semiconductor chip may include a logic IC or semiconductor chip for RF power applications. In embodiments, semiconductor components may be used as one or more sensors or actuators in a microelectromechanical system (MEMS), such as as a pressure sensor or accelerometer, as a microphone, as a speaker, etc.
[0044] A semiconductor substrate (i.e., a silicon substrate) can be used as the substrate or wafer for the semiconductor component. Alternatively, silicon oxide or another insulating substrate can be provided. A germanium substrate or a III-V semiconductor material may also be implemented. For example, exemplary embodiments can be implemented using GaN or SiC technology.
[0045] Furthermore, exemplary embodiments may utilize standard semiconductor processing techniques, such as appropriate etching techniques (including isotropic and anisotropic etching techniques, particularly plasma etching, dry etching, and wet etching), patterning techniques (which may involve photolithographic masks), and deposition techniques (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.). Attached Figure Description
[0046] The accompanying drawings illustrate exemplary embodiments and are included to provide a further understanding of the exemplary embodiments, and form part of the specification.
[0047] In the attached diagram:
[0048] Figure 1 A cross-sectional view of an electronic component according to an exemplary embodiment is shown.
[0049] Figure 2 A cross-sectional view of a wafer that has been separated into multiple electronic components according to an exemplary embodiment is shown.
[0050] Figures 3 to 9 A cross-sectional view of a structure obtained during the execution of a method for separating electronic components from a wafer, according to an exemplary embodiment, is shown.
[0051] Figure 10 A flowchart of a method for separating electronic components from a wafer according to an exemplary embodiment is shown.
[0052] Figures 11 to 17 A cross-sectional view of a structure obtained during the execution of a method for separating electronic components from a wafer, according to another exemplary embodiment, is shown. Detailed Implementation
[0053] The illustrations in the attached figures are schematic and not necessarily drawn to scale.
[0054] Before describing exemplary embodiments in more detail with reference to the accompanying drawings, some general considerations will be outlined based on exemplary embodiments that have been developed.
[0055] Compared to other methods, plasma cutting is a preferred method for separating very small dies due to the smaller required scribe line width (e.g., about 30 μm). Therefore, separating electronic components from wafers via plasma cutting can significantly increase the number of semiconductor dies available per wafer.
[0056] For example, typical die sizes for some applications can be 600 × 600 μm or 600 × 1200 μm. Considering a typical scribing width of, for example, 60 μm, a significant amount of wafer area is lost due to sizing. More specifically, plasma dicing can reduce the scribing width from 60 μm to 24 μm, which allows for a significant increase in the number of dies per wafer. When processing expensive wafers, especially due to complex wafer-to-wafer bonding processes, the wafer area loss due to dicing can be particularly problematic. Given the above, it is highly desirable to increase the number of semiconductor dies per wafer. Compared to mechanical dicing processes, plasma dicing can ensure a considerably large scribing width, such as 30 μm.
[0057] However, there may be applications and scenarios where plasma cutting is not desired or considered. For example, there may be applications requiring a back-side protective strip that cannot be separated by plasma. Additionally, applications using die thicknesses from 200μm to 250μm may be too thick for effective plasma cutting. When supplying solder balls, for example, with a diameter of 170μm, to electronic components, a thick coating is required during plasma processing, which can complicate the manufacturing process.
[0058] According to an exemplary embodiment, a semiconductor wafer can be efficiently separated into individual electronic components. Each electronic component, including the wafer and the electronic components initially still integrally attached to the wafer composite, can have an active region with an integrated circuit on the front side and an attachment functional layer on the back side. The separation process can initially include forming a back-side groove extending through the functional layer and a connection portion of the semiconductor substrate of the wafer. In one or more additional processing stages, a groove extension can be formed in the front side having its active region and aligned with the back-side groove, such that the front-side groove and the groove extension together separate the wafer into individual electronic components. Advantageously, the groove extension can be laterally narrower than the back-side groove, such that only a small amount of material is removed during separation from the front side having its active region. Therefore, due to the minimal loss from dicing in the front side, the number of electronic components obtainable from the wafer can be very large. The larger material loss on the back side can be acceptable because the back side is spatially spaced from the active region, allowing dicing techniques that ensure rapid back-side groove formation to be used to accelerate the individualization process. For example, electronic components obtained from such a manufacturing method may have a recessed sidewall portion on the back side covered by a functional layer. The recess may be a feature formed during individualization of the back side groove.
[0059] More specifically, as an example of a functional layer, an exemplary embodiment can implement plasma cutting for individualizing electronic components with permanent back-side tape. The functional layer, together with the connected semiconductor portion, can be subjected to rapid mechanical cutting to form a back-side groove. Subsequently, the groove extension can be formed at least partially in the front side by plasma cutting, optionally and preferably supported by laser grooving. Due to plasma cutting, very small scribe lines can be achieved on the front side, thereby enabling a large number of electronic components per wafer. Therefore, the semiconductor thickness can be locally reduced using a rapid mechanical cutting method (e.g., mechanical cutting) to open the back-side functional layer into the semiconductor substrate. Subsequently, an optional laser cutting process (which can have narrower scribe lines than the aforementioned mechanical cutting process) can be performed from the front side, cutting through another portion of the back-end process structure and the semiconductor substrate, and then the remaining wafer thickness can be cut by plasma etching with very narrow scribe lines.
[0060] In one embodiment, a method for plasma cutting a die having a back-side adhesive tape is provided. More specifically, a method for wafer plasma cutting can be provided, wherein the wafer includes adhesive tape on its back side. The method may include: grinding the wafer and laminating its back side with the tape, mechanically cutting and creating a half-cut in the back side, applying a plurality of balls to the front side and embedding them into the tape, performing a tape cut on the back side, coating the balls and the front side with a high-viscosity coating material (e.g., a laser and plasma compatible coating), laser grooving the front side, plasma cutting the die, and cleaning (e.g., using water).
[0061] By integrating plasma dicing from the front side into the dicing process, smaller scribe lines (e.g., in the range of 10 μm to 20 μm) can be obtained, which can be significantly smaller than the scribe line width obtained by mechanical dicing. This can increase the number of dies per wafer. Advantageously, mechanical dicing from the back side can allow dicing through tape or other types of functional layers (e.g., with scribe line widths in the range of 25 μm to 40 μm). Therefore, such a process can allow for easy patterning of the back side tape. Furthermore, an efficient mechanical dicing process is possible through single-cut and high feed rates. In addition, the mechanical dicing process can be operated on unseparated wafers. Since the die-to-die distance on the front side can be smaller than the dicing channel, the dicing blade width does not limit the number of dies per wafer. Further advantageously, the execution of the mechanical dicing process for groove formation can allow the die thickness range to extend to thicknesses that are no longer efficient for simple plasma dicing. Furthermore, due to the larger die-to-die distance on the back side, die impacts during pick-up can be less likely.
[0062] In another embodiment, it is possible to reduce the plasma etching width to 3 μm to 10 μm and use a strip extension to achieve the final die-to-die distance.
[0063] In another embodiment, it is possible to change the processing order, i.e., to perform front-side processing before back-side processing.
[0064] Furthermore, the process flow may or may not have spheres or columns, making it optional.
[0065] Figure 1 A cross-sectional view of an electronic component 100 according to an exemplary embodiment is shown. The electronic component 100 shown may be a semiconductor die, such as a power semiconductor die.
[0066] In its vertical central portion, the electronic component 100 includes a semiconductor substrate 104, such as a silicon substrate. For example, the thickness of the semiconductor substrate 104 can range from 100 μm to 500 μm, for example, 250 μm. An active region 108 can be formed in the positive side portion at the positive side 106 of the semiconductor substrate 104. For example, the active region 108 can extend to a depth of up to 10 μm to 40 μm (particularly from 20 μm to 30 μm) in the semiconductor substrate 104. For example, the active region 108 can include one or more monolithic integrated circuit elements, such as field-effect transistors and / or diodes. The active region 108 can be formed using semiconductor technology.
[0067] A back-end process (BEOL) structure 124 can be formed on the active region 108. The BEOL structure 124 may include, for example, a patterned metal interconnect layer on the semiconductor substrate 104 that is connected to integrated devices in the active region 108. The BEOL structure 124 may also interconnect one or more integrated circuit elements (e.g., transistors, capacitors, resistors, etc.) with metal wiring. For example, the BEOL structure 124 may include a front-side metallization portion having a patterned metal layer stack.
[0068] As shown in the figure, electronic component 100 may include one or more conductive connection structures 130 on a back-end process structure 124 above active region 108. For example, such conductive connection structure 130 may be a solder bump. In the illustrated embodiment, a plurality of solder bumps (e.g., having a diameter of 170 μm) implemented as solder balls are provided. Alternatively, other conductive connection structures 130 are contemplated, such as sintering paste, conductive adhesive, etc.
[0069] Opposite to the front side 106 of the semiconductor substrate 104 is its back side 110. A functional layer 112 may be attached to the back side 110 of the semiconductor substrate 104. For example, the vertical thickness of the functional layer 112 may range from 10 μm to 50 μm. In the illustrated embodiment, the functional layer 112 may be a black adhesive tape (e.g., comprising a plastic material) attached to the back side 110. The functional layer 112 remains permanently attached to the semiconductor substrate 104 and can therefore be referred to as a permanent functional layer 112. However, in other embodiments, the functional layer 112 may have different functions. For example, functional layer 112 may be a protective layer (e.g., protecting the interior of electronic component 100 from chemical or mechanical effects), an insulating layer (e.g., protecting electronic component 100 from electrical creepage current), a metallization layer (e.g., shielding electronic component 100 from electromagnetic radiation), a die attachment layer (e.g., including an adhesive for attaching electronic component 100 to a support), an opaque layer (for protecting electronic component 100 from light), and / or a light contrast enhancement layer (e.g., for enhancing light contrast or for engraving alphanumeric information).
[0070] The sidewall 136 of the electronic component 100 forms the outer peripheral and lateral boundary surface of the electronic component 100 between the horizontal front side 106 and the horizontal back side 110. For example, the electronic component 100 may have a substantially rectangular or cuboid shape. For example, each of the four outer peripheral sidewall portions may have Figure 1 The shapes of the opposing sidewalls 136 are shown. As shown, each of the two opposing sidewalls 136 has a notch 138 that extends laterally into the functional layer 112 and into the connection portion 142 of the semiconductor substrate 104. More specifically, the notch 138 extends laterally from the back side 110 into the entire functional layer 112 and into the connection portion of the semiconductor substrate 104, and upwards to the central portion of the semiconductor substrate 104. As shown, the transition at the notch 138 between the functional layer 112 and the connection portion 142 of the semiconductor substrate 104 is continuous and stepless. Therefore, there is no structural discontinuity in the notch 138 at the back side 110, thus forming an interface between the functional layer 112 and the semiconductor substrate 104. Although not shown, the sidewall 136 may have a notch 138 extending along the entire outer perimeter of the electronic component 100. Therefore, the notch 138 may be a closed-loop notch extending along the lateral perimeter of the electronic component 100.
[0071] refer to Figure 1Each sidewall in the sidewalls 136 may have a step 146 between the recess 138 and another connection portion 144 of the semiconductor substrate 104. The other connection portion 144 extends from the step 146 at the upper end of the recess 138 toward the positive end 106 of the semiconductor substrate 104. As shown, the other connection portion 144 has a straight vertical segment 148 adjacent to the step 146 and extending upward from the step 146 to another step 152. For example, the vertical thickness of the sidewall portion between the step 146 and the other step 152 can be in the range of 20 μm to 150 μm. Furthermore, the other connection portion 144 has another recess 140 adjacent to the vertical segment 148 and extending upward from the other step 152 to the positive side 106 and beyond the entire back-end process structure 124. For example, the vertical extension of the other recess 140 can be in the range of 5 μm to 20 μm. Figure 1 It can also be seen that the deeper recess 138 extends laterally into the semiconductor substrate 104 more deeply than the shallower recess 140.
[0072] In an alternative embodiment (not shown), a vertical segment 148 of another connecting portion 144 can extend straight up from step 146 to the front side 106 and optionally also extend through the rear-end process structure 124. Therefore, it is possible that another notch 140 and another step 152 are missing (e.g., if the material in the rear-end process structure 124 does not contain a low dielectric). Then, for example, when plasma etching replaces the laser processing, the slot or another notch 140 formed by the laser processing (described below) can be omitted. The further step 152 can then be omitted, and the entire portion of the sidewall 136 above step 146 already has the width of the vertical segment 148 extending to the upper main surface of the electronic component 100.
[0073] For example, Figure 1 The electronic component 100 can be referenced below. Figures 3 to 9 The described manufacturing process is formed. No alternative to the notch 140 described above can be obtained through this manufacturing process. Note that the two-stage laser processing and plasma cutting to the front side 106 can be replaced by a single plasma cutting process without laser processing. The plasma cutting process may be slower than the mechanical cutting process used to form the notch 138, but it can achieve a narrow bottleneck in the interior of the wafer 102 between two adjacent electronic components 100. Advantageously, using plasma cutting can save wafer area and can increase the yield of the electronic components 100 due to the narrow plasma cutting lines.
[0074] Figure 2 A cross-sectional view of a wafer 102 that has been separated into a plurality of electronic components 100 according to an exemplary embodiment is shown. Figures 3 to 9 The following description will explain how to obtain Figure 2 The structure within. (See reference) Figure 2 This will describe some of the geometric properties of the structure. Figure 2 Two electronic components 102 are shown, arranged side by side adjacent to each other and separated from a common wafer 102. Figure 2 The separate electronic components 100 are still mounted on the common dicing tape 154. Between adjacent electronic components 100, through-hole type separation channels or grooves 156 are formed, extending through the functional layer 112, the entire semiconductor substrate 104 from the front side 106 to the back side 110, and the back-end process structure 124.
[0075] For example Figure 2 As shown, the back-side recess 114 of the notch 138 forming the electronic component 100 in wafer 102 has a maximum horizontal width w1 preferably in the range of 25 μm to 35 μm. For example, the vertical extension of the back-side recess 114 can be at least 50%, particularly at least 60%, of the thickness of the electronic component 100. The back-side recess 114 can preferably be formed by mechanical cutting using a dicing blade or by laser ablation. Furthermore, the outer portion 120 of the recess extension 116 of another notch 140 forming the electronic component 100 in wafer 102 has a maximum horizontal width w2 preferably in the range of 15 μm to 25 μm. Furthermore, the inner portion 122 of the recess extension 116 of the straight vertical segment 148 forming the electronic component 100 in wafer 102 has a maximum horizontal width w3 preferably in the range of 10 μm to 20 μm. The maximum horizontal width w3 can also be expressed as the plasma etching width, as it can be defined by a plasma etching process. As shown in the figure, the mentioned maximum horizontal widths w1, w2, and w3 are formed to satisfy the condition w1 > w2 > w3. Advantageously, w2 and w3 are smaller than w1, which allows for efficient use of the wafer area 102 to form a large number of electronic components 100 without excessive loss due to scribing. However, the segments according to w1 can be formed by a rapid mechanical dicing process without affecting the active regions 108 of the corresponding electronic components 100. Therefore, the efficient use of wafer area can be combined synergistically with the rapid dicing process.
[0076] The minimum opening required for plasma etching (e.g., from 10 μm to 20 μm) can correspond to the bottom laser slot width. The top width of the laser slot (corresponding to the maximum horizontal width w2) can, for example, be in the range of 15 μm to 25 μm. Furthermore, a tapered shape (due to the laser profile) can be formed between the top and bottom slot widths, for example, with a dimension of approximately 5 μm.
[0077] Figures 3 to 9A cross-sectional view of the structure obtained during the execution of a method for separating electronic component 100 from wafer 102, according to an exemplary embodiment, is shown.
[0078] refer to Figure 3 A wafer 102 is provided after the formation of integrated circuit elements in the wafer 102 is completed. The wafer 102 is provided with a semiconductor substrate 104 (e.g., a silicon body) having a front side 106 with active regions 108 and integrated circuit elements and a back side 110. The wafer 102 includes a plurality of electronic components 100 (e.g., semiconductor dies) arranged side-by-side and still integrally connected. For example, the integrally connected electronic components 100 may be arranged in rows and columns within a wafer composite. As shown, the semiconductor substrate 104 has a back-end process structure 124 (i.e., a BEOL stack, such as a patterned metallization) on the active regions 108. Furthermore, conductive connection structures 130 (e.g., solder bumps) may be formed on the front side 106. For example, the conductive connection structures 130 may have a diameter in the range of 100 μm to 250 μm, such as solder balls with a diameter of 170 μm. After having individual electronic components 100, electronic components 100 can be connected to electronic peripherals (e.g., mounting bases such as printed circuit boards or carriers such as lead frame structures) by establishing solder connections using solder-type conductive connection structures 130.
[0079] Figure 3 The wafer 102 shown is ready to be separated into its individual electronic components 100. Therefore, Figure 3 The loaded wafer 102 is shown after ball application and wafer testing.
[0080] refer to Figure 4 The conductive connection structure 130 can be embedded in a temporary protective carrier 132. For example, the temporary protective carrier 132 can be a grinding tape or a glass carrier. The temporary protective carrier 132 can be used to embed the spherical conductive connection structure 130 to protect the spherical conductive connection structure 130 during subsequent thinning processes, especially for slurries or grinding debris generated during such thinning processes.
[0081] Subsequently, by removing material from the back side 110 of the semiconductor substrate 104 until the target thickness of the semiconductor substrate 104 is achieved, the resulting structure can undergo thinning of the back side 110. This can be achieved, for example, by mechanical polishing.
[0082] refer to Figure 5After thinning, the functional layer 112 (e.g., a back-side protective strip) is attached to the back side 110. This can be done, for example, by adhesive or by lamination. Therefore, the functional layer 112 can be formed on the back side 110 of the thinned semiconductor substrate 104 before the back-side recess 114 is formed. Thereafter, the process continues to form a back-side recess 114 extending through the functional layer 112 into the semiconductor substrate 104 between adjacent electronic components 100. Advantageously, the back-side recess 114 is formed by a rapid dicing process (e.g., mechanical dicing). Alternatively, laser dicing can be performed to form the back-side recess 114 extending through the entire back-side portion of the functional layer 112 and the semiconductor substrate 104. The process of forming the back-side recess 114 terminates within the semiconductor substrate 104. During the described mechanical dicing from the back side 110 of the semiconductor substrate 104, back-side alignment may be advantageous. For example, such back-side alignment can be achieved by capturing a camera image from the bottom side.
[0083] refer to Figure 6 The diagram shows a cross-sectional view of the entire wafer 102 after a plurality of parallel back-side grooves 114 have been formed between each of two adjacent electronic components 100. Similarly, additional back-side grooves 114 may be formed in a direction perpendicular to the surface plane of the wafer 102, to separate all four sides of the respective electronic component 100. Optionally, for stability, dicing is not performed along the entire wafer edge (e.g., the cut-in portion).
[0084] refer to Figure 7 The functional layer 112, constructed simultaneously from the back side groove 114, has been mounted on the cutting strip 154. Furthermore, the temporary protective carrier 132 can be removed after thinning and after the back side groove 114 has been formed. Thereafter, the exposed conductive connection structure 130 can be coated with an anti-plasma coating 134. This anti-plasma coating 134 protects the conductive connection structure 130 during subsequent plasma cutting processes. Furthermore, the anti-plasma coating 134 can also provide some protection for the conductive connection structure 130 during subsequent laser processes. Therefore, the material of the anti-plasma coating 134 can be a laser- and plasma-compatible coating material, preferably having a high viscosity.
[0085] Subsequently, the first of two processes for forming the groove extension 116 is performed. Through this first process, the outer portion 120 of the groove extension 116 is formed to extend into the front side 106 by laser grooving. As... Figure 7 As shown, the outer portion 120 of the groove extension 116 extends through the entire thickness of the anti-plasma coating 134, through the back-end process structure 124, and into the front side portion of the semiconductor substrate 104. As shown, the laser grooving process is performed from the front side 106. From... Figure 7It can also be seen that the horizontal width of the outer portion 120 of the groove extension 116 currently being formed is smaller than the horizontal width of the back groove 114. This is because the outer portion 120 is formed by laser grooving, while the back groove 114 is formed by mechanical cutting.
[0086] In summary, wafer 102 can have its functional layer 112 mounted on dicing tape 154, anti-plasma coating 134 is provided on conductive connection structure 130 with a high-viscosity laser and plasma compatible coating material, and then laser grooving is performed from the front side 106.
[0087] refer to Figure 8 The second process in a two-stage process for forming the recess extension 116 is performed to complete the separation of the individual electronic components 100. During the second process, the remaining thickness of the semiconductor substrate 104 between the outer portion 120 of the recess extension 116 and the back-side recess 114 is bridged by removing further material of the semiconductor substrate 104 between them through plasma cutting from the front side 106, thereby forming a narrow inner portion 122 of the recess extension 116. Thus, the formation of the recess extension 116, which connects to the back-side recess 114, can be completed, thereby forming a through-hole 118 extending vertically through the entire wafer 102 to separate adjacent electronic components 100 from each other. Advantageously, the recess extension 116 can have its outer portion 120 formed by laser grooving and its inner portion 122 formed by plasma cutting. Therefore, the vertical formation of the inner portion 122 of the recess extension 116 between the back-side recess 114 and the outer portion 120 can be achieved by plasma cutting. Plasma cutting can be performed until the opposing back-side recess 114 or saw hole is reached. Therefore, the recess extension 116 can be formed by machining from the front side 106 until the recess extension 116 connects with the back-side recess 114. Specifically, plasma cutting can be achieved using reactive ion etching (RIE). Advantageously, plasma cutting can form very narrow scribe lines, resulting in minimal loss of wafer volume through individualization processes, and a large number of electronic components 100 per unit area wafer 102 can be obtained. After forming the recess extension 116, the individual electronic components 100 are separated from the wafer composite. As shown, according to... Figure 1 100 electronic components.
[0088] It is possible that the inner portion 122 of the groove extension 116 has a substantially vertical sidewall 150 formed in the straight vertical section 148. Furthermore, a concave tapering section 126 may be formed at the interface between the outer portion 120 of the groove extension 116 and the inner portion 122 of the groove extension 116. Additionally, another concave tapering section 128 may be formed at the interface between the back groove 114 and the inner portion 122 of the groove extension 116.
[0089] Also refer to Figure 2 The back-side groove 114 is formed with a maximum horizontal width w1 greater than the maximum horizontal width w2 of the groove extension 116. The minimum width at the bottleneck of the through-hole 118 between the two separate electronic components 100 can be the maximum horizontal width w3 in the inner portion 122 formed by plasma cutting. Therefore, the back-side groove 114 can be wider than the outer portion 120 of the groove extension 116, wherein the inner portion 122 of the groove extension 116 is formed to be even narrower than the outer portion 120 of the groove extension 116.
[0090] In another embodiment (not shown), it is also possible that the entire groove extension 116 is formed by a single further cutting process (preferably by plasma cutting only).
[0091] refer to Figure 9 The anti-plasma coating 134 can be removed to expose the conductive connection structure 130. This removal process can be implemented, for example, as a water rinsing process. Afterward, the electronic component 100 can be removed from the dicing strip 154. The easily manufactured electronic component 100 can be used, for example, for packaging. This can involve establishing a solder connection between the exposed conductive connection structure 130 and another electronic component.
[0092] Figure 10 A flowchart 200 illustrates a method for separating electronic components 100 from wafer 102 according to an exemplary embodiment.
[0093] Reference box 202 (comparison) Figure 3 Conductive connection structure 130 is formed on the front side 106 of wafer 102.
[0094] Reference box 204 (comparison) Figure 4 The resulting structure undergoes thinning on the back side 110.
[0095] Reference box 206 (comparison) Figure 5 The functional layer 112 is attached to the back side 110 and forms a back side groove 114.
[0096] Reference box 208 (comparison) Figure 7The first of two processes for forming the groove extension 116 is performed by forming the outer portion 120 of the groove extension 116 extending into the front side 106.
[0097] Reference box 210 (comparison) Figure 8 The second process in the two-stage process for forming the groove extension 116 is performed to complete the separation of the individual electronic component 100.
[0098] Figures 11 to 17 A cross-sectional view of a structure obtained during a method of separating electronic component 100 from wafer 102, according to another exemplary embodiment, is shown.
[0099] refer to Figure 11 The wafer 100 may have a central semiconductor substrate 104, which has an active region 108 on its front side 106 and a back-end process structure 124 thereon. A functional layer 112 may be attached to the back side 110 of the semiconductor substrate 104. Therefore, Figure 11 Wafer 102 is shown after grinding and lamination of functional layer 112, which can be implemented as a backside strip.
[0100] refer to Figure 12 The back-side groove 114 can be formed by mechanically cutting through the functional layer 112 and into the back side 110 of the semiconductor substrate 104. The mechanical cutting process can be performed from the back side 110, wherein a back-side alignment process can be advantageous.
[0101] refer to Figure 13 This provides an overview of the entire wafer 102. Optionally, for stability purposes, there may be no cuts at the edges of the entire wafer.
[0102] refer to Figure 14 For electrical connection purposes, the conductive connection structure 130 (e.g., solder ball) can be attached to the back-end process structure 124.
[0103] refer to Figure 15 A plasma-resistant coating 134 can be formed to cover the conductive connection structure 130. The wafer 102 can be mounted on the diced strip 154 at its functional layer 112. Subsequently, a laser grooving process is performed to form the outer portion 120 of the groove extension 116 (in... Figure 16 (Fully shown in the middle).
[0104] refer to Figure 16The inner portion 122 of the groove extension 116 is formed by plasma cutting. A through-hole 118 is formed extending through the wafer 102 to separate individual electronic components 100 by a combination of the back side groove 114 and the groove extension 116 (which consists of its inner portion 122 and its outer portion 120).
[0105] refer to Figure 17 The anti-plasma coating 134 is removed by a water rinsing process. Individual electronic components 100 can be removed from the cutting strip 154 and can be further processed.
[0106] It should be noted that the term "comprising" does not exclude other elements or features, and "a" does not exclude a plurality. Elements described in conjunction with different embodiments may also be combined. It should also be noted that reference numerals in the drawings should not be construed as limiting the scope of the claims. Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.
Claims
1. A method for separating electronic components (100) from a wafer (102), wherein, The method includes: A semiconductor substrate (104) is provided for the wafer (102), the semiconductor substrate (104) having a front side (106) with an active region (108) and a back side (110) covered by a functional layer (112), the wafer (102) including a plurality of integrally connected electronic components (100) arranged side by side; A back-side recess (114) is formed, the back-side recess (114) extending between adjacent electronic components (100) through the functional layer (112) into the semiconductor substrate (104); and A groove extension (116) is formed to connect to the back side groove (114), thereby forming a through hole (118) extending through the front side (106) to separate adjacent electronic components (100) from each other, wherein the back side groove (114) is formed with a maximum horizontal width (w1) greater than the maximum horizontal width (w2) of the groove extension (116).
2. The method according to claim 1, wherein, The method includes forming the back side groove (114) by mechanical cutting or by laser cutting.
3. The method according to claim 1 or 2, wherein, The method includes forming the groove extension (116) by machining from the front side (106) until the groove extension (116) is connected to the back side groove (114).
4. The method according to any one of claims 1 to 3, wherein, The method includes forming at least a portion of the groove extension (116) by plasma cutting.
5. The method according to any one of claims 1 to 4, wherein, The method includes forming the groove extension (116) through two processing stages.
6. The method according to any one of claims 1 to 5, wherein, The method includes: forming an upwardly extending outer portion (120) of the groove extension (116) to the front side (106) by laser grooving.
7. The method according to claim 6, wherein, The method includes forming an inner portion (122) of the groove extension (116) vertically located between the back groove (114) and the outer portion (120) by plasma cutting.
8. The method according to any one of claims 1 to 7, wherein, The method includes: providing a back-end process structure (124) for the semiconductor substrate (104) on the active region (108), and forming the groove extension (116) to extend through the back-end process structure (124).
9. The method according to any one of claims 1 to 8, comprising at least one of the following features: in, The method includes: forming the back side groove (114) to have a maximum horizontal width (w1) in the range of 20 μm to 50 μm, particularly in the range of 25 μm to 35 μm; The method includes forming the outer portion (120) of the groove extension (116) to have a maximum horizontal width (w2) in the range of 10 μm to 35 μm, particularly in the range of 15 μm to 25 μm. The method includes forming the inner portion (122) of the groove extension (116) to have a maximum horizontal width (w3) in the range of 5 μm to 30 μm, particularly in the range of 10 μm to 20 μm.
10. The method according to any one of claims 1 to 9, wherein, The method includes: forming the back side groove (114) wider than the outer portion (120) of the groove extension (116), wherein, in particular, the inner portion (122) of the groove extension (116) is formed narrower than the outer portion (120) of the groove extension (116).
11. The method according to claim 10, wherein, The method includes forming the inner portion (122) of the groove extension (116) to have substantially vertical sidewalls (150).
12. The method according to claim 10 or 11, wherein, The method includes forming a concave tapering section (126) at the interface between the outer portion (120) of the groove extension (116) and the inner portion (122) of the groove extension (116).
13. The method according to any one of claims 10 to 12, wherein, The method includes forming a concave tapering section (128) at the interface between the back side groove (114) and the inner portion (122) of the groove extension (116).
14. The method according to any one of claims 1 to 13, wherein, The method includes: A conductive connection structure (130) is formed on the positive side (106), and the conductive connection structure (130) is embedded in a temporary protective carrier (132); Subsequently, the semiconductor substrate (104) is thinned at the back side (110); Subsequently, prior to forming the back-side recess (114), the functional layer (112) is formed on the back side (110) of the thinned semiconductor substrate (104); and After the back side groove (114) is formed, the temporary protective carrier (132) is removed.
15. The method according to any one of claims 1 to 14, wherein, The method includes: A conductive connection structure (130) is formed on the positive side (106), and the conductive connection structure (130) is coated with an anti-plasma coating (134); Subsequently, the groove extension (116) is formed in the semiconductor substrate (104) and extends through the anti-plasma coating (134); and Subsequently, the anti-plasma coating (134) is removed.
16. An electronic component (100), comprising: Semiconductor substrate (104); The active region (108) at the positive side (106) of the semiconductor substrate (104); and A functional layer (112) on the back side (110) of the semiconductor substrate (104); The sidewall (136) of the electronic component (100) has a notch (138) that extends laterally into the functional layer (112) and into the connection portion (142) of the semiconductor substrate (104).
17. The electronic component (100) according to claim 16, wherein, The sidewall (136) has a step (146) between the recess (138) and another connection portion (144) of the semiconductor substrate (104).
18. The electronic component (100) according to claim 17, wherein, The other connecting portion (144) has a vertical section (148) adjacent to the step (146).
19. The electronic component (100) according to claim 18, comprising one of the following features: in, The other connecting portion (144) has another notch (140) adjacent to the vertical segment (148), wherein, more specifically, the notch (138) extends laterally into the semiconductor substrate (104) more deeply than the other notch (140); The vertical section (148) of the other connecting portion (144) extends from the step (146) all the way to the front side (106).
20. The electronic component (100) according to any one of claims 16 to 19, comprising at least one of the following features: in, The transition at the notch (138) between the functional layer (112) and the connection portion (142) of the semiconductor substrate (104) is continuous and without steps; The functional layer (112) includes at least one of a protective layer, an isolation layer, a metallization layer, a plastic layer, a die attachment layer, an opaque layer, and a light contrast enhancement layer. Includes the back-end process structure (124) on the active region (108); Includes at least one conductive connection structure (130) on or above the active region (108), particularly on the back-end process structure (124) on the active region (108); The sidewall (136) has a notch (138) extending along the entire outer periphery of the electronic component (100).