Silicon-on-insulator and method of making same
By employing multiple low-dose hydrogen ion implantations and stepwise energy adjustments, the problems of non-uniform damage and stress gradient in the buried oxide layer during SOI fabrication were solved, achieving uniformity and thickness control of the buried oxide layer and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-03-24
AI Technical Summary
In existing SOI fabrication technologies, high-energy hydrogen ion implantation leads to non-uniform damage to the buried oxide layer, microbubble aggregation, and stress gradients, affecting the yield and performance of nanoscale devices.
A multi-stage ion implantation process is employed, with low-dose hydrogen ion implantation performed step by step, gradually increasing the implantation energy to form an embrittlement layer at the target lift-off depth. This is combined with the Smart Cut™ process to fabricate silicon-on-insulator.
It significantly improves the continuity and thickness uniformity of the buried oxide layer, reduces lattice damage, improves the interface quality and thickness measurement accuracy of the buried oxide layer, and meets the dielectric performance requirements of ultrathin buried oxide layers.
Smart Images
Figure CN121729062A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to silicon-on-insulator and its manufacturing method. Background Technology
[0002] SOI (Silicon-on-Insulator) is a three-layer semiconductor material consisting of a top layer of single-crystal silicon, a buried oxide layer (BOX) of silicon dioxide, and a silicon substrate. Its core advantage lies in achieving electrical isolation between the device and the substrate through the buried oxide layer, significantly reducing parasitic capacitance and leakage current, and improving chip speed, energy efficiency, and radiation resistance. It is particularly suitable for high-performance computing, 5G RF, and automotive electronics. Currently, mainstream SOI wafer fabrication technologies include SIMOX (Separation by Implantation of Oxygen), BESOI (Bonding Etching-Back), and Smart-Cut™ (Smart Stripping Technology). SIMOX involves implanting a high dose of oxygen ions into the silicon substrate, followed by high-temperature annealing to form the buried oxide layer. However, it suffers from problems such as significant implantation damage, limited buried oxide layer thickness, and high cost. BESOI (Bond-Etched-Back Injection) involves bonding two wafers (one with a thermally buried oxide layer) and then thinning the top silicon layer through mechanical grinding and chemical mechanical polishing (CMP). This yields high-quality crystals, but thickness uniformity control is difficult and material waste is significant. Smart-Cut™ is the mainstream process. It first implants hydrogen ions into a silicon wafer to form an embrittled layer, then bonds another silicon wafer and performs thermal annealing to peel off the layer, achieving precise transfer of a thin silicon layer. This process combines high uniformity and material recyclability with significant cost-effectiveness. However, in advanced processes, such as FD-SOI devices below 3nm, the demand for ultra-thin buried oxide layers is increasing, and the requirements for dielectric uniformity and film thickness control precision far exceed the capabilities of traditional processes. During ion implantation, high-energy hydrogen ions can cause non-uniform damage, microbubble aggregation, and stress gradients in the buried oxide layer, severely limiting the yield and performance of nanoscale devices. Summary of the Invention
[0003] The purpose of this invention is to provide silicon on insulator and its manufacturing method to solve the problems of non-uniform damage, microbubble aggregation and stress gradient caused by high-energy hydrogen ions in the buried oxide layer during ion implantation.
[0004] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing silicon on an insulator, comprising:
[0005] A device substrate is provided, on which a buried oxide layer is formed;
[0006] Multiple ion implantation processes are performed to form an embrittlement layer at the target stripping depth; the ion implantation process is a single hydrogen ion implantation process and the implantation energy increases sequentially in the multiple ion implantation processes.
[0007] Optionally, the steps of performing multiple ion implantation processes include:
[0008] The first ion implantation process is performed to implant hydrogen ions into the first depth region and form initial defects and hydrogen accumulation points;
[0009] A second ion implantation process is performed to create extended damage to the target ablation depth;
[0010] A third ion implantation process is performed to implant hydrogen ions into the second depth region and complete homogenization.
[0011] Optionally, the implantation energy of the first ion implantation process is 10 keV to 30 keV, the implantation energy of the second ion implantation process is 30 keV to 50 keV, and the implantation energy of the third ion implantation process is 50 keV to 100 keV.
[0012] Optionally, the depth of the second depth region is greater than the target peeling depth, and the target peeling depth is greater than the depth of the first depth region.
[0013] Optionally, the depth of the first depth region is 50nm to 100nm, the target stripping depth is 200nm to 300nm, and the depth of the second depth region is 300nm to 400nm.
[0014] Optionally, the implantation dose of the second ion implantation process is greater than the implantation dose of the third ion implantation process, and the implantation dose of the third ion implantation process is greater than the implantation dose of the first ion implantation process.
[0015] Optionally, the implantation dose for the first ion implantation process is 1.5 E16 cm⁻¹. -2 Up to 2E16 cm -2 The implantation dose for the second ion implantation process is 3.2 E16 cm⁻¹. -2 Up to 10E16 cm -2 The implantation dose for the third ion implantation process is 1.7 E16 cm⁻¹. -2 Up to 3E16 cm -2 .
[0016] Optionally, the total implantation dose for the multiple ion implantation processes is 6.2E16 cm⁻¹. -2 .
[0017] Optionally, the electron beam current is the same in all the ion implantation processes described.
[0018] Based on the same inventive concept, the present invention also provides silicon on insulator, which is prepared by the silicon on insulator manufacturing method described in any of the above claims.
[0019] In the method for manufacturing silicon-on-insulator provided by this invention, a device substrate is provided, on which a buried oxide layer is formed; a multiple ion implantation process is performed to form an embrittlement layer at a target lift-off depth; the ion implantation process is a single hydrogen ion implantation process, and the implantation energy increases sequentially in the multiple ion implantation processes. The multiple ion implantation process optimizes the process through a step-by-step, low-dose strategy, significantly improving accuracy: for example, ion implantation is performed in three stages, with the total dose remaining constant, and the dose of each implantation is lower, reducing the accumulation of lattice damage from a single ion implantation. The continuity of the buried oxide layer is improved, and the thickness deviation can be controlled. Multiple ion implantation combined with gradient implantation energy adjustment can precisely control the oxygen ion distribution: by adjusting the implantation energy of each stage, overlapping oxygen concentration peaks are formed in the longitudinal direction, which fuse into a uniform buried oxide layer after annealing. Attached Figure Description
[0020] Figure 1 This is a flowchart of a method for manufacturing silicon-on-insulator according to an embodiment of the present invention. Detailed Implementation
[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the silicon-on-insulator and its manufacturing method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0022] The current mainstream SOI preparation technology is the Smart-Cut™ method, which relies on hydrogen ion implantation to achieve layer transfer. However, single high-dose hydrogen ion implantation causes problems such as non-uniform damage to the buried oxide layer, microbubble aggregation, and stress-induced optical distortion. A single implantation creates a hydrogen concentration peak region at a specific depth, which disrupts the SiO2 network through nuclear blocking mechanisms (elastic collisions) and electron blocking mechanisms (ionization), leading to dielectric constant fluctuations and thickness measurement errors, thus causing non-uniform damage to the buried oxide layer. During annealing, hydrogen aggregates in the peak region, forming microbubbles and causing uneven density distribution in the buried oxide layer. The lateral stress gradient in the implanted region changes the refractive index through photoelasticity, interfering with the accuracy of measuring instruments (ellipsometers) and causing stress-induced optical distortion. Existing improvement methods such as high-temperature annealing or helium ion implantation cannot completely eliminate intrinsic non-uniformity and increase costs or introduce new defects.
[0023] In one example, the fabrication process based on ion implantation microbubble layer separation includes three stages: ion implantation, reinforcement bonding, and heat treatment. In the ion implantation stage, hydrogen ions or rare gas ions (such as He) are implanted onto the semiconductor wafer surface. + By controlling the implantation energy, ions are used to form a microbubble defect layer at a specific depth on the subsurface, which separates the wafer into a lower host substrate and an upper thin film region. During the reinforcement bonding stage, the implanted wafer surface is bonded to a rigid support substrate (such as a silicon oxide-coated wafer) via electrostatic bonding, adhesive-assisted bonding, and direct deposition bonding. In the thermal treatment stage, the bonded structures are thermally treated, and thin film separation is achieved through the synergistic effect of crystal rearrangement and internal pressure release. The crystal rearrangement effect involves the aggregation and expansion of microbubbles; the internal pressure release effect involves the gas pressure within the bubbles breaking through the lattice bonding forces. This example reduces costs by avoiding heterogeneous substrates and using high-dose implantation, but the microbubble merging process may leave surface pits or microcracks, affecting the uniformity of the buried oxide layer thickness.
[0024] Therefore, the core idea of this invention is to provide a device substrate on which a buried oxide layer is formed; to perform multiple ion implantation processes to form an embrittlement layer at the target lift-off depth; the ion implantation process is a single hydrogen ion implantation process, and the implantation energy increases sequentially in each of the multiple ion implantation processes. The multiple ion implantation process in this invention optimizes the process through a step-by-step, low-dose strategy, significantly improving accuracy: for example, ion implantation is performed in three stages, with the total dose remaining constant, but the dose for each implantation is lower, reducing the accumulation of lattice damage from a single ion implantation. The continuity of the buried oxide layer is improved, and thickness deviation can be controlled. Multiple ion implantation combined with stepped implantation energy adjustment can precisely control the oxygen ion distribution: by adjusting the implantation energy for each stage, overlapping oxygen concentration peaks are formed in the longitudinal direction, which fuse into a uniform buried oxide layer after annealing.
[0025] Figure 1 This is a flowchart of a method for manufacturing silicon-on-insulator according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for manufacturing silicon-on-insulator, including:
[0026] Step S10: Provide a device substrate on which a buried oxide layer is formed;
[0027] Step S20: Perform multiple ion implantation processes to form an embrittlement layer at the target stripping depth; the ion implantation process is a single hydrogen ion implantation process and the implantation energy in the multiple ion implantation processes increases sequentially.
[0028] In step S10, the device substrate can be a single-crystal silicon or polycrystalline silicon substrate, or it can be made of semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, etc., or it can be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art can select a suitable substrate type according to the needs of the device, and the type of substrate should not limit the scope of protection of this invention. A buried oxide layer is formed on the device substrate, and the thickness of the buried oxide layer is, for example, 1000 angstroms.
[0029] In step S20, the steps of performing multiple ion implantation processes include:
[0030] Step S21: Perform the first ion implantation process to implant hydrogen ions into the first depth region and form initial defects and hydrogen accumulation points;
[0031] Step S22: Perform a second ion implantation process to create extended damage to the target peeling depth;
[0032] Step S23: Perform the third ion implantation process to implant hydrogen ions into the second depth region and complete homogenization.
[0033] The implantation energy of the first ion implantation process is less than that of the second ion implantation process, and the implantation energy of the second ion implantation process is less than that of the third ion implantation process. The depth of the second depth region is greater than the target stripping depth, and the target stripping depth is greater than the depth of the first depth region. The implantation dose of the second ion implantation process is greater than that of the third ion implantation process, and the implantation dose of the third ion implantation process is greater than that of the first ion implantation process. The electron beam current of the first ion implantation process, the electron beam current of the second ion implantation process, and the electron beam current of the third ion implantation process are the same.
[0034] In step S21, the implantation energy of the first ion implantation process is, for example, 10 keV to 30 keV, and can also be 20 keV. The implantation dose of the first ion implantation process is, for example, 1.5 E16 cm⁻¹. -2 Up to 2E16 cm -2 The beam current for the first ion implantation process is, for example, 10 mA. The depth of the first depth region is 50 nm to 100 nm. Low-energy implantation is performed on the device substrate to form a shallow damage layer. In this embodiment, low-energy implantation uses an implantation energy of 20 keV to form initial defects and hydrogen accumulation points in a shallow region with a depth of approximately 50 nm to 100 nm. This is equivalent to creating a buffer layer near the surface of the device substrate to prevent subsequent high-energy implantation from directly impacting the deeper layers.
[0035] In step S22, the implantation energy of the second ion implantation process is 30 keV to 50 keV, and can also be 40 keV. The implantation dose of the second ion implantation process is 3.2 E16 cm⁻¹. -2 Up to 10E16 cm -2 The implantation electron beam current in the second ion implantation process is, for example, 10 mA. The target lift-off depth is 200 nm to 300 nm. Medium-energy implantation is performed on the device substrate to extend the damage to the target lift-off depth. In this embodiment, a medium-energy implantation of 40 keV is used in the second ion implantation process to extend the damage to the target lift-off depth of approximately 200 nm to 300 nm. Medium-energy ions penetrate deeper, overlapping with shallow damage to form continuous defect bands, promoting uniform nucleation of hydrogen bubbles.
[0036] In step S23, the implantation energy of the third ion implantation process is 50 keV to 100 keV, and can also be 74 keV. The implantation dose of the third ion implantation process is 1.7 E16 cm⁻¹. -2 Up to 3E16 cm -2 When selecting within this range, the chosen implantation dose can be greater than that of the first ion implantation process. The implantation beam current for the third ion implantation process is, for example, 10 mA. The depth of the second depth region is 300 nm to 400 nm. High-energy implantation is performed on the device substrate to achieve deep homogenization. In this embodiment, 74 keV high-energy implantation is used in the third ion implantation process to achieve homogenization in a deeper region of approximately 300 nm to 400 nm. The implantation dose for the third ion implantation process is, for example, 1.7E16 cm⁻¹. -2 (The implantation dose for the first ion implantation process can be selected as 1.6E16 cm⁻¹) -2 Less than 1.7E16 cm -2 The implantation dose is relatively low, and the high-energy ion dose is relatively low. By overlapping the damage peaks, the overall hydrogen concentration distribution is smoothed out, reducing the stress gradient. After annealing, the damaged layer fuses into a uniform weakened zone, making crack propagation more controllable during peeling.
[0037] Subsequently, the device substrate after the three ion implantation processes is subjected to plasma processing using the Smart Cut™ process to bond the device substrate to the support substrate, peel off along the embrittlement layer to remove part of the device substrate thickness, and perform hardening, chemical mechanical polishing (CMP) and other steps to obtain the SOI wafer. The thickness of the SOI wafer reaches the target thickness, such as 3000 Å.
[0038] This embodiment also provides silicon-on-insulator (SOI), fabricated using any of the above-described methods. It includes a device substrate, a support substrate, and a buried oxide layer located between the device substrate and the support substrate.
[0039] The applicant conducted experimental verification. The experiment included a first control group, a second control group, and an experimental group.
[0040] In the first control group, a single-crystal silicon wafer with a buried oxide layer (as a buried oxide layer) on its surface was selected as the device substrate. The thickness of the device substrate ranged from 773 μm to 775 μm, the resistivity was 8 Ω·cm to 15 Ω·cm, and the thickness of the buried oxide layer ranged from 800 nm to 1200 nm. The buried oxide layer was formed by thermal oxidation. A single-crystal silicon wafer was provided as a support substrate. The thickness of the support substrate ranged from 773 μm to 775 μm, the resistivity was 3 kΩ·cm to 20 kΩ·cm. Ion implantation was performed on the buried oxide layer on the surface of the device substrate. The implantation ion source was H implantation, the implantation electron beam current was, for example, 10 mA, the implantation energy was, for example, 74 keV, and the implantation dose was, for example, 6.2E16 cm⁻¹. -2 The device substrate and support substrate surfaces are pre-cleaned using an RCA cleaning process. Plasma treatment is then applied to the device substrate and support substrate surfaces to activate them. The device substrate and support substrate are then bonded, possibly using vacuum bonding. The bonded wafer is then peeled off to form a silicon-on-insulator (SOS) structure. The SOS is then hardened: the wafer is placed in a furnace under a pure argon (Ar) atmosphere; the temperature is raised to a first temperature of 850°C, and the atmosphere is changed to a first atmosphere of pure oxygen; then the temperature is raised to a second temperature of 1100°C, and the atmosphere is changed to a second atmosphere of pure Ar. The SOS undergoes single-wafer cleaning and oxide layer rinsing and etching, followed by a standard RCA cleaning process; the SOS surface is then planarized using CMP polishing. The SOS structure is then examined using transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS) line scanning.
[0041] Table 1.1 Thickness of Buried Oxygen Layer MAX MEAN MIN RANGE 1120.974 1117.071 1113.149 7.825
[0042] Table 1.2 Si and O content element Content (wt%) Si 44.8 O 55.2
[0043] As shown in Tables 1.1 and 1.2, the buried oxide layer thickness is greater than 1000 angstroms, and the Si to O content ratio is not 1:2. Experimental results indicate anomalies in the thickness measurement of the silicon BOX layer on the insulator prepared by this process and in the Si to O content ratio. A single high-dose hydrogen ion implantation causes a sudden increase in local temperature of the silicon substrate, triggering high-energy implantation that results in an uneven silicon / oxide interface, leading to fluctuations in the BOX layer thickness. High-dose implantation easily forms discrete SiO2 precipitates rather than a continuous and uniform buried oxide layer.
[0044] In the second control group, a single-crystal silicon wafer with an oxide layer (as a buried oxide layer) on its surface was selected as the device substrate. The thickness of the device substrate ranged from 773 μm to 775 μm, and the resistivity ranged from 8 Ω·cm to 15 Ω·cm. The thickness of the buried oxide layer ranged from 800 nm to 1200 nm, and the oxide layer was formed by thermal oxidation. A single-crystal silicon wafer was provided as a support substrate. The thickness of the support substrate ranged from 773 μm to 775 μm, and the resistivity ranged from 3 kΩ·cm to 20 kΩ·cm. Ion implantation was performed on the oxide layer on the surface of the device substrate. The implantation ion source was H implantation. The implantation electron beam current in the first ion implantation process was, for example, 10 mA, the implantation energy was, for example, 20 keV, and the implantation dose was, for example, 2.5E16 cm⁻¹. -2 The implantation electron beam current in the second ion implantation process is, for example, 10 mA, the implantation energy is, for example, 74 keV, and the implantation dose is, for example, 3.7E16 cm⁻¹. -2 The device substrate and support substrate surfaces are pre-cleaned using an RCA cleaning process. The surfaces are then activated by plasma treatment. The device substrate and support substrate are bonded, possibly using vacuum bonding. The bonded wafer is then peeled off to form a silicon-on-insulator (SOS) structure. The SOS is then hardened: the wafer is placed in a furnace tube in a pure Ar atmosphere; the temperature is raised to a first temperature, and the atmosphere changes to a first atmosphere of pure oxygen at 850°C; then the temperature is raised to a second temperature, and the atmosphere changes to a second atmosphere of pure Ar at 1100°C. The SOS is then individually cleaned, and the oxide layer is rinsed and etched before switching to the standard RCA cleaning process. The SOS surface is then CMP polished and planarized. Finally, the SOS structure is inspected using TEM and EDS line scans.
[0045] Table 2.1 Thickness of Buried Oxygen Layer MAX MEAN MIN RANGE 1150.247 1147.836 1144.557 5.69
[0046] Table 2.2 Si and O content element Content (wt%) Si 60.8 O 39.2
[0047] As shown in Tables 2.1 and 2.2, the buried oxide layer thickness is greater than 1000 angstroms, and the Si to O content ratio is not 1:2. Experimental results indicate that the thickness measurement of the silicon BOX layer on the insulator prepared by this process and the Si to O content ratio still show anomalies.
[0048] In the experimental group, a single-crystal silicon wafer with an oxide layer (as a buried oxide layer) on its surface was selected as the device substrate. The thickness of the device substrate ranged from 773 μm to 775 μm, and the resistivity ranged from 8 Ω·cm to 15 Ω·cm. The thickness of the buried oxide layer ranged from 800 nm to 1200 nm, and the oxide layer was formed by thermal oxidation. A single-crystal silicon wafer was provided as a support substrate. The thickness of the support substrate ranged from 773 μm to 775 μm, and the resistivity ranged from 3 kΩ·cm to 20 kΩ·cm. Ion implantation was performed on the oxide layer on the surface of the device substrate. The implantation ion source was H implantation. The implantation electron beam current in the first ion implantation process was, for example, 10 mA, the implantation energy was, for example, 20 keV, and the implantation dose was, for example, 1.5E16cm. -2 The implantation electron beam current in the second ion implantation process is, for example, 10 mA, the implantation energy is, for example, 40 keV, and the implantation dose is, for example, 3E16 cm⁻¹. -2 The implantation electron beam current in the third ion implantation process is, for example, 10 mA, the implantation energy is, for example, 74 keV, and the implantation dose is, for example, 1.7E16 cm⁻¹. -2 The device substrate and support substrate surfaces are pre-cleaned using an RCA cleaning process. The surfaces are then activated by plasma treatment. The device substrate and support substrate are bonded, possibly using vacuum bonding. The bonded wafer is then peeled off to form a silicon-on-insulator (SOS) structure. The SOS is then hardened: the wafer is placed in a furnace tube in a pure Ar atmosphere; the temperature is raised to a first temperature, and the atmosphere changes to a first atmosphere of pure oxygen at 850°C; then the temperature is raised to a second temperature, and the atmosphere changes to a second atmosphere of pure Ar at 1100°C. The SOS is then individually cleaned, and the oxide layer is rinsed and etched before switching to the standard RCA cleaning process. The SOS surface is then CMP polished and planarized. Finally, the SOS structure is inspected using TEM and EDS line scans.
[0049] Table 3.1 Thickness of Buried Oxygen Layer MAX MEAN MIN RANGE 1002.59 999.06 995.63 6.96
[0050] Table 3.2 Si and O content element Content (wt%) Si 36.5 O 63.5
[0051] Tables 3.1 and 3.2 show that the average thickness of the buried oxide layer is less than and close to 1000 angstroms, and the Si to O content ratio is close to 1:2. The results indicate that the thickness measurement of the silicon-on-insulator (BOX) layer prepared by this process is normal, and the thickness range is within a reasonable range. The Si to O content ratio is also normal. Multiple implantation, through a step-by-step, low-dose strategy, significantly improves accuracy: the total dose remains constant, but implantation is performed in three stages, with each implantation having a lower dose, reducing the accumulation of lattice damage from a single implantation. The continuity of the BOX layer is improved, and thickness deviation can be controlled. Multiple implantation combined with gradient energy adjustment allows for precise control of oxygen ion distribution: by adjusting the energy of each implantation, overlapping oxygen concentration peaks are formed in the longitudinal direction, which fuse into a uniform BOX layer after annealing.
[0052] Experimental verification showed that dividing the ion implantation process into three ion implantations resulted in normal buried oxide layer thickness measurements after high-energy implantation, while a single high-dose implantation (first control group) led to abnormal buried oxide layer thickness, proving the effectiveness of stepwise dose control. Therefore, reducing the dose is a key factor in minimizing buried oxide layer damage.
[0053] In this embodiment, the risk of damage to the buried oxide layer is low during the high-energy injection phase, mainly due to the reduced dose and the stepwise strategy. The total dose is 6.2E16 cm⁻¹. -2 However, after stepwise injection, the high-energy injection dose was only 1.7E16 cm⁻¹. -2 (Approximately 27% of the total dose). Compared to a single high-dose injection (first control group, dose 6.2E16 cm⁻¹). -2 The energy of a single damage event is significantly reduced, minimizing local thermal spikes and lattice damage, thus minimizing the impact on the BOX layer (SiO2). While high-energy ions may reach the vicinity of the BOX layer (depth approximately 300-400 nm), they are implanted in stages: the first two steps (low-energy and medium-energy implantation) pre-form damage bands, dispersing stress. During high-energy implantation, hydrogen ions primarily ionize atoms through electron blocking mechanisms rather than direct collisions via nuclear blocking mechanisms, resulting in a milder impact on SiO2.
[0054] In this embodiment, multiple single-H implantations, through stepwise dose control and stepped energy adjustment, significantly reduce lattice damage and interface roughening caused by a single high-dose implantation, thereby achieving precise control of the BOX layer thickness at the atomic scale. This improves the interface quality and thickness measurement accuracy of the buried oxide layer (BOX).
[0055] In summary, the silicon-on-insulator manufacturing method provided in this invention includes a device substrate on which a buried oxide layer is formed; multiple ion implantation processes are performed to form an embrittlement layer at a target lift-off depth; the ion implantation process is a single hydrogen ion implantation process, and the implantation energy increases sequentially in each of the multiple ion implantation processes. The multiple ion implantation process in this invention optimizes the process through a step-by-step, low-dose strategy, significantly improving accuracy: for example, ion implantation is performed in three stages, with the total dose remaining constant, but each implantation dose is lower, reducing the accumulation of lattice damage from a single ion implantation. The continuity of the buried oxide layer is improved, and thickness deviations can be controlled. Multiple ion implantation combined with stepped implantation energy adjustment allows for precise control of oxygen ion distribution: by adjusting the implantation energy for each stage, overlapping oxygen concentration peaks are formed vertically, which fuse into a uniform buried oxide layer after annealing.
[0056] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing silicon-on-insulator, characterized in that, include: A device substrate is provided, on which a buried oxide layer is formed; Multiple ion implantation processes are performed to form an embrittlement layer at the target peeling depth; The ion implantation process is a single-hydrogen ion implantation process, and the implantation energy increases sequentially in the multiple ion implantation processes.
2. The method for manufacturing silicon-on-insulator as described in claim 1, characterized in that, The steps involved in performing a multiple ion implantation process include: The first ion implantation process is performed to implant hydrogen ions into the first depth region and form initial defects and hydrogen accumulation points; A second ion implantation process is performed to create extended damage to the target ablation depth; A third ion implantation process is performed to implant hydrogen ions into the second depth region and complete homogenization.
3. The method for manufacturing silicon-on-insulator as described in claim 2, characterized in that, The implantation energy of the first ion implantation process is 10 keV to 30 keV, the implantation energy of the second ion implantation process is 30 keV to 50 keV, and the implantation energy of the third ion implantation process is 50 keV to 100 keV.
4. The method for manufacturing silicon-on-insulator as described in claim 2, characterized in that, The depth of the second depth region is greater than the target peeling depth, and the target peeling depth is greater than the depth of the first depth region.
5. The method for manufacturing silicon-on-insulator as described in claim 4, characterized in that, The depth of the first depth region is 50nm to 100nm, the target stripping depth is 200nm to 300nm, and the depth of the second depth region is 300nm to 400nm.
6. The method for manufacturing silicon-on-insulator as described in claim 2, characterized in that, The implantation dose in the second ion implantation process is greater than the implantation dose in the third ion implantation process, and the implantation dose in the third ion implantation process is greater than the implantation dose in the first ion implantation process.
7. The method for manufacturing silicon-on-insulator as described in claim 6, characterized in that, The implantation dose for the first ion implantation process was 1.5 E16 cm⁻¹. -2 Up to 2E16 cm -2 The implantation dose for the second ion implantation process is 3.2 E16cm. -2 Up to 10E16 cm -2 The implantation dose for the third ion implantation process is 1.7 E16 cm⁻¹. -2 Up to 3E16 cm -2 .
8. The method for manufacturing silicon-on-insulator as described in claim 1, characterized in that, The total implantation dose for the multiple ion implantation processes described herein is 6.2E16 cm⁻¹. -2 .
9. The method for manufacturing silicon-on-insulator as described in claim 1, characterized in that, The electron beam current is the same in all the ion implantation processes described.
10. A silicon-on-insulator, characterized in that, It is prepared by the method for manufacturing silicon on insulator as described in any one of claims 1 to 9.