SOI wafer manufacturing method
By employing two ion implantation processes with different energies during SOI wafer fabrication to form ion implantation regions, and then peeling off a portion of the device substrate along the ion implantation regions, the problem of high surface roughness in traditional processes is solved, resulting in a smoother peeled surface and lower roughness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-03-24
AI Technical Summary
Traditional ion implantation processes result in high surface roughness of SOI wafer substrates, which affects device performance.
An ion implantation region is formed in the device substrate using at least two ion implantation processes with different energies. A portion of the device substrate is then peeled off along the ion implantation region using a stripping process to form a bimodal concentration distribution to improve surface flatness.
It improves the uniformity of the peeled surface, reduces the surface roughness after peeling, and improves the surface quality of the device substrate.
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Figure CN121729064A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit technology, and in particular to a manufacturing method of SOI wafer. BACKGROUND
[0002] With the process node gradually tending to the physical limit, using SOI (silicon-on-insulator) substrate gradually becomes an important trend of integrated circuit technology development. Since the SOI substrate is a stacked structure of top silicon, insulating layer and bottom silicon, the device on the top silicon is well electrically isolated from the bottom silicon, and therefore has more advantages in integrated circuit applications, such as reducing device substrate leakage, reducing process, reducing parasitic capacitance, and isolating noise.
[0003] In the process of preparing SOI wafer, it is usually necessary to perform ion implantation on the device substrate to form an ion implantation region, and to perform device substrate peeling from the position of the ion implantation region, thereby forming a top silicon layer. However, the traditional ion implantation process makes the surface roughness of the peeled device substrate larger, thereby affecting the device performance. SUMMARY
[0004] The purpose of the present application is to provide a manufacturing method of SOI wafer to improve the surface roughness.
[0005] To achieve the above purpose, the present application provides a manufacturing method of SOI wafer, comprising:
[0006] providing a device substrate;
[0007] performing at least two ion implantation processes with different energies on the device substrate in sequence to form an ion implantation region in the device substrate;
[0008] performing a peeling process to peel off a portion of the thickness of the device substrate along the ion implantation region.
[0009] Optionally, in the manufacturing method of SOI wafer, performing at least two ion implantation processes with different energies on the device substrate in sequence comprises:
[0010] performing a first ion implantation process;
[0011] performing a second ion implantation process, the implantation energy of the second ion implantation process being greater than the implantation energy of the first ion implantation process, and the ion implantation region being formed after the first ion implantation process and the second ion implantation process.
[0012] Optionally, in the manufacturing method of SOI wafer, the ratio of the dose of the first ion implantation process to the dose of the second ion implantation is greater than or equal to 3:2.
[0013] Optionally, in the method of manufacturing the SOI wafer, the energy of the first ion implantation process is greater than or equal to 50 KeV and less than or equal to 80 KeV, and the dose of the first ion implantation process is greater than or equal to 4E16 atoms / cm 2 and less than or equal to 6E16 atoms / cm 2 .
[0014] Optionally, in the method of manufacturing the SOI wafer, the energy of the second ion implantation process is greater than or equal to 80 KeV and less than or equal to 110 KeV.
[0015] Optionally, in the method of manufacturing the SOI wafer, the dose of the second ion implantation process is greater than or equal to 1E16 atoms / cm 2 and less than or equal to 3E16 atoms / cm 2 .
[0016] Optionally, in the method of manufacturing the SOI wafer, before sequentially performing at least two ion implantation processes with different energies on the device substrate, the method of manufacturing the SOI wafer further comprises:
[0017] forming an oxide layer on the surface of the device substrate, and performing the ion implantation process on the device substrate from the surface of the oxide layer when sequentially performing at least two ion implantation processes with different energies on the device substrate.
[0018] Optionally, in the method of manufacturing the SOI wafer, the thickness of the oxide layer is 500 angstroms to 2000 angstroms.
[0019] Optionally, in the method of manufacturing the SOI wafer, before performing the stripping process, the method of manufacturing the SOI wafer further comprises:
[0020] providing a support substrate;
[0021] bonding the support substrate with the device substrate, and the oxide layer is located between the device substrate and the support substrate.
[0022] In the method for manufacturing the SOI wafer, the ion implantation zone is formed in the device substrate by sequentially performing at least two ion implantation processes with different energies on the device substrate; and then, a stripping process is performed to strip part of the thickness of the device substrate along the ion implantation zone. Since the ion implantation zone is formed by at least two ion implantation processes with different energies, a bimodal concentration distribution can be formed in the thickness direction of the ion implantation zone, and the region between the two peaks forms a platform-like structure due to the gentle change of ion concentration, so that the stripping surface after the subsequent stripping process is smoother, the uniformity of the stripping surface is improved, and the surface roughness after stripping is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 is a flowchart of the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0024] Figures 2 to 7 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0025] Figures 8 to 11 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0026] Figure 12 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0027] Figure 13 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0028] Figure 14 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0029] Figure 15 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0030] Figure 16 is a schematic diagram of the structure formed in the method for manufacturing the SOI wafer according to an embodiment of the present application;
[0031] In the specification, the reference signs are as follows:
[0032] 101 - device substrate; 102 - oxide layer; 103 - ion implantation zone; 104 - support substrate. DETAILED DESCRIPTION
[0033] The manufacturing method of the SOI wafer according to the embodiments of the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions only for the purpose of conveniently and clearly illustrating the embodiments of the present application. In addition, the structures shown in the accompanying drawings are often a part of the actual structures. In particular, the emphasis of each of the accompanying drawings is different, and different proportions are used at times.
[0034] Figure 1 is a flowchart of the manufacturing method of the SOI wafer according to the embodiments of the present application. As shown in Figure 1 , the manufacturing method of the SOI wafer according to the embodiments of the present application comprises the following steps.
[0035] Step S1: providing a device substrate;
[0036] Step S2: sequentially performing at least two ion implantation processes with different energies on the device substrate to form an ion implantation region in the device substrate;
[0037] Step S3: performing a lift-off process to lift off a partial thickness of the device substrate along the ion implantation region.
[0038] Figures 2 to 7 is a schematic diagram of the structure formed in the manufacturing method of the SOI wafer according to the embodiments of the present application. The manufacturing method of the SOI wafer according to the embodiments will be described in further detail below. Figures 2 to 7
[0039] First, step S1 is performed, as shown in Figure 2 , a device substrate 101 is provided. The device substrate 101 may, for example, be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc. In other embodiments, the device substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP) or silicon carbide (SiC), etc., a laminated structure such as silicon / silicon germanium (Si / SiGe), etc., or other epitaxial structures such as SGOI (silicon germanium on insulator), etc. In the present embodiment, the device substrate 101 is a silicon substrate.
[0040] Next, as shown in Figure 3 As shown, the step S2 is performed, and the device substrate 101 is sequentially subjected to at least two ion implantation processes with different energies to form an ion implantation region 103 in the device substrate 101. Since the ion implantation region 103 is formed by at least two ion implantation processes with different energies, a bimodal concentration distribution can be formed in the thickness direction of the ion implantation region, and a region between the two peaks forms a platform-like structure due to the gentle change of ion concentration, so that better uniformity of the separation surface can be obtained, and the roughness of the device surface after separation is reduced, and the surface roughness of the device substrate is improved.
[0041] Specifically, as shown in Figure 3 The method of sequentially performing at least two ion implantation processes with different energies on the device substrate 101 includes: first forming an oxide layer 102 on the surface of the device substrate 101, and the thickness of the oxide layer is 500 angstroms to 2000 angstroms; and then performing the ion implantation process on the device substrate 101 from the surface of the oxide layer 102.
[0042] In some embodiments, as shown in Figure 3 The ion implantation region is formed by sequentially performing two ion implantation processes on the device substrate 101. Specifically, a first ion implantation process is performed first. The energy of the first ion implantation process is greater than or equal to 50 KeV and less than or equal to 80 KeV, for example, 60 KeV or 70 KeV; the dose of the first ion implantation process is greater than or equal to 4E16 atoms / cm 2 and less than or equal to 6E16 atoms / cm 2 The ions of the first ion implantation process can be hydrogen ions.
[0043] Then, with reference to Figure 3 The second ion implantation process is performed, and the ion implantation region 103 is formed after the first ion implantation process and the second ion implantation process. Specifically, the ion implantation region formed after the first ion implantation process and the second ion implantation process has a bimodal concentration distribution (i.e., two concentration peaks are formed), the interval between the two peaks is reduced, and the region between the two peaks forms a platform-like structure due to the gentle change of ion concentration, so that the jagged morphology of the separation surface can be reduced when the separation process is performed subsequently. Compared with the ion implantation region formed by the single-peak ion implantation process, the ion implantation region formed by the two ion implantation processes with different energies in this embodiment improves the flatness of the separation surface after the separation process, thereby improving the uniformity of the separation surface, and further reducing the surface roughness after separation.
[0044] In the embodiment, the energy of the second ion implantation process is 80KeV~110KeV, for example, 90KeV or 100KeV, that is, the implantation energy of the second ion implantation process is greater than the implantation energy of the first ion implantation process, for example, the implantation energy of the first ion implantation process is 80KeV, and the implantation energy of the second ion implantation process can be 100KeV.
[0045] Preferably, the ratio of the dose of the first ion implantation process to the dose of the second ion implantation is greater than or equal to 3:2.
[0046] In the embodiment, the dose of the second ion implantation process is greater than or equal to 1E16 atoms / cm 2 and less than or equal to 3E16 atoms / cm 2 . Wherein, the dose of the second ion implantation process is less than the dose of the first ion implantation process.
[0047] For example, when the dose of the first ion implantation process is 4E16 atoms / cm 2 , the dose of the second ion implantation process is 2E16 atoms / cm 2 .
[0048] In the embodiment, the ion of the second ion implantation process is hydrogen ion.
[0049] In some embodiments, as Figure 4 shown, three ion implantation processes are sequentially performed on the device substrate 101 to form the ion implantation region 103, that is, after the second ion implantation process is performed, a third ion implantation process is performed on the device substrate 101, and the ion implantation region 103 is formed after the first ion implantation process, the second ion implantation process and the third ion implantation process.
[0050] In the embodiment, the energy of the third ion implantation process is less than the energy of the first ion implantation process, for example, the energy of the third ion implantation process can be 30KeV~45KeV.
[0051] In the embodiment, the dose of the third ion implantation process is greater than or equal to 1E16 atoms / cm 2 and less than or equal to 3E16 atoms / cm 2 , that is, the dose of the third ion implantation process is less than the dose of the first ion implantation process.
[0052] In the embodiment, the ion of the third ion implantation process is hydrogen ion, that is, the ion of the third ion implantation process is the same as the ion of the second ion implantation process and the ion of the first ion implantation process.
[0053] Then, as shown in Figure 6 step S3 is performed to perform a lift-off process to strip part of the thickness of the device substrate 101 along the ion implantation region 103. Specifically, since the ion implantation region 103 is formed by at least two ion implantation processes with different energies, compared to a single ion implantation process, a double peak concentration distribution can be formed in the thickness direction of the ion implantation region, and the region between the two peaks forms an approximately flat structure due to the gradual change in ion concentration, so that the surface cracked during the lift-off process is smoother, i.e. the lift-off surface is smoother, the uniformity of the lift-off surface is improved, and the surface roughness after lift-off is reduced.
[0054] Specifically, the method of performing the lift-off process includes: as shown in Figure 5 first, providing a support substrate 104; then, bonding the support substrate 104 and the device substrate 101, with the oxide layer 102 between the device substrate 101 and the support substrate 104; then, as shown in Figure 6 performing a lift-off process to strip part of the thickness of the device substrate 101 along the ion implantation region 103, thereby forming a bonded wafer.
[0055] After that, as shown in Figure 7 the thickness of the device substrate 101 in the bonded wafer is thinned.
[0056] An embodiment and a comparative example are provided below to further illustrate the effect of the method of manufacturing an SOI wafer provided in the embodiment.
[0057] In Example One, a device substrate 101 is provided; at least two ion implantation processes with different energies are performed on the device substrate 101 in sequence to form an ion implantation region 103 in the device substrate 101; a support substrate is provided, and the support substrate and the device substrate are bonded; then, a lift-off process is performed to strip part of the thickness of the device substrate 101 along the ion implantation region 103; after that, the device substrate 101 is thinned.
[0058] Figure 12 is a comparison diagram of single-energy ion implantation and multi-energy ion implantation in the method of manufacturing an SOI wafer in the embodiment. Figure 12 The vertical axis in -2 is the doping concentration of ions (atoms / m Figure 12As shown, the superposition curve of multi-energy ions (blue solid line) forms an ion concentration distribution plateau (the longitudinal distribution is the plateau region) in the depth range of 0.2μm~0.8μm. Compared with single ion implantation, the ion implantation region 103 formed by using at least two ion implantation processes with different energies forms a bimodal concentration distribution in the thickness direction. The region between the two peaks forms an approximately plateau-shaped structure due to the gradual change in ion concentration, thereby achieving better uniformity of the peeled surface.
[0059] Figure 13 This is a schematic diagram of the surface roughness distribution of the device substrate after the lift-off process in the SOI wafer manufacturing method of this embodiment of the invention. Figure 13 As shown, the surface roughness (Ra, i.e., average roughness) of the device substrate is <0.4 nm.
[0060] In Comparative Example 1, such as Figure 8 As shown, a device substrate 101 is provided, and an oxide layer 102 is formed on the surface of the device substrate 101; a single ion implantation process is performed on the device substrate 101 to form an ion implantation region 103 in the device substrate 101; as Figure 9 As shown, a support substrate 104 is provided, and the support substrate 104 is bonded to the device substrate 101; as Figure 10 As shown, a stripping process is performed to strip a portion of the device substrate 101 along the ion implantation region 103; as Figure 11 As shown, the device substrate 101 is thinned.
[0061] It should be noted that the process parameters (e.g., thickness) of the device substrate and the support substrate in Comparative Example 1 are exactly the same. The only difference between Comparative Example 1 and Example 1 is the ion implantation process; all other processes are the same.
[0062] like Figure 12 As shown, during the ion implantation process, in the single-energy ion implantation process, the ions show a single peak (red dashed line) at a depth of 0.4 μm and then rapidly drop to 1.0 μm.
[0063] Figure 14 This is a schematic diagram showing the surface roughness of the device substrate after the lift-off process in a comparative example of the SOI wafer manufacturing method of this invention. Figure 14 As shown, the surface roughness (Ra, i.e., average roughness) of the device substrate is 0.9 nm.
[0064] Figure 15 This is a schematic diagram of the morphology of the device substrate surface after the stripping process in Comparative Example 1 of the SOI wafer manufacturing method of this invention. Figure 16This is a schematic diagram of the surface morphology of the device substrate after the lift-off process in Embodiment 1 of the SOI wafer manufacturing method of the present invention. This is in comparison with Embodiment 1 and Comparative Example 1. Figure 15 and Figure 16 As can be seen, the SOI wafer manufacturing method provided in this embodiment, which forms the ion implantation region through at least two ion implantations of different energies, results in a smoother surface morphology of the device substrate after the stripping process compared to forming the ion implantation region by a single ion implantation (Comparative Example 1). This reduces the jagged morphology of the device substrate surface after the stripping process, improves the uniformity of the stripped surface, and reduces the roughness of the device substrate surface after stripping.
[0065] In summary, in the SOI wafer manufacturing method provided in this embodiment of the invention, an ion implantation region is formed in the device substrate by performing at least two ion implantation processes with different energies sequentially. The ion doping concentration in the ion implantation region is gradient-distributed along the thickness direction of the device substrate. Then, a lift-off process is performed to peel off a portion of the device substrate along the ion implantation region. Since the ion implantation region is formed by using at least two ion implantation processes with different energies, a bimodal concentration distribution can be formed in the thickness direction of the ion implantation region. The region between the two peaks forms a platform-like structure due to the gradual change in ion concentration, thereby making the peeled surface smoother after the subsequent lift-off process, improving the uniformity of the peeled surface, and thus reducing the surface roughness after peeling.
[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing an SOI wafer, characterized in that, include: Provide device substrates; At least two ion implantation processes with different energies are sequentially performed on the device substrate to form an ion implantation region in the device substrate; A stripping process is performed to strip a portion of the device substrate along the ion implantation region.
2. The method for manufacturing an SOI wafer as described in claim 1, characterized in that, Performing at least two ion implantation processes with different energies sequentially on the device substrate includes: Perform the first ion implantation process; A second ion implantation process is performed, wherein the implantation energy of the second ion implantation process is greater than that of the first ion implantation process, and the ion implantation region is formed after the first ion implantation process and the second ion implantation process.
3. The method for manufacturing an SOI wafer as described in claim 2, characterized in that, The ratio of the dose of the first ion implantation process to the dose of the second ion implantation process is greater than or equal to 3:
2.
4. The method for manufacturing an SOI wafer as described in claim 2, characterized in that, The energy of the first ion implantation process is greater than or equal to 50 keV and less than or equal to 80 keV.
5. The method for manufacturing an SOI wafer as described in claim 2, characterized in that, The dose of the first ion implantation process is greater than or equal to 4E16 atoms / cm². 2 And less than or equal to 6E16 atoms / cm 2 .
6. The method for manufacturing an SOI wafer as described in claim 2, characterized in that, The energy of the second ion implantation process is greater than or equal to 80 keV and less than or equal to 110 keV.
7. The method for manufacturing an SOI wafer as described in claim 2, characterized in that, The dose in the second ion implantation process is greater than or equal to 1E16 atoms / cm². 2 And less than or equal to 3E16 atoms / cm 2 .
8. The method for manufacturing an SOI wafer as described in claim 1, characterized in that, Before sequentially performing at least two ion implantation processes with different energies on the device substrate, the method for manufacturing the SOI wafer further includes: An oxide layer is formed on the surface of the device substrate; The ion implantation process is performed on the device substrate from the surface of the oxide layer when at least two ion implantation processes with different energies are performed sequentially on the device substrate.
9. The method for manufacturing an SOI wafer as described in claim 8, characterized in that, The thickness of the oxide layer is 500 angstroms to 2000 angstroms.
10. The method for manufacturing an SOI wafer as described in claim 1, characterized in that, The method for manufacturing an SOI wafer as described in claim 1, characterized in that, prior to performing the lift-off process, the method for manufacturing an SOI wafer further includes: Provide a supporting substrate; The supporting substrate is bonded to the device substrate, and the oxide layer is located between the device substrate and the supporting substrate.