Semiconductor test structure, preparation method thereof, test method and wafer

Abstract

The embodiment of the invention provides a semiconductor test structure, a preparation method thereof, a test method and a wafer, and the semiconductor test structure comprises at least one capacitor contact structure; the capacitor array structure is positioned on the at least one capacitor contact structure and comprises a plurality of capacitors which are arranged in an array along a first direction and a second direction; wherein the number of the capacitors is greater than that of the capacitor contact structures; the capacitor contact structure is connected with the plurality of capacitors.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and relates to, but is not limited to, a semiconductor test structure, a preparation method thereof, a test method and a wafer. BACKGROUND

[0002] With the continuous miniaturization of semiconductor devices, the manufacturing process of semiconductor devices is becoming more and more difficult, and the performance requirements of semiconductor devices are also increasing. In the semiconductor manufacturing process, it is usually necessary to manufacture a wafer acceptance test (WAT) structure on a scribe line between semiconductor devices on a wafer, so as to detect the performance of the semiconductor devices. However, the complexity of semiconductor devices and the continuous miniaturization of the size greatly increase the difficulty of testing, making it difficult to provide accurate and reliable electrical performance test results, and unable to effectively monitor the process flow and device structure, so as to quickly find and solve problems in the process flow, thereby affecting the yield of semiconductor devices. SUMMARY

[0003] Therefore, the main purpose of the present disclosure is to provide a semiconductor test structure, a preparation method thereof, a test method and a wafer.

[0004] To achieve the above-mentioned purpose, the technical solution of the present disclosure is as follows:

[0005] According to a first aspect of an embodiment of the present disclosure, a semiconductor test structure is provided, comprising:

[0006] at least one capacitor contact structure;

[0007] a capacitor array structure located on the at least one capacitor contact structure, comprising a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; and the capacitor contact structure is connected with a plurality of capacitors.

[0008] In an optional embodiment, a plurality of capacitors arranged along the first direction form a row capacitor group.

[0009] The capacitor contact structure is connected with at least one row capacitor group.

[0010] In an optional embodiment, the semiconductor test structure further comprises:

[0011] a plurality of transistors corresponding one-to-one to the plurality of capacitors;

[0012] a first source / drain region of the plurality of transistors is connected with a first surface of the capacitor contact structure.

[0013] a plurality of capacitors connected to a second surface of the capacitor contact structure; wherein the first surface and the second surface are two opposite surfaces of the capacitor contact structure.

[0014] In an alternative embodiment, the transistor comprises the first source / drain region, the channel region and the second source / drain region arranged along a third direction; the third direction is perpendicular to both the first direction and the second direction.

[0015] The capacitor contact structure is connected to a plurality of the row capacitor groups.

[0016] In an alternative embodiment, the capacitor contact structure is square-shaped in a plane formed by the first direction and the second direction.

[0017] In an alternative embodiment, the transistor comprises the first source / drain region, the channel region and the second source / drain region arranged along the second direction.

[0018] The capacitor contact structure is connected to one of the row capacitor groups.

[0019] In an alternative embodiment, the capacitor contact structure is strip-shaped in a plane formed by the first direction and the second direction and the capacitor contact structures are spaced apart along the second direction.

[0020] In an alternative embodiment, the semiconductor test structure further comprises:

[0021] a plurality of conductive pillars connected to the first surface or the second surface of the capacitor contact structure; the number of the conductive pillars is equal to the number of the capacitor contact structures.

[0022] In an alternative embodiment, the capacitor comprises a first electrode, a dielectric layer and a second electrode; the dielectric layer covers a surface of the first electrode and the second electrode covers a surface of the dielectric layer.

[0023] The capacitor contact structure is connected to the first electrodes of the plurality of capacitors.

[0024] According to a second aspect of the embodiments of the present disclosure, a wafer is provided, comprising:

[0025] a plurality of semiconductor devices;

[0026] a plurality of scribe lanes respectively between the semiconductor devices to separate the semiconductor devices; and

[0027] a semiconductor test structure as described in any one of the first aspect in the scribe lanes.

[0028] According to a third aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor test structure is provided, comprising:

[0029] forming at least one capacitor contact structure;

[0030] forming a capacitor array structure on the at least one capacitor contact structure, the capacitor array structure comprising a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of the capacitors is greater than the number of the capacitor contact structures; and the capacitor contact structure is connected with the plurality of capacitors.

[0031] In an optional implementation, the method further comprises:

[0032] forming a plurality of transistors arranged in an array along the first direction and the second direction;

[0033] forming a conductive material covering at least a first source / drain region of the plurality of transistors;

[0034] removing part of the conductive material to form at least one capacitor contact structure; the plurality of transistors arranged along the first direction constitutes a transistor row, and the capacitor contact structure is connected with at least one transistor row.

[0035] In an optional implementation, the method further comprises:

[0036] forming a second source / drain region, a channel region and the first source / drain region arranged along a third direction; the third direction is perpendicular to the first direction and the second direction; and the capacitor contact structure is connected with a plurality of transistor rows.

[0037] In an optional implementation, the method further comprises:

[0038] forming a second source / drain region, a channel region and the first source / drain region arranged along the second direction; and the capacitor contact structure is connected with one transistor row.

[0039] In an optional implementation, the method further comprises:

[0040] forming a conductive pillar, the conductive pillar being in contact with the capacitor contact structure, and the number of the conductive pillar is equal to the number of the capacitor contact structure.

[0041] According to a third aspect of embodiments of the present disclosure, a method for testing a semiconductor test structure is provided, applied to the semiconductor test structure as described in any one of the first aspect, the method comprising:

[0042] testing the plurality of capacitors via the capacitor contact structure by a test probe.

[0043] This disclosure provides a semiconductor test structure, its fabrication method, testing method, and wafer. The semiconductor test structure includes: at least one capacitor contact structure; a capacitor array structure located on the at least one capacitor contact structure, comprising multiple capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; and the capacitor contact structures are connected to the multiple capacitors. By reducing the number of capacitor contact structures in the semiconductor test structure and setting each capacitor contact structure to correspond to multiple capacitors, the manufacturing process of the semiconductor test structure is simplified, reducing process complexity and manufacturing costs. Simultaneously, it reduces parasitic capacitance and resistance caused by multiple independent capacitor contact structures, improving the overall electrical performance of the semiconductor test structure and increasing the accuracy of subsequent testing of the semiconductor test structure. Attached Figure Description

[0044] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this disclosure and should not be construed as limiting the scope of this disclosure.

[0045] Figure 1 This is a schematic cross-sectional view of a semiconductor test structure provided in an embodiment of the present disclosure;

[0046] Figure 2 for Figure 1 A three-dimensional structural diagram of the structure within the dashed box;

[0047] Figure 3A This is a cross-sectional schematic diagram of a semiconductor test structure provided in yet another embodiment of the present disclosure;

[0048] Figure 3B for Figure 3A Top view of the local structure Figure 1 ;

[0049] Figure 3C for Figure 3A Top view of the local structure Figure 2 ;

[0050] Figure 4A This is a cross-sectional schematic diagram of a semiconductor test structure provided in another embodiment of the present disclosure;

[0051] Figure 4B for Figure 4A Top view of the local structure Figure 1 ;

[0052] Figure 4C forFigure 4A Top view of the local structure Figure 1 ;

[0053] Figure 5A This is a top view schematic diagram of a semiconductor test structure provided in yet another embodiment of the present disclosure;

[0054] Figure 5B for Figure 5A Enlarged 3D schematic diagram of region A in the middle;

[0055] Figure 6A A schematic diagram of the structural form of the capacitor provided in the embodiments of this disclosure. Figure 1 ;

[0056] Figure 6B A schematic diagram of the structural form of the capacitor provided in the embodiments of this disclosure. Figure 2 ;

[0057] Figure 6C Schematic diagram three showing the structural configuration of the capacitor provided in the embodiments of this disclosure;

[0058] Figure 7 This is a schematic diagram of a wafer provided according to an embodiment of the present disclosure;

[0059] Figure 8 This is a schematic diagram illustrating the specific implementation process of a method for fabricating a semiconductor test structure according to an embodiment of this disclosure. Detailed Implementation

[0060] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0061] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0062] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0064] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0065] With the continuous development of semiconductor devices, the manufacturing process involves many complex steps, each of which may have specific manufacturing deviations, ultimately leading to a decrease in yield. To improve the yield of semiconductor devices, wafer acceptance testing is commonly used to obtain the data necessary for improving manufacturing processes and design yield.

[0066] Taking Dynamic Random Access Memory (DRAM) as an example, during the development and manufacturing of DRAM, it is necessary to study and test various characteristics of the capacitors in the DRAM. For instance, semiconductor test structures set in the dicing grooves between semiconductor devices on a wafer correspond to the processes or structures in the semiconductor devices that need to be monitored. Testing these semiconductor test structures reflects the electrical performance of the semiconductor devices. For example... Figure 1 As shown, the semiconductor test structure includes multiple transistors 103, each transistor 103 including a source 1032, a channel 1033, and a drain 1031 arranged from bottom to top.

[0067] Figure 1 The semiconductor test structure shown also includes multiple capacitors 101 and multiple capacitor contact structures 102, wherein each capacitor 101 and capacitor contact structure 102 is arranged in a one-to-one correspondence. Here, the capacitor 101 is described as a cup-shaped capacitor CUP. The capacitor 101 includes a first electrode 1011, a second electrode 1013, and a dielectric layer 1012 located between the first electrode 1011 and the second electrode 1013. The first electrode 1011 of the capacitor 101 is connected to the drain 1031 of the transistor 103 via the capacitor contact structure 102. The source 1032 of the transistor 103 is connected to the bit line 105, wherein, as... Figure 2 As shown, bit line 105 extends along the second direction and is arranged along the first direction. Word line 104 extends along the first direction and covers one sidewall of channel 1033.

[0068] It should be noted that, here and below, both the first and second directions are parallel to the plane containing the capacitor contact structure, both are perpendicular to the third direction, and intersect each other. In some specific embodiments, the first direction is perpendicular to the second direction. For example, the first direction may be the extension of the Y-axis shown in the figures, the second direction may be the extension of the X-axis shown in the figures, and the third direction may be the extension of the Z-axis shown in the figures.

[0069] For example, a dielectric layer covering the drain 1031 of multiple transistors and a mask layer having multiple openings are sequentially formed. Multiple capacitor contact holes are formed in the dielectric layer using the mask layer. Metal material is deposited into the multiple capacitor contact holes, and then the metal material is subjected to chemical mechanical polishing (CMP) treatment to form multiple independent capacitor contact structures 102 spaced apart from each other.

[0070] It should be noted that, in order to facilitate a visual description of the positional relationship between the capacitor 101, capacitor contact structure 102, transistor 103, word line 104, and bit line 105 in the semiconductor test structure, Figure 1 Other structures (such as dielectric layers) are omitted, and only capacitor 101, capacitor contact structure 102, transistor 103, word line 104, and bit line 105 are shown.

[0071] For example, in the case of Figure 1When the capacitor 101 of the semiconductor test structure shown is tested, the test path sequentially passes through bit lines 105, the source 1032 of the transistor, the channel 1033 of the transistor, the drain 1031 of the transistor, the capacitor contact structure 102, the first electrode 1011 of the capacitor 101, and the second electrode 1013 of the capacitor 101. In some embodiments, multiple bit lines 105 are connected to test pads and test probes through multiple contact structures, while the second electrode 1013 is grounded or connected to the test pads and test probes through a common plate, thereby realizing the testing of the capacitor of the semiconductor test structure.

[0072] Figure 1 The capacitor contact structure 102 in the semiconductor test structure shown is difficult and costly to fabricate. Furthermore, with miniaturization, it becomes difficult to precisely control the number of capacitor contact structures, leading to discrepancies between the designed number and the actual number, thus affecting the representativeness and accuracy of the test results. Additionally, testing multiple capacitors requires connecting multiple independent capacitor contact structures, each introducing additional parasitic capacitance and resistance, further reducing the accuracy of the test results. Moreover, the bit lines, source, channel, and drain structures traversed in the test path of the aforementioned semiconductor test structure all introduce parasitic capacitance, and the channel resistance also affects signal transmission. Testing the performance of multiple capacitors also requires connecting multiple transistors, potentially causing even more parasitic effects and poor contact.

[0073] To address at least one of the aforementioned problems, embodiments of this disclosure provide a semiconductor test structure, its fabrication method, a test method, and a wafer.

[0074] In a first aspect, embodiments of this disclosure provide a semiconductor testing structure, such as... Figure 3A As shown, the semiconductor test structure includes: at least one capacitor contact structure 202; a capacitor array structure located on the at least one capacitor contact structure 202, including a plurality of capacitors 201 arranged in an array along a first direction and a second direction; wherein the number of capacitors 201 is greater than the number of capacitor contact structures 202; the capacitor contact structure 202 is connected to the plurality of capacitors 201.

[0075] Thus, reducing the number of capacitor contact structures simplifies the manufacturing process of semiconductor test structures, reducing process complexity and manufacturing costs.

[0076] In some embodiments, such as Figure 3AAs shown, capacitor 201 includes a first electrode 2011, a dielectric layer 2012, and a second electrode 2013; the dielectric layer 2012 covers the surface of the first electrode 2011, and the second electrode 2013 covers the surface of the dielectric layer 2012; capacitor contact structure 202 is connected to the first electrode 2011 of the plurality of capacitors 201.

[0077] In some embodiments, the capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0078] For example, such as Figure 6A As shown, capacitor 201 may include a cup-shaped capacitor CUP; exemplarily, as Figure 6B As shown, capacitor 201 may include a cylindrical capacitor CYL; exemplarily, as Figure 6C As shown, capacitor 201 may include a pillar-shaped capacitor PIL. Cup-shaped capacitor CUP, cylindrical capacitor CYL, and pillar-shaped capacitor PIL all include a first electrode 2011, a second electrode 2013, and a dielectric layer 2012 located between the first electrode 2011 and the second electrode 2013. It should be noted that, when the areas of the first electrode 2011 in cup-shaped capacitor CUP, cylindrical capacitor CYL, and pillar-shaped capacitor PIL are equal, the area of ​​the second electrode 2013 in cylindrical capacitor CYL is the largest, followed by the cylindrical capacitor CYL and pillar-shaped capacitor PIL. Based on this, in practical applications, cylindrical capacitor CYL can be used as a storage unit in a memory, which is beneficial for improving the integration density of the memory.

[0079] In some embodiments, such as Figure 3A As shown, the semiconductor test structure also includes a dielectric layer 200 and a capacitor contact 207 that contacts the common plate 206 of the second electrode 2013 to couple the second electrode 2013 of the capacitor 201 to an external circuit or directly to ground.

[0080] In other embodiments, the second electrode 2013 can be coupled to an external circuit via a backside through-via (BTV) and a backside through-metal layer.

[0081] In some embodiments, the semiconductor test structure further includes: a plurality of transistors disposed in one-to-one correspondence with the plurality of capacitors; a first source / drain region of the plurality of transistors connected to a first surface of the capacitor contact structure; and a plurality of capacitors connected to a second surface of the capacitor contact structure; wherein the first surface and the second surface are two opposing surfaces of the capacitor contact structure.

[0082] In some embodiments, such as Figure 3AAs shown, the semiconductor test structure also includes: a plurality of transistors 203 corresponding to a plurality of capacitors 201; a first source / drain region 2031 of the plurality of transistors 203 connected to a first surface 2021 of the capacitor contact structure 202; and a plurality of capacitors 201 connected to a second surface 2022 of the capacitor contact structure 202; wherein the first surface 2021 and the second surface 2022 are two surfaces of the capacitor contact structure 202 that are opposite each other along a third direction (X direction).

[0083] In some embodiments, a plurality of capacitors arranged along the first direction constitute a row capacitor group; the capacitor contact structure is connected to at least one of the row capacitor groups.

[0084] In some specific implementation methods, such as Figure 3B As shown, a plurality of capacitors 201 arranged along a first direction constitute a row capacitor group 201'; a capacitor contact structure 202 is connected to the plurality of row capacitor groups 201'. For example, as... Figure 3A As shown, transistor 203 includes a second source / drain region 2032, a channel region 2033, and a first source / drain region 2031 disposed along a third direction.

[0085] In some embodiments, such as Figure 3A As shown, the semiconductor test structure further includes: multiple word lines 204 extending along a first direction and covering the sidewalls of the channel region 2033 of the transistor 203; and bit lines 205 extending along a second direction and spaced apart along the first direction. The bit lines 205 are connected to the second source / drain regions 2032 of the transistor 203.

[0086] It is understandable that when the transistor is a vertical transistor, a capacitor contact structure 202 is connected to multiple row capacitor banks 201', such as... Figure 3B As shown, a capacitor contact structure 202 is connected to four rows of capacitor banks 201'.

[0087] In other implementations, such as Figure 3C As shown, the semiconductor test structure includes two capacitor contact structures 202, each of which is connected to four rows of capacitor banks 201'.

[0088] In some embodiments, in the plane (XY section) formed by the first and second directions, the orthographic projection of the capacitor connected to the capacitor contact structure lies within the range of the orthographic projection of the capacitor contact structure. Thus, by having the orthographic projection of the capacitor contact structure cover the orthographic projections of multiple capacitors, the alignment accuracy between the capacitor contact structure and the multiple capacitors can be improved, the differences between multiple independent capacitor contact structures caused by process variations can be reduced, and the parasitic capacitance and resistance caused by multiple independent capacitor contact structures can be reduced, thereby improving the overall electrical performance of the semiconductor test structure.

[0089] In some specific implementations, such as Figure 3B and Figure 3C As shown, the orthographic projections of the 16 capacitors in the four rows of capacitor banks 201' connected to the capacitor contact structure 202 are located within the range of the orthographic projection of the capacitor contact structure 202.

[0090] Here, to clearly show the positional relationships between word lines, bit lines, transistors, capacitor contact structures, capacitors, etc., some structures are shown in... Figure 3B and 3C The dielectric layer, capacitor contacts, and other structures are not shown in the diagram.

[0091] In practical applications, the capacitor contact structure can be configured according to the required size of the semiconductor test structure. Figures 3A to 3C The number of capacitor contact structures shown is merely an example and should not unduly limit the scope of this disclosure. In practical applications, the number of capacitor contact structures included in a semiconductor test structure can be set according to actual needs, such as being reasonably set based on the number of capacitors contained in a capacitor array.

[0092] In some embodiments, such as Figure 3B and Figure 3C As shown, the semiconductor test structure also includes word line contact structures 209 for electrically leading out word lines 204. When the spacing between word lines is small, multiple word line contact structures 209 need to be staggered (located on different sides of the word lines) to avoid short circuits between multiple word lines, while also reducing device size and improving space utilization.

[0093] In some embodiments, the semiconductor test structure further includes conductive contacts 208 for connecting corresponding bit lines to test pads and test probes when testing the semiconductor test structure. In some specific embodiments, the number of conductive contacts 208 is equal to the number of capacitor contact structures.

[0094] In some embodiments, the capacitor contact structure has a square shape in the plane (XY section) formed by the first direction and the second direction. For example, as shown... Figure 3A and Figure 3B As shown, the plane (XY section) formed by the capacitor contact structure 202 in the first and second directions is rectangular.

[0095] In other embodiments, the plane (XY section) formed by the capacitor contact structure in the first and second directions is square.

[0096] The shape of the capacitor contact structure described above allows for more efficient use of space in a planar layout, improving device integration and enabling more uniform current distribution, thus reducing parasitic capacitance and resistance caused by local non-uniformity. Furthermore, the shape of the capacitor contact structure makes alignment easier in semiconductor processes, thereby simplifying the manufacturing process and reducing its complexity.

[0097] In some embodiments, the semiconductor test structure further includes conductive pillars connected to a first surface or a second surface of the capacitor contact structure; the number of conductive pillars is equal to the number of capacitor contact structures. The conductive pillars can alter the test path of the semiconductor test structure, avoiding interference from channel resistance and parasitic effects introduced by transistors in traditional test paths.

[0098] In some embodiments, the materials of the conductive pillars include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), etc.

[0099] like Figure 4A As shown, the semiconductor test structure includes a conductive post 210 connected to the first surface 2021 of the capacitor contact structure 202, for coupling the second electrode 2013 of the capacitor 201 to an external circuit or directly to ground.

[0100] The number of conductive posts 210 is equal to the number of capacitor contact structures 202. It can be understood that the conductive posts 210 and the capacitor contact structures 202 are set in a one-to-one correspondence.

[0101] When the transistor is a vertical transistor, one capacitor contact structure 202 of the semiconductor test structure is connected to multiple row capacitor banks 201', such as Figure 4B As shown, a capacitor contact structure 202 is connected to four rows of capacitor banks 201'.

[0102] In other implementations, such as Figure 4C As shown, the semiconductor test structure includes two capacitor contact structures 202 and two conductive pillars 210, with each capacitor contact structure 202 connected to four rows of capacitor banks 201'.

[0103] In practical applications, the capacitor contact structure and conductive pillars can be configured according to the required size of the semiconductor test structure. Figures 4A to 4C The capacitor contact structure and the number of conductive posts shown are merely examples and should not unduly limit the scope of this disclosure.

[0104] Figure 5A This is a top view schematic diagram of a semiconductor test structure provided in yet another embodiment of the present disclosure. Figure 5B for Figure 5A An enlarged 3D schematic diagram of region A in the middle. (See diagram below.) Figure 5A and Figure 5B As shown, the semiconductor test structure includes: a plurality of capacitor contact structures 302; a capacitor array structure located on the plurality of capacitor contact structures 302, including a plurality of capacitors 301 arranged in an array along a first direction and a second direction; wherein the number of capacitors 301 is greater than the number of capacitor contact structures 302; and the capacitor contact structures 302 are connected to the plurality of capacitors 301.

[0105] In practical applications, capacitors can take on various structures.

[0106] refer to Figure 6A , Figure 6B and Figure 6C In some embodiments, the capacitor includes a cup-shaped, cylindrical, or pillar-shaped capacitor.

[0107] In some embodiments, such as Figure 5A As shown, the semiconductor test structure also includes a plurality of transistors 303 corresponding one-to-one with a plurality of capacitors; the first source / drain regions of the plurality of transistors 303 are connected to the first surface of the capacitor contact structure 302; the plurality of capacitors 301 are connected to the second surface of the capacitor contact structure 302; wherein, the first surface and the second surface are two opposing surfaces of the capacitor contact structure 302. For example, as... Figure 5B As shown, the transistor includes a second source / drain region 3032, a channel region 3033, and a first source / drain region 3031 disposed along the second direction. The first source / drain regions 3031 of the plurality of transistors 303 are connected to the first surface of the capacitor contact structure 302; the plurality of capacitors 301 are connected to the second surface of the capacitor contact structure 302; wherein the first surface and the second surface are two surfaces of the capacitor contact structure 302 opposite to each other along the third direction (Z direction).

[0108] like Figure 5BAs shown, the transistor is a buried channel array transistor (BCAT), and the first source / drain region 3031 and the second source / drain region 3032 of the transistor are located on both sides of the word line 304 horizontally (along the second direction).

[0109] In some embodiments, such as Figure 5A As shown, the semiconductor test structure also includes word lines 304 extending along a first direction; bit lines 305 extending along a second direction and arranged along the first direction; and word line contact structures 306 for electrically leading out the word lines 304. Wherein, as... Figure 5B As shown, bit line 305 is connected to the second source / drain region 3032 of multiple transistors 303 via bit line contact structure 307. It can be understood that bit line 305 and capacitor 301 are both located on the same side of word line 304 along a third direction.

[0110] In some embodiments, the capacitor contact structure is connected to a row capacitor bank, thereby preventing short circuits between the capacitor contact structure and the bit lines. In some specific embodiments, such as Figure 5A As shown, there are 16 capacitors 301 and 4 capacitor contact structures 302; each capacitor contact structure 302 is connected to four capacitors 301 in a row of capacitors 301'.

[0111] In some embodiments, such as Figure 5A As shown, the orthographic projections of the four capacitors 301 in the four rows of capacitor banks 301' connected to the capacitor contact structure 302 are located within the range of the orthographic projection of the capacitor contact structure 302.

[0112] In some embodiments, the size of the capacitor contact structure 302 in the third direction is smaller than the size of the bit line contact structure 307 in the third direction, so as to avoid short circuit between the capacitor contact structure and the bit line.

[0113] Here, to clearly show the positional relationships between word lines, bit lines, transistors, capacitor contact structures, capacitors, etc., some structures are shown in... Figure 5A and Figure 5B Not shown in the text, for example, Figure 5A The dielectric layer, capacitor contacts, and other structures are not shown. Additionally, Figure 5B The diagram only shows a portion of the capacitor contact structure 302. In reality, the capacitor contact structure 302 covers the first source / drain regions 3031 of multiple transistors along the first direction (Y direction).

[0114] It should be noted that, Figure 5A The top view shown is a perspective view, extending upwards along the third line. Figure 5AAlong the third direction from bottom to top are transistor 303, word line 304, capacitor contact structure 302, capacitor 301 and bit line 305, and there is no contact between capacitor contact structure 302 and bit line 305.

[0115] In some embodiments, the capacitor contact structure is strip-shaped on a plane formed by the first direction and the second direction, and the capacitor contact structures are spaced apart in the second direction. For example, as... Figure 5A As shown, the capacitor contact structure 302 is strip-shaped on the plane (XY plane) formed by the first direction and the second direction, and the capacitor contact structures 302 are spaced apart in the second direction. In other words, the capacitor contact structures 302 extend along the first direction.

[0116] In some embodiments, the semiconductor test structure further includes conductive pillars (not shown). The conductive pillars are connected to a first surface or a second surface of the capacitor contact structure; the number of conductive pillars is equal to the number of capacitor contact structures.

[0117] In some embodiments, the conductive post and the capacitor may be located on the same side of the capacitor contact structure along a third direction, i.e., both the conductive post and the capacitor are connected to the second surface of the capacitor contact structure. In other embodiments, the conductive post and the capacitor may be located on different sides of the capacitor contact structure along a third direction, i.e., the conductive post is connected to the first surface of the capacitor contact structure, and the capacitor is connected to the second surface of the capacitor contact structure.

[0118] This disclosure provides a semiconductor test structure that simplifies the manufacturing process and reduces process complexity and manufacturing cost by reducing the number of capacitor contact structures and setting each capacitor contact structure to correspond to multiple capacitors. Simultaneously, it reduces parasitic capacitance and resistance caused by multiple independent capacitor contact structures, thereby improving the overall electrical performance of the semiconductor test structure.

[0119] Secondly, embodiments of this disclosure provide a wafer, including: a plurality of semiconductor devices; dicing grooves respectively located between the semiconductor devices to separate the semiconductor devices; and a semiconductor test structure located in the dicing grooves as described in any of the foregoing embodiments.

[0120] In some embodiments, such as Figure 7 As shown, wafer 400 includes: a plurality of semiconductor devices 410; dicing grooves 420, respectively located between the semiconductor devices 410 to separate the semiconductor devices 410; and a semiconductor test structure as described in the foregoing embodiments located in the dicing grooves 420.

[0121] In some embodiments, the semiconductor device includes: a plurality of independent capacitor contact pads; a capacitor array structure including a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is equal to the number of capacitor contact structures, and the capacitor contact pads are arranged in a one-to-one correspondence with the capacitors.

[0122] In some embodiments, the semiconductor test structure further includes a plurality of transistors arranged in a one-to-one correspondence with the plurality of capacitors, wherein the transistors may be vertical transistors (see reference). Figure 2 It can also be used for buried channel transistors (see reference). Figure 5B ).

[0123] It should be noted that the semiconductor test structures set in the dicing groove 420 correspond to the processes or structures of the semiconductor device 410 that need to be monitored. For example, the capacitors and transistors in the dicing groove have the same manufacturing processes as the capacitors and transistors of the semiconductor device.

[0124] The semiconductor testing structure described in any of the foregoing embodiments, which is set in the dicing groove of the wafer, is beneficial for providing numerical references for the design of semiconductor devices and improving the yield of semiconductor devices.

[0125] The semiconductor testing structure of the wafer provided in this disclosure is similar to that in the semiconductor testing structures in the embodiments of the first aspect described above. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0126] Thirdly, embodiments of this disclosure provide a method for fabricating a semiconductor test structure. Figure 8 This is a schematic diagram illustrating the specific implementation process of a method for fabricating a semiconductor test structure according to an embodiment of this disclosure.

[0127] like Figure 8 As shown, the specific steps of the fabrication method for this semiconductor test structure include:

[0128] Step S10: Form at least one capacitor contact structure.

[0129] Step S20: A capacitor array structure is formed on the at least one capacitor contact structure, the capacitor array structure comprising a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; the capacitor contact structure is connected to the plurality of capacitors.

[0130] In some embodiments, the method further includes: forming a plurality of transistors arranged in an array along the first direction and the second direction; forming a conductive material that at least covers a first source / drain region of the plurality of transistors; removing a portion of the conductive material to form at least one capacitor contact structure; the plurality of transistors arranged along the first direction forming a transistor row, the capacitor contact structure being connected to at least one transistor row.

[0131] In some implementations, such as Figure 4A and Figure 4B As shown, a plurality of transistors 203 are formed on a substrate (not shown) in an array along a first direction and a second direction.

[0132] In some embodiments, the substrate material may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0133] In some embodiments, the substrate structure can be selected according to actual needs, and the composite stack structure includes a bottom substrate layer (not shown), a pad oxide layer (not shown), and a top substrate layer (not shown) stacked sequentially. The material of the top substrate layer may include silicon, germanium, or germanium-silicon, etc.; the material of the bottom substrate layer may include silicon, the material of the pad oxide layer may include silicon oxide, and the material of the top substrate layer may include polycrystalline silicon. In some specific embodiments, the pad oxide layer on the bottom substrate layer and the top substrate layer can both be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0134] In some embodiments, a certain number of impurity ions are doped into the substrate as needed. The impurity ions can be N-type impurity ions or P-type impurity ions.

[0135] In various embodiments of this disclosure, the etching (or removal) process employed may include wet etching, dry etching, etc., such as plasma etching. The deposition (or filling) process employed may include PVD, CVD, or ALD, such as plasma enhanced chemical vapor deposition (PECVD).

[0136] In some embodiments, a second source / drain region, a channel region, and a first source / drain region are formed along a third direction, the second source / drain region, the channel region, and the first source / drain region constituting a transistor; the third direction is perpendicular to both the first direction and the second direction; the capacitor contact structure is connected to a plurality of the transistor rows. Exemplarily, as... Figure 4A As shown, a second source / drain region 2032, a channel region 2033, and a first source / drain region 2031 are formed along a third direction.

[0137] In some embodiments, a conductive material is formed to cover at least the first source / drain regions of multiple transistors; a portion of the conductive material is removed to form at least one capacitor contact structure.

[0138] In some embodiments, the number of transistors is greater than the number of capacitor contact structures; the capacitor contact structures are connected to multiple transistors.

[0139] The plurality of transistors arranged along a first direction constitute a transistor row, and a capacitor contact structure is connected to at least one transistor row.

[0140] For example, conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), nickel (Ni), etc.

[0141] For example, photolithography and etching processes are used to remove part of the conductive material, and the remaining conductive material forms a capacitor contact structure, which is connected to the first electrode of the capacitor. Compared with forming multiple capacitor contact holes through a mask layer, depositing metal material into the multiple capacitor contact holes, and then performing CMP processing to form the capacitor contact structure, the above-described method in this disclosure reduces process complexity (e.g., it can avoid defects caused by voids generated when depositing metal material into the capacitor contact holes) and manufacturing costs, and can more accurately define the geometry and size of the capacitor contact structure, and the fabrication process reduces performance differences caused by process fluctuations.

[0142] In some embodiments, a capacitor array structure is formed on at least one capacitor contact structure, the capacitor array structure including a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; and the capacitor contact structure is connected to the plurality of capacitors.

[0143] In some embodiments, a plurality of transistors are arranged in a one-to-one correspondence with a plurality of capacitors. A plurality of transistors arranged along a first direction constitute a transistor row, and a capacitor contact structure is connected to at least one transistor row.

[0144] When the transistor is a vertical transistor, one capacitor contact structure 202 of the semiconductor test structure is connected to multiple row capacitor banks 201', such as Figure 4B As shown, a capacitor contact structure 202 is connected to four rows of capacitor banks 201'.

[0145] In other implementations, such as Figure 4C As shown, the semiconductor test structure includes two capacitor contact structures 202, each of which is connected to four rows of capacitor banks 201'.

[0146] In some embodiments, in the plane (XY section) formed by the first direction and the second direction, the orthographic projection of the capacitor connected to the capacitor contact structure lies within the range of the orthographic projection of the capacitor contact structure. Thus, by covering the orthographic projections of multiple capacitors with the orthographic projection of the capacitor contact structure, the alignment accuracy between the capacitor contact structure and the multiple capacitors can be improved, the differences between multiple independent capacitor contact structures caused by process variations can be reduced, and the parasitic capacitance and resistance caused by multiple independent capacitor contact structures can be reduced, thereby improving the overall electrical performance of the semiconductor test structure.

[0147] In some specific implementations, such as Figure 4B and Figure 4C As shown, the orthographic projections of the 16 capacitors in the four rows of capacitor banks 201' connected to the capacitor contact structure 202 are located within the range of the orthographic projection of the capacitor contact structure 202.

[0148] In other embodiments, the method further includes fabricating word lines on the front side of the substrate and fabricating bit lines on the back side of the substrate. For example... Figure 3A As shown, multiple word lines 204 are formed on the front side of the substrate, extending along a first direction and covering the sidewalls of the channel region 2033 of the transistor 203; bit lines 205 are formed on the back side of the substrate, extending along a second direction and spaced apart along the first direction. The bit lines 205 are connected to the second source / drain regions 2032 of the transistor 203.

[0149] In some embodiments, the method further includes: forming conductive pillars that are in contact with the capacitor contact structure, wherein the number of conductive pillars is equal to the number of capacitor contact structures.

[0150] For example, after forming structures such as transistors, capacitor contact structures, and capacitors, the aforementioned structures are flipped, and the substrate is thinned on the back side to form conductive holes. Conductive material is then filled into the conductive holes to form conductive pillars 210, wherein the conductive pillars 210 contact the first surface 2021 of the capacitor contact structure 202. The placement of the conductive pillars can alter the test path of the semiconductor test structure, avoiding interference from channel resistance and parasitic effects caused by transistors in traditional test paths.

[0151] In some embodiments, the materials of the conductive pillars include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and nickel (Ni).

[0152] In some embodiments, the transistors in the semiconductor test structure are Figure 5B The buried channel transistor is shown. The method for fabricating the semiconductor test structure further includes: forming a second source / drain region, a channel region, and a first source / drain region disposed along the second direction; the capacitor contact structure is connected to one of the transistor rows.

[0153] In some embodiments, a conductive material is formed to cover at least the first source / drain regions of multiple transistors; a portion of the conductive material is removed to form multiple capacitor contact structures. The number of transistors is greater than the number of capacitor contact structures; the capacitor contact structures are connected to the multiple transistors.

[0154] The plurality of transistors arranged along the first direction constitute a transistor row, and each capacitor contact structure is connected to a transistor row.

[0155] In some embodiments, a capacitor array structure is formed on a plurality of capacitor contact structures, the capacitor array structure including a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; each capacitor contact structure is connected to a plurality of capacitors.

[0156] In some embodiments, a plurality of transistors are arranged in a one-to-one correspondence with a plurality of capacitors. A plurality of transistors arranged along a first direction constitute a transistor row, and each capacitor contact structure is connected to a transistor row.

[0157] In some specific implementation methods, such as Figure 5A As shown, there are 16 capacitors 301 and 4 capacitor contact structures 302; each capacitor contact structure 302 is connected to four capacitors 301 in a row of capacitors 301'.

[0158] In some embodiments, such as Figure 5AAs shown, the orthographic projections of the four capacitors 301 in the four rows of capacitor banks 301' connected to the capacitor contact structure 302 are located within the range of the orthographic projection of the capacitor contact structure 302.

[0159] In some embodiments, such as Figure 5A As shown, the method for fabricating a semiconductor test structure further includes: forming a word line 304 extending along a first direction; forming a word line contact structure 306 for electrically leading out the word line 304; and forming a bit line 305 extending along a second direction and arranged along the first direction. Wherein, as... Figure 5B As shown, bit line 305 is connected to the second source / drain region 3032 of multiple transistors 303 via bit line contact structure 307. It can be understood that bit line 305 and capacitor 301 are both located on the same side of word line 304 along a third direction.

[0160] In some embodiments, such as Figure 5A As shown, the method for fabricating the semiconductor test structure further includes: forming conductive pillars (not shown). The conductive pillars are connected to a first surface or a second surface of the capacitor contact structure; the number of conductive pillars is equal to the number of capacitor contact structures.

[0161] In some embodiments, the conductive post and the capacitor may be located on the same side of the capacitor contact structure along a third direction, i.e., both the conductive post and the capacitor are connected to the second surface of the capacitor contact structure. In other embodiments, the conductive post and the capacitor may be located on different sides of the capacitor contact structure along a third direction, i.e., the conductive post is connected to the first surface of the capacitor contact structure, and the capacitor is connected to the second surface of the capacitor contact structure.

[0162] The semiconductor test structure prepared by the method of this disclosure is similar to the semiconductor test structure in the embodiments of the first aspect above. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0163] Fourthly, embodiments of this disclosure provide a testing method for a semiconductor test structure, applied to any of the semiconductor test structures described in the foregoing embodiments, the method comprising: testing a plurality of capacitors via a test probe through the capacitor contact structure.

[0164] In some embodiments, multiple capacitors are tested via test probes and test pads through conductive contacts, bit lines, transistors, and capacitor contact structures. For example, as shown... Figure 3AAs shown, multiple capacitors 201 are tested via test probes and test pads through conductive contacts 208, bit lines 205, transistors 203, and capacitor contact structures 202. An electrical signal (e.g., voltage) is applied to the bit line 205 via the test probes and test pads through the conductive contact 208. The voltage is transmitted through the bit line 205 to the transistor 203, and then through the capacitor contact structure 202 to the first electrode 2011 of the capacitor 201. Simultaneously, an electrical signal (e.g., voltage) is applied to the second electrode 2013 of the capacitor 201 via the test probes and test pads, thereby achieving the testing of the semiconductor test structure.

[0165] It should be noted that during the above test process, the electrical performance parameters of multiple capacitors in the semiconductor test structure can be obtained. At the same time, the electrical performance parameters of one or more transistors can be obtained by controlling the number of transistors connected to the test path (one or more).

[0166] Since the number of capacitor contact structures is less than that of capacitors, and each capacitor contact structure corresponds to multiple capacitors, the above test path reduces the parasitic capacitance and resistance caused by multiple independent capacitor contact structures when testing the electrical performance of multiple capacitors. At the same time, it eliminates the need to connect multiple transistors with the same number of capacitors, avoiding parasitic effects and poor contact caused by connecting multiple transistors simultaneously during testing. This improves the accuracy of test results and is beneficial for providing numerical references for semiconductor device design and improving the yield of semiconductor devices.

[0167] In some embodiments, multiple capacitors are tested via test probes and test pads through conductive pillars and capacitor contact structures. For example, as shown... Figure 4A As shown, multiple capacitors 201 are tested via test probes and test pads through conductive pillars 210 and capacitor contact structures 202. At the same time, an electrical signal (e.g., voltage) is applied to the second electrode 2013 of the capacitors 201 via test probes and test pads to achieve testing of the semiconductor test structure.

[0168] Since the number of capacitor contact structures is less than that of capacitors, and each capacitor contact structure corresponds to multiple capacitors, and the capacitor contact structures are directly led out for testing through conductive posts, the above test path not only reduces the parasitic capacitance and parasitic resistance caused by multiple independent capacitor contact structures, but also avoids the parasitic capacitance introduced by bit lines, source, channel and drain structures, as well as the channel resistance caused by the channel, thus improving the accuracy of the test results. This is beneficial for providing numerical references for the design of semiconductor devices and improving the yield of semiconductor devices.

[0169] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0170] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the protection scope of this disclosure.

Claims

1. A semiconductor testing structure, characterized in that, include: At least one capacitor contact structure; A capacitor array structure located on the at least one capacitor contact structure includes a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; and the capacitor contact structures are connected to the plurality of capacitors.

2. The semiconductor test structure according to claim 1, characterized in that, The plurality of capacitors arranged along the first direction constitute a row capacitor bank; The capacitor contact structure is connected to at least one of the row capacitor banks.

3. The semiconductor test structure according to claim 2, characterized in that, The semiconductor testing structure also includes: Multiple transistors are configured in a one-to-one correspondence with the plurality of capacitors; The first source / drain regions of the plurality of transistors are connected to the first surface of the capacitor contact structure; The plurality of capacitors are connected to the second surface of the capacitor contact structure; wherein the first surface and the second surface are two opposing surfaces of the capacitor contact structure.

4. The semiconductor test structure according to claim 3, characterized in that, The transistor includes a second source / drain region, a channel region, and a first source / drain region disposed along a third direction; the third direction is perpendicular to both the first direction and the second direction. The capacitor contact structure is connected to the plurality of the row capacitor banks.

5. The semiconductor test structure according to claim 4, characterized in that, The capacitor contact structure forms a square plane in the first direction and the second direction.

6. The semiconductor test structure according to claim 3, characterized in that, The transistor includes a second source / drain region, a channel region, and a first source / drain region disposed along the second direction; the first source / drain region and the channel region; The capacitor contact structure is connected to one of the row capacitor banks.

7. The semiconductor test structure according to claim 6, characterized in that, The capacitor contact structure is strip-shaped on the plane formed by the first direction and the second direction, and the capacitor contact structures are spaced apart in the second direction.

8. The semiconductor test structure according to claim 2, characterized in that, The semiconductor testing structure also includes: A conductive post is connected to a first surface or a second surface of the capacitor contact structure; the number of conductive posts is equal to the number of capacitor contact structures.

9. The semiconductor test structure according to claim 1, characterized in that, The capacitor includes a first electrode, a dielectric layer, and a second electrode; the dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the dielectric layer. The capacitor contact structure is connected to the first electrode of the plurality of capacitors.

10. A wafer, characterized in that, include: Multiple semiconductor devices; Dicing grooves are located between the semiconductor devices to separate them; as well as The semiconductor test structure located in the dicing groove as described in any one of claims 1 to 9.

11. A method for fabricating a semiconductor test structure, characterized in that, include: Form at least one capacitor contact structure; A capacitor array structure is formed on the at least one capacitor contact structure, the capacitor array structure comprising a plurality of capacitors arranged in an array along a first direction and a second direction; wherein the number of capacitors is greater than the number of capacitor contact structures; the capacitor contact structure is connected to the plurality of capacitors.

12. The preparation method according to claim 11, characterized in that, The method further includes: Forming a plurality of transistors arranged in an array along the first direction and the second direction; A conductive material is formed to at least cover the first source / drain regions of the plurality of transistors; A portion of the conductive material is removed to form at least one capacitor contact structure; a plurality of transistors arranged along the first direction constitute a transistor row, and the capacitor contact structure is connected to at least one transistor row.

13. The preparation method according to claim 12, characterized in that, The method further includes: A second source / drain region, a channel region, and a first source / drain region are formed along a third direction, and the first source / drain region, the channel region, and the second source / drain region constitute the transistor; the third direction is perpendicular to both the first direction and the second direction; the capacitor contact structure is connected to a plurality of the transistor rows.

14. The preparation method according to claim 12, characterized in that, The method further includes: A second source / drain region, a channel region, and a first source / drain region are formed along the second direction, the first source / drain region, the channel region, and the second source / drain region constituting the transistor; the capacitor contact structure is connected to one of the transistor rows.

15. The preparation method according to claim 11, characterized in that, The method further includes: Conductive pillars are formed, and the conductive pillars are in contact with the capacitor contact structure. The number of conductive pillars is equal to the number of capacitor contact structures.

16. A testing method for a semiconductor test structure, applied to the semiconductor test structure as described in any one of claims 1 to 9, characterized in that, The method includes: The capacitors are tested using test probes via the capacitor contact structure.

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