Multilayer ceramic capacitor, method for manufacturing multilayer ceramic capacitor, and method for manufacturing mounting structure of multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (1) according to the present invention is provided with a capacitor body (10), a first external electrode (20A), and a second external electrode (20B). The first main surface (101) is a surface on one side in the stacking direction (DS) of the capacitor body (10). The first external electrode (20A) includes a first base electrode layer (21A) and a first surface electrode layer (22A). The first base electrode layer (21A) is provided on the first main surface (101) so as to cover the first via conductor (13A). The first surface electrode layer (22A) directly covers the first base electrode layer (21A). The second external electrode (20B) is provided on the first main surface (101) so as to cover the second via hole conductor (13B) with a gap therebetween from the first external electrode (20A). An outer surface (221A) of the first surface electrode layer (22A) extends from an end edge (21AE) of the first base electrode layer (21A) on the first main surface (101) so as to be separated from the first main surface (101).

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors, a method for manufacturing multilayer ceramic capacitors, and a method for manufacturing an mounting structure for multilayer ceramic capacitors. Background Technology

[0002] A multilayer ceramic capacitor is known to have multiple via conductors and multiple external terminals electrically connected to these via conductors.

[0003] For example, the multilayer capacitor disclosed in Japanese Patent Application Publication No. 7-201651 (Patent Document 1) is characterized in that at least a portion of the front and back main surfaces of the multilayer containing the dielectric and the internal electrodes are each formed with an external electrode, the internal electrodes and the external electrodes being of the same polarity are interconnected by a plurality of columnar connecting members, and columnar connecting members (through-hole conductors) are provided where the magnetic fields formed by the current flowing through the internal electrodes cancel each other out.

[0004] For example, Japanese Patent Application Publication No. 2006-135333 (Patent Document 2) discloses a stacked capacitor array comprising: a capacitor body; a first internal electrode and a second internal electrode, which are alternately arranged opposite each other with stacked dielectric layers sandwiched in between; a first external terminal and a second external terminal formed on one or more of the upper and lower surfaces of the body; and a first conductive via and a second conductive via formed in the stacking direction of the body and connected to the first external terminal and the second external terminal, respectively.

[0005] Prior art literature

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 7-201651

[0008] Patent Document 2: Japanese Patent Application Publication No. 2006-135333 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] Regarding the multilayer ceramic capacitors described in Patent Documents 1 and 2, it is stated that the equivalent series inductance (ESL) can be reduced. However, there is room for further improvement in reducing the ESL of such multilayer ceramic capacitors.

[0011] The present invention was made in view of the above-mentioned problems, and its object is to provide a multilayer ceramic capacitor that can further reduce the equivalent series inductance (ESL) of the multilayer ceramic capacitor, a method for manufacturing the multilayer ceramic capacitor, and a method for manufacturing the mounting structure of the multilayer ceramic capacitor.

[0012] Technical solutions for solving the problem

[0013] A multilayer ceramic capacitor according to one aspect of the present invention includes a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor. The plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction, sandwiching the dielectric layer. The first via conductor is electrically connected to the plurality of first internal electrode layers. The first via conductor extends from the interior of the capacitor body to a first main surface. The first main surface is one side of the capacitor body in the stacking direction. The second via conductor is electrically connected to the plurality of second internal electrode layers. The second via conductor extends from the interior of the capacitor body to the first main surface. The first external electrode includes a first base electrode layer and a first surface electrode layer. The first base electrode layer is disposed on the first main surface such that it covers the first via conductor. The first surface electrode layer directly covers the first base electrode layer. The second external electrode is disposed on the first main surface, spaced apart from the first external electrode, such that it covers the second via conductor. The outer surface of the first surface electrode layer extends from the end edge of the first base electrode layer on the first main surface, such that it is far away from the first main surface.

[0014] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention comprises: preparing a capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction, sandwiching the dielectric layer; a first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; a second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface; providing a first external electrode comprising a first base electrode layer and a first surface electrode layer, the first base electrode layer being disposed on the first main surface such that it covers the first via conductor, and a first surface electrode layer directly covering the first base electrode layer; and providing a second external electrode spaced apart from the first external electrode on the first main surface such that it covers the second via conductor. Setting the first external electrode includes: forming a first base electrode layer; forming a first plating layer by plating on the first base electrode layer; heating and melting the first plating layer; and cooling the heated and melted first plating layer, thereby forming a first surface electrode layer.

[0015] A multilayer ceramic capacitor according to another aspect of the present invention includes: a capacitor body; a first external electrode; and a second external electrode. The capacitor body includes a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor, and a second via conductor. The plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction, sandwiching the dielectric layer. The first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface. The first main surface is one side of the capacitor body in the stacking direction. The second via conductor is electrically connected to the plurality of second internal electrode layers. The second via conductor extends from the interior of the capacitor body to the first main surface. A first external electrode is disposed on the first main surface such that it covers the first via conductor. A second external electrode is disposed on the first main surface at a distance from the first external electrode such that it covers the second via conductor. The outer surface of the first external electrode extends from an end edge of the first via conductor in the first main surface such that it is moved away from the first main surface.

[0016] A method for manufacturing a multilayer ceramic capacitor according to another aspect of the present invention comprises: preparing a capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, wherein the plurality of first internal electrode layers and the plurality of second internal electrode layers are alternately stacked in a stacking direction, sandwiching the dielectric layer; the first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; the second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface; a first external electrode is disposed on the first main surface such that it covers the first via conductor; and a second external electrode is disposed on the first main surface at a distance from the first external electrode such that it covers the second via conductor. The first external electrode is formed by: forming a first plating layer 30 by plating it onto a first via conductor in the first main surface; heating and melting the first plating layer; and cooling the heated and melted first plating layer, thereby forming the first external electrode.

[0017] Invention Effects

[0018] According to the present invention, the equivalent series inductance (ESL) of multilayer ceramic capacitors can be further reduced. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view showing a multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0020] Figure 2 It is along the direction of the arrow on line II-II. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation.

[0021] Figure 3 It is along the direction of the arrow on line III-III. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation.

[0022] Figure 4 It is along the direction of the arrow on line IV-IV. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation.

[0023] Figure 5 This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0024] Figure 6A This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the first modified example.

[0025] Figure 6B This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the second variation.

[0026] Figure 6C This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the third variation.

[0027] Figure 6D This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the fourth variation.

[0028] Figure 6E This is a cross-sectional view of the multilayer ceramic capacitor involved in the fifth variation, through the first inner electrode layer.

[0029] Figure 6F This is a cross-sectional view of the ceramic capacitor involved in the fifth variation, at a section passing through the second internal electrode layer.

[0030] Figure 6G This is a cross-sectional view of the multilayer ceramic capacitor involved in the sixth variation, through the first internal electrode layer.

[0031] Figure 6H This is a cross-sectional view of the ceramic capacitor involved in the sixth variation, at a section passing through the second internal electrode layer.

[0032] Figure 7 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0033] Figure 8This is a schematic cross-sectional view showing the state immediately after the first plating layer is formed in the manufacturing method of the multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0034] Figure 9 This is a cross-sectional SEM image of the state immediately after the formation of the first plating layer, observed in an experimental example of manufacturing a ceramic capacitor according to Embodiment 1 of the present invention.

[0035] Figure 10 This is a cross-sectional SEM image showing the formation of a first surface electrode layer observed in an experimental example of manufacturing a ceramic capacitor according to Embodiment 1 of the present invention.

[0036] Figure 11 This is a schematic cross-sectional view showing the appearance of the multilayer ceramic capacitor and electronic components according to Embodiment 1 of the present invention.

[0037] Figure 12 This is a schematic cross-sectional view illustrating the mounting structure of a multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0038] Figure 13 This is a cross-sectional view showing a multilayer ceramic capacitor according to Embodiment 2 of the present invention.

[0039] Figure 14 This is a cross-sectional view showing the multilayer ceramic capacitor according to Embodiment 3 of the present invention.

[0040] Figure 15 This is a cross-sectional view showing the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0041] Figure 16 This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0042] Figure 17 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0043] Figure 18 This is a schematic cross-sectional view showing the state immediately after the first plating layer is formed in the manufacturing method of the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0044] Figure 19 This is a schematic cross-sectional view showing the appearance of the multilayer ceramic capacitor and electronic components according to Embodiment 4 of the present invention.

[0045] Figure 20 This is a schematic cross-sectional view illustrating the mounting structure of the multilayer ceramic capacitor according to Embodiment 4 of the present invention. Detailed Implementation

[0046] Hereinafter, with reference to the figures, we will describe the multilayer ceramic capacitor, the method for manufacturing the multilayer ceramic capacitor, and the method for manufacturing the mounting structure of the multilayer ceramic capacitor according to various embodiments of the present disclosure. In the following description of the embodiments, the same or equivalent parts of the figures will be labeled with the same reference numerals, and their descriptions will not be repeated.

[0047] (Implementation Method 1)

[0048] Multilayer ceramic capacitors

[0049] Figure 1 This is a cross-sectional view showing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 2 It is along the direction of the arrow on line II-II. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation. Figure 3 It is along the direction of the arrow on line III-III. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation. Figure 4 It is along the direction of the arrow on line IV-IV. Figure 1 A cross-sectional view of a multilayer ceramic capacitor during observation.

[0050] like Figures 1 to 4 As shown, the multilayer ceramic capacitor 1 includes a capacitor body 10, a first external electrode 20A, and a second external electrode 20B.

[0051] The shape of the capacitor body 10 is arbitrary. In this embodiment, the capacitor body 10 has a shape that is generally cuboid. The shape that is generally cuboid means, for example, a shape that has rounded corners and edges like a cuboid, although it is not a perfect cuboid, but has 6 surfaces and can be generally shaped like a cuboid.

[0052] The capacitor body 10 has a first main surface 101, a second main surface 102, and a peripheral surface 103. The first main surface 101 is one side of the capacitor body 10 in the stacking direction DS. The second main surface 102 is the opposite side of the first main surface 101 in the capacitor body 10. Viewed from the stacking direction DS, the first main surface 101 and the second main surface 102 may also have a rectangular shape. The peripheral surface 103 connects the first main surface 101 and the second main surface 102.

[0053] The size of the capacitor body 10 is arbitrary. For example, when viewed from the first main surface 101, the longitudinal dimension of the rectangle can be set to 0.3 mm or more and 3.0 mm or less, the transverse dimension can be set to 0.3 mm or more and 3.0 mm or less, and the dimension in the stacking direction DS can be set to 50 μm or more and 200 μm or less.

[0054] The capacitor body 10 includes multiple dielectric layers 11, multiple first internal electrode layers 12A and multiple second internal electrode layers 12B, multiple first via conductors 13A and multiple second via conductors 13B.

[0055] The plurality of dielectric layers 11 include a first outer layer portion 111 and a second outer layer portion 112. The first outer layer portion 111 is the dielectric layer 11 located closest to the first main surface 101 among the plurality of dielectric layers 11. The first outer layer portion 111 forms a portion of the first main surface 101. The second outer layer portion 112 is the dielectric layer 11 located closest to the second main surface 102 among the plurality of dielectric layers 11. The second outer layer portion 112 forms the entire second main surface 102. The peripheral surface 103 is entirely formed by the plurality of dielectric layers 11 including the first outer layer portion 111 and the second outer layer portion 112.

[0056] The dielectric layer 11 can be made of any material, for example, a ceramic material with BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as the main component. Secondary components, selected from the group containing Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, but in smaller quantities than the main components, can also be added to these main components.

[0057] Multiple first internal electrode layers 12A and multiple second internal electrode layers 12B are alternately stacked one layer at a time in the stacking direction DS, sandwiching a dielectric layer 11. In the multilayer ceramic capacitor 1, the first internal electrode layers 12A and the second internal electrode layers 12B are positioned opposite each other with the dielectric layer 11 in between, thereby forming an electrostatic capacitor. Furthermore, the multiple first internal electrode layers 12A and multiple second internal electrode layers 12B are stacked as described above, thereby making the multilayer ceramic capacitor 1 a multilayer ceramic capacitor with high capacitance density, in which multiple capacitor functional parts are arranged in parallel.

[0058] In this embodiment, each of the plurality of first internal electrode layers 12A is integrally formed within the same layer (see reference). Figure 3 Viewed from the stacking direction DS, the first internal electrode layer 12A has a rectangular shape. Each of the multiple first internal electrode layers 12A has multiple first through holes 12Ah for inserting multiple second via conductors 13B.

[0059] In this embodiment, multiple second internal electrode layers 12B are each integrally formed within the same layer (see reference). Figure 4 Viewed from the stacking direction DS, the second inner electrode layer 12B has a rectangular shape that is approximately the same as that of the first inner electrode layer 12A. In each of the plurality of second inner electrode layers 12B, a plurality of second through holes 12Bh are formed to allow the plurality of first via conductors 13A described later to pass through.

[0060] The materials of the first internal electrode layer 12A and the second internal electrode layer 12B are arbitrary, for example, containing metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals as the main components. The first internal electrode layer 12A and the second internal electrode layer 12B may also contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 11 as a common material. In this case, the proportion of the common material contained in the first internal electrode layer 12A and the second internal electrode layer 12B is, for example, 20 vol% or less.

[0061] The thickness of each of the first internal electrode layer 12A and the second internal electrode layer 12B is arbitrary, for example, it can be set to a thickness of 0.3 μm or more and 1.0 μm or less. The number of the first internal electrode layer 12A and the second internal electrode layer 12B is arbitrary, for example, the two combined can be set to a thickness of 10 or more and 150 or less.

[0062] Each of the plurality of first via conductors 13A is electrically connected to at least one of the plurality of first internal electrode layers 12A. In this embodiment, each of the plurality of first via conductors 13A is electrically connected to each of the plurality of first internal electrode layers 12A.

[0063] Multiple first via conductors 13A extend from the interior of the capacitor body 10 to the first main surface 101. The multiple first via conductors 13A extend along the stacking direction DS. The first via conductors 13A do not protrude from the second main surface 102. The multiple first via conductors 13A are inserted through second through-holes 12Bh formed in each of the multiple second internal electrode layers 12B. Therefore, the multiple first via conductors 13A are insulated from the multiple second internal electrode layers 12B.

[0064] Each of the plurality of second via conductors 13B is electrically connected to at least one of the plurality of second internal electrode layers 12B. In this embodiment, each of the plurality of second via conductors 13B is electrically connected to each of the plurality of second internal electrode layers 12B.

[0065] Multiple second via conductors 13B extend from the interior of the capacitor body 10 to the first main surface 101. The multiple second via conductors 13B extend along the stacking direction DS. The second via conductors 13B do not protrude from the second main surface 102. The multiple second via conductors 13B are inserted through second through-holes 12Bh formed in each of the multiple first internal electrode layers 12A. Therefore, the multiple second via conductors 13B are insulated from the multiple first internal electrode layers 12A.

[0066] The shapes of the plurality of first via conductors 13A and second via conductors 13B are arbitrary, for example, they can be cylindrical. In this case, the diameters of the first via conductors 13A and second via conductors 13B are, for example, between 20 μm and 150 μm. Furthermore, the distance between adjacent first via conductors 13A and second via conductors 13B (more specifically, the distance between the center of the first via conductor 13A and the center of the second via conductor 13B) is, for example, between 50 μm and 500 μm.

[0067] The materials of the first via conductor 13A and the second via conductor 13B are arbitrary. For example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used. In this embodiment, the materials of the first via conductor 13A and the second via conductor 13B are preferably Ni or Ni-containing alloys.

[0068] Figure 5 This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 1 as well as Figure 5 As shown, a plurality of first external electrodes 20A are disposed on the first main surface 101, such that they respectively cover the corresponding first via conductor 13A. More specifically, the plurality of first external electrodes 20A respectively cover the edge of the corresponding first via conductor 13A and dielectric layer 11 (first outer layer 111) on the first main surface 101.

[0069] Each of the plurality of first external electrodes 20A includes a first base electrode layer 21A and a first surface electrode layer 22A. The first base electrode layer 21A is disposed on the first main surface 101 such that it covers the corresponding first via conductor 13A. Specifically, the first base electrode layer 21A covers the boundary between the corresponding first via conductor 13A and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101.

[0070] The specific internal structure of the first base electrode layer 21A is not particularly limited. In this embodiment, the first base electrode layer 21A includes a burn-on electrode layer 211A, a first base plating layer 212A as a base plating layer, and a second base plating layer 213A.

[0071] A sintered electrode layer 211A is disposed on the first main surface 101, directly covering the first via conductor 13A. Specifically, the sintered electrode layer 211A covers the boundary between the corresponding first via conductor 13A and the dielectric layer 11 (first outer layer 111) on the first main surface 101. The sintered electrode layer 211A preferably contains a metal of the same type as the metal contained in the first via conductor 13A. In this embodiment, the material of the sintered electrode layer 211A is preferably Ni or an alloy containing Ni. To improve the bonding strength with the dielectric layer 11, a ceramic material is also added to the sintered electrode layer 211A as a common material.

[0072] The substrate plating layer covers the entire portion of the surface of the sintered electrode layer 211A that is not in contact with the first main surface 101. Specifically, the first substrate plating layer 212A directly covers the entire portion of the surface of the sintered electrode layer 211A that is not in contact with the first main surface 101. Viewed from the first substrate plating layer 212A, the second substrate plating layer 213A is covered on the opposite side of the sintered electrode layer 211A.

[0073] Materials constituting the substrate plating layer include Cu, Ni, and Au. In this embodiment, the first substrate plating layer 212A contains Cu, and the second substrate plating layer 213A contains Ni.

[0074] The shape of the first substrate electrode layer 21A when viewed from the stacking direction DS is not particularly limited. For example, the shape of the first substrate electrode layer 21A when viewed from the stacking direction DS can be circular. When the shape of the first substrate electrode layer 21A when viewed from the stacking direction DS is circular, the shapes of the sintered electrode layer 211A, the first substrate plating layer 212A, and the second substrate plating layer 213A when viewed from the stacking direction DS are also circular. Furthermore, the thickness of each of the sintered electrode layer 211A, the first substrate plating layer 212A, and the second substrate plating layer 213A is, for example, 1 μm or more and 10 μm or less.

[0075] The first surface electrode layer 22A directly covers the first base electrode layer 21A. The first surface electrode layer 22A covers the entire portion of the first base electrode layer 21A that is not in contact with the first main surface 101.

[0076] The outer surface 221A of the first surface electrode layer 22A extends from the end edge 21AE of the first base electrode layer 21A on the first main surface 101, such that it is far away from the first main surface 101. Furthermore, the outer surface 221A of the first surface electrode layer 22A includes a first region 221Ap and a second region 221Aq in the stacking direction DS.

[0077] Region 221Ap is connected to edge 21AE. Region 221Aq is located on the opposite side of the first main surface 101 when viewed from region 221Ap. Region 221Ap extends such that the cross-sectional area of ​​the first external electrode 20A increases with distance from the first main surface 101 when viewed from the stacking direction DS. Region 221Aq extends such that the cross-sectional area of ​​the first external electrode 20A decreases with distance from the first main surface 101 when viewed from the stacking direction DS.

[0078] More specifically, the outer surface 221A of the first surface electrode layer 22A extends in a generally curved shape. When the shape of the first base electrode layer 21A is circular when viewed from the stacking direction DS, the outer surface 221A of the first surface electrode layer 22A extends in a generally spherical shape.

[0079] The thickness T1 of the central portion of the first surface electrode layer 22A in the planar direction DP parallel to the first main surface 101 in the stacking direction DS is greater than the average thickness of the first surface electrode layer 22A, which is the average thickness of the first surface electrode layer 22A from the inner surface 222A, which is the surface in contact with the first base electrode layer 21A, to the outer surface 221A. Furthermore, in this embodiment, the central portion of the first surface electrode layer 22A in the planar direction DP is the central portion (center of gravity) of the first surface electrode layer 22A when viewed from the stacking direction DS. Moreover, the thickness from the inner surface 222A to the outer surface 221A when viewed from any point on the inner surface 222A is the thickness of the first surface electrode layer 22A along the normal line when a normal line is imaginarily drawn from the inner surface 222A at that point. The average thickness from the inner surface 222A to the outer surface 221A can be calculated, for example, by averaging the thicknesses observed from five points at different positions on the inner surface 222A.

[0080] The height dimension H of the first surface electrode layer 22A in the stacking direction DS from the first main surface 101 is, for example, 10 μm or more and 20 μm or less. The larger the height dimension H of the first surface electrode layer 22A, the greater the distance between the capacitor body 10 and the electronic component can be when the first surface electrode layer 22A is reflow soldered to the electronic component. Therefore, by setting the height dimension H to 10 μm or more, it is easy to inject bottom-filling resin to fill the gap between the capacitor body 10 and the electronic component. However, the height dimension H of the first surface electrode layer 22A is not limited to the range described above.

[0081] The width dimension W of the first surface electrode layer 22A, which is the maximum dimension in the planar direction DP, can be appropriately set to correspond to the dimension in the planar direction DP of the first via conductor 13A. When the shape of the first surface electrode layer 22A is approximately circular when viewed from the stacking direction DS, the width dimension W is the diameter of the first surface electrode layer 22A when viewed from the stacking direction DS. The width dimension W of the first surface electrode layer 22A is, for example, 120 μm or less, preferably 100 μm or less, and more preferably 75 μm or less. The smaller the width dimension W of the first surface electrode layer 22A, the smaller the center distance in the planar direction DP between the first external electrode 20A and the second external electrode 20B (described later) can be designed. There is no particular limitation on the lower limit of the width dimension W of the first surface electrode layer 22A, but the width dimension W of the first surface electrode layer 22A can, for example, be 30 μm or more, or 50 μm or more.

[0082] The ratio (W / H) of the first surface electrode layer 22A, which is the value when the width dimension W is divided by the height dimension H, is preferably 3.0 or less, and more preferably 1.5 or less. The smaller the ratio (W / H) becomes, the smaller the center distance in the face direction DP between the first external electrode 20A and the second external electrode 20B (described later) can be designed, and the greater the distance between the capacitor body 10 and the electronic component can be when the first surface electrode layer 22A is reflow soldered to the electronic component.

[0083] The first surface electrode layer 22A is preferably formed of a material having a melting point lower than that of the material constituting the first base electrode layer 21A. This makes it easier to maintain the shape of the first base electrode layer 21A when the first surface electrode layer 22A is reflow soldered to an electronic component. Furthermore, it becomes easier to form the first surface electrode layer 22A into the shape described above (which will be described in detail later). The first surface electrode layer 22A is preferably formed, for example, of Sn or an alloy containing metals such as Sn and Ag.

[0084] like Figure 1 As shown, a plurality of second external electrodes 20B are spaced apart from a plurality of first external electrodes 20A. The plurality of second external electrodes 20B are disposed on the first main surface 101 such that they respectively cover the corresponding second via conductor 13B. More specifically, the plurality of second external electrodes 20B respectively cover the boundary between the corresponding second via conductor 13B and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101. The second external electrode 20B, when viewed from the corresponding second via conductor 13B, can have the same structure as the first external electrode 20A when viewed from the corresponding first via conductor 13A.

[0085] Each of the plurality of second external electrodes 20B includes a second base electrode layer 21B and a second surface electrode layer 22B. The second base electrode layer 21B is disposed on the first main surface 101 such that it covers the corresponding second via conductor 13B. Specifically, the second base electrode layer 21B covers the boundary between the corresponding second via conductor 13B and the dielectric layer 11 (first outer layer portion 111) on the first main surface 101. The second base electrode layer 21B in the second external electrode 20B can have the same structure as the first base electrode layer 21A in the first external electrode 20A. In this embodiment, the second base electrode layer 21B has the same burn-in electrode layer, first base plating layer, and second base plating layer (not shown) as the first base electrode layer 21A.

[0086] The second surface electrode layer 22B directly covers the second base electrode layer 21B. The second surface electrode layer 22B covers the entire portion of the second base electrode layer 21B that is not in contact with the first main surface 101.

[0087] The outer surface 221B of the second surface electrode layer 22B extends from the end edge 21BE of the second base electrode layer 21B on the first main surface 101, such that it is far away from the first main surface 101. Furthermore, the second surface electrode layer 22B, when viewed from the corresponding second base electrode layer 21B and the second via conductor 13B, can have the same structure as the first surface electrode layer 22A when viewed from the corresponding first base electrode layer 21A and the first via conductor 13A.

[0088] In this embodiment, the height dimension H of the first surface electrode layer 22A (and the second surface electrode layer 22B) can take various values. Furthermore, in this embodiment, the first base electrode layer 21A (and the second base electrode layer 21B) can also have various layer structures. Here, the multilayer ceramic capacitors according to various modifications of this embodiment will be described. In the description of each modification, structures identical to those in Embodiment 1 will not be repeated.

[0089] Figure 6A This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the first modified example. Figure 6A As shown, the first variation of Embodiment 1 of the present invention involves a multilayer ceramic capacitor 1w and the first surface electrode layer 22A in this embodiment (see reference). Figure 5 Compared to the previous version, the height dimension H is larger.

[0090] Figure 6B This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the second variation. Figure 6BAs shown, in the multilayer ceramic capacitor 1x according to the second variation of Embodiment 1 of the present invention, the substrate plating layer in the first substrate electrode layer 21A is composed only of the first substrate plating layer 212A. In this variation, the first surface electrode layer 22A directly covers the first substrate plating layer 212A.

[0091] Figure 6C This is a partial cross-sectional view showing the first external electrode and its periphery of the multilayer ceramic capacitor involved in the third variation. Figure 6C As shown, in the multilayer ceramic capacitor 1y according to the third modification of Embodiment 1 of the present invention, the first base electrode layer 21A does not include a sintered electrode layer. In this modification, the first base electrode layer 21A only includes a first base plating layer 212A and a second base plating layer 213A. In this modification, the first base plating layer 212A is disposed on the first main surface 101, such that it directly covers the first via conductor 13A.

[0092] Figure 6D This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor involved in the fourth variation. Figure 6D As shown, in the multilayer ceramic capacitor 1z according to the fourth modification of Embodiment 1 of the present invention, the first base electrode layer 21A only includes the first base plating layer 212A. Therefore, in this modification, the first base plating layer 212A is disposed on the first main surface 101, such that it directly covers the first via conductor 13A, and the first surface electrode layer 22A directly covers the first base plating layer 212A.

[0093] Furthermore, in this embodiment, when viewed from the stacking direction DS, the first via conductor 13A and the second via conductor 13B are alternately arranged in two directions: one in a certain direction and the other in a direction orthogonal to that direction (see reference). Figure 3 as well as Figure 4 However, the arrangement of the first via conductor 13A and the second via conductor 13B when viewed from the stacking direction DS is not limited to the above arrangement.

[0094] Figure 6E This is a cross-sectional view of the multilayer ceramic capacitor involved in the fifth variation, through the first inner electrode layer. Figure 6F This is a cross-sectional view of the multilayer ceramic capacitor involved in the fifth variation, taken through the second inner electrode layer. Figure 6E as well as Figure 6FAs shown, in the multilayer ceramic capacitor 1m according to the fifth modification, when viewed from the stacking direction DS, multiple first via conductors 13Am are adjacent to each other in one direction, and multiple second via conductors 13Bm are adjacent to each other. Furthermore, the first internal electrode layer 12Am contains multiple separate first internal electrode portions 121A and 122A within the same layer. In this modification, only one second internal electrode layer 12Bm is located within the same layer; however, the second internal electrode layer 12Bm may also contain multiple separate second internal electrode layers within the same layer.

[0095] Figure 6G This is a cross-sectional view of the multilayer ceramic capacitor involved in the sixth variation, through the first internal electrode layer. Figure 6H This is a cross-sectional view of the multilayer ceramic capacitor involved in the sixth variation, at a section passing through the second inner electrode layer. Figure 6G as well as Figure 6H As shown, in the multilayer ceramic capacitor 1n involved in the sixth modified example, when viewed from the stacking direction DS, the arrangement direction of the first via conductor 13An and the second via conductor 13Bn is such that it intersects one side of the peripheral side surface 103 that extends in a rectangular shape.

[0096] [Manufacturing method of multilayer ceramic capacitors]

[0097] Next, the manufacturing method of the multilayer ceramic capacitor according to Embodiment 1 of the present invention will be described. Figure 7 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 7 As shown, the manufacturing method of the multilayer ceramic capacitor according to Embodiment 1 of the present invention includes a step S1 of preparing a capacitor body, a step S2 of setting a first external electrode, and a step S3 of setting a second external electrode.

[0098] In step S1 of preparing the capacitor body, preparation Figure 1The capacitor body 10 is shown. The specific method for preparing the capacitor body 10 is not particularly limited. In this embodiment, for example, in step S1 of preparing the capacitor body, firstly, a plurality of ceramic green sheets corresponding to a plurality of dielectric layers 11 and conductive paste layers corresponding to a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B are stacked together in a given pattern to form a laminate. A plurality of through holes penetrating in the stacking direction of the laminate are formed by laser irradiation. Then, conductive paste is filled into these plurality of through holes. Thus, a plurality of columnar conductive pastes corresponding to a plurality of first through-hole conductors 13A and a plurality of second through-hole conductors 13B of the capacitor body 10 are provided in the laminate. Furthermore, an outer ceramic green sheet corresponding to at least a portion of the second outer layer 112 is further stacked in the laminate, such that one side covers these columnar conductive pastes. Thus, on one side of the laminate (the side corresponding to the second main surface 102), the plurality of columnar conductive pastes are not exposed.

[0099] Then, the laminate containing multiple columnar conductive pastes and an outer ceramic green sheet is fired. This forms the capacitor body 10.

[0100] In step S2 of setting the first external electrode, Figure 1 as well as Figure 5 The first external electrode 20A shown is disposed on the first main surface 101 of the capacitor body 10. For example... Figure 7 As shown, the process S2 for setting the first external electrode includes a process S21 for forming a first base electrode layer, a process S22 for forming a first plating layer, a process S23 for heating and melting the first plating layer, and a process S24 for forming a first surface electrode layer by cooling the first plating layer.

[0101] In step S21 of forming the first base electrode layer, a electrode is provided on the main surface of the capacitor body 10. Figure 1 as well as Figure 5 The first base electrode layer 21A is shown. First, a conductive paste surface layer corresponding to the burn-on electrode layer 211A is provided on the first main surface 101 of the capacitor body 10, covering the first through-hole conductor 13A, and then further fired to form the burn-on electrode layer 211A. The conductive paste surface layer may also be provided in a laminate before firing the capacitor body 10. In this case, the firing of the laminate and the firing of the conductive paste surface layer can be performed simultaneously.

[0102] After the sintered electrode layer 211A is formed, a first substrate plating layer 212A is formed by plating the sintered electrode layer 211A. Then, a second substrate plating layer 213A is formed by plating the first substrate plating layer 212A. These plating processes can be, for example, plating processes using a spin plating method. Additionally, in the third variation of this embodiment (see...) Figure 6C ) and the 4th variation (see Figure 6D In this process, a first substrate plating layer 212A is formed by plating the first via conductor 13A. In this case, the first substrate plating layer 212A is also grown in the planar direction DP during the plating process. Therefore, the first substrate plating layer 212A is configured to cover the boundary between the dielectric layer 11 (first outer layer 111) and the first via conductor 13A.

[0103] Figure 8 This is a schematic cross-sectional view showing the state immediately after the first plating layer has been formed in the manufacturing method of the multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 8 As shown, in step S22 of forming the first plating layer, the first plating layer 30A is formed by plating onto the first base electrode layer 21A. Specifically, the first plating layer 30A is formed by plating the first base electrode layer 21A.

[0104] The first plating layer 30A is formed to cover the entire portion of the first base electrode layer 21A that is not in contact with the first main surface 101. The outer surface 301A of the first plating layer 30A, which is the exposed surface, is located away from the end edge 21AE of the first base electrode layer 21A on the first main surface 101. Furthermore, the thickness Tp1 of the central portion of the first plating layer 30A in the surface direction DP in the stacking direction DS is approximately equal to the average thickness of the first plating layer 30A, which is the average thickness of the first plating layer 30A from the inner surface 302A, which is the surface in contact with the first base electrode layer 21A, to the outer surface 301A. The first plating layer 30A is formed by plating, so that it grows from the first base electrode layer 21A, and therefore the thickness from the inner surface 302A to the outer surface 301A becomes approximately uniform. The average thickness of the first plating layer 30A is, for example, 3 μm or more and 50 μm or less. The average thickness of the first plating layer 30A can be appropriately designed taking into account the distance between the center of the first via conductor 13A in the face direction DP and the center of the second via conductor 13B in the face direction DP, as well as the separation distance between the first via conductor 13A and the second via conductor 13B.

[0105] In step S23, where the first plating layer is heated and melted, the first plating layer 30A formed as described above is heated and melted. As a result, the molten first plating layer 30A deforms into a curved shape due to its surface tension, making the area of ​​the outer surface 301A infinitely close to the minimum area of ​​the volume of the first plating layer 30A; more specifically, it deforms into a roughly spherical shape. Through this deformation, the thickness Tp1 at the central portion of the first plating layer 30A increases, and the height dimension Hp of the first plating layer 30A in the stacking direction DS also increases. On the other hand, through this deformation, the width dimension Wp of the first plating layer 30A, which is the maximum dimension in the planar direction DP, decreases. Furthermore, the bonding strength between the first plating layer 30A and the first outer layer 111 is relatively low, while the bonding strength between the first plating layer 30A and the first base electrode layer 21A is relatively high. Therefore, the outer surface 301A of the first plating layer 30A is deformed to extend relative to the first main surface 101 from the end edge 21AE of the first base electrode layer 21A on the first main surface 101.

[0106] Then, in step S24, which forms the first surface electrode layer by cooling the first plating layer, the first plating layer 30A, which has been melted and deformed as described above, is cooled and solidified. Thus, a first surface electrode layer is formed as described above. Figure 1 as well as Figure 5 The first surface electrode layer 22A is shown. Therefore, by adjusting the average thickness of the first plating layer 30A, the average thickness of the first surface electrode layer 22A, the thickness T1 at the central portion, the height dimension H, and the width dimension W, etc., can be controlled.

[0107] Here, an experimental example of the multilayer ceramic capacitor according to this embodiment is shown, and the first plating layer 30A and the first surface electrode layer 22A are described. Figure 9 This is a cross-sectional SEM image of the state immediately after the formation of the first plating layer, observed in an experimental example of manufacturing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 10 This is a cross-sectional SEM image showing the formation of the first surface electrode layer in an experimental example of manufacturing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. Figure 9 as well as Figure 10 In the figure, reference numerals corresponding to those marked in the description of the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention are used.

[0108] Like in Figure 9 as well as Figure 10 As shown in the diagram, by melting the first plating layer 30A, the outer surface 301A of the first plating layer 30A is deformed into a generally spherical shape. Then, the molten first plating layer 30A is cooled and solidified, thereby forming a first surface electrode layer 22A with a generally spherical outer surface 221A.

[0109] Therefore, in this embodiment, the width dimension W of the first surface electrode layer 22A becomes smaller than the width dimension Wp of the first plating layer 30A before heating and melting. The height dimension H of the first surface electrode layer 22A becomes larger than the height dimension Hp of the first plating layer 30A before heating and melting. The thickness T1 at the central portion of the first surface electrode layer 22A becomes thicker than the thickness Tp1 at the central portion of the first plating layer 30A before heating and melting. The ratio (W / H) of the first surface electrode layer 22A becomes smaller than the ratio (Wp / Hp) of the first plating layer 30A before heating and melting, which is the value when the width dimension Wp is divided by the height dimension Hp.

[0110] Furthermore, the smaller the dimension of the first base electrode layer 21A in the planar direction DP, the greater the difference between the height dimension H of the first surface electrode layer 22A and the height dimension Hp of the first plating layer 30A. Moreover, the greater the thickness Tp1 at the central portion of the first plating layer 30A before heating and melting, the greater the height dimension H of the first surface electrode layer 22A. In addition, the heating and cooling conditions in steps S33 and S34 can be appropriately adjusted according to the material of the first plating layer 30A (first surface electrode layer 22A). These heating and cooling conditions can be the same as those for solder reflow soldering following IPC / J-STD. The peak temperature in step S33 is, for example, 260°C.

[0111] In step S3 of setting the second external electrode, a electrode is set on the first main surface 101 of the capacitor body 10. Figure 1 The second external electrode 20B is shown. (As shown in the image.) Figure 7 As shown, the process S3 for setting the second external electrode includes a process S31 for forming the second base electrode layer, a process S32 for forming the second plating layer, a process S33 for heating and melting the second plating layer, and a process S34 for forming the second surface electrode layer by cooling the second plating layer.

[0112] The process S3 for setting the second external electrode can also be performed simultaneously and in parallel with the process S2 for setting the first external electrode. Specifically, the process S31 for forming the second base electrode layer is performed simultaneously with the process S21 for forming the first base electrode layer. The process S32 for forming the second plating layer is performed simultaneously with the process S22 for forming the first plating layer. The process S33 for heating and melting the second plating layer is performed simultaneously with the process S23 for heating and melting the first plating layer. The process S34 for forming the second surface electrode layer by cooling the second plating layer is performed simultaneously with the process S24 for forming the first surface electrode layer by cooling the first plating layer.

[0113] In step S31 of forming the second base electrode layer, a electrode is provided on the main surface of the capacitor body 10. Figure 1 as well as Figure 5 The second base electrode layer 21B is shown. As a method for forming the second base electrode layer 21B when viewed from the corresponding second via conductor 13B, the same method as the method for forming the first base electrode layer 21A when viewed from the first via conductor 13A can be used.

[0114] In step S32, which forms the second plating layer, the second plating layer can be formed on the second base electrode layer 21B using the same method as that used to form the first plating layer 30A on the first base electrode layer 21A. The heating conditions in step S33, which heats and melts the second plating layer, can also be the same as those in step S23, which heats and melts the first plating layer. Therefore, the second plating layer is deformed in the same way as the first plating layer 30A. The cooling conditions for the heated and melted second plating layer in step S34, which cools the second plating layer to form the second surface electrode layer 22B, can also be the same as those in step S24, which cools the first surface electrode layer 22A.

[0115] The multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention can be manufactured using the manufacturing method described above. However, the manufacturing method of the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention is not limited to the manufacturing method described above.

[0116] [Manufacturing method for mounting structure of multilayer ceramic capacitors]

[0117] Next, the manufacturing method of the mounting structure of the multilayer ceramic capacitor according to Embodiment 1 of the present invention will be described. Figure 11 This is a schematic cross-sectional view showing the appearance of the multilayer ceramic capacitor and electronic components according to Embodiment 1 of the present invention. Figure 12 This is a schematic cross-sectional view illustrating the mounting structure of a multilayer ceramic capacitor according to Embodiment 1 of the present invention.

[0118] like Figure 11 as well as Figure 12 As shown, the manufacturing method of the mounting structure of the multilayer ceramic capacitor includes: a step of preparing a multilayer ceramic capacitor 1 manufactured by the above-described manufacturing method; and a step of reflow soldering a plurality of first surface electrode layers 22A of the multilayer ceramic capacitor 1 to an electronic component 500, thereby electrically connecting the plurality of first surface electrode layers 22A to the electronic component 500. Thus, the mounting structure 1000 of the multilayer ceramic capacitor can be manufactured.

[0119] Furthermore, the manufacturing method of the stacked ceramic capacitor mounting structure in this embodiment also includes a step of reflow soldering a plurality of second surface electrode layers 22B to an electronic component 500, thereby electrically connecting the plurality of second surface electrode layers 22B to the electronic component 500. This step can be performed simultaneously with the step of reflow soldering the first surface electrode layer 22A.

[0120] The plurality of first surface electrode layers 22A and the plurality of second surface electrode layers 22B manufactured by the manufacturing method of the multilayer ceramic capacitor in this embodiment have a relatively large thickness in the central portion in the planar direction DP, as described above. Therefore, reflow soldering of the plurality of first surface electrode layers 22A and the plurality of second surface electrode layers 22B becomes easier. Consequently, the multilayer ceramic capacitor 1 can be more easily mounted to the electronic component 500, and the mounting structure 1000 of the multilayer ceramic capacitor can be manufactured more easily.

[0121] As described above, the laminated ceramic capacitor 1 according to Embodiment 1 of the present invention includes a capacitor body 10, a first external electrode 20A, and a second external electrode 20B. The capacitor body 10 includes a dielectric layer 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, a first via conductor 13A, and a second via conductor 13B. The plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B are alternately laminated in the lamination direction DS, sandwiching the dielectric layer 11. The first via conductor 13A is electrically connected to the plurality of first internal electrode layers 12A. The first via conductor 13A extends from the interior of the capacitor body 10 to a first main surface 101. The first main surface 101 is one side of the capacitor body 10 in the lamination direction DS. The second via conductor 13B is electrically connected to the plurality of second internal electrode layers 12B. The second via conductor 13B extends from the interior of the capacitor body 10 to the first main surface 101. The first external electrode 20A includes a first base electrode layer 21A and a first surface electrode layer 22A. The first base electrode layer 21A is disposed on the first main surface 101, such that it covers the first via conductor 13A. The first surface electrode layer 22A directly covers the first base electrode layer 21A. The second external electrode 20B is disposed on the first main surface 101 spaced apart from the first external electrode 20A, such that it covers the second via conductor 13B. The outer surface 221A of the first surface electrode layer 22A extends from the end edge 21AE of the first base electrode layer 21A on the first main surface 101, such that it is located away from the first main surface 101.

[0122] According to the above structure, near the end edge 21AE of the first base electrode layer 21A, the thickness of the first surface electrode layer 22A in the planar direction DP, which is orthogonal to the stacking direction DS, becomes relatively small. Therefore, the center distance between the first external electrode 20A and the second external electrode 20B in the planar direction DP can be designed to be small, thereby reducing the spacing between the first via conductor 13A and the second via conductor 13B. If the spacing between the first via conductor 13A and the second via conductor 13B can be reduced, the magnetic field induced by the current flowing through the first via conductor 13A and the magnetic field induced by the current flowing through the second via conductor 13B become more easily canceled out.

[0123] Therefore, based on the above structure, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1 can be reduced.

[0124] Furthermore, in this embodiment, the thickness T1 of the central portion of the first surface electrode layer 22A in the planar direction DP parallel to the first main surface 101 in the stacking direction DS is greater than the average thickness of the first surface electrode layer 22A. The average thickness of the first surface electrode layer 22A is the average thickness of the first surface electrode layer 22A from the inner surface 222A, which is the surface that is in contact with the first base electrode layer 21A, to the outer surface 221A.

[0125] According to the above structure, the thickness T1 of the first surface electrode layer 22A in the stacking direction DS becomes relatively large. When such a stacked ceramic capacitor 1 is mounted to the electronic component 500, and the first surface electrode layer 22A is reflow soldered to the electronic component 500, the distance between the capacitor body 10 and the electronic component 500 can be relatively large. Therefore, it is easy to provide bottom-filling resin for filling the gap between the capacitor body 10 and the electronic component 500 in this gap.

[0126] Furthermore, in this embodiment, the outer surface 221A of the first surface electrode layer 22A includes a first region 221Ap and a second region 221Aq in the stacking direction DS. The first region 221Ap is in contact with the end edge 21AE. The second region 221Aq is located on the opposite side of the first main surface 101 when viewed from the first region 221Ap. The first region 221Ap extends such that the cross-sectional area of ​​the first external electrode 20A increases with distance from the first main surface 101 when viewed from the stacking direction DS. The second region 221Aq extends such that the cross-sectional area of ​​the first external electrode 20A decreases with distance from the first main surface 101 when viewed from the stacking direction DS.

[0127] According to the above structure, it is possible to prevent the thickness from becoming too small from the inner surface 222A to the outer surface 221A of the first surface electrode layer 22A in the first region 221Ap, thus ensuring the strength of the first surface electrode layer 22A. Furthermore, in the second region 221Aq, the size of the first surface electrode layer 22A in the planar direction DP can be reduced. This further reduces the center distance between the first external electrode 20A and the second external electrode 20B in the planar direction DP. Consequently, the spacing between the first via conductor 13A and the second via conductor 13B can be further reduced, further reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1.

[0128] Furthermore, in this embodiment, the first via conductor 13A and the second via conductor 13B are not exposed from the second main surface 102, which is the opposite side of the first main surface 101 in the capacitor body 10.

[0129] According to the above structure, it is possible to suppress short circuits in the multilayer ceramic capacitor 1 and other electronic components disposed on the second main surface 102 side of the multilayer ceramic capacitor 1.

[0130] Furthermore, the manufacturing method of the multilayer ceramic capacitor according to Embodiment 1 of the present invention includes: preparing a capacitor body 10, the capacitor body 10 comprising a dielectric layer 11, a plurality of first internal electrode layers 12A and a plurality of second internal electrode layers 12B, a first via conductor 13A and a second via conductor 13B, the plurality of first internal electrode layers 12A and the plurality of second internal electrode layers 12B being alternately stacked in the stacking direction DS, sandwiching the dielectric layer 11, the first via conductor 13A being electrically connected to the plurality of first internal electrode layers 12A and extending from the interior of the capacitor body 10 to a first main surface 101, the first main surface 101 being the stack of the capacitor body 10. On one side of the surface in direction DS, a second via conductor 13B is electrically connected to a plurality of second internal electrode layers 12B and extends from the interior of the capacitor body 10 to the first main surface 101; a first external electrode 20A is provided, the first external electrode 20A comprising a first base electrode layer 21A and a first surface electrode layer 22A, the first base electrode layer 21A being disposed on the first main surface 101 such that it covers the first via conductor 13A, and the first surface electrode layer 22A directly covers the first base electrode layer 21A; and a second external electrode 20B is provided on the first main surface 101 at a distance from the first external electrode 20A such that it covers the second via conductor 13B. Setting the first external electrode 20A includes: forming a first base electrode layer 21A; forming a first plating layer 30A by plating on the first base electrode layer 21A; heating and melting the first plating layer 30A; and cooling the heated and melted first plating layer 30A, thereby forming a first surface electrode layer 22A.

[0131] According to the above structure, by heating and melting the first plating layer 30A, the outer surface of the first plating layer 30A is deformed into a generally spherical shape. The first plating layer 30A, deformed by heating and melting, is cooled to form the first surface electrode layer 22A, thereby making the dimension of the first surface electrode layer 22A in the planar direction DP smaller than the dimension of the first plating layer 30A in the planar direction DP. Therefore, the center distance between the first external electrode 20A and the second external electrode 20B in the planar direction DP can be designed to be small, and further, the spacing between the first via conductor 13A and the second via conductor 13B can be reduced. If the spacing between the first via conductor 13A and the second via conductor 13B can be reduced, the magnetic field induced by the current flowing through the first via conductor 13A and the magnetic field induced by the current flowing through the second via conductor 13B become more easily canceled out.

[0132] Therefore, based on the above structure, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1 can be reduced.

[0133] Furthermore, the first plating layer 30A, which is deformed by heating and melting, is cooled to form the first surface electrode layer 22A. As a result, the thickness T1 at the central portion of the first surface electrode layer 22A becomes greater than the thickness Tp1 at the central portion of the first plating layer 30A. When the multilayer ceramic capacitor 1 manufactured according to the above structure is mounted to the electronic component 500, the distance between the capacitor body 10 and the electronic component 500 can be made larger when the first surface electrode layer 22A is reflow soldered to the electronic component 500. Therefore, bottom-filling resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily provided in this gap.

[0134] The manufacturing method of the mounting structure of the multilayer ceramic capacitor according to Embodiment 1 of the present invention includes: preparing a multilayer ceramic capacitor 1 manufactured by the above-described manufacturing method; and reflow soldering the first surface electrode layer 22A of the multilayer ceramic capacitor 1 to an electronic component 500, thereby electrically connecting the first surface electrode layer 22A to the electronic component 500.

[0135] According to the above structure, bottom filling resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily disposed in the gap.

[0136] (Implementation Method 2)

[0137] Next, the multilayer ceramic capacitor according to Embodiment 2 of the present invention will be described. The multilayer ceramic capacitor according to Embodiment 2 of the present invention differs from the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention in that it further includes a third external electrode and a fourth external electrode. Therefore, the same structure and effects as those of the multilayer ceramic capacitor according to Embodiment 1 of the present invention will not be repeated.

[0138] Figure 13 This is a cross-sectional view showing a multilayer ceramic capacitor according to Embodiment 2 of the present invention. Figure 13 As shown, the multilayer ceramic capacitor 1a also includes a third external electrode 20Ca and a fourth external electrode 20Da. A first via conductor 13Aa extends from the interior of the capacitor body 10 to the second main surface 102. A second via conductor 13Ba extends from the interior of the capacitor body 10 to the second main surface 102.

[0139] The third external electrode 20Ca includes a third base electrode layer 21Ca and a third surface electrode layer 22Ca. The third base electrode layer 21Ca is disposed on the second main surface 102 such that it covers either the first via conductor 13Aa or the second via conductor 13Ba. The third surface electrode layer 22Ca directly covers the third base electrode layer 21Ca.

[0140] The fourth external electrode 20Da is spaced apart from the third external electrode 20Ca and disposed on the second main surface 102, such that it covers either the first via conductor 13Aa or the second via conductor 13Ba.

[0141] The outer surface 221Ca of the third surface electrode layer 22Ca extends from the end edge 21CEa of the third base electrode layer 21Ca on the second main surface 102, such that it is far away from the second main surface 102.

[0142] According to the above structure, even when an external electrode is provided on the second main surface 102 side, the center distance between the third external electrode 20Ca and the fourth external electrode 20Da in the surface direction DP can be designed to be small. Furthermore, the spacing between the first via conductor 13Aa and the second via conductor 13Ba can be reduced in order to reduce the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1a.

[0143] Specifically, the multilayer ceramic capacitor 1a according to this embodiment includes a plurality of third external electrodes 20Ca and a plurality of fourth external electrodes 20Da. The plurality of third external electrodes 20Ca are disposed on the second main surface 102, respectively covering a plurality of first via conductors 13Aa. A third base electrode layer 21Ca is disposed on the second main surface 102, covering the corresponding first via conductor 13Aa. In this embodiment, the third external electrodes 20Ca, when viewed from the second main surface 102, can have the same structure as the first external electrodes 20A, when viewed from the first main surface 101.

[0144] Multiple fourth external electrodes 20Da are disposed on the second main surface 102, such that they cover multiple second via conductors 13Ba. The fourth external electrodes 20Da include a fourth base electrode layer 21Da and a fourth surface electrode layer 22Da. The fourth base electrode layer 21Da is disposed on the second main surface 102, such that it covers the second via conductors 13Ba. The fourth surface electrode layer 22Da directly covers the fourth base electrode layer 21Da.

[0145] Furthermore, the outer surface 221Da of the fourth surface electrode layer 22Da also extends from the end edge 21DEa of the fourth base electrode layer 21Da on the second main surface 102, thus moving away from the second main surface 102. In this embodiment, the fourth external electrode 20Da, when viewed from the second main surface 102, can have the same structure as the second external electrode 20B when viewed from the first main surface 101.

[0146] The method for manufacturing a multilayer ceramic capacitor according to this embodiment further includes the steps of setting the third external electrode 20Ca and setting the fourth external electrode 20Da. Viewed from the second main surface 102, the step of setting the third external electrode 20Ca can have the same structure as step S2 of setting the first external electrode 20A when viewed from the first main surface 101. The step of setting the third external electrode 20Ca can also be performed simultaneously and in parallel with step S2 of setting the first external electrode 20A. Viewed from the second main surface 102, the step of setting the fourth external electrode 20Da can have the same structure as step S3 of setting the second external electrode 20B when viewed from the first main surface 101. The step of setting the fourth external electrode 20Da can also be performed simultaneously and in parallel with step S3 of setting the second external electrode 20B.

[0147] Furthermore, in this embodiment, the steps of setting the third external electrode 20Ca and the fourth external electrode 20Da can be implemented, for example, by clamping the capacitor body 10 with a jig so that the structures for the third external electrode 20Ca and the fourth external electrode 20Da are not grounded. Furthermore, in the step S1 of preparing the capacitor body in this embodiment, in order to prevent the two sides of the columnar conductive paste in the stacking direction DS from being covered by the outer layer, an outer ceramic green sheet is not stacked on the laminate.

[0148] (Implementation Method 3)

[0149] Next, the multilayer ceramic capacitor according to Embodiment 3 of the present invention will be described. In the multilayer ceramic capacitor according to Embodiment 3 of the present invention, the shapes of the third surface electrode layer and the fourth surface electrode layer are different from those of the multilayer ceramic capacitor according to Embodiment 2 of the present invention. Therefore, the same structure and effects as those of the multilayer ceramic capacitor according to Embodiment 2 of the present invention will not be repeated.

[0150] Figure 14 This is a cross-sectional view illustrating a multilayer ceramic capacitor according to Embodiment 3 of the present invention. Figure 14 As shown, in the multilayer ceramic capacitor 1b according to Embodiment 3 of the present invention, the thickness T3 of the central portion of the third surface electrode layer 22Cb in the planar direction DP parallel to the first main surface 101 in the stacking direction DS is smaller than the thickness T1 of the central portion of the first surface electrode layer 22A in the planar direction DP parallel to the first main surface 101 in the stacking direction DS. According to this structure, the overall size of the multilayer ceramic capacitor 1b in the stacking direction DS can be made smaller.

[0151] Furthermore, in this embodiment, the thickness T4 of the central portion in the planar direction DP of the fourth surface electrode layer 22Db in the stacking direction DS is smaller than the thickness T1 of the central portion in the planar direction DP of the first surface electrode layer 22A that is parallel to the first main surface 101 in the stacking direction DS.

[0152] In the manufacturing method of the multilayer ceramic capacitor 1b according to this embodiment, in the step of heating and melting the plating layer provided on each base electrode layer to form the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db, the plating layer can be heated and melted while the orientation of the capacitor body 10 is fixed such that the second main surface 102 of the capacitor body 10 faces upward in the vertical direction. As a result, the heated and melted plating layer deforms under its own weight, becoming flattened, and a third surface electrode layer 22Cb and a fourth surface electrode layer 22Db with a relatively small thickness in the central portion can be formed. Alternatively, in the step of heating and melting the plating layer provided on each base electrode layer to form the third surface electrode layer 22Cb and the fourth surface electrode layer 22Db, a portion of the heated and melted plating layer can be absorbed, thereby forming a third surface electrode layer 22Cb and a fourth surface electrode layer 22Db with a relatively small thickness in the central portion.

[0153] (Implementation Method 4)

[0154] Next, the multilayer ceramic capacitor and its manufacturing method, as well as the manufacturing method of the mounting structure of the multilayer ceramic capacitor, according to Embodiment 4 of the present invention, will be described. In the multilayer ceramic capacitor according to Embodiment 4 of the present invention, the structures of the first external electrode and the second external electrode are different from those of the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention. In the following description of Embodiment 4, the same structures and effects as those of the multilayer ceramic capacitor 1 and its manufacturing method, as well as the manufacturing method of the mounting structure of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, will not be repeated.

[0155] Multilayer ceramic capacitors

[0156] Figure 15 This is a cross-sectional view showing the multilayer ceramic capacitor according to Embodiment 4 of the present invention. Figure 16 This is a partial cross-sectional view showing the first external electrode and its surrounding area of ​​the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0157] like Figure 15 as well as Figure 16 As shown, in the multilayer ceramic capacitor 1c according to Embodiment 4 of the present invention, the outer surface 201Ac of the first external electrode 20Ac extends from the end edge 13AE of the first through conductor 13A in the first main surface 101, such that it is far away from the first main surface 101.

[0158] According to the above structure, the first external electrode 20Ac covers the first via conductor 13A. Even so, the dimension of the first external electrode 20Ac in the planar direction DP can still be reduced near the end edge 13AE of the first via conductor 13A. Therefore, the center distance in the planar direction DP between the first external electrode 20Ac and the second external electrode 20Bc can be designed to be small, thereby reducing the gap between the first via conductor 13A and the second via conductor 13B. If the gap between the first via conductor 13A and the second via conductor 13B can be reduced, the magnetic field induced by the current flowing through the first via conductor 13A and the magnetic field induced by the current flowing through the second via conductor 13B become easier to cancel each other out.

[0159] Therefore, based on the above structure, the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c can be reduced.

[0160] Furthermore, in this embodiment, the outer surface 201Ac of the first external electrode 20Ac includes a first region 201Acp and a second region 201Acq in the stacking direction DS. The first region 201Acp is in contact with the end edge 13AE. The second region 201Acq is located on the opposite side of the first main surface 101 when viewed from the first region 201Acp. The first region 201Acp extends such that the cross-sectional area of ​​the first external electrode 20Ac increases with distance from the first main surface 101 when viewed from the stacking direction DS. The second region 201Acq extends such that the cross-sectional area of ​​the first external electrode 20Ac decreases with distance from the first main surface 101 when viewed from the stacking direction DS.

[0161] According to the above structure, it is possible to prevent the size of the first external electrode 20Ac in the planar direction DP of the first region 201Acp from becoming too small, thus ensuring the strength of the first external electrode 20Ac. Furthermore, in the second region 201Acq, the size of the first external electrode 20Ac in the planar direction DP can be reduced. This further reduces the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP. Consequently, the spacing between the first via conductor 13A and the second via conductor 13B can be further reduced, further lowering the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c.

[0162] The first external electrode 20Ac and the second external electrode 20Bc in Embodiment 4 of the present invention will be described in detail.

[0163] More specifically, the outer surface 201Ac of the first external electrode 20Ac extends in a generally curved shape, and more specifically, in a generally spherical shape. The height dimension Hc of the first external electrode 20Ac in the stacking direction DS is, for example, between 10 μm and 20 μm. The larger the height dimension Hc of the first external electrode 20Ac, the greater the distance between the capacitor body 10 and the electronic component can be when the first external electrode 20Ac is reflow soldered to the electronic component. Therefore, by setting the height dimension Hc to 10 μm or less, it is easy to inject the bottom filling resin used to fill the gap between the capacitor body 10 and the electronic component into the gap. There is no particular upper limit to the height dimension Hc of the first external electrode 20Ac. However, the height dimension Hc of the first external electrode 20Ac is not limited to the range described above.

[0164] The width dimension Wc of the first external electrode 20Ac, which is the maximum dimension in the planar direction DP, can be appropriately set to correspond to the dimension of the first via conductor 13A in the planar direction DP. The aforementioned width dimension Wc is, for example, 120 μm or less, preferably 100 μm or less, and more preferably 75 μm or less. The smaller the width dimension Wc of the first external electrode 20Ac, the smaller the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP can be designed. There is no particular lower limit set for the width dimension Wc of the first external electrode 20Ac, but this width dimension Wc can, for example, be 30 μm or more, or 50 μm or more.

[0165] The ratio (Wc / Hc) of the first external electrode 20Ac, which is the value when the width dimension Wc is divided by the height dimension Hc, is preferably 3.0 or less, and more preferably 1.5 or less. The smaller the ratio (Wc / Hc) becomes, the smaller the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP can be designed, and the greater the distance between the capacitor body 10 and the electronic component can be when the first external electrode 20Ac is reflow soldered to the electronic component.

[0166] Each of the plurality of first external electrodes 20Ac comprises a single component. The plurality of first external electrodes 20Ac are preferably formed of a material having a melting point lower than that of the material constituting the first via conductor 13A. This makes it easier to form the first surface electrode layer 22A into the shape described above (which will be described in detail later). The first external electrodes 20Ac are preferably formed, for example, of Sn or an alloy containing metals such as Sn and Ag.

[0167] The outer surface 201Bc of the second external electrode 20Bc extends from the end edge 13BE of the corresponding second via conductor 13B in the first main surface 101, such that it is far away from the first main surface 101. In this way, the second external electrode 20Bc, when viewed from the corresponding second via conductor 13B, can have the same structure as the first external electrode 20Ac when viewed from the corresponding first via conductor 13A.

[0168] [Manufacturing method of multilayer ceramic capacitors]

[0169] Next, the manufacturing method of the multilayer ceramic capacitor according to Embodiment 4 of the present invention will be described. Figure 17 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to Embodiment 4 of the present invention. Figure 18 This is a schematic cross-sectional view showing the state immediately after the first plating layer is formed in the manufacturing method of the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0170] like Figure 17 as well as Figure 18 As shown, in the manufacturing method of the multilayer ceramic capacitor according to Embodiment 4 of the present invention, setting the first external electrode 20Ac (S2c) includes: forming a first plating layer 30Ac by plating on the first through-hole conductor 13A in the first main surface 101 (S22c); heating and melting the first plating layer 30Ac (S23c); and cooling the heated and melted first plating layer 30Ac, thereby forming the first external electrode 20Ac (S24c).

[0171] According to the above structure, by heating and melting the first plating layer 30Ac, the outer surface of the first plating layer 30Ac is deformed into a generally spherical shape. The first plating layer 30Ac, deformed by heating and melting, is cooled to form the first external electrode 20Ac, thereby making the width dimension Wc of the first external electrode 20Ac smaller than the width dimension Wpc of the first plating layer 30Ac, which is the maximum dimension in the planar direction DP. Therefore, the center distance between the first external electrode 20Ac and the second external electrode 20Bc in the planar direction DP can be designed to be small, thereby reducing the spacing between the first via conductor 13A and the second via conductor 13B. If the spacing between the first via conductor 13A and the second via conductor 13B can be reduced, the magnetic field induced by the current flowing through the first via conductor 13A and the magnetic field induced by the current flowing through the second via conductor 13B become more easily canceled out.

[0172] Therefore, according to the above structure, the spacing between the first via conductor 13A and the second via conductor 13B can be reduced, and the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1c can be reduced.

[0173] Furthermore, the first plating layer 30Ac, which has been deformed by heating and melting, is cooled to form the first external electrode 20Ac, thereby making the height dimension Hc of the first external electrode 20Ac larger than the height dimension Hpc of the first plating layer 30A. When the multilayer ceramic capacitor 1c manufactured according to the above structure is mounted to an electronic component, the distance between the capacitor body 10 and the electronic component can be relatively large when the first external electrode 20Ac is reflow soldered to the electronic component. Therefore, the bottom filling resin for filling the gap between the capacitor body 10 and the electronic component can be easily provided in the gap.

[0174] The manufacturing method of the multilayer ceramic capacitor in Embodiment 4 of the present invention will be described in more detail. For example... Figure 17 As shown, in this embodiment, the process S2c of setting the first external electrode includes a process S22c of forming the first plating layer, a process S23c of heating and melting the first plating layer, and a process S24c of forming the first external electrode by cooling the first plating layer.

[0175] like Figure 18 As shown, in step S22c of forming the first plating layer, the first plating layer 30Ac is formed by plating the first via conductor 13A. This plating process can be, for example, a plating process using a spin plating method. In the plating process, the first plating layer 30Ac is also grown in the planar direction DP. Therefore, the first plating layer 30Ac is configured to cover the boundary between the dielectric layer 11 (first outer layer 111) and the first via conductor 13A.

[0176] In step S23c, where the first plating layer is heated and melted, the first plating layer 30Ac formed as described above is heated and melted. As a result, the molten first plating layer 30Ac deforms into a curved shape due to its surface tension, making the area of ​​the outer surface 301Ac infinitely close to the minimum area under the volume of the first plating layer 30Ac; more specifically, it deforms into a roughly spherical shape. Through this deformation, the height dimension Hpc of the first plating layer 30Ac increases. On the other hand, through this deformation, the width dimension Wpc of the first plating layer 30Ac decreases. Furthermore, the bonding strength between the first plating layer 30Ac and the first outer layer portion 111 is relatively low, while the bonding strength between the first plating layer 30Ac and the first via conductor 13A is relatively high. Therefore, the outer surface 301Ac of the first plating layer 30Ac is deformed to extend relative to the first main surface 101 from the end edge 13AE of the first via conductor 13A on the first main surface 101.

[0177] Then, in step S24c, where the first external electrode is formed by cooling the first plating layer, the first plating layer 30Ac, which has been melted and deformed as described above, is cooled and solidified. Thus, a first external electrode is formed as described above. Figure 15as well as Figure 16 The first external electrode 20Ac is shown. Therefore, by adjusting the height dimension Hpc of the first plating layer 30Ac, the height dimension Hc and width dimension Wc of the first external electrode 20Ac can be controlled.

[0178] Therefore, in this embodiment, the width dimension Wc of the first external electrode 20Ac becomes smaller than the width dimension Wpc of the first plating layer 30Ac before heating and melting. The height dimension Hc of the first external electrode 20Ac becomes larger than the height dimension Hpc of the first plating layer 30Ac before heating and melting. The ratio (Wc / Hc) of the first external electrode 20Ac becomes smaller than the ratio (Wpc / Hpc) of the first plating layer 30A before heating and melting.

[0179] like Figure 17 As shown, in this embodiment, the process S3c for setting the second external electrode includes a process S32c for forming the second plating layer, a process S33c for heating and melting the second plating layer, and a process S34c for forming the second external electrode by cooling the second plating layer. The process S32c for forming the second plating layer is performed simultaneously with the process S22c for forming the first plating layer. The process S33c for heating and melting the second plating layer is performed simultaneously with the process S23c for heating and melting the first plating layer. The process S34c for forming the second surface electrode layer by cooling the second plating layer is performed simultaneously with the process S24c for forming the first surface electrode layer by cooling the first plating layer.

[0180] As for the method of forming the second external electrode 20Bc when viewed from the corresponding second via conductor 13B, the same method as the method of forming the first external electrode 20Ac when viewed from the first via conductor 13A can be used. Specifically, in step S32c of forming the second plating layer, the second plating layer can be formed on the second via conductor 13B by the same method as the method of forming the first plating layer 30A on the first via conductor 13A. The heating conditions of step S33c of heating and melting the second plating layer can also be the same as the heating conditions of step S23c of heating and melting the first plating layer. As a result, the second plating layer is also deformed in the same way as the first plating layer 30Ac. In step S34c of forming the second external electrode 20Bc by cooling the second plating layer, the cooling conditions of the heated and melted second plating layer can also be the same as the cooling conditions in step S24 of forming the first external electrode 20Ac by cooling the first plating layer.

[0181] The multilayer ceramic capacitor 1c according to Embodiment 4 of the present invention can be manufactured using the manufacturing method described above. However, the manufacturing method of the multilayer ceramic capacitor 1c according to Embodiment 4 of the present invention is not limited to the manufacturing method described above.

[0182] [Manufacturing method for mounting structure of multilayer ceramic capacitors]

[0183] Figure 19 This is a schematic cross-sectional view showing the appearance of the multilayer ceramic capacitor and electronic components according to Embodiment 4 of the present invention. Figure 20 This is a schematic cross-sectional view illustrating the mounting structure of the multilayer ceramic capacitor according to Embodiment 4 of the present invention.

[0184] like Figure 19 as well as Figure 20 As shown, the manufacturing method of the mounting structure of the multilayer ceramic capacitor according to Embodiment 4 of the present invention includes: a step of preparing a multilayer ceramic capacitor 1c manufactured by the above-described manufacturing method of multilayer ceramic capacitor; and a step of reflow soldering the first external electrode 20Ac of the multilayer ceramic capacitor 1c to the electronic component 500, thereby electrically connecting the first external electrode 20Ac to the electronic component 500.

[0185] Based on the above structure, a mounting structure 1000c for a multilayer ceramic capacitor can be manufactured. Furthermore, based on the above structure, bottom-filling resin for filling the gap between the capacitor body 10 and the electronic component 500 can be easily disposed in the gap.

[0186] Furthermore, the manufacturing method of the stacked ceramic capacitor mounting structure in this embodiment also includes a step of reflow soldering the second external electrode 20Bc to the electronic component 500, thereby electrically connecting the second external electrode 20Bc to the electronic component 500. This step can be performed simultaneously with the step of reflow soldering the first external electrode 20Ac.

[0187] (Postscript)

[0188] As described above, this embodiment includes the following disclosures.

[0189] <1>

[0190] A multilayer ceramic capacitor, comprising:

[0191] Capacitor body;

[0192] The first external electrode; and

[0193] Second external electrode,

[0194] The capacitor body comprises:

[0195] Dielectric layer;

[0196] Multiple first internal electrode layers and multiple second internal electrode layers are alternately stacked in the stacking direction, sandwiching the dielectric layer;

[0197] A first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; and

[0198] The second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface.

[0199] The first external electrode includes:

[0200] A first base electrode layer is disposed on the first main surface, such that it covers the first via conductor; and

[0201] The first surface electrode layer directly covers the first base electrode layer.

[0202] The second external electrode is spaced apart from the first external electrode and disposed on the first main surface, thereby covering the second via conductor.

[0203] The outer surface of the first surface electrode layer extends from the end edge of the first base electrode layer on the first main surface, such that it is far away from the first main surface.

[0204] <2>

[0205] according to <1> The aforementioned multilayer ceramic capacitor, wherein,

[0206] The thickness of the central portion of the first surface electrode layer in the direction parallel to the first main surface in the stacking direction is greater than the average thickness of the first surface electrode layer, which is the average thickness of the first surface electrode layer from the inner surface of the surface that is in contact with the first base electrode layer to the outer surface.

[0207] <3>

[0208] according to <1> or <2> The aforementioned multilayer ceramic capacitor, wherein,

[0209] The outer surface of the first surface electrode layer includes, in the stacking direction, a first region connected to the end edge and a second region located on the opposite side of the first main surface when viewed from the first region.

[0210] The first region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, increases with distance from the first main surface.

[0211] The second region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, decreases as it moves away from the first main surface.

[0212] <4>

[0213] according to <1> to <3> The multilayer ceramic capacitor described in any one of the following, wherein,

[0214] The first via conductor and the second via conductor are not exposed from the second main surface, which is the opposite side of the first main surface in the capacitor body.

[0215] <5>

[0216] according to <1> to <4> The multilayer ceramic capacitor described in any one of the following, wherein,

[0217] It also has:

[0218] The third external electrode; and

[0219] Fourth external electrode,

[0220] The first via conductor extends from the interior of the capacitor body to the second main surface, which is the opposite side of the first main surface in the capacitor body.

[0221] The second via conductor extends from the interior of the capacitor body to the second main surface.

[0222] The third external electrode includes:

[0223] A third base electrode layer is disposed on the second main surface, such that it covers either the first via conductor or the second via conductor; and

[0224] The third surface electrode layer directly covers the third base electrode layer.

[0225] The fourth external electrode is spaced apart from the third external electrode and disposed on the second main surface, such that it covers either the first via conductor or the second via conductor.

[0226] The outer surface of the third surface electrode layer extends from the end edge of the third base electrode layer on the second main surface, such that it is far away from the second main surface.

[0227] <6>

[0228] according to <5> The aforementioned multilayer ceramic capacitor, wherein,

[0229] The thickness of the central portion of the third surface electrode layer in the plane direction parallel to the first main surface in the stacking direction is smaller than the thickness of the central portion of the first surface electrode layer in the plane direction parallel to the first main surface in the stacking direction.

[0230] <7>

[0231] A method for manufacturing a multilayer ceramic capacitor, comprising:

[0232] Prepare a capacitor body, the capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, the plurality of first internal electrode layers and the plurality of second internal electrode layers being alternately stacked in a stacking direction sandwiching the dielectric layer, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction, the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface;

[0233] A first external electrode is provided, the first external electrode comprising a first base electrode layer and a first surface electrode layer, the first base electrode layer being disposed on the first main surface such that it covers the first via conductor, and the first surface electrode layer directly covering the first base electrode layer; and

[0234] A second external electrode is disposed on the first main surface, spaced apart from the first external electrode, such that it covers the second via conductor.

[0235] in,

[0236] The first external electrode is configured to include:

[0237] Form the first substrate electrode layer;

[0238] The first plating layer is formed by plating onto the first base electrode layer;

[0239] The first coating layer is heated and melted; and

[0240] The first plating layer, which has been heated and melted, is cooled to form the first surface electrode layer.

[0241] <8>

[0242] A method for manufacturing a mounting structure for a multilayer ceramic capacitor, comprising:

[0243] Preparing to pass <7> The multilayer ceramic capacitor manufactured by the aforementioned method; and

[0244] The first surface electrode layer of the multilayer ceramic capacitor is reflow soldered to the electronic component, thereby electrically connecting the first surface electrode layer to the electronic component.

[0245] <9>

[0246] A multilayer ceramic capacitor, comprising:

[0247] Capacitor body;

[0248] The first external electrode; and

[0249] Second external electrode,

[0250] The capacitor body comprises:

[0251] Dielectric layer;

[0252] Multiple first internal electrode layers and multiple second internal electrode layers are alternately stacked in the stacking direction, sandwiching the dielectric layer;

[0253] A first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; and

[0254] The second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface.

[0255] The first external electrode is disposed on the first main surface, thereby covering the first via conductor.

[0256] The second external electrode is spaced apart from the first external electrode and disposed on the first main surface, thereby covering the second via conductor.

[0257] The outer surface of the first external electrode extends from the end edge of the first via conductor in the first main surface, such that it is far away from the first main surface.

[0258] <10>

[0259] according to <9> The aforementioned multilayer ceramic capacitor, wherein,

[0260] The outer surface of the first external electrode includes, in the stacking direction, a first region that is in contact with the end edge and a second region located on the opposite side of the first main surface when viewed from the first region.

[0261] The first region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, increases with distance from the first main surface.

[0262] The second region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, decreases as it moves away from the first main surface.

[0263] <11>

[0264] A method for manufacturing a multilayer ceramic capacitor, comprising:

[0265] Prepare a capacitor body, the capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, the plurality of first internal electrode layers and the plurality of second internal electrode layers being alternately stacked in a stacking direction sandwiching the dielectric layer, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction, the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface;

[0266] A first external electrode is provided on the first main surface, such that it covers the first through-hole conductor;

[0267] A second external electrode is disposed on the first main surface, spaced apart from the first external electrode, such that it covers the second via conductor.

[0268] in,

[0269] The first external electrode is configured to include:

[0270] A first plating layer is formed by plating onto the first via conductor in the first main surface;

[0271] The first coating layer is heated and melted; and

[0272] The first plating layer, which has been heated and melted, is cooled to form the first external electrode.

[0273] <12>

[0274] A method for manufacturing a mounting structure for a multilayer ceramic capacitor, comprising:

[0275] Preparing to pass <11> The multilayer ceramic capacitor manufactured by the aforementioned method; and

[0276] The first external electrode of the multilayer ceramic capacitor is reflow soldered to the electronic component, thereby electrically connecting the first external electrode to the electronic component.

[0277] In the above description of the implementation methods and embodiments, the structures that can be combined can also be combined with each other.

[0278] It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the invention is set forth not by the foregoing description but by the claims, and is intended to include all modifications equivalent to and within the scope of the claims.

[0279] Explanation of reference numerals in the attached figures

[0280] 1, 1a, 1b, 1c, 1m, 1n, 1w, 1x, 1y, 1z: Multilayer ceramic capacitors;

[0281] 10: Capacitor body;

[0282] 101: 1st main surface;

[0283] 102: 2nd main surface;

[0284] 103: Side view;

[0285] 11: Dielectric layer;

[0286] 111: First outer layer;

[0287] 112: Second outer layer;

[0288] 12A, 12Am: First internal electrode layer;

[0289] 12Ah: First through hole;

[0290] 121A, 122A: First internal electrode section;

[0291] 12B, 12Bm: Second internal electrode layer;

[0292] 12Bh: Second through hole;

[0293] 13A, 13Aa, 13Am, 13An: First via conductor;

[0294] 13B, 13Ba, 13Bm, 13Bn: Second via conductor;

[0295] 20A, 20Ac: First external electrode;

[0296] 20B, 20Bc: Second external electrode;

[0297] 20Ca: Third external electrode;

[0298] 20Da: Fourth external electrode;

[0299] 21A: First base electrode layer;

[0300] 211A: Electrode layer sintered;

[0301] 212A: First substrate coating layer;

[0302] 213A: Second substrate coating layer;

[0303] 21B: Second base electrode layer;

[0304] 21Ca: Third base electrode layer;

[0305] 21Da: Fourth base electrode layer;

[0306] 22A: First surface electrode layer;

[0307] 22B: Second surface electrode layer;

[0308] 22Ca, 22Cb: Third surface electrode layer;

[0309] 22Da, 22Db: Fourth surface electrode layer;

[0310] 30, 30A, 30Ac: First plating layer;

[0311] 500: Electronic components;

[0312] 1000, 1000c: Installation structure.

Claims

1. A multilayer ceramic capacitor, comprising: Capacitor body; The first external electrode; and Second external electrode, The capacitor body comprises: Dielectric layer; Multiple first internal electrode layers and multiple second internal electrode layers are alternately stacked in the stacking direction, sandwiching the dielectric layer; A first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; and The second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface. The first external electrode includes: A first base electrode layer is disposed on the first main surface, such that it covers the first via conductor; and The first surface electrode layer directly covers the first base electrode layer. The second external electrode is spaced apart from the first external electrode and disposed on the first main surface, thereby covering the second via conductor. The outer surface of the first surface electrode layer extends from the end edge of the first base electrode layer on the first main surface, such that it is far away from the first main surface.

2. The multilayer ceramic capacitor according to claim 1, wherein, The thickness of the central portion of the first surface electrode layer in the direction parallel to the first main surface in the stacking direction is greater than the average thickness of the first surface electrode layer, which is the average thickness of the first surface electrode layer from the inner surface of the surface that is in contact with the first base electrode layer to the outer surface.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The outer surface of the first surface electrode layer includes, in the stacking direction, a first region connected to the end edge and a second region located on the opposite side of the first main surface when viewed from the first region. The first region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, increases with distance from the first main surface. The second region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, decreases as it moves away from the first main surface.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The first via conductor and the second via conductor are not exposed from the second main surface, which is the opposite side of the first main surface in the capacitor body.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, It also has: The third external electrode; and Fourth external electrode, The first via conductor extends from the interior of the capacitor body to the second main surface, which is the opposite side of the first main surface in the capacitor body. The second via conductor extends from the interior of the capacitor body to the second main surface. The third external electrode includes: A third base electrode layer is disposed on the second main surface, such that it covers either the first via conductor or the second via conductor; as well as The third surface electrode layer directly covers the third base electrode layer. The fourth external electrode is spaced apart from the third external electrode and disposed on the second main surface, such that it covers either the first via conductor or the second via conductor. The outer surface of the third surface electrode layer extends from the end edge of the third base electrode layer on the second main surface, such that it is far away from the second main surface.

6. The multilayer ceramic capacitor according to claim 5, wherein, The thickness of the central portion of the third surface electrode layer in the plane direction parallel to the first main surface in the stacking direction is smaller than the thickness of the central portion of the first surface electrode layer in the plane direction parallel to the first main surface in the stacking direction.

7. A method for manufacturing a multilayer ceramic capacitor, comprising: Prepare a capacitor body, the capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, the plurality of first internal electrode layers and the plurality of second internal electrode layers being alternately stacked in a stacking direction sandwiching the dielectric layer, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction, the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface; A first external electrode is provided, the first external electrode comprising a first base electrode layer and a first surface electrode layer, the first base electrode layer being disposed on the first main surface such that it covers the first via conductor, and the first surface electrode layer directly covering the first base electrode layer; and A second external electrode is disposed on the first main surface, spaced apart from the first external electrode, such that it covers the second via conductor. in, The first external electrode is configured to include: Form the first substrate electrode layer; The first plating layer is formed by plating onto the first base electrode layer; The first coating layer is heated and melted; as well as The first plating layer, which has been heated and melted, is cooled to form the first surface electrode layer.

8. A method for manufacturing a mounting structure for a multilayer ceramic capacitor, comprising: A multilayer ceramic capacitor to be manufactured by the manufacturing method of the multilayer ceramic capacitor according to claim 7; and The first surface electrode layer of the multilayer ceramic capacitor is reflow soldered to the electronic component, thereby electrically connecting the first surface electrode layer to the electronic component.

9. A multilayer ceramic capacitor, comprising: Capacitor body; The first external electrode; and Second external electrode, The capacitor body comprises: Dielectric layer; Multiple first internal electrode layers and multiple second internal electrode layers are alternately stacked in the stacking direction, sandwiching the dielectric layer; A first via conductor is electrically connected to the plurality of first internal electrode layers and extends from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction; and The second via conductor is electrically connected to the plurality of second internal electrode layers and extends from the interior of the capacitor body to the first main surface. The first external electrode is disposed on the first main surface, thereby covering the first via conductor. The second external electrode is spaced apart from the first external electrode and disposed on the first main surface, thereby covering the second via conductor. The outer surface of the first external electrode extends from the end edge of the first via conductor in the first main surface, such that it is far away from the first main surface.

10. The multilayer ceramic capacitor according to claim 9, wherein, The outer surface of the first external electrode includes, in the stacking direction, a first region that is in contact with the end edge and a second region located on the opposite side of the first main surface when viewed from the first region. The first region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, increases with distance from the first main surface. The second region extends such that the cross-sectional area of ​​the first external electrode, when viewed from the stacking direction, decreases as it moves away from the first main surface.

11. A method for manufacturing a multilayer ceramic capacitor, comprising: Prepare a capacitor body, the capacitor body comprising a dielectric layer, a plurality of first internal electrode layers and a plurality of second internal electrode layers, a first via conductor and a second via conductor, the plurality of first internal electrode layers and the plurality of second internal electrode layers being alternately stacked in a stacking direction sandwiching the dielectric layer, the first via conductor being electrically connected to the plurality of first internal electrode layers and extending from the interior of the capacitor body to a first main surface, the first main surface being one side of the capacitor body in the stacking direction, the second via conductor being electrically connected to the plurality of second internal electrode layers and extending from the interior of the capacitor body to the first main surface; A first external electrode is provided on the first main surface, such that it covers the first through-hole conductor; A second external electrode is disposed on the first main surface, spaced apart from the first external electrode, such that it covers the second via conductor. in, The first external electrode is configured to include: A first plating layer is formed by plating onto the first via conductor in the first main surface; The first coating layer is heated and melted; and The first plating layer, which has been heated and melted, is cooled to form the first external electrode.

12. A method for manufacturing a mounting structure for a multilayer ceramic capacitor, comprising: A multilayer ceramic capacitor to be manufactured by the manufacturing method of the multilayer ceramic capacitor according to claim 11; and The first external electrode of the multilayer ceramic capacitor is reflow soldered to the electronic component, thereby electrically connecting the first external electrode to the electronic component.

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