Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having a high operating speed. The semiconductor device includes a transistor including a plurality of oxide semiconductors each having a fin shape in a cross-sectional view in a channel width direction. The source electrode includes a first conductor and a second conductor on the first conductor. The drain electrode includes a third conductor and a fourth conductor on the third conductor. The first and third conductors protrude from the second and fourth conductors, respectively. An interlayer insulating film is provided on the third and fourth conductors. The interlayer insulating film has an opening overlapping the oxide semiconductor. A blocking insulator is provided inside the opening so as to be in contact with the side surfaces of the first and second conductors and the side surfaces of the third and fourth conductors. A gate insulator is provided on the barrier insulator so as to be in contact with the oxide semiconductor, the side surface of the first conductor, and the side surface of the second conductor, and a gate electrode is provided on the gate insulator.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor layer. Another aspect of the present invention relates to a method for manufacturing the aforementioned semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and methods for driving or manufacturing such devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory being the main components used in them. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) formed by processing semiconductor wafers to create chips, and semiconductor elements having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] In addition, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, while oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0008] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187; [Patent Document 2] Japanese Patent Application Publication No. 2011-151383. Summary of the Invention

[0009] The technical problem that the invention aims to solve One objective of this invention is to provide a semiconductor device with high operating speed. Another objective is to provide a semiconductor device capable of miniaturization or high integration. Another objective is to provide a semiconductor device with good electrical characteristics. Another objective is to provide a semiconductor device with small transistor electrical characteristic non-uniformity. One objective is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device with high on-state current. Another objective is to provide a semiconductor device with low power consumption. Another objective is to provide a novel semiconductor device. Another objective is to provide a method for manufacturing a semiconductor device with high productivity. Another objective is to provide a novel method for manufacturing a semiconductor device.

[0010] Furthermore, one objective of this invention is to provide a storage device capable of miniaturization or high integration. Another objective of this invention is to provide a storage device with large storage capacity. Another objective of this invention is to provide a storage device with high operating speed. Another objective of this invention is to provide a storage device with low power consumption. Finally, one objective of this invention is to provide a novel storage device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0012] means of solving technical problems One aspect of the present invention is a semiconductor device comprising a transistor, a first insulator, a second insulator, and a third insulator. The transistor comprises an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fourth insulator. The first insulator is disposed on a substrate. The oxide semiconductor is disposed on the first insulator. The first and second conductors are both disposed on the oxide semiconductor. The third conductor is in contact with the top surface of the first conductor, and the fourth conductor is in contact with the top surface of the second conductor. The distance between the first and second conductors is smaller than the distance between the third and fourth conductors. The second insulator is disposed on the third and fourth conductors and includes an opening that overlaps with a region of the oxide semiconductor located between the third and fourth conductors when viewed from a planar perspective. The third insulator has a region in contact with the top surface of the first conductor and a region in contact with the top surface of the second conductor. The transistor is disposed inside the opening in such a way that it has a top surface contact area, a side contact area with the third conductor, a side contact area with the fourth conductor, and a side contact area with the second insulator. The fourth insulator is disposed inside the opening in such a way that it has a contact area with the oxide semiconductor, a side contact area with the first conductor, and a side contact area with the second conductor. The fifth conductor is disposed on the fourth insulator inside the opening. In at least the area overlapping with the opening, the shape of the first insulator in plan view is the same as or substantially the same as the shape of the oxide semiconductor in plan view. When viewed in cross-section in the channel width direction of the transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section in the channel width direction of the transistor, the height of the oxide semiconductor is greater than or equal to the width of the oxide semiconductor. When viewed in plan view, the area where the oxide semiconductor and the fifth conductor overlap is two or more.

[0013] In addition, in the above-mentioned method, the third insulator may also be less permeable to oxygen compared to the second insulator.

[0014] Alternatively, in the above-described manner, the third insulator may also comprise silicon nitride.

[0015] In addition, in the above-described manner, the first insulator may also contain a metal oxide.

[0016] Another aspect of the present invention is a semiconductor device comprising a transistor, a capacitor, a first insulator, a second insulator, and a third insulator. The transistor comprises an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fourth insulator. The capacitor comprises an oxide semiconductor, a second conductor, a sixth conductor, and a fifth insulator. The first insulator is disposed on a substrate, the oxide semiconductor is disposed on the first insulator, and both the first and second conductors are disposed on the oxide semiconductor. The third conductor is in contact with the top surface of the first conductor, and the fourth conductor is in contact with the top surface of the second conductor. The distance between the first and second conductors is smaller than the distance between the third and fourth conductors. The second insulator is disposed on the third and fourth conductors and includes a first opening that overlaps with a region of the oxide semiconductor located between the first and second conductors when viewed from a planar perspective. The second insulator includes a second opening that overlaps with the oxide semiconductor and extends to the second conductor. The third insulator has a region in contact with the top surface of the first conductor. A first insulator is disposed inside the first opening such that it has a region in contact with the top surface of the second conductor, a region in contact with the side surface of the third conductor, a region in contact with the side surface of the fourth conductor, and a region in contact with the side surface of the second insulator. The fourth insulator is disposed inside the first opening such that it has a region in contact with the oxide semiconductor, a region in contact with the side surface of the first conductor, and a region in contact with the side surface of the second conductor. A fifth conductor is disposed inside the first opening on the fourth insulator and overlaps with the second conductor. A sixth conductor is disposed inside the second opening on the fifth insulator. In at least the region overlapping with the first opening, the shape of the first insulator in plan view is the same as or substantially the same as the shape of the oxide semiconductor in plan view. When viewed in cross-section in the channel width direction of the transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section in the channel width direction of the transistor, the height of the oxide semiconductor is greater than or equal to the width of the oxide semiconductor. When viewed in plan view, there are two or more overlapping regions between the oxide semiconductor and the fifth conductor.

[0017] In addition, in the above-mentioned method, the third insulator may also be less permeable to oxygen compared to the second insulator.

[0018] Alternatively, in the above-described manner, the third insulator may also comprise silicon nitride.

[0019] In addition, in the above-described manner, the first insulator may also contain a metal oxide.

[0020] In addition, in the above-described manner, when viewed from a plane, the regions where the oxide semiconductor and the sixth conductor overlap can be two or more.

[0021] In addition, in the above-mentioned methods, metal oxides can also have the function of capturing or fixing hydrogen.

[0022] In addition, in the above methods, the metal oxide can also be a high-k material.

[0023] In addition, in the above-described manner, the metal oxide may also be an oxide containing one or both of aluminum and hafnium.

[0024] Alternatively, in the above method, the metal oxide can also be hafnium silicate.

[0025] In addition, in the above-described manner, when viewed from a plane, the oxide semiconductor can also appear as a ring with both ends aligned or roughly aligned.

[0026] In addition, in the above-described manner, when viewed from a plane, the side of the opening may be consistent with or substantially consistent with the side of the third conductor and the side of the fourth conductor.

[0027] Furthermore, in the above-described manner, when viewed in cross-section along the channel width direction of the transistor, the width of the oxide semiconductor can be 5 nm or more and 50 nm or less, and when viewed in cross-section along the channel width direction of the transistor, the height of the oxide semiconductor can be 1.5 times or more and 10 times or less the width of the oxide semiconductor.

[0028] In addition, in the above-described manner, the oxide semiconductor may also contain indium, and the oxide semiconductor may be formed perpendicular or substantially perpendicular to the substrate surface. Furthermore, when observing the cross-section of the oxide semiconductor using a transmission electron microscope, it can be confirmed that bright spots are arranged in layers in a direction perpendicular to the substrate surface.

[0029] In addition, in the above-described manner, the oxide semiconductor may also contain indium, and the oxide semiconductor may be formed perpendicular or substantially perpendicular to the surface of the substrate. The oxide semiconductor may also have a first region, a second region in contact with the first region, and a third region in contact with the second region. When observing the cross-section of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the substrate surface can be identified in each of the first, second, and third regions.

[0030] In addition, in the above-described manner, the second region may also contain zinc, and the second region may also contain a crystal, the c-axis of which may be approximately parallel to the normal direction of the side surface of the oxide semiconductor.

[0031] In addition, in the above method, the indium content in the first region can be higher than that in the second region, and the indium content in the third region can also be higher than that in the second region.

[0032] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: depositing an insulating film on a substrate; forming a first insulator on the insulating film; depositing an oxide semiconductor film to cover the first insulator; processing the oxide semiconductor film by anisotropic etching until the top surface of the first insulator is exposed to form an oxide semiconductor in contact with the side surface of the first insulator; removing the first insulator; forming a second insulator by removing regions of the insulating film that do not overlap with the oxide semiconductor; forming a first conductor and a second conductor on the first conductor to cover the oxide semiconductor and the second insulator; forming a third insulator on the second conductor; and processing the third insulator to form a third conductor in the third insulator. A first opening overlapping with an oxide semiconductor is formed; a third and fourth conductor are formed by processing a second conductor so that they sandwich the first opening when viewed in a planar view; a fourth insulator is formed in contact with the first, third, fourth conductors, and a third insulator; a second opening is formed in the fourth insulator in a manner that overlaps with at least a portion of the first opening; a fifth and sixth conductor are formed by processing the first conductor so that they sandwich the second opening when viewed in a planar view; a fifth insulator is formed on the fourth insulator in a manner that contacts the region of the oxide semiconductor overlapping the second opening; and a seventh conductor is formed on the fifth insulator in a manner that is embedded in the first opening.

[0033] Alternatively, in the above method, aluminum oxide or silicon nitride can also be used as the first insulator.

[0034] One aspect of the present invention is a semiconductor device including a transistor, a capacitor, a first insulator, a second insulator, and a third insulator. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fourth insulator. The capacitor includes an oxide semiconductor, a second conductor, a sixth conductor, and a fifth insulator. The first insulator is disposed on a substrate. The oxide semiconductor is disposed on the first insulator. The first and second conductors are both disposed on the oxide semiconductor. The third conductor is in contact with the top surface of the first conductor, and the fourth conductor is in contact with the top surface of the second conductor. The distance between the first and second conductors is smaller than the distance between the third and fourth conductors. The second insulator is disposed on the third and fourth conductors. The second insulator includes a first opening that overlaps with a region of the oxide semiconductor located between the first and second conductors when viewed from a plane. The second insulator includes a second opening that overlaps with the oxide semiconductor and reaches the second conductor. The third insulator has a region in contact with the top surface of the first conductor. The first opening is provided with a region that contacts the top surface of the second conductor, a region that contacts the side surface of the third conductor, a region that contacts the side surface of the fourth conductor, and a region that contacts the side surface of the second insulator. The fourth insulator is provided inside the first opening with a region that contacts the oxide semiconductor, a region that contacts the side surface of the first conductor, and a region that contacts the side surface of the second conductor. The fifth conductor is provided inside the first opening on the fourth insulator and is provided inside the second opening in a manner that overlaps with the second conductor. The sixth conductor is provided inside the second opening on the fifth insulator. In the region that overlaps with the first opening, the shape of the first insulator in plan view is the same as or substantially the same as the shape of the oxide semiconductor in plan view. When viewed in cross-section in the channel width direction of the transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section in the channel width direction of the transistor, the height of the oxide semiconductor is greater than or equal to the width of the oxide semiconductor. When viewed in plan view, there are two or more overlapping regions between the oxide semiconductor and the fifth conductor.

[0035] Additionally, one aspect of the present invention is a semiconductor device comprising a first transistor, a second transistor, a first capacitor, a second capacitor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first transistor comprises an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fifth insulator. The second transistor comprises an oxide semiconductor, a first conductor, a third conductor, a sixth conductor, a seventh conductor, an eighth conductor, and a sixth insulator. The first capacitor comprises an oxide semiconductor, a second conductor, a ninth conductor, and a seventh insulator. The second capacitor comprises an oxide semiconductor, a sixth conductor, a tenth conductor, and an eighth insulator. An insulator is disposed on a substrate, an oxide semiconductor is disposed on the first insulator, and a first conductor, a second conductor, and a sixth conductor are all disposed on the oxide semiconductor. A third conductor is in contact with the top surface of the first conductor, a fourth conductor is in contact with the top surface of the second conductor, and a seventh conductor is in contact with the top surface of the sixth conductor. The distance between the first and second conductors is smaller than the distance between the third and fourth conductors, and the distance between the first and sixth conductors is smaller than the distance between the third and seventh conductors. A second insulator is disposed on the third, fourth, and seventh conductors, and the second insulator includes a first conductor that overlaps with a region of the oxide semiconductor located between the first and second conductors when viewed from a planar perspective. The first insulator has an opening and a second opening that overlaps with the region between the first conductor and the sixth conductor. A second insulator overlaps with the oxide semiconductor and includes a third opening reaching the second conductor. A second insulator overlaps with the oxide semiconductor and includes a fourth opening reaching the sixth conductor. The third insulator is disposed inside the first opening such that it has a region contacting the top surface of the first conductor, a region contacting the top surface of the second conductor, a region contacting the side surface of the third conductor, a region contacting the side surface of the fourth conductor, and a region contacting the side surface of the second insulator. The fourth insulator has a region contacting the top surface of the first conductor, a region contacting the top surface of the sixth conductor, a region contacting the side surface of the third conductor, and a region contacting the side surface of the seventh conductor. A fifth insulator is disposed inside the second opening such that it has a region that contacts the side of the conductor and a region that contacts the side of the first conductor. A sixth insulator is disposed inside the second opening such that it has a region that contacts the oxide semiconductor, a region that contacts the side of the first conductor, and a region that contacts the side of the second conductor. A fifth conductor is disposed on the fifth insulator inside the first opening. An eighth conductor is disposed on the sixth insulator inside the second opening. A seventh insulator is disposed inside the third opening in a manner that overlaps with the second conductor.An eighth insulator is disposed inside the fourth opening, overlapping with the sixth conductor. A ninth conductor is disposed on top of the seventh insulator inside the third opening. A tenth conductor is disposed on top of the eighth insulator inside the fourth opening. In the regions overlapping at least with the first and second openings, the shape of the first insulator, viewed from a planar perspective, is identical or substantially identical to the shape of the oxide semiconductor, viewed from a planar perspective. When viewed in cross-section along the channel width direction of the first transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section along the channel width direction of the second transistor, the bottom surface of the eighth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section along both the channel width directions of the first and second transistors, the height of the oxide semiconductor is greater than or equal to its width. When viewed from a planar perspective, there are at least two regions where the oxide semiconductor overlaps with the fifth conductor and two regions where the oxide semiconductor overlaps with the eighth conductor.

[0036] In addition, in the above-mentioned method, the third insulator may also be less permeable to oxygen compared to the second insulator.

[0037] Alternatively, in the above-described manner, the third insulator may also comprise silicon nitride.

[0038] In addition, in the above-described manner, the first insulator may also contain a metal oxide.

[0039] In addition, in the above-described manner, when viewed from a plane, the regions where the oxide semiconductor and the sixth conductor overlap can be two or more.

[0040] In addition, in the above-mentioned methods, metal oxides can also have the function of capturing or fixing hydrogen.

[0041] In addition, in the above methods, the metal oxide can also be a high-k material.

[0042] In addition, in the above-described manner, the metal oxide may also be an oxide containing one or both of aluminum and hafnium.

[0043] Alternatively, in the above method, the metal oxide can also be hafnium silicate.

[0044] In addition, in the above-described manner, when viewed from a plane, the oxide semiconductor can also appear as a ring with both ends aligned or roughly aligned.

[0045] In addition, in the above-described manner, when viewed from a plane, the side of the first opening may be consistent with or substantially consistent with the side of the third conductor and the side of the fourth conductor.

[0046] Furthermore, in the above-described manner, when viewed in cross-section along the channel width direction of the transistor, the width of the oxide semiconductor can be 5 nm or more and 50 nm or less, and when viewed in cross-section along the channel width direction of the transistor, the height of the oxide semiconductor can be 1.5 times or more and 10 times or less the width of the oxide semiconductor.

[0047] In addition, in the above-described manner, the oxide semiconductor may also contain indium, and the oxide semiconductor may be formed perpendicular or substantially perpendicular to the substrate surface. Furthermore, when observing the cross-section of the oxide semiconductor using a transmission electron microscope, it can be confirmed that bright spots are arranged in layers in a direction perpendicular to the substrate surface.

[0048] In addition, in the above-described manner, the oxide semiconductor may also contain indium, and the oxide semiconductor may be formed perpendicular or substantially perpendicular to the surface of the substrate. The oxide semiconductor may also have a first region, a second region in contact with the first region, and a third region in contact with the second region. When observing the cross-section of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the substrate surface can be identified in each of the first, second, and third regions.

[0049] In addition, in the above-described manner, the second region may also contain zinc, and the second region may also contain a crystal, the c-axis of which may be approximately parallel to the normal direction of the side surface of the oxide semiconductor.

[0050] In addition, in the above method, the indium content in the first region can be higher than that in the second region, and the indium content in the third region can also be higher than that in the second region.

[0051] Invention Effects According to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with small non-uniformity in the electrical characteristics of transistors can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. Furthermore, according to one aspect of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0052] Furthermore, according to one aspect of the present invention, a storage device capable of miniaturization or high integration can be provided. Additionally, according to one aspect of the present invention, a storage device with large storage capacity can be provided. Furthermore, according to one aspect of the present invention, a storage device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a storage device with low power consumption can be provided. According to one aspect of the present invention, a novel storage device can be provided.

[0053] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Furthermore, effects other than those described above can be extracted from the description, drawings, and claims.

[0054] Brief description of the attached figures Figure 1A Figure 1C is a perspective view showing an example of a semiconductor device.

[0055] Figure 2A This is a plan view showing an example of a semiconductor device. Figures 2B to 2D This is a cross-sectional view showing an example of a semiconductor device.

[0056] Figure 3A and Figure 3B This is a cross-sectional view showing an example of a semiconductor device.

[0057] Figures 4A to 4C This is a cross-sectional view showing an example of a semiconductor device.

[0058] Figures 5A to 5C This is a cross-sectional view showing an example of a semiconductor device.

[0059] Figure 6A and Figure 6B This is a plan view showing an example of a portion of a semiconductor device.

[0060] Figures 7A to 7D This is a cross-sectional view illustrating an example of a method for manufacturing an oxide semiconductor.

[0061] Figures 8A to 8D This is a cross-sectional view showing an example of an oxide semiconductor.

[0062] Figure 9A and Figure 9B This is a cross-sectional view showing an example of a semiconductor device.

[0063] Figure 10 This is a cross-sectional view showing an example of a semiconductor device.

[0064] Figure 11A This is a plan view showing an example of a semiconductor device. Figures 11B to 11DThis is a cross-sectional view showing an example of a semiconductor device.

[0065] Figure 12A This is a plan view showing an example of a semiconductor device. Figures 12B to 12D This is a cross-sectional view showing an example of a semiconductor device.

[0066] Figures 13A to 13C This is a perspective view showing an example of a semiconductor device.

[0067] Figure 14A This is a plan view showing an example of a semiconductor device. Figures 14B to 14D This is a cross-sectional view showing an example of a semiconductor device.

[0068] Figure 15A This is a plan view showing an example of a semiconductor device. Figure 15B This is a cross-sectional view showing an example of a semiconductor device.

[0069] Figures 16A to 16C This is a cross-sectional view showing an example of a semiconductor device.

[0070] Figure 17A This is a plan view showing an example of a semiconductor device. Figures 17B to 17D This is a cross-sectional view showing an example of a semiconductor device.

[0071] Figure 18 This is a cross-sectional view showing an example of a semiconductor device.

[0072] Figures 19A to 19D This is a cross-sectional view showing an example of a semiconductor device.

[0073] Figure 20A and Figure 20B This is a perspective view showing an example of a semiconductor device.

[0074] Figure 21A This is a plan view showing an example of a semiconductor device. Figure 21B This is a cross-sectional view showing an example of a semiconductor device.

[0075] Figure 22A and Figure 22B This is a cross-sectional view showing an example of a semiconductor device.

[0076] Figure 23 This is a plan view showing an example of a semiconductor device.

[0077] Figure 24A and Figure 24B This is a cross-sectional view showing an example of a semiconductor device.

[0078] Figure 25AThis is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 25B to 25D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0079] Figure 26A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 26B to 26D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0080] Figure 27A and Figure 27B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0081] Figure 28A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 28B to 28D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0082] Figure 29A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 29B to 29D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0083] Figure 30A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 30B to 30D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0084] Figure 31A and Figure 31B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0085] Figure 32A and Figure 32B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0086] Figure 33A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 33B to 33D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0087] Figure 34A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 34B to 34D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0088] Figure 35A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 35B to 35D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0089] Figure 36A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 36B to 36D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0090] Figure 37A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 37B to 37D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0091] Figure 38A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 38B to 38D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0092] Figure 39A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 39B to 39D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0093] Figure 40A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 40B to 40D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0094] Figure 41A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 41B to 41D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0095] Figure 42 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0096] Figures 43A to 43H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0097] Figure 44A and Figure 44B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0098] Figure 45 This is a block diagram illustrating the CPU.

[0099] Figure 46 This is a block diagram illustrating the CPU.

[0100] Figure 47A and Figure 47B It is a 3D diagram of a semiconductor device.

[0101] Figure 48A and Figure 48B It is a 3D diagram of a semiconductor device.

[0102] Figure 49A and Figure 49B This is a diagram illustrating the hierarchy of memory devices in a semiconductor device.

[0103] Figure 50A and Figure 50B This is a diagram illustrating an example of an electronic device. Figures 50C to 50E This is a diagram illustrating an example of a large computer.

[0104] Figure 51 This is a diagram illustrating an example of a space device.

[0105] Figure 52 This is a diagram illustrating an example of a storage system that can be used in a data center.

[0106] Methods of implementing the invention The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0107] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Additionally, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0108] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0109] Furthermore, especially in plan or perspective drawings, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines are sometimes omitted.

[0110] Note that in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, sometimes the ordinal numbers used for constituent elements in one part of this specification differ from those used for the same constituent element in another part of this specification or in the claims.

[0111] Furthermore, depending on the situation or condition, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be replaced with a "conductive film." Additionally, an "insulating film" can be replaced with an "insulating layer." Furthermore, depending on the situation or condition, a "conductor" can be replaced with a "conductive layer" or a "conductive film." Furthermore, depending on the situation or condition, an "insulator" can be replaced with an "insulating layer" or an "insulating film."

[0112] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes states where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -20 degrees and less than 20 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes states where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 70 degrees and less than 110 degrees.

[0113] In addition, the accompanying drawings used in this embodiment show the case where the sidewall of the insulator in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the surface to which it is formed, but the sidewall may also be tapered.

[0114] In this specification, openings include, for example, slots, slits, etc.

[0115] Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (hereinafter, sometimes referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90°. Note that the side surface of the constituent element and the substrate surface do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0116] Note that in this specification, "height consistent or substantially consistent" refers to a structure that has the same height from a reference surface (e.g., a flat surface such as a substrate surface) when viewed in cross-section. For example, in the manufacturing process of a memory device, sometimes a planarization process (typically CMP) exposes the surfaces of one or more layers. In this case, the surface being processed by CMP has a structure with the same height from the reference surface. Note that depending on the processing apparatus, processing method, or material of the surface being processed during CMP, the heights of multiple layers may differ. In this specification, "height consistent or substantially consistent" also includes the above-mentioned cases. For example, when a layer includes two heights relative to a reference surface (referred to herein as the first layer and the second layer), it can also be said that the height difference between the top surface of the first layer and the top surface of the second layer is less than 20 nm.

[0117] In this specification, "side-end consistency or substantially consistency" means that at least a portion of the edges between stacked layers overlap when viewed from a plane (sometimes referred to as a top view). This includes, for example, cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, sometimes the edges do not overlap, but the edge of the upper layer is located inside the edge of the lower layer or outside the edge of the lower layer; in such cases, it can also be described as "side-end consistency or substantially consistency."

[0118] In this specification, "consistent or substantially consistent shape when viewed from a plane" means that at least a portion of the edges of each layer in a stack overlaps. This includes cases where the upper and lower layers are processed using the same mask pattern or a mask pattern that is partially the same. However, there are actually cases where the edges do not overlap; sometimes the upper layer is positioned inside or outside the lower layer. In these cases, it can also be said that the shape is "consistent or substantially consistent when viewed from a plane." Furthermore, when the shape is consistent or substantially consistent when viewed from a plane, it can also be said that the ends are aligned or substantially aligned, or the side ends are aligned or substantially consistent.

[0119] Note that in this specification, etc., "island" refers to the state in which two or more layers formed in the same process and using the same material are physically separated.

[0120] (Implementation Method 1) In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device are described with reference to the accompanying drawings.

[0121] One aspect of the present invention is a semiconductor device including a transistor comprising a plurality of oxide semiconductors that are fin-shaped when viewed in cross-section along the channel width direction. In this semiconductor device, a gate insulator is disposed to cover the fin-shaped oxide semiconductors, and a gate electrode is disposed on the gate insulator. Thus, the oxide semiconductors and the gate electrode are arranged such that, when viewed in cross-section along the channel width direction of the transistor, they are positioned opposite each other across the top and side surfaces of the oxide semiconductors, separated by the gate insulator. Therefore, by making the oxide semiconductors fin-shaped, the area of ​​overlap between the oxide semiconductors and the gate electrode across the gate insulator can be increased compared to making the oxide semiconductors planar. Consequently, the channel width of the transistor can be increased.

[0122] In another embodiment of the semiconductor device of the present invention, one of the source electrode and drain electrode of the transistor includes a first conductor and a second conductor on the first conductor. The other of the source electrode and drain electrode of the transistor includes a third conductor and a fourth conductor on the third conductor. An interlayer insulating film is disposed on the third conductor and the fourth conductor. The interlayer insulating film has an opening that overlaps with the region of the oxide semiconductor located between the source electrode and the drain electrode when viewed in plan view. The first conductor has a region that protrudes into the opening of the interlayer insulating film compared to the second conductor. The third conductor has a region that protrudes into the opening of the interlayer insulating film compared to the fourth conductor. When viewed in plan view, the side end portion of the second conductor on the opening side and the side end portion of the fourth conductor on the opening side may coincide with or substantially coincide with the sidewall of the opening of the interlayer insulating film.

[0123] A barrier insulator is provided inside the opening, having a region contacting the top surface of the first conductor, a region contacting the side surface of the second conductor, a region contacting the top surface of the third conductor, a region contacting the side surface of the fourth conductor, and a region contacting the side surface of the interlayer insulating film. A portion of the side end of the barrier insulator may coincide with or substantially coincide with the side end of the opening of the first conductor. Furthermore, another portion of the side end of the barrier insulator may coincide with or substantially coincide with the side end of the opening of the third conductor. The barrier insulator is oxygen-resistant.

[0124] Note that in this specification, etc., a barrier insulator refers to an insulator that has barrier properties. In this specification, "barrier property" means having the property of hindering the transmission of the corresponding substance (also called low permeability). For example, a barrier insulator has the property that the corresponding substance does not easily diffuse into the interior of the insulator. For example, a barrier insulator has the function of trapping or fixing (also called gettering) the corresponding substance inside the insulator.

[0125] A gate insulator is disposed inside the opening of the interlayer insulating film, having a region that contacts the oxide semiconductor, a region that contacts the side of the first conductor, and a region that contacts the side of the third conductor. The gate insulator is disposed inside the barrier insulator, having a region disposed on the barrier insulator inside the opening of the interlayer insulating film. Furthermore, a gate electrode is disposed on the gate insulator inside the opening of the interlayer insulating film.

[0126] One of the source and drain electrodes has a region where the first conductor protrudes into the opening of the interlayer insulating film compared to the second conductor, and the other of the source and drain electrodes has a region where the third conductor protrudes into the opening of the interlayer insulating film compared to the fourth conductor. This allows the distance between the source and drain electrodes of the transistor to be smaller than if the first and third conductors did not have the aforementioned protruding regions. This shortens the channel length of the transistor. Consequently, the on-state current of the transistor can be increased. Therefore, a semiconductor device with high operating speed can be provided.

[0127] Furthermore, by providing an oxygen-barrier barrier insulator with regions contacting the sides of the second conductor and the fourth conductor, and by providing a gate insulator inside the barrier insulator, oxidation of the sides of the second and fourth conductors can be suppressed. Therefore, a decrease in the transistor's on-state current or a decrease in its field-effect mobility can be suppressed. Thus, a semiconductor device with excellent electrical characteristics can be provided.

[0128] Furthermore, in one embodiment of the semiconductor device of the present invention, an insulator, whose shape is identical or substantially identical to that of the oxide semiconductor when viewed from a planar perspective, is disposed beneath the oxide semiconductor. Moreover, the thickness of the insulator beneath the oxide semiconductor is made greater than the thickness of the gate insulator. Therefore, when viewed in cross-section along the channel width direction of the transistor, the bottom surface of the gate electrode can be positioned lower than the bottom surface of the oxide semiconductor.

[0129] By positioning the bottom surface of the gate electrode lower than the bottom surface of the oxide semiconductor, a sufficient gate electric field can be applied from the top to the bottom of the oxide semiconductor. In other words, when viewed in cross-section along the channel width direction of the transistor, the electric field of the gate electrode can surround the entire oxide semiconductor, which can then be used as the channel formation region. This improves the electrical characteristics of the transistor. Furthermore, the channel width of the transistor can be increased.

[0130] Insulators under oxide semiconductors preferably have the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the oxide semiconductor. Therefore, defects formed by hydrogen entering oxygen vacancies in the channel formation region (hereinafter sometimes referred to as V0) can be reduced. O H). Therefore, transistors can achieve good electrical characteristics.

[0131] <Example 1 of semiconductor device structure> The following describes a structural example of a semiconductor device according to one aspect of the present invention. Figures 1A to 4C This is a diagram illustrating an example of the structure of a semiconductor device including a transistor 200 on a substrate (not shown).

[0132] Figure 1AThis is a perspective view showing an example of the structure of transistor 200. Figure 1B From Figure 1A A three-dimensional view with some constituent elements removed. Figure 1C is from... Figure 1B The three-dimensional diagrams of some of the constituent elements were also deleted.

[0133] Figure 2A It shows including Figure 1A A plan view illustrating an example structure of the semiconductor device, transistor 200. Additionally, Figures 2B to 3B This is a cross-sectional view of the semiconductor device. Here, Figure 2B , Figure 2C and Figure 2D They are along Figure 2A The cross-sectional views of the dashed lines A1-A2, A3-A4, and A5-A6 in the diagram are also cross-sectional views of the channel width direction of transistor 200. Additionally, Figure 3A and Figure 3B They are along Figure 2A The cross-sectional views of dashed lines B1-B2 and B3-B4 in the diagram are also cross-sectional views along the channel length of transistor 200. Here, dashed line B1-B2 is orthogonal to dashed lines A1-A2, A3-A4, and A5-A6. Similarly, dashed line B3-B4 is orthogonal to dashed lines A1-A2, A3-A4, and A5-A6. Furthermore, dashed lines A1-A2, A3-A4, and A5-A6 are parallel to each other. Moreover, dashed lines B1-B2 and B3-B4 are parallel to each other. Note that in... Figure 1A The perspective view to Figure 1C and Figure 2A In the plan view, some constituent elements have been omitted for clarity. Additionally, in... Figure 2A In the plan view, some constituent elements are shown transparently. Sometimes, some constituent elements are also omitted in subsequent 3D and plan views. Additionally, sometimes, some constituent elements are also shown transparently in subsequent plan views.

[0134] Figure 4A Show Figure 3A A magnified view of the conductor around 260. Figure 4B Show Figure 2B A magnified view of the oxide semiconductor 230. Figure 4C Show Figure 2C A magnified view of the oxide semiconductor 230.

[0135] The semiconductor device according to this embodiment includes an insulator 215 on a substrate (not shown), an insulator 216 on the insulator 215, an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, conductors 242a1 and 242b1 on the oxide semiconductor 230 and the insulator 222, conductors 242a2 on the conductor 242a1, conductors 242b2 on the conductor 242b1, conductors 242a1, conductors 242b1 and the insulator 222, an insulator 255 on the insulator 222, an oxide semiconductor 230, an insulator 255 and an insulator 250 on the insulator 222, and conductors 260 (conductors 260a and 260b) on the insulator 250. Note that in Figure 2A In the diagram, insulator 255 is shaded. Shaded lines are also sometimes added to insulator 255 in later plan views.

[0136] Note that, hereinafter, conductors 242a1 and 242a2 are sometimes collectively referred to as conductor 242a, and conductors 242b1 and 242b2 are also sometimes collectively referred to as conductor 242. Additionally, conductors 242a and 242b are sometimes collectively referred to as conductor 242. Conductor 242a can be said to have a two-layer stacked structure consisting of conductor 242a1 and conductor 242a2 on conductor 242a1. Conductor 242b can be said to have a two-layer stacked structure consisting of conductor 242b1 and conductor 242b2 on conductor 242b1. Conductor 242a2 can be in contact with the top surface of conductor 242a1. Conductor 242b2 can be in contact with the top surface of conductor 242b1.

[0137] Figure 1A The diagram shows the insulator 224, oxide semiconductor 230, conductor 242a1, conductor 242a2, conductor 242b1, conductor 242b2, and conductor 260, which are components included in the semiconductor device according to this embodiment. Figure 1B From Figure 1A Remove conductor 260. In Figure 1C, from Figure 1B Conductors 242a1, 242a2, 242b1, and 242b2 are also removed. Figure 1C shows insulator 224 and oxide semiconductor 230.

[0138] like Figure 4AAs shown, when viewed in cross-section along the channel length of transistor 200, the distance L1 between conductors 242a1 and 242b1 is less than the distance L2 between conductors 242a2 and 242b2. Here, distance L1 refers to the shortest distance between the opposing sides of conductors 242a1 and 242b1. Similarly, distance L2 refers to the shortest distance between the opposing sides of conductors 242a2 and 242b2. By employing this structure, the distance between the source and drain can be further shortened, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a high-speed semiconductor device can be provided.

[0139] As conductors 242a1 and 242b1 in contact with the oxide semiconductor 230, conductive materials that are not easily oxidized or conductive materials that have the function of inhibiting oxygen diffusion are preferably used. This, for example, can prevent the oxidation of conductors 242a1 and 242b1 by oxygen contained in the oxide semiconductor 230, thus preventing a decrease in the conductivity of conductors 242a and 242b. Furthermore, it can prevent the extraction of oxygen from the oxide semiconductor 230, thus preventing the formation of excessive oxygen vacancies. Metal nitrides are examples of conductive materials that are not easily oxidized or conductive materials that have the function of inhibiting oxygen diffusion. Examples of such metal nitrides include tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides. In one aspect of the invention, tantalum nitrides are particularly preferred. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., can be used as conductors 242a1 and 242b1.

[0140] Furthermore, when materials that readily absorb (extract) hydrogen are used as conductors 242a1 and 242b1, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Therefore, defects (V0) formed by hydrogen entering oxygen vacancies in the channel formation region can be reduced. O H).

[0141] When a VoH is formed in the oxide semiconductor 230, electrons are sometimes generated to become charge carriers. Therefore, when a VoH is formed in the channel formation region of the oxide semiconductor 230, the transistor 200 sometimes exhibits always-on characteristics (the characteristic that current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, when the VoH in the channel formation region is reduced, a semiconductor device with good electrical characteristics can be provided, where the channel formation region is i-typed or substantially i-typed.

[0142] The conductivity of conductors 242a2 and 242b2 is preferably higher than that of conductors 242a1 and 242b1. For example, the thickness of conductors 242a2 and 242b2 is preferably greater than that of conductors 242a1 and 242b1. Conductive materials with tungsten, copper, or aluminum as the main components can be used as conductors 242a2 and 242b2, for example. By adopting the above structure, the resistance of conductors 242a2 and 242b2 can be reduced. Therefore, the on-state current of transistor 200 can be increased. Thus, a semiconductor device with high operating speed can be provided.

[0143] For example, tantalum nitride or titanium nitride can be used as conductors 242a1 and 242b1, and tungsten can be used as conductors 242a2 and 242b2.

[0144] Insulator 275 is disposed on conductor 242a2, conductor 242b2, and insulator 222, and insulator 280 is disposed on insulator 275. Insulator 280 is used as an interlayer film. Alternatively, the interlayer film may also include insulator 275.

[0145] Insulators 275 and 280 include an opening 201 that overlaps with the region of oxide semiconductor 230 located between conductors 242a1 and 242b2 when viewed from a planar perspective. Conductors 242a1 and 242b1 are in contact with oxide semiconductor 230. Conductors 242a1 and 242b2 are arranged opposite to each other with respect to the opening 201 when viewed from a planar perspective.

[0146] The opening 201 overlaps with the areas between conductors 242a2 and 242b2. Conductor 242a1 has a region that protrudes from conductor 242a2 toward the opening 201. Conductor 242b1 has a region that protrudes from conductor 242b2 toward the opening 201. When viewed in plan view, the side ends of conductor 242a2 and conductor 242b2 on the opening 201 side may be aligned with or substantially aligned with the sidewall of the opening 201. Therefore, the aforementioned protruding regions of conductor 242a1 and conductor 242b1 can be regions that overlap with the opening 201.

[0147] The insulator 255 is disposed inside the opening 201 in such a manner that it has a region that contacts the top surface of the conductor 242a1, a region that contacts the top surface of the conductor 242b1, a region that contacts the side surface of the conductor 242a2, a region that contacts the side surface of the conductor 242b2, and a region that contacts the side surface of the opening 201 of the insulator 280. A portion of the side end of the insulator 255 may coincide with or substantially coincide with the side end of the conductor 242a1 at the opening 201. Furthermore, another portion of the side end of the insulator 255 may coincide with or substantially coincide with the side end of the conductor 242b1 at the opening 201.

[0148] Insulator 255 is preferably an oxygen-barrier insulator (also known as an oxygen-barrier insulator). Insulator 255 is preferably at least less permeable to oxygen than insulator 280.

[0149] As described above, the insulator 255 is disposed in contact with the sides of the conductors 242a1 and 242b2. Therefore, the insulator 255 functions to protect the conductors 242a2 and 242b2. Preferably, heat treatment is performed in an oxygen-containing atmosphere after the conductors 242a1 and 242b1 are separated and before the insulator 250 is deposited; this will be explained in detail later. At this time, by disposing the insulator 255 in contact with the sides of the conductors 242a2 and 242b2, oxidation of the sides of the conductors 242a2 and 242b2 can be suppressed. Therefore, a decrease in the on-state current or the field-effect mobility of the transistor 200 can be suppressed. Thus, a semiconductor device with excellent electrical characteristics can be provided.

[0150] Examples of oxygen barrier insulators include nitrides, specifically silicon nitride, silicon oxynitride, and aluminum nitride. Other examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, and gallium oxide. Furthermore, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0151] The insulator 255 may also have a laminated structure with two or more layers using the aforementioned materials. In this case, at least one layer is preferably an oxygen-barrier insulator. For example, the layer in contact with conductors 242a2 and 242b2 is preferably an oxygen-barrier insulator. The insulator 255 may have a two-layer structure, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0152] The insulator 250 is disposed inside the opening 201 such that it has a region that contacts the oxide semiconductor 230, a region that contacts the side surface of the conductor 242a1, and a region that contacts the side surface of the conductor 242b1. The insulator 250 is disposed inside the insulator 255 such that it has a region disposed on the insulator 255 inside the opening 201. Furthermore, the insulator 250 may have a region that contacts the side surface of the insulator 255, a region that contacts the top surface of the opening 201 of the insulator 255, a region that contacts the top surface of the insulator 222, and a region that contacts the side surface of the insulator 224.

[0153] The conductor 260 is disposed on the insulator 250 inside the opening 201. Specifically, the conductor 260 is disposed on the insulator 250 such that it is embedded in the opening 201. In addition, an insulator 282 is disposed on both the insulator 280 and the conductor 260. Furthermore, an insulator 283 is disposed on the insulator 282.

[0154] Insulators 275, 280, 282, and 283 include an opening 202a leading to conductor 242a and an opening 202b leading to conductor 242b. Insulator 241a is provided in contact with the sidewall of opening 202a, and conductor 240a is provided in contact with the side surface of insulator 241a. The bottom surface of conductor 240a contacts the top surface of conductor 242a. Similarly, insulator 241b is provided in contact with the sidewall of opening 202b, and conductor 240b is provided in contact with the side surface of insulator 241b. The bottom surface of conductor 240b contacts the top surface of conductor 242b. Hereinafter, conductor 240a and conductor 240b are sometimes collectively referred to as conductor 240. Insulators 241a and insulator 241b are sometimes collectively referred to as insulator 241. Furthermore, openings 202a and 202b are sometimes collectively referred to as opening 202.

[0155] exist Figure 2A In the case of the opening 202, the shape when viewed from a plane is a quadrilateral, but it is not limited to this. For example, the shape of the opening 202 when viewed from a plane can also be a circle, an ellipse or other roughly circular shape, a quadrilateral or other polygonal shape, or a shape in which the corners of the quadrilateral or other polygonal shape are rounded.

[0156] The oxide semiconductor 230 has a region that serves as the channel formation region of the transistor 200. Additionally, the conductor 260 has a region that serves as the first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that serves as the first gate insulator of the transistor 200.

[0157] Conductor 242a has a region that serves as one of the source and drain electrodes of transistor 200. Conductor 240a is used as a connector for connection to conductor 242a. Conductor 242b has a region that serves as the other of the source and drain electrodes of transistor 200. Conductor 240b is used as a connector for connection to conductor 242b.

[0158] The oxide semiconductor 230 is disposed in contact with the top surface of the insulator 224. The shape of the insulator 224 as viewed from a plane (sometimes referred to as the top surface shape) is the same as or substantially the same as the shape of the oxide semiconductor 230 as viewed from a plane. Figure 2A The diagram shows that, when viewed from a plane, both the insulator 224 and the oxide semiconductor 230 appear as hollow quadrilaterals, specifically, as examples of hollow quadrilaterals with rounded corners. Figure 2A In the example shown, the oxide semiconductor 230 has a region parallel to the channel width direction and a region parallel to the channel length direction. Figure 2D An example of a cross-sectional structure of the region of the oxide semiconductor 230 parallel to the channel width direction is shown. Figure 3A An example of a cross-sectional structure of a region parallel to the channel length direction of the oxide semiconductor 230 is shown.

[0159] When viewed from a planar perspective, the oxide semiconductor 230 overlaps with the insulator 224. The bottom surface of the insulator 224 contacts the insulator 222. The side surfaces of the insulator 224 contact the insulator 250, conductors 242a and 242b. The top surface of the insulator 224 contacts the bottom surface of the oxide semiconductor 230. Alternatively, insulators 221 and 222 may be omitted. In this case, the bottom surface of the insulator 224 contacts the insulator 216.

[0160] like Figure 4B and Figure 4C As shown, the oxide semiconductor 230 has a high aspect ratio when viewed in cross-section along the channel width direction of the transistor 200. Therefore, the oxide semiconductor 230 can be described as fin-shaped. Furthermore, the stack including the insulator 224 and the oxide semiconductor 230 on the insulator 224 can also be described as fin-shaped.

[0161] Here, when viewed in cross-section along the channel width direction of transistor 200, the aspect ratio of oxide semiconductor 230 refers to the ratio of the length L3 (also referred to as the width L3) of oxide semiconductor 230 in the A1-A2 direction to the length H (also referred to as the height H) of oxide semiconductor 230 in the direction perpendicular to the formed surface (e.g., insulator 222). When the height H is greater than or equal to the width L3, oxide semiconductor 230 can be described as fin-shaped. That is, when viewed in cross-section along the channel width direction of transistor 200, when the height of oxide semiconductor 230 is greater than or equal to the width of oxide semiconductor 230, oxide semiconductor 230 can be described as fin-shaped. Furthermore, when the height H is less than the width L3, oxide semiconductor 230 can sometimes be described as having a plate shape. Width L3 can be the width of the bottom surface of oxide semiconductor 230.

[0162] Preferably, the aspect ratio of the oxide semiconductor 230 is as large as possible within a range that will not cause the oxide semiconductor 230 to collapse during the manufacturing process of the transistor 200. The height H of the oxide semiconductor 230 can be more than 1 and less than 100 times the width L3 of the oxide semiconductor 230, preferably more than 1 and less than 50 times, more preferably more than 1 and less than 30 times, and even more preferably more than 1.5 and less than 10 times. The width L3 can be, for example, more than 5 nm and less than 100 nm, preferably more than 5 nm and less than 50 nm, and even more preferably more than 10 nm and less than 30 nm. The height H can be, for example, more than 5 nm and less than 2000 nm, preferably more than 7.5 nm and less than 1000 nm, more preferably more than 10 nm and less than 500 nm, and even more preferably more than 15 nm and more than 300 nm. By setting the aspect ratio of the oxide semiconductor 230 to the above range, the insulator 250, conductor 260, conductor 242, and conductor 240 can be provided in a manner that provides high coverage over the oxide semiconductor 230.

[0163] In addition, such as Figure 4B As shown, when viewed in cross-section along the channel width direction of transistor 200, the angle θ formed by the side surface of oxide semiconductor 230 and the top surface of insulator 224 is preferably perpendicular or substantially perpendicular. For example, angle θ is preferably 80° or more and 100° or less, more preferably 85° or more and 95° or less. Alternatively, the angle formed by the side surface of insulator 224 and the top surface of insulator 222 may also be set as angle θ.

[0164] An insulator 250, a conductor 260, and a conductor 242 are provided to cover the high aspect ratio oxide semiconductor 230. For example... Figure 4BAs shown, in transistor 200, an insulator 250 and a portion of a conductor 260 are disposed in a folded state, sandwiching an oxide semiconductor 230. Therefore, when viewed in cross-section along the channel width direction of transistor 200, the oxide semiconductor 230 and the conductor 260 are positioned opposite each other, separated by the insulator 250, on the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. In other words, the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 are all used as channel formation regions. Therefore, compared to the case where the oxide semiconductor 230 is planar, the channel width of transistor 200 is increased by the portion of the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0165] By increasing the channel width as described above, the on-state current, transconductance, and frequency characteristics of the transistor 200 can be improved. This provides a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using this semiconductor device can be increased. In the above structure, by incorporating the oxide semiconductor 230, the channel width can be increased without expanding the occupied area of ​​the transistor 200. This allows for miniaturization or high integration of the semiconductor device. Additionally, the storage capacity of a memory device using this semiconductor device can be increased. Moreover, by adopting the above structure, the relative area of ​​the conductor 260 and the oxide semiconductor 230 is increased, thus allowing for threshold control to keep the transistor 200 in a normally off state.

[0166] In addition, such as Figure 4B and Figure 4C As shown, the top surface of the oxide semiconductor 230 can also have a curved shape. By having this curved shape, defects such as voids can be prevented from forming in the insulator 250 and conductor 242 near the top surface of the oxide semiconductor 230. Note that in Figure 4B and Figure 4C In some cases, a symmetrical structure with a curved shape is adopted on both sides of the top surface of the oxide semiconductor 230, namely the A1 side (A3 side) and the A2 side (A4 side). However, the present invention is not limited to this. For example, sometimes one of the A1 side (A3 side) and the A2 side (A4 side) of the top surface of the oxide semiconductor 230 is provided with a curved asymmetrical structure.

[0167] Since the oxide semiconductor 230 has a high aspect ratio, it is preferably formed as a sidewall on the side of the pillar (insulator 223 described later). Therefore, the oxide semiconductor 230 is preferably formed using an atomic layer deposition (ALD) method with good coverage. In addition, when the oxide semiconductor 230 has a multilayer structure, it is preferable to deposit at least one layer using the ALD method, preferably the layer in contact with the pillar.

[0168] A sidewall-shaped oxide semiconductor 230 is formed by contacting the sides of multiple pillars, such as... Figure 2A As shown, multiple oxide semiconductors 230 can be formed simultaneously. Thus, by forming multiple oxide semiconductors 230, the distance between adjacent oxide semiconductors 230 can be set according to the size and shape of the pillars. Therefore, by reducing the distance between each oxide semiconductor 230 and reducing the area occupied by the transistor 200, high integration of the semiconductor device can be achieved.

[0169] Because the oxide semiconductor 230 is formed as a sidewall in a manner that contacts the pillar, therefore, Figure 2A As shown, the oxide semiconductor 230, when viewed from a planar perspective, has a ring-shaped (or frame-shaped, loop-shaped, donut-shaped, or closed curve-shaped) form with both ends being uniform or substantially uniform. Alternatively, the oxide semiconductor 230 can be described as having a shape with an opening in the center. Note that in Figure 2A In the present invention, the oxide semiconductor 230 has a shape symmetrical about the center line A1-A2 when viewed from a planar perspective, but the invention is not limited to this. For example, the shape of the oxide semiconductor 230 when viewed from a planar perspective can also be asymmetrical. Furthermore, since the shape of the insulator 224 when viewed from a planar perspective is the same as or substantially the same as the shape of the oxide semiconductor 230 when viewed from a planar perspective, and the insulator 224 overlaps with the oxide semiconductor 230, the shape of the insulator 224 when viewed from a planar perspective is also a ring shape with both ends being the same or substantially the same. Additionally, similar to the oxide semiconductor 230, the insulator 224 can also be described as having an opening in its central portion.

[0170] Figure 2A The structure shown is as follows: two pillars are arranged in the A1-A2 direction, forming a ring-shaped oxide semiconductor 230 in contact with the side surfaces of each pillar. For example... Figure 2A As shown, when viewed from a planar perspective, the oxide semiconductor 230 preferably overlaps with the conductor 260 in two or more portions. In other words, a semiconductor device according to one aspect of the present invention has two or more regions where the oxide semiconductor 230 and the conductor 260 overlap. By adopting the above structure, as Figure 2B As shown, a plurality of finned oxide semiconductors 230 are disposed when the transistor 200 is viewed in cross-section along the channel width direction. All of the finned oxide semiconductors 230 serve as channel forming regions. In other words, the transistor 200 is used as a multi-channel transistor. Therefore, the channel width can be further increased in the transistor 200.

[0171] Here, as Figure 4BAs shown, the thickness t2 of the insulator 250 inside the opening 201 is preferably smaller than the thickness t1 of the insulator 224. In other words, the thickness t1 is preferably larger than the thickness t2. By adopting this structure, when viewed in cross-section in the channel width direction of the transistor 200, the bottom surface of the conductor 260 (conductor 260a) disposed inside the opening 201 can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference between the thickness t1 and the thickness t2 (t1-t2).

[0172] By positioning the bottom surface of the conductor 260 lower than the bottom surface of the oxide semiconductor 230, a sufficient gate electric field can be applied from the upper end to the lower end of the oxide semiconductor 230. In other words, when viewed in cross-section along the channel width of the transistor 200, the electric field of the conductor 260 can surround the entire oxide semiconductor 230, which can then be used as the channel formation region. This structure prevents the lower end of the oxide semiconductor 230 from being used as a parasitic channel, thus reducing leakage current between the source and drain electrodes. Furthermore, it suppresses characteristic defects in the transistor caused by this parasitic channel, such as constant-on behavior. In other words, the electrical characteristics of the transistor 200 can be improved.

[0173] Furthermore, as described above, by using the upper to lower ends of the oxide semiconductor 230 as the channel formation region, the channel width can be increased. This, in turn, improves the on-state current, transconductance, and frequency characteristics of the transistor 200.

[0174] When the bottom surface of the conductor 260 is positioned lower than the bottom surface of the oxide semiconductor 230, at least a portion of the insulator 224 can be used as the gate insulator of the transistor 200. For example, the region in the insulator 224 located between the bottom surface of the conductor 260 (conductor 260a) and the oxide semiconductor 230 in cross-section can be used as the gate insulator of the transistor 200.

[0175] Note that in this specification, the transistor structure described above, in which the electric field of the gate electrode forms a region around the channel, is referred to as a surrounded channel (S-channel) structure. In an S-channel structure, the gate electrode is arranged with at least two or more surfaces surrounding the channel (specifically, two, three, or four surfaces, etc.). By employing an S-channel structure, tolerance to short-channel effects can be improved; in other words, transistors that are less prone to short-channel effects can be realized.

[0176] The S-channel structure is a structure in which electricity forms a region around the channel, so it can be said that this structure is substantially the same as the GAA (Gate All Around) structure or the LGAA (Lateral Gate All Around) structure. By giving the transistor 200 an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be considered as the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, and thus an increase in the transistor's on-state current or field-effect mobility can be expected. Furthermore, in one embodiment of the invention, the oxide semiconductor 230 has a CAAC structure and a fin structure. The CAAC structure is formed with its ab plane parallel to or substantially parallel to the channel length direction. By employing this structure, the current path flowing from one of the source and drain of the transistor through the other can potentially be parallel to the ab plane of the CAAC structure. In other words, an oxide semiconductor with a CAAC structure and a fin structure has a conduction path equivalent to that of a two-dimensional semiconductor material. By using this oxide semiconductor as the semiconductor layer of a transistor, devices with two-dimensional conductivity can be fabricated.

[0177] Insulator 224 preferably has the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of oxide semiconductor 230. Therefore, defects (V0) formed by hydrogen entering oxygen vacancies in the channel formation region can be reduced. O H). Therefore, a semiconductor device with good electrical properties can be provided.

[0178] Metal oxides with amorphous structures can be cited as insulators capable of trapping or fixing hydrogen. For example, magnesium oxide or oxides containing one or both of aluminum and hafnium are preferred as insulators 224. These metal oxides with amorphous structures sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. In other words, metal oxides with amorphous structures have a high ability to trap or fix hydrogen.

[0179] Furthermore, the insulator 224 is preferably made of a high-k material. An example of a high-k material is an oxide comprising one or both of aluminum and hafnium. By using a high-k material as the insulator 224, it is easy to use the insulator 224 as a gate insulator. Therefore, the entire oxide semiconductor 230, including the bottom surface and its vicinity, can be used as the channel formation region. This increases the current density flowing through the transistor 200, thus improving the on-state current or field-effect mobility of the transistor 200. Additionally, improvements in the electrical characteristics of the transistor 200 are expected.

[0180] Note that in this specification, high-k materials refer to materials with a higher relative permittivity than silicon oxide.

[0181] As the insulator 224, an oxide containing one or both of aluminum and hafnium is preferred, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferred. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). Hafnium silicate is preferred as an example of insulator 224.

[0182] Note that materials with a low relative permittivity can also be used as insulator 224. Examples of materials that can be used as insulator 224 include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, or resin. By using a material with a low relative permittivity as insulator 224, parasitic capacitance generated between wirings (not shown) can be reduced. Silicon nitride and silicon oxynitride have high hydrogen barrier properties, so when used as insulator 224, they can provide a semiconductor device with good electrical characteristics, and are therefore preferred.

[0183] Figure 5A , Figure 5B and Figure 5C These are respectively showing from Figure 2B , Figure 2C and Figure 3A A cross-sectional view of an example where insulators 221 and 222 are removed and insulator 225 is provided below insulator 224. Figure 5A , Figure 5B and Figure 5C They are Figure 2B , Figure 2C and Figure 3A The enlarged view of the area near insulator 224 is shown in the image.

[0184] The shape of insulator 225 when viewed from a planar perspective is the same as or substantially the same as the shape of insulator 224 when viewed from a planar perspective. As described above, the shape of insulator 224 when viewed from a planar perspective is the same as or substantially the same as the shape of oxide semiconductor 230 when viewed from a planar perspective. Thus, the shape of insulator 225 when viewed from a planar perspective is the same as or substantially the same as the shape of oxide semiconductor 230 when viewed from a planar perspective. When viewed from a planar perspective, insulator 225 overlaps with insulator 224 and oxide semiconductor 230. The bottom surface of insulator 225 contacts insulator 216, the side surface of insulator 225 contacts insulator 250, conductor 242a and conductor 242b, and the top surface of insulator 225 contacts the bottom surface of insulator 224. Note that insulator 225 and insulator 224 can also be considered as a single insulator in a stacked structure. Alternatively, at least one of insulators 221 and 222 may be provided between insulator 216 and insulators 225, 250, 275 and conductor 242.

[0185] The insulator 225 preferably comprises an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. Examples of materials that can be used as the insulator 225 include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon oxynitride. Silicon nitride, which has particularly high hydrogen barrier properties, is preferably used as the insulator 225.

[0186] Furthermore, while the above description describes a structure with two annular oxide semiconductors 230, the present invention is not limited thereto. For example, one or more annular oxide semiconductors 230 may be provided. Additionally, an oxide semiconductor 230 with a shape including multiple openings may be formed by combining the annular oxide semiconductors 230. For example, as... Figure 6A As shown, an oxide semiconductor 230 can also be formed with three openings arranged in the A1-A2 direction when viewed from a planar perspective. In this case, three pillars are formed adjacent to each other at short distances, and the oxide semiconductor 230 is formed between these pillars. Alternatively, for example, as... Figure 6B As shown, an oxide semiconductor 230 that appears as a lattice when viewed from a planar perspective can also be formed. In this case, a lattice-shaped trench is formed in the pillar, and the oxide semiconductor 230 is formed by embedding the trench. Note that the oxide semiconductor 230 is not limited to two; one or more may be provided. Thus, the oxide semiconductor 230 preferably has multiple portions extending in the channel width direction (A1-A2 direction) and multiple portions extending in the channel length direction (B1-B2 direction). This can suppress the oxide semiconductor 230 from collapsing during the transistor manufacturing process when the oxide semiconductor 230 has a high aspect ratio structure. Note that in Figure 6A and Figure 6BInsulator 255 is not shown in the diagram.

[0187] [Oxide semiconductor layer] Here, an oxide semiconductor layer that can be used in oxide semiconductor 230 is described. This oxide semiconductor layer contains metal oxide.

[0188] Furthermore, it is preferable to minimize the amount of hydrogen in the oxide semiconductor layer. Hydrogen in the oxide semiconductor layer and oxygen vacancies (V0) contained in the oxide semiconductor are... O ) bond to form hydrogen that enters V O Defects (V) O Therefore, transistor characteristics (e.g., the initial Id-Vg characteristic of the transistor or the Id-Vg characteristic in long-term reliability testing) may be degraded. Thus, materials with low hydrogen release are preferably used as the material surrounding the oxide semiconductor layer, such as the material used for the insulator in contact with the oxide semiconductor layer. Examples of materials with low hydrogen release include silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide. This suppresses hydrogen incorporation into the oxide semiconductor layer. In particular, by using silicon nitride for at least one of the insulators in contact with the oxide semiconductor layer, transistor reliability can be improved. Furthermore, materials with low hydrogen release sometimes have the function of trapping or fixing (also known as gettering) hydrogen inside the insulator.

[0189] When metal oxides are used as the semiconductor layer of a transistor, lattice defects in the metal oxide can lead to carrier generation or trapping. Therefore, when a metal oxide with many lattice defects is used as the semiconductor layer of a transistor, the transistor's electrical characteristics may be unstable. Thus, it is preferable to use metal oxides with few lattice defects in the semiconductor layer of a transistor. Lattice defects refer to point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.

[0190] By using crystalline metal oxides in oxide semiconductor layers, the defect state density in the oxide semiconductor layer can be reduced. Examples of crystalline metal oxide structures include CAAC (c-axisaligned crystal) structures, polycrystalline structures, and nanocrystalline structures.

[0191] In one embodiment of the present invention, the oxide semiconductor layer comprises a metal oxide having multiple microcrystals. Furthermore, no distinct grain boundaries are observed between the multiple microcrystals. Preferably, the oxide semiconductor layer of one embodiment of the present invention comprises a metal oxide having multiple oriented microcrystals, and when viewed from the orientation direction, has a crystal structure in which the multiple microcrystals are connected in a state without distinct grain boundaries.

[0192] One embodiment of the oxide semiconductor layer of the present invention comprises a metal oxide, the crystal structure of which differs from both single-crystal and polycrystalline structures. Particularly preferred embodiments of the oxide semiconductor layer of the present invention comprise a metal oxide having a CAAC structure.

[0193] A CAAC structure refers to a crystal structure in which multiple microcrystals (typically, multiple microcrystals with a hexagonal crystal system) have a c-axis orientation and are connected on the ab plane without defined grain boundaries. When a cross-section of an oxide semiconductor layer with a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that an oxide semiconductor layer with a CAAC structure has layered crystalline regions. In the cross-section of the oxide semiconductor layer observed using TEM images, the layered metal atoms are observed as bright spots. These bright spots are, for example, arranged in a direction parallel to the plane where the oxide semiconductor layer is formed.

[0194] Additionally, the following structure is sometimes referred to as a CAAC structure: in each of a plurality of crystallites, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface being formed, and the layers containing the metal atoms are stacked in a direction perpendicular or substantially perpendicular to the surface being formed. When a crystallite has the above structure, its crystal structure is not limited to the hexagonal crystal system. For example, a portion of a plurality of crystallites may also have a crystal structure other than the hexagonal crystal system (e.g., a cubic crystal structure).

[0195] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface being formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface being formed. In the region having the CAAC structure, the angle of the c-axis relative to the surface being formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), even more preferably within 90° ± 10° (80° or more and 110° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0196] Polycrystalline structures possess grain boundaries. Furthermore, when heat treatment is performed after forming a polycrystalline oxide semiconductor layer, tiny gaps (also called nanocracks or microcracks) or tiny spaces (also called nanospaces or microspaces) may form between the crystalline portions. When tiny gaps or tiny spaces are formed within the oxide semiconductor layer, the resistance of the oxide semiconductor layer increases. This is because the resistance of tiny gaps or tiny spaces is extremely high, for example, infinite. When an oxide semiconductor layer with tiny gaps or tiny spaces is used in the channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source and drain electrodes increases. Therefore, this adversely affects the initial characteristics or reliability of the transistor. On the other hand, no distinct grain boundaries are observed on the ab surface of a CAAC structure, thus enabling highly reliable semiconductor devices. Additionally, due to fewer grain boundaries, the potential barrier for carrier conduction in the transistor channel is smaller, and an increase in on-state current can be expected. Furthermore, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby enabling transistors suitable for high-speed driving.

[0197] The channel formation region of a transistor preferably uses a metal oxide that increases the transistor's on-state current. For example, the on-state current of the transistor can be increased by improving the mobility of the metal oxide used in the transistor. To improve the mobility of the metal oxide, it is necessary to increase the transport of charge carriers (electrons in an n-channel transistor) or reduce the scattering factor that facilitates charge carrier transport. Furthermore, charge carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region where charge carriers can easily flow along the channel length, the on-state current of the transistor can be increased.

[0198] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, it can be analyzed by combining several of the above methods.

[0199] When an oxide semiconductor layer with a CAAC structure is subjected to electron diffraction, spots (bright spots) representing the c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in the direction parallel to the normal vector of the formed surface of the oxide semiconductor layer or the normal vector of the surface of the oxide semiconductor layer.

[0200] In addition, the FFT pattern obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction pattern.

[0201] By obtaining a cross-sectional TEM image of an oxide semiconductor layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to create an FFT image, the crystal axis orientation of each region can be calculated from the created FFT image. Specifically, in the spots observed in the created FFT image, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center is the crystal axis orientation. Regions whose angle relative to the formed surface, calculated from the FFT pattern, is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), even more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0202] When an oxide semiconductor layer with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements with crystallinity are observed on the ab surface. Furthermore, in Voronoi diagrams created through image analysis of TEM images of the oxide semiconductor layer with a CAAC structure observed from a direction perpendicular to the formed surface, pentagonal, hexagonal, and heptagonal Voronoi regions are predominantly observed, with hexagonal Voronoi regions being particularly prominent. For example, the proportion of hexagonal Voronoi regions observed in Voronoi diagrams is more than 30% but less than 100%.

[0203] This section explains how to create a Voronoi diagram. First, when analyzing a TEM image, after performing FFT processing, filtering is applied to retain only a certain range of information. An inverse Fast Fourier Transform (IFFT) is then performed to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are constructed. The point where the three perpendicular bisectors intersect is designated as a Voronoi point, and the polygonal region enclosed by the line segments connecting the Voronoi points is designated as the Voronoi region. Through these steps, a Voronoi diagram can be created.

[0204] Note that, as an example of the observation range of the TEM in the fabrication of the Voronoi diagram, a rectangular region with a vertical side length of 50 nm and a horizontal side length of 50 nm is observed. Note that the observation range is not limited to this.

[0205] Furthermore, when analyzing the orientation distribution of the hexagonal lattice using lattice points extracted through image analysis of planar TEM images, the following was observed: the difference in orientation between the hexagonal lattice at the boundary of two structures with different orientations is small, the boundary is blurred, and the two structures are intertwined and connected. In other words, no clear boundary is observed in the CAAC structure.

[0206] Note that the orientation of a hexagonal lattice can be calculated from the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0207] Note that there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. The oxide semiconductor layer sometimes includes one or more of the following: amorphous semiconductor (a semiconductor with an amorphous structure), single-crystal semiconductor (a semiconductor with a single-crystal structure), and semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in a portion thereof). When the oxide semiconductor layer is crystallinous, it can sometimes suppress the degradation of transistor characteristics.

[0208] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide may contain indium as a main component, and may also contain element M. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more elements selected from indium, gallium, and zinc. Note that in this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and sometimes the "metallic elements" described in this specification and the like include half-metallic elements.

[0209] The main component of a metal oxide refers to a metal element that accounts for, for example, 0.1 atomic% or more or 1 atomic% or more of the proportion of all metal elements contained in the metal oxide.

[0210] In cross-sections of oxide semiconductor layers observed using TEM images, it was confirmed that metal atoms were arranged in layers parallel to or substantially parallel to the formed surface. In the TEM images, the metal atoms were observed as bright spots. For example, in metal oxides containing indium, a layered arrangement of indium was confirmed. Furthermore, for example, in metal oxides containing indium and zinc, a layered arrangement of indium and zinc was confirmed.

[0211] As one embodiment of the metal oxide according to the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. Alternatively, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon. Additionally, indium oxide can be used as the metal oxide in one aspect of the invention. Furthermore, gallium oxide, zinc oxide, etc., can be used as the metal oxide in one aspect of the invention.

[0212] When the ratio of the number of indium atoms to the total number of atoms of all metal elements in a metal oxide is increased, transistors can achieve large on-state current and high frequency characteristics.

[0213] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystallizable, thereby suppressing the diffusion of impurities within the metal oxide. This suppresses variations in the electrical characteristics of the transistor, thus improving reliability.

[0214] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state current. Additionally, fluctuations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0215] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can contain one or more metals with high period numbers in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers include those belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0216] In addition, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0217] [Manufacturing method of oxide semiconductor layer] In one aspect of the present invention, the oxide semiconductor layer can be fabricated by forming a metal oxide using two deposition methods.

[0218] In manufacturing the oxide semiconductor layer according to one aspect of the present invention, a metal oxide having a CAAC structure is deposited. At this time, by using sputtering as the deposition method, a highly crystalline metal oxide can be formed. Alternatively, deposition methods such as pulsed laser deposition (PLD) can also be used.

[0219] Here, when forming a metal oxide using the aforementioned deposition method (hereinafter, the first deposition method), a mixed layer sometimes forms at the interface between the metal oxide and the surface to be formed. This mixed layer may hinder the crystallization of the metal oxide. By pre-forming a first layer of a metal oxide using a deposition method (hereinafter, the second deposition method) that causes less damage compared to sputtering, PLD, or similar methods as described in the first deposition method, and then setting a second layer of a metal oxide using the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface to be formed can be suppressed. Furthermore, impurities contained in the surface to be formed can be suppressed from entering the second layer. This further improves the crystallinity of the second layer.

[0220] Compared to sputtering, ALD and Chemical Vapor Deposition (CVD) methods can suppress damage to the surface being formed, making them suitable as secondary deposition methods. Other examples of secondary deposition methods include Molecular Beam Epitaxy (MBE) and wet deposition. Examples of CVD methods include Plasma Enhanced CVD (PECVD), Thermal CVD, Photochemical CVD, and Metal-Organic CVD (MOCVD). MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate, and it can be considered one of the deposition methods that causes minimal damage to the surface being formed. Wet deposition methods are also among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spraying.

[0221] Alternatively, a third layer can be formed on top of the second layer. The third layer can be formed, for example, using a second deposition method.

[0222] After depositing the oxide semiconductor layer, heat treatment is preferably performed.

[0223] In one embodiment of the oxide semiconductor layer deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (first and third layers) can be improved by using a highly crystalline second layer (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor layer. In other words, by using the second layer as a nucleus or seed, metal oxides are grown in the upper and lower oxide semiconductor layers in a solid phase, thereby forming a highly crystalline oxide semiconductor layer. The oxide semiconductor layer formed using this deposition method, specifically, an oxide semiconductor layer with a CAAC structure, can be referred to as an axially grown CAAC (AG CAAC).

[0224] Even if the deposition method for the first and third layers does not use a method that easily forms highly crystalline metal oxides, the crystallinity of the first and third layers can be improved by using the oxide semiconductor layer deposition method of one aspect of the present invention. Furthermore, heat treatment plays an auxiliary role in improving the crystallinity of the first and third layers.

[0225] The following is for reference Figures 7A to 7D An example illustrating a method for manufacturing oxide semiconductor 30. Oxide semiconductor 30 can, for example, be used as oxide semiconductor 230.

[0226] First, layer 29 is formed. Layer 29 corresponds to the insulating or conductive film included in the semiconductor device. For example, insulating films such as silicon oxide film, silicon oxynitride film, silicon nitride film, silicon oxynitride film, aluminum oxide film, and hafnium oxide film can be used as layer 29. Alternatively, conductive films used as electrodes in the semiconductor device can also be used as layer 29. Layer 29 may also be amorphous. In other words, layer 29 may have an amorphous structure. Furthermore, if layer 29 is crystalline, it may have a crystal structure with low lattice matching to the metal oxide included in the oxide semiconductor 30.

[0227] Next, an oxide semiconductor 30a is formed on layer 29. Figure 7A ).

[0228] As described later, in one aspect of the manufacturing method of the present invention, an oxide semiconductor 30b is formed using a sputtering method. When depositing a metal oxide film using a sputtering method, sometimes a mixed layer (also called alloying) is formed due to sputtering particles released from a target or the energy applied to the substrate side by sputtering particles. This mixture of components of the deposited metal oxide and components contained in the layer on the formed surface can be formed. Due to alloying, the crystallization of the oxide semiconductor layer on top may be hindered. Furthermore, when alloying occurs, it is difficult to improve the crystallinity of the alloyed region even during the heat treatment described later. Additionally, there is a concern that using an oxide semiconductor layer with alloyed regions in a transistor can negatively impact the initial characteristics or reliability of the transistor.

[0229] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is pre-formed using a deposition method that minimizes damage to the surface to be formed. This suppresses the alloying of the components contained in the oxide semiconductor 30 with those contained in layer 29, and reduces the thickness of the alloyed region or thins it to an unobservable level. Here, the oxide semiconductor 30a is formed using the ALD method.

[0230] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0231] Unlike deposition methods that use particles released from a target, ALD (Alternating Discharge) deposition is a deposition method where a film is formed due to a reaction on the surface of the workpiece. ALD allows for atomic deposition layer by layer, resulting in advantages such as: extremely thin deposition layers; the ability to deposit on structures with high aspect ratios or surfaces with large steps; deposition with fewer defects such as pinholes; high coverage; and the ability to deposit at low temperatures. By using ALD to form oxide semiconductors 30a and 30c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can effectively cover high aspect ratio steps, openings, and the like.

[0232] Furthermore, in the PEALD method, deposition can be performed at lower temperatures by utilizing plasma, making it sometimes preferred. The precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, films formed using the ALD method sometimes contain more carbon or chlorine than films formed using other deposition methods.

[0233] Here, we will describe the method for forming In-M-Zn oxide as an oxide semiconductor 30a using the ALD method.

[0234] First, a source gas containing an indium precursor is introduced into the processing chamber, causing the precursor to adsorb onto the surface of layer 29. Next, an oxidant is introduced into the processing chamber as a reactant, causing the oxidant to react with the adsorbed precursor. While the indium is adsorbed onto the substrate, components other than indium are desorbed, thereby forming a layer formed by indium and oxygen bonding.

[0235] Next, a source gas containing a precursor of element M is introduced into the processing chamber, causing it to adsorb onto the indium-oxygen bonded layer. Then, an oxidant is introduced into the processing chamber as a reactant, causing it to react with the adsorbed precursor. While element M is adsorbed onto the substrate, components other than element M are desorbed, thereby forming the layer of element M bonded to oxygen.

[0236] Next, a source gas containing a zinc precursor is introduced into the processing chamber, causing it to adsorb onto the layer bonded to element M and oxygen. Then, an oxidant is introduced into the processing chamber as a reactant, reacting with the adsorbed precursor to desorb components other than zinc while zinc is adsorbed onto the substrate, thereby forming a zinc-oxygen bonded layer.

[0237] By repeating the above method, In-M-Zn oxide can be formed on layer 29 as oxide semiconductor 30a using the ALD method.

[0238] The substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor. Here, in the thermal ALD process where triethylin is used as the precursor containing indium, triethylgallium is used as the precursor containing gallium, and diethylzinc is used as the precursor containing zinc, for example, the substrate heating temperature is 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0239] In the above embodiments, preferably, after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, the treatment chamber is purged, and then the remaining precursor and reaction products are discharged from the treatment chamber. Alternatively, preferably, after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, the treatment chamber is purged, and then the remaining reactants and reaction products are discharged from the treatment chamber.

[0240] Furthermore, in this specification and other descriptions, unless otherwise specified, when ozone, oxygen, and water are used as reactants or oxidants, they also include plasma states, free radical states, and ionic states, and are not limited to gaseous states or molecular states.

[0241] In addition, when forming oxide semiconductor 30a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures that have lower crystallinity than the CAAC structure are formed.

[0242] Next, an In-M-Zn oxide is formed on the oxide semiconductor 30a as the oxide semiconductor 30b by sputtering. Figure 7B The oxide semiconductor 30b preferably employs a composition suitable for forming a CAAC structure.

[0243] Here, when the oxide semiconductor 30b is formed using a sputtering method, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. Furthermore, due to sputtering particles during the formation of the oxide semiconductor 30b, or energy applied to the substrate side by sputtering particles, small crystalline regions may sometimes form in the mixed layer 31. In subsequent heat treatment processes, at least a portion of the oxide semiconductor 30a may crystallize using the mixed layer 31 or the small crystalline regions formed in the mixed layer 31 as nuclei.

[0244] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. DC sputtering is suitable for depositing conductive metal films and offers a high deposition rate, thus improving productivity. Pulsed DC sputtering is suitable for depositing both conductive metal films and semiconductor films. Furthermore, RF sputtering is suitable for depositing insulating films. Compounds such as oxides, nitrides, and carbides can be deposited using reactive sputtering with reactive gases. In one embodiment of the present invention, the deposition of the metal oxide in the oxide semiconductor layer can be appropriately selected from these methods based on factors such as the conductivity of the sputtering target.

[0245] In-M-Zn oxides can be used as the target material for sputtering. When forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen in the sputtering gas, excess oxygen in the deposited oxide film can be increased.

[0246] In addition, sometimes the higher the oxygen flow rate ratio relative to the overall deposit gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline metal oxides can be formed.

[0247] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess oxide semiconductor layers in the channel formation region can achieve higher reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0248] When metal oxides are formed using sputtering, the composition of the formed metal oxide sometimes differs from that of the sputtering target. In particular, the zinc content of the formed metal oxide can sometimes be reduced to about 50% of the zinc content in the sputtering target.

[0249] When depositing oxide semiconductor 30b using sputtering, it is preferable to heat the substrate. When forming metal oxides, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form highly crystalline metal oxides. When depositing oxide semiconductor 30b using sputtering, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0250] Here, we describe a model for the formation of a CAAC structure using sputtering. First, during sputtering deposition, crystallites are formed. These crystallites are sometimes formed by energy applied to one side of the substrate by sputtering particles (sometimes called atomic particles) or gas particles. Alternatively, planar or granular sputtering particles (sometimes called nanoclusters) deposited on the surface to be formed, detached from the sputtering target, sometimes form these crystallites. Next, sputtering particles adhere to the ends of the crystallites, and the crystallites grow in the lateral direction (roughly parallel to the surface to be formed). As the crystallites grow in the lateral direction, adjacent crystallites connect to each other, and the ends of the crystallites disappear. When the ends of the crystallites disappear, sputtering particles adhere to the crystallites, and the crystallites grow in the longitudinal direction (roughly perpendicular to the surface to be formed). Sputtering particles adhere to the ends of the crystallites growing in the longitudinal direction, and the crystallites grow in the lateral direction. Thus, the crystallites repeatedly grow in the lateral and longitudinal directions, thereby forming a CAAC structure. In other words, a CAAC structure is formed by growing microcrystals in an oxide semiconductor using microcrystals as nuclei or seeds.

[0251] Furthermore, oxide semiconductors containing impurities such as silicon, carbon, and water are not easily able to form CAAC structures. Therefore, the oxide semiconductor 30b is preferably formed using a deposition method that minimizes the incorporation of these impurities. By using a sputtering target with reduced impurity concentration and a deposition gas with reduced impurity content, an oxide semiconductor with low impurity concentration can be formed, making sputtering a suitable method for forming the oxide semiconductor 30b.

[0252] Next, oxide semiconductor 30c is formed on oxide semiconductor 30b. Figure 7C Here, the oxide semiconductor 30c is formed using the ALD method. For details on the formation of the oxide semiconductor 30c using the ALD method, please refer to the formation method of the oxide semiconductor 30a.

[0253] When an oxide semiconductor 30c with lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b using the ALD method, the oxide semiconductor 30c is sometimes epitaxially grown using the oxide semiconductor 30b as a core. Therefore, when the oxide semiconductor 30c is formed, it sometimes includes a region with a CAAC structure. Furthermore, this region with the CAAC structure is preferably formed throughout the oxide semiconductor 30c.

[0254] Oxide semiconductor 30c can be used, for example, as a layer in contact with the gate insulator of a transistor. By increasing the crystallinity of the layer in contact with the gate insulator, the carrier mobility can be improved when the transistor is in the on state.

[0255] In addition, by using the ALD method to form oxide semiconductor 30c, damage to oxide semiconductor 30b is reduced, thereby enabling oxide semiconductor 30 to have high crystallinity as a whole.

[0256] By using the high-coverage ALD method as the deposition method for oxide semiconductors 30a and 30c, the oxide semiconductor layer can achieve overall coverage. Furthermore, by forming a highly crystalline oxide semiconductor 30b using sputtering, and through epitaxial growth from this layer, the crystallinity of the upper and lower oxide semiconductor layers (oxide semiconductors 30a and 30c) is also improved, thereby enhancing the overall crystallinity of the oxide semiconductor 30 layer. Thus, the oxide semiconductor 30 can possess both high coverage and high crystallinity.

[0257] Next, a heat treatment process can be carried out.

[0258] The heat treatment temperature is, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, the heat treatment temperature is set to 400°C ± 25°C (375°C or higher and 425°C or lower). Furthermore, the treatment time is, for example, 10 hours or less, 1 minute or more and 5 hours or less, or 1 minute or more and 2 hours or less. Additionally, when using an RTA (Rapid Thermal Annealing) apparatus, the treatment time is set to, for example, 1 second or more and 5 minutes or less. Through this heat treatment, it is expected that the gaps in the atomic-level crystalline portions of the CAAC structure of the oxide semiconductor 30b will be repaired by the oxide semiconductor 30c (in other words, the individual crystal molecules formed using the ALD method).

[0259] There are no particular restrictions on the heating devices used for heat treatment; devices that utilize heat conduction or thermal radiation generated by heating elements such as resistance heating elements can also be used to heat the workpiece. For example, electric furnaces or RTA devices such as LRTA (Lamp Rapid Thermal Anneal) devices and GRTA (Gas Rapid Thermal Anneal) devices can be used. LRTA devices use the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps to heat the workpiece. GRTA devices use high-temperature gases for heat treatment.

[0260] This heat treatment process sometimes improves the crystallinity of the region with the CAAC structure in the oxide semiconductor 30c. Additionally, after deposition using the ALD method, when this region is only formed below the oxide semiconductor 30c, this heat treatment process sometimes causes the region to extend upwards. Figure 7D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the oxide semiconductor 30c.

[0261] In addition, through this heat treatment process, the oxide semiconductor 30b is sometimes further repaired by the oxide semiconductor 30c (in other words, each crystal molecule formed using the ALD method) that fills the gaps in the atomic-level crystal portion of the CAAC structure of the oxide semiconductor 30b.

[0262] Furthermore, it is preferable that at least a portion of the oxide semiconductor 30a undergoes CAAC treatment during this heat treatment process. Figure 7D It is expected that CAAC formation can easily occur using the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b as a core or seed. The CAAC formation region in the oxide semiconductor 30a is preferably large, and preferably extends to the vicinity of layer 29.

[0263] Furthermore, since CAAC formation occurs from the top to the bottom of the oxide semiconductor 30a, it is not limited by the material or crystallinity of layer 29, and the vicinity of layer 29 can also be CAAC-formed. For example, even if layer 29 has an amorphous structure, a highly crystalline oxide semiconductor 30a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0264] Alternatively, microwave plasma treatment can be performed after the oxide semiconductor 30c is formed.

[0265] In this specification and the like, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0266] Microwave plasma treatment in an oxygen-containing atmosphere is preferably performed to reduce the impurity concentration in the oxide semiconductor 30. Hydrogen and carbon are particularly suitable impurities. Note that the above describes a structure in which the metal oxide is subjected to microwave plasma treatment in an oxygen-containing atmosphere, but the process is not limited to this. For example, an insulating film disposed near the metal oxide, more specifically, a silicon oxide film, can also be subjected to microwave plasma treatment in an oxygen-containing atmosphere. Furthermore, the crystallinity of the oxide semiconductor layer is sometimes improved due to the heat generated during microwave plasma treatment.

[0267] Microwave plasma treatment is preferably performed under reduced pressure, preferably between 10 Pa and 1000 Pa, more preferably between 300 Pa and 700 Pa. Microwave plasma treatment is preferably performed while the substrate is heated. The substrate temperature is preferably between room temperature (e.g., 25°C) and 500°C, more preferably between 100°C and 500°C, further preferably between 200°C and 500°C, even more preferably between 300°C and 500°C, and still more preferably between 400°C and 500°C. For example, it can be set to between 400°C and 450°C.

[0268] Alternatively, heating treatment can be performed continuously after microwave plasma treatment without exposure to external air. The heating temperature is preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0269] For example, microwave plasma treatment can be performed using oxygen and argon gases. By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, allowing this oxygen plasma to act on the oxide semiconductor layer. Through the action of plasma, microwaves, etc., defects (V0) formed by hydrogen entering oxygen vacancies in the oxide semiconductor layer can be removed. O H) is separated into oxygen vacancies and hydrogen, while hydrogen, which is an impurity, is removed from the oxide semiconductor layer. In this way, V in the oxide semiconductor layer can be reduced. O H. At this time, carbon bonded to oxygen or hydrogen can sometimes be removed. Thus, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. In addition, by supplying oxygen free radicals generated in the aforementioned oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0270] Oxygen implanted into the oxide semiconductor layer can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O free radicals, which are atoms, molecules, or ions containing unpaired electrons). The oxygen implanted into the oxide semiconductor layer can be any one or more of the above forms, with oxygen free radicals being particularly preferred.

[0271] The above steps can reduce impurities in the oxide semiconductor layer. By performing crystal growth with a reduced impurity concentration in the oxide semiconductor layer, crystallinity can be further improved.

[0272] In addition, either or both of the above-mentioned heat treatment and microwave plasma treatment can be performed directly on the oxide semiconductor layer, or after forming an insulating film on the oxide semiconductor layer.

[0273] Furthermore, compared to oxide semiconductor layers with CAAC structures formed using one deposition method, oxide semiconductor layers with CAAC structures formed using the two deposition methods described above sometimes have higher relative permittivity, film density, and film hardness, among one or more of these.

[0274] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0275] In oxide semiconductor 30, the region having CAAC structure is preferably present extensively throughout the layer including oxide semiconductor 30a and oxide semiconductor 30c. Figure 8A The diagram shows the crystallized state of oxide semiconductors 30a, 30b, and 30c. The crystals of the CAAC-structured regions in oxide semiconductor 30a are connected to the crystals of the CAAC-structured regions in oxide semiconductor 30b. Similarly, the crystals of the CAAC-structured regions in oxide semiconductor 30c are connected to the crystals of the CAAC-structured regions in oxide semiconductor 30b. Sometimes, oxide semiconductor 30 can be described as a layer without a clearly observed interface. Sometimes, oxide semiconductor 30 can be described as a single layer.

[0276] In oxide semiconductors 30a, 30b, and 30c, regions with CAAC structures can be observed as bright spots parallel to the formed surface, for example, during cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in oxide semiconductors 30a, 30b, and 30c is preferably approximately parallel to the normal direction of the formed surface of the oxide semiconductor layer.

[0277] In addition, sometimes a portion of oxide semiconductor 30a or oxide semiconductor 30c is not crystallized. Figure 8B The example shown illustrates a case where the area near the interface with layer 29 in oxide semiconductor 30a is not crystallized. Figure 8C This illustrates the case where the surface of the oxide semiconductor 30c is not crystallized. Figure 8D This shows the situation where the area near the interface between oxide semiconductor 30a and layer 29 and the area near the surface of oxide semiconductor 30c are not crystallized.

[0278] In one embodiment of the present invention, the oxide semiconductor layer exhibits high overall crystallinity. Therefore, in the oxide semiconductor 30, the boundaries between the stacked films in oxide semiconductors 30a, 30b, and 30c are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries of the stacked films. For example, cross-sectional TEM, cross-sectional STEM, etc., can be used to confirm the presence or absence of boundaries between the stacked films.

[0279] Furthermore, the lattice mismatch between the crystal contained in oxide semiconductor 30b and the crystal contained in oxide semiconductor 30a or oxide semiconductor 30c is preferably small. Therefore, oxide semiconductor 30a or oxide semiconductor 30c can form a crystal that reflects the orientation of the crystal contained in oxide semiconductor 30b. At this time, for example, when observing a cross-section of oxide semiconductor 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in oxide semiconductor 30a or oxide semiconductor 30c.

[0280] As long as the lattice mismatch between the crystal contained in oxide semiconductor 30b and the crystal contained in oxide semiconductor 30a or oxide semiconductor 30c is small, there are no particular restrictions on the crystal structure of oxide semiconductor 30a or oxide semiconductor 30c. The crystal structure of oxide semiconductor 30a or oxide semiconductor 30c can be any of the following: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0281] The oxide semiconductor layer of one aspect of the present invention can be used as the semiconductor layer of a transistor.

[0282] When the oxide semiconductor 30 is used as the semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, and even more preferably 20 nm or more and 50 nm or less. Furthermore, in transistors used in more miniaturized semiconductor devices, the thickness of the oxide semiconductor 30 is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 15 nm or less, and even more preferably 5 nm or more and 12 nm or less.

[0283] The oxide semiconductor 30b is preferably 200 nm or less. In addition, when the oxide semiconductor 30b is layered, the thickness is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and even more preferably 2 nm or more and 100 nm or less.

[0284] Alternatively, if the oxide semiconductor 30b can act as a crystal nucleus, it may exist not as a layer but as an aggregate of island-like regions. In this case, for example, the island-like regions of the oxide semiconductor 30b are dispersed.

[0285] Oxide semiconductor 30a and oxide semiconductor 30c are preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, and even more preferably 2 nm or more and 20 nm or less.

[0286] The thickness of the region where the components in oxide semiconductor 30 are alloyed with the components in layer 29 is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Figure 7A and Figure 7B An example is shown where no alloying region is formed between layer 29 and oxide semiconductor 30a.

[0287] In addition, the thickness of the alloyed region can sometimes be calculated by performing compositional line analysis on the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0288] For example, using the direction perpendicular to the surface to which the oxide semiconductor 30a is formed as the depth direction, EDX line analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth at which the quantitative value of a metal (In if the oxide semiconductor 30a contains In) that is a major component of the oxide semiconductor 30a but not a major component of the layer forming the surface (here, layer 29) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the oxide semiconductor 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is a major component of the layer forming the surface but not a major component of the oxide semiconductor 30a reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer forming the surface. Through these steps, the thickness of the alloyed region can be calculated.

[0289] Additionally, for example, when a silicon oxide layer is used as layer 29 and SIMS analysis is performed on the oxide semiconductor 30 formed on layer 29, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration of layer 29, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 The preferred reduction is 5.0 × 10 20 atoms / cm 3 More preferably, reduced to 1.0 × 10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t_s. The thickness t_s is preferably less than 3 nm, and more preferably less than 2 nm.

[0290] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region on the surface to be formed of the oxide semiconductor 30 that is greater than 0 nm and less than 3 nm in the substantially vertical direction, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0291] Oxide semiconductor 30a, for example, has a region on its top surface that is 0 nm or more and 3 nm or less from the top surface of the release layer 29. Oxide semiconductor 30c, for example, is located at a distance of 0 nm or more and 3 nm or less from the top surface of oxide semiconductor 30. Furthermore, the thicknesses of oxide semiconductors 30a, 30b, and 30c are, for example, approximately the same. Alternatively, the thicknesses of oxide semiconductors 30a, 30b, and 30c may also be different from each other.

[0292] Note that while the oxide semiconductor 30 is described above as having a three-layer structure of oxide semiconductor 30a to oxide semiconductor 30c, the present invention is not limited thereto. The oxide semiconductor 30 may have a two-layer structure or a stacked structure of four or more layers.

[0293] When the oxide semiconductor 30 has a two-layer structure, the oxide semiconductor 30 can have a structure in which oxide semiconductor 30a and oxide semiconductor 30b are stacked sequentially. By adopting this structure, alloying of the components contained in the oxide semiconductor 30 with the components contained in layer 29 can be suppressed, the thickness of the alloyed region can be reduced, or the alloyed region can be thinned to an unobservable degree.

[0294] Alternatively, when the oxide semiconductor 30 has a five-layer structure, the oxide semiconductor 30 may have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are sequentially stacked. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed using a second deposition method, and more preferably using an ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed using a first deposition method, and more preferably using a sputtering method. By adopting this structure, even if the third oxide semiconductor has a composition that makes it difficult to form a CAAC structure, crystal growth is promoted from one or both of the second oxide semiconductor and the fourth oxide semiconductor, thereby improving the crystallinity of the third oxide semiconductor.

[0295] When the oxide semiconductor 30 has a stacked structure with two or more layers, typically a stacked structure with two to five layers, it is preferable to deposit each layer continuously without exposure to the atmosphere. For example, it is preferable to use a multi-chamber deposition apparatus to deposit each layer continuously. As a result, the oxide semiconductor 30 can be deposited while suppressing impurities that can be mixed into each layer.

[0296] [c-axis orientation] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, the crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation.

[0297] The CAAC structure of oxide semiconductor layers can sometimes be evaluated using diagrams representing crystal orientation. For example, a crystal orientation oriented towards the c-axis can be observed in regions with a CAAC structure.

[0298] For example, a cross-sectional TEM image can be obtained, and a Fast Fourier Transform (FFT) can be performed on each region of the cross-sectional TEM image to create an FFT pattern. The crystal axis orientation of each region can then be calculated, thereby obtaining a pattern showing the crystal orientation. Specifically, for example, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects the same reciprocal space information as the electron diffraction pattern.

[0299] The degree of c-axis orientation can be calculated by determining the proportion of regions oriented toward the c-axis in a diagram showing crystal orientation.

[0300] In one embodiment of the present invention, in an oxide semiconductor layer, for example, the c-axis orientation can be calculated using the above-described diagram showing crystal orientation by performing TEM observation on a cross-section or plane of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also called the FFT window) can, for example, be a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0301] Additionally, when using cross-sectional TEM images for analysis, for example, the observation area of ​​the cross-sectional TEM image can be set to a region with a longitudinal direction perpendicular to the formed surface and a transverse width of 100 nm. Note that the observation area is not limited to this.

[0302] In an oxide semiconductor layer according to one aspect of the present invention, when the c-axis orientation degree is calculated to be, for example, the proportion of the region whose difference from the c-axis is within 20°, the c-axis orientation degree is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0303] Furthermore, the c-axis orientation degrees of the regions deposited as oxide semiconductor 30a, oxide semiconductor 30b, and oxide semiconductor 30c are Rc1, Rc2, and Rc3, respectively. Here, it is preferable that the c-axis orientation degree is calculated, for example, as the proportion of regions whose difference from the c-axis is within 20°. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Similarly, Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0304] [Composition of the oxide semiconductor layer] The composition of oxide semiconductor 30a is preferably different from that of oxide semiconductor 30b. Similarly, the composition of oxide semiconductor 30c is preferably different from that of oxide semiconductor 30b. Alternatively, oxide semiconductor 30a may use the same composition as oxide semiconductor 30c. Or, the composition of oxide semiconductor 30a may also be different from that of oxide semiconductor 30c.

[0305] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. For example, the oxide semiconductor 30b preferably contains zinc. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor 30b preferably contains element M in addition to zinc. By including element M in the oxide semiconductor 30b, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Specifically, as the oxide semiconductor 30b, a metal oxide with the following compositions can be used: In:M:Zn = 1:1:1 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:1.2 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:0.5 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:1:2 [atomic ratio] or a near-atomic ratio; In:M:Zn = 4:2:3 [atomic ratio] or a near-atomic ratio; In:M:Zn = 1:3:2 [atomic ratio] or a near-atomic ratio; or In:M:Zn = 1:3:4 [atomic ratio] or a near-atomic ratio. Furthermore, the near-atomic composition includes a range of ±30% of the desired atomic ratio. Additionally, one or more of gallium, tin, yttrium, and aluminum are preferably used as element M.

[0306] The oxide semiconductor 30b may also not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn composition of 1:1 (atomic ratio) or near, In:Zn composition of 2:1 (atomic ratio) or near, or In:Zn composition of 4:1 (atomic ratio) or near. Alternatively, indium oxide may be used. Additionally, it may contain trace amounts of element M. For example, it may be an In:Ga:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Ga:Zn composition of 2:0.1:1 (atomic ratio) or near. Alternatively, it may be an In:Sn:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Sn:Zn composition of 2:0.1:1 (atomic ratio) or near.

[0307] Oxide semiconductors 30a and 30c can be metal oxides with a high In content. Oxide semiconductors 30a and 30c are particularly preferably metal oxides with a higher In content than oxide semiconductor 30b. Oxide semiconductors 30a and 30c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than element M are especially preferred. By using metal oxides with a high In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics improved.

[0308] Oxide semiconductors with high In content tend to polycrystalline. Using polycrystalline metal oxides in transistors negatively impacts the initial characteristics and reliability of the transistors. In one embodiment of the present invention, the crystal orientation of oxide semiconductor 30b can be reflected in oxide semiconductors 30a and 30c with high In content. Therefore, even when using metal oxides with high In content as oxide semiconductors 30a and 30c, polycrystalline formation can be suppressed.

[0309] Alternatively, oxide semiconductors 30a and 30c may not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide may be used. Furthermore, oxide semiconductors 30a and 30c may also contain trace amounts of element M. Specifically, it may be an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0310] Alternatively, metal oxides with a high Ga ratio can be used as oxide semiconductors 30a and 30c. For example, metal oxides with a higher Ga ratio than oxide semiconductor 30b can be used as oxide semiconductors 30a and 30c. For example, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar can be preferred as oxide semiconductors 30a and 30c. By increasing the Ga ratio, the band gap of oxide semiconductors 30a and 30c can sometimes be made larger than that of oxide semiconductor 30b. Thus, oxide semiconductor 30b is sandwiched between oxide semiconductors 30a and 30c with large band gaps, and oxide semiconductor 30b can be mainly used as the current path (channel). In addition, the trapped states at and near the interface of oxide semiconductor 30b can be reduced. Thus, embedded-channel transistors with channels far from the insulator interface can be realized, and improvements can be made. In addition, the influence of interface states that can be formed on the back channel side is reduced, which can suppress the optical degradation of the transistor (e.g., optical negative bias degradation), thereby improving the reliability of the transistor.

[0311] Alternatively, one of the oxide semiconductors 30a and 30c may use a metal oxide with a higher proportion of In compared to oxide semiconductor 30b, and the other may use a metal oxide with a higher proportion of Ga compared to oxide semiconductor 30b.

[0312] Alternatively, multiple layers having the above-described composition may be stacked in oxide semiconductors 30a, 30b, and 30c. For example, oxide semiconductor 30c may also have a structure in which a metal oxide with a high proportion of In is stacked on top of a metal oxide with a high proportion of Ga.

[0313] Alternatively, oxide semiconductors 30a and 30c can also use metal oxides with the same composition as oxide semiconductor 30b. By using the same composition, it is sometimes easier to achieve CAAC after heat treatment.

[0314] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductors 30a and 30c are composed of elements that are not easily formed into a CAAC structure when forming a monolayer, the entire oxide semiconductor layer including oxide semiconductors 30a and 30c can have a CAAC structure by crystal growth with oxide semiconductor 30b as the core. Alternatively, at least a portion of the region including each of oxide semiconductors 30a and 30c up to the region of oxide semiconductor 30b can have a CAAC structure.

[0315] In the analysis of the composition of the metal oxide used in oxide semiconductor 30, methods such as EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined. Note that the content of elements with low abundance may sometimes differ from the analytically obtained content due to the influence of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0316] Impurities in oxide semiconductors Here, the effects of various impurities in the oxide semiconductor 30 are explained. The quantification of impurities contained in the oxide semiconductor 30 can be performed using XPS, SIMS, EDX, ICP-MS, ICP-AES, etc.

[0317] The channel formation region of a transistor using oxide semiconductor 30 as the semiconductor layer preferably has fewer oxygen vacancies than the source and drain regions, or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. When oxygen vacancies (V0) are present in the channel formation region of oxide semiconductor 30... O When impurities are present, the electrical properties are prone to change, sometimes reducing reliability. Additionally, hydrogen near oxygen vacancies forms V... O H may generate electrons that become charge carriers. Therefore, when the channel formation region in the oxide semiconductor 30 contains oxygen vacancies, the transistor tends to have always-on characteristics. Therefore, in the channel formation region, V OH is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistivity region with low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0318] Therefore, reducing the impurity concentration in the oxide semiconductor 30 is effective in stabilizing the electrical characteristics of the transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in the oxide semiconductor 30 refer, for example, to elements other than the main components constituting the oxide semiconductor 30. For example, elements with a concentration below 1 atomic% or below 0.1 atomic% are sometimes referred to as impurities.

[0319] When the oxide semiconductor 30 contains silicon or carbon, one of the elements in Group 14, defect states are formed in the oxide semiconductor 30. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor 30, as measured by SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Additionally, the silicon concentration in the channel formation region of the oxide semiconductor 30, as measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0320] When the oxide semiconductor 30 contains nitrogen, electrons are readily generated as charge carriers, increasing the charge carrier concentration and resulting in n-type configuration. Consequently, transistors using the nitrogen-containing oxide semiconductor 30 tend to exhibit always-on characteristics. Alternatively, when the oxide semiconductor 30 contains nitrogen, trapped states may sometimes form. As a result, the electrical characteristics of the transistor may sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor 30, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0321] Hydrogen contained in the oxide semiconductor 30 reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using the oxide semiconductor 30 containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor 30. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor 30, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably below 5×10 19 atoms / cm 3 More preferably, less than 1×10 19 atoms / cm 3 Further optimization of less than 5×10 18 atoms / cm 3 Further optimization is to select those with a value lower than 1×10 18 atoms / cm 3 Furthermore, it is preferred to have a value lower than 1×10 17 atoms / cm 3 .

[0322] Furthermore, when the oxide semiconductor 30 contains alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductor 30 containing alkali metals or alkaline earth metals tend to have always-on characteristics. Therefore, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor 30, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0323] By using oxide semiconductor 30 with sufficiently reduced impurities in the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0324] The average thickness of the channel formation region of the oxide semiconductor 30 is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0325] The oxide semiconductor 30a is an oxide semiconductor layer formed on the surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0326] Furthermore, in one aspect of the semiconductor device of the present invention, when observing a cross-section of the oxide semiconductor 230, it is sometimes possible to confirm that the metal atoms of the metal oxide are arranged in a layered manner in the region having the CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular to or substantially perpendicular to the substrate surface.

[0327] In regions with a CAAC structure, layered metal atoms can be observed as bright spots in cross-sections of the oxide semiconductor layer viewed using TEM images. Therefore, in a semiconductor device according to one aspect of the present invention, when observing the cross-section of the oxide semiconductor 230, it can sometimes be confirmed that the bright spots are arranged in a direction perpendicular to or substantially perpendicular to the substrate surface.

[0328] The oxide semiconductor 30, which is an AG CAAC, can be used as the oxide semiconductor 230 of the transistor 200. For example, as Figure 4B and Figure 4C As shown, the oxide semiconductor 230 may include oxide semiconductor 230a, oxide semiconductor 230b in contact with oxide semiconductor 230a, and oxide semiconductor 230c in contact with oxide semiconductor 230b. Here, oxide semiconductor 230a corresponds to oxide semiconductor 30a, oxide semiconductor 230b corresponds to oxide semiconductor 30b, and oxide semiconductor 230c corresponds to oxide semiconductor 30c.

[0329] Here, the aforementioned pillar (insulator 223 described later) corresponds to layer 29. That is, the surface of oxide semiconductor 230 is formed as a pillar, and this pillar is removed in transistor 200. During the manufacturing process, one side of oxide semiconductor 230a contacts the pillar, and the other side contacts oxide semiconductor 230b. After the pillar is removed, one side of oxide semiconductor 230a contacts insulator 250. One side of oxide semiconductor 230b contacts oxide semiconductor 230a, and the other side contacts oxide semiconductor 230c. One side of oxide semiconductor 230c contacts oxide semiconductor 230b, and the other side contacts insulator 250. Here, since the side of the pillar is formed perpendicular to or substantially perpendicular to the substrate surface (also referred to as the surface of insulator 222), the side of oxide semiconductor 230 (oxide semiconductor 230a to oxide semiconductor 230c) is also perpendicular to or substantially perpendicular to the substrate surface.

[0330] As described above, in the cross-sections of oxide semiconductor 230 (oxide semiconductor 230a to oxide semiconductor 230c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction parallel to or substantially parallel to the surface to which they were formed. In other words, in the cross-sections of oxide semiconductor 230 (oxide semiconductor 230a to oxide semiconductor 230c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction perpendicular to or substantially perpendicular to the substrate surface. Furthermore, it can be stated that the c-axis of AG CAAC is substantially parallel to the normal direction of the side surface of oxide semiconductor 230.

[0331] Thus, by using oxide semiconductor 230 as AG CAAC in the channel formation region of transistor 200, transistors with good on-state current, field-effect mobility, S-value, frequency characteristics and reliability can be provided.

[0332] Furthermore, as described above, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductor 230a to oxide semiconductor 230c, oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are sequentially formed around the region where the pillars are formed. Therefore, as Figure 9AAs shown, when viewed in cross-section along the channel width direction of transistor 200, oxide semiconductors 230c, 230b, 230a, 230a, 230b, and 230c are arranged symmetrically in sequence. That is, in order to achieve a bilaterally symmetrical structure in cross-section, oxide semiconductors 230a and 230c preferably have substantially the same composition. Furthermore, oxide semiconductors 230a and 230c preferably have substantially the same thickness. Additionally, when the angle θ formed by the side surface of oxide semiconductor 230 and the top surface of insulator 222 is 80° or more and less than 90°, i.e., when the side surface of oxide semiconductor 230 is slightly tilted, such as... Figure 9B As shown, the oxide semiconductors 230 are arranged in a manner that makes their tilt symmetrical. Furthermore, in the case where the oxide semiconductors 230 are formed at an angle, as... Figure 9B As shown, sometimes the upper part of the oxide semiconductor 230 is thinner than the lower part of the oxide semiconductor 230.

[0333] The oxide semiconductor 230 has a channel forming region for the transistor 200, as well as a source region and a drain region disposed in a manner that clamps the channel forming region. At least a portion of the channel forming region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can also be interchanged.

[0334] The channel formation region is a high-resistivity region with fewer oxygen vacancies or lower impurity concentrations and carrier concentrations compared to the source and drain regions. Therefore, the channel formation region can be described as an i-type (intrinsic) or essentially i-type region.

[0335] Furthermore, the source and drain regions are low-resistance regions with high carrier concentrations due to the abundance of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel formation region.

[0336] In addition, the preferred carrier concentration in the channel formation region is 1×10⁻⁶. 18 cm -3 The following are less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×1012 cm -3 Less than 1×10 11 cm -3 Or less than 1×10 10 cm -3 Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0337] When aiming to reduce the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 can be reduced to decrease the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Additionally, oxide semiconductors (or metal oxides) with low carrier concentration are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0338] To stabilize the electrical characteristics of transistor 200, reducing the impurity concentration in the channel formation region of oxide semiconductor 230 is effective. To further reduce the impurity concentration in oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in oxide semiconductor 230 refer, for example, to elements other than the main components constituting oxide semiconductor 230. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0339] Furthermore, in oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to vary in stages for each region; they can vary gradually within each region. That is, the closer to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen should be.

[0340] As described above, in the channel formation region of an oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V0. O H. In other words, preferably, the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsic) or substantially i-typed. Here, by performing heat treatment with an insulator containing oxygen (hereinafter sometimes referred to as excess oxygen) that has been removed by heating near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulator, thereby reducing oxygen vacancies and V. OH. Note that supplying excessive oxygen to the source or drain region may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, when the amount of oxygen supplied to the source or drain region is uneven within the substrate surface, the semiconductor device characteristics, including the transistor, become uneven. Additionally, when oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductors such as the gate, source, and drain electrodes, these conductors may sometimes be oxidized, leading to a loss of conductivity and thus negatively impacting the transistor's electrical characteristics and reliability.

[0341] Therefore, preferably, in the oxide semiconductor, the channel formation region is a region with reduced carrier concentration and is i-type or substantially i-type, while the source and drain regions are regions with high carrier concentration and are n-type. In other words, it is preferable to reduce oxygen vacancies and V0 in the channel formation region of the oxide semiconductor. O H. Additionally, preferably, the source and drain regions are not supplied with excessive oxygen, and the V of the source and drain regions... O The amount of hydrogen (H) is not excessively reduced. Furthermore, a structure that suppresses the decrease in conductivity of conductors 260, 242a, and 242b is preferred. For example, a structure that suppresses the oxidation of conductors 260, 242a, and 242b is preferred. Note that hydrogen in oxide semiconductors may form V2. O H, therefore, in order to reduce V O The amount of H needs to be reduced, so the hydrogen concentration needs to be lowered.

[0342] Therefore, in this embodiment, the hydrogen concentration in the channel formation region is reduced in the semiconductor device to suppress the oxidation of conductors 242a, 242b and 260, and to suppress the decrease in hydrogen concentration in the source and drain regions.

[0343] [Insulators and Conductors] The insulator 250 in contact with the channel formation region in the oxide semiconductor 230 preferably has the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Consequently, the Vg in the channel formation region can be reduced. O H, which can make the channel forming region type i or substantially type i.

[0344] Here, as Figure 4A and Figure 4B As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulators 250a and 250c preferably have the function of capturing or fixing hydrogen.

[0345] As insulators capable of trapping or fixing hydrogen, examples include metal oxides with amorphous structures as described above. Magnesium oxide or oxides containing one or both of aluminum and hafnium are preferred, for example, as insulators 250a and 250c.

[0346] Furthermore, high-k materials are preferably used as insulators 250a and 250c. An example of a high-k material is an oxide comprising one or both of aluminum and hafnium, as described above. By using high-k materials as insulators 250a and 250c, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Additionally, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0347] As insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0348] In this embodiment, an alumina film is used as the insulator 250a. Furthermore, this alumina preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively trapped and immobilized.

[0349] In this embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be captured and fixed more effectively.

[0350] Next, the insulator 250b is preferably made of a thermally stable insulator such as silicon oxide or silicon oxynitride. Note that in this specification, oxynitride refers to a material in which the oxygen content is higher than the nitrogen content in its composition, while oxynitride refers to a material in which the nitrogen content is higher than the oxygen content in its composition. For example, when described as silicon oxynitride, this refers to a material in which the oxygen content is higher than the nitrogen content in its composition, while when described as silicon oxynitride, this refers to a material in which the nitrogen content is higher than the oxygen content in its composition.

[0351] The silicon oxide film used as the insulator 250b is preferably formed using the PEALD method.

[0352] Furthermore, in order to suppress the oxidation of conductors 242a, 242b, and 260, it is preferable to provide an oxygen-barrier insulator near each of conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, such insulators are, for example, insulators 250a, 250d, 250c, 255, and 275.

[0353] Insulator 250a preferably has oxygen-barrier properties. Insulator 250a is preferably at least less permeable to oxygen than insulator 280. Insulator 250a has regions that contact the sides of conductor 242a1 and conductor 242b1. When insulator 250a has oxygen-barrier properties, oxidation of the sides of conductor 242a1 and conductor 242b1, preventing the formation of an oxide film on those sides, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of transistor 200 can be suppressed. Thus, a semiconductor device with good electrical characteristics can be provided.

[0354] Furthermore, the insulator 250a is disposed in contact with the top and side surfaces of the oxide semiconductor 230, the side surface of the insulator 224, and the top surface of the insulator 222. When the insulator 250a has oxygen-barrier properties, oxygen can be suppressed from escaping from the channel formation region of the oxide semiconductor 230 during heat treatment or similar processes. As a result, oxygen vacancies formed in the oxide semiconductor 230 can be reduced.

[0355] Furthermore, by providing insulator 250a, excessive oxygen supply from insulator 280 to oxide semiconductor 230 can be suppressed, while an appropriate amount of oxygen can be supplied to oxide semiconductor 230. Therefore, the decrease in on-state current or field-effect mobility of transistor 200 due to excessive oxidation of the source and drain regions can be suppressed.

[0356] Because oxides containing one or both of aluminum and hafnium have oxygen-blocking properties, they can be suitable for use as insulators 250a.

[0357] The insulator 250d preferably also has oxygen-barrier properties. The insulator 250d is disposed between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. By employing this structure, the diffusion of oxygen from the channel formation region of the oxide semiconductor 230 to the conductor 260, thus preventing the formation of oxygen vacancies in the channel formation region of the oxide semiconductor 230, can be suppressed. Furthermore, the diffusion of oxygen contained in the oxide semiconductor 230 and the insulator 280 to the conductor 260, thereby preventing oxidation of the conductor 260, can be suppressed. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0358] Furthermore, the insulator 250d preferably has hydrogen-blocking properties. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0359] The insulator 275 preferably also has oxygen-barrier properties. The insulator 275 is disposed between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This suppresses the diffusion of oxygen contained in the insulator 280 into the conductor 242. Therefore, it suppresses the oxidation of the conductor 242 by oxygen contained in the insulator 280, which would increase the resistivity. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0360] To suppress the decrease in hydrogen concentration in the source and drain regions of the oxide semiconductor 230, it is preferable to provide an insulator that blocks hydrogen (also referred to as a hydrogen-blocking insulator) near each of the source and drain regions. In the semiconductor device described in this embodiment, the hydrogen-blocking insulator is, for example, insulator 275.

[0361] Examples of hydrogen barrier insulators include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as silicon nitride. For example, the insulator 275 preferably employs a single-layer structure or a multilayer structure of the aforementioned hydrogen barrier insulators.

[0362] By setting the aforementioned insulator 275, hydrogen diffusion from the source and drain regions to the outside can be suppressed, thus preventing the decrease in hydrogen concentration in the source and drain regions. Therefore, the source and drain regions can be n-type.

[0363] By adopting the above structure, the channel forming region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still possess excellent electrical characteristics. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased.

[0364] Insulators 250a to 250d are used as part of the gate insulator. Insulators 250a to 250d are disposed together with conductor 260 inside the opening 201 formed in insulators 275 and 280. To achieve miniaturization of the transistor 200, the thickness of insulators 250a to 250d is preferably small. The thickness of each of insulators 250a to 250d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Furthermore, at least a portion of each of insulators 250a to 250d preferably has a region with the thickness described above.

[0365] In addition, the thickness of the silicon oxide film used as insulator 250 is preferably 0.7 nm or more and 3 nm or less.

[0366] To reduce the thickness of insulators 250a to 250d as described above, deposition using the ALD method is preferred. Furthermore, to deposit insulators 250a to 250d inside the opening 201, deposition using the ALD method is preferred. ALD methods include thermal ALD (using only thermal energy to react the precursors and reactants) and PEALD (Plasma Enhanced ALD) (using reactants excited by plasma). In the PEALD method, deposition can be performed at lower temperatures by utilizing plasma, and therefore it is sometimes preferred.

[0367] As described above, the ALD method can deposit atoms layer by layer, thus possessing the advantages of being able to deposit extremely thin layers, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve high coverage, and deposit at low temperatures. Therefore, the insulator 250 can be deposited with the aforementioned small thickness and high coverage on the sides of the opening 201 provided in the insulator 275 and the side ends of the conductors 242a and 242b. Furthermore, by using the ALD method in the same way as the insulator 250, the insulator 255 can be deposited with high coverage on the sides of the opening 201 and the side ends of the conductors 242a and 242b, which is therefore preferred.

[0368] Furthermore, the precursors used in the ALD method sometimes contain carbon and other impurities. Therefore, films formed using the ALD method sometimes contain more carbon and other impurities compared to films formed using other deposition methods. Additionally, the quantification of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0369] Note that in the above description, insulator 250 has a four-layer structure of insulators 250a to 250d, but the present invention is not limited thereto. Insulator 250 may include at least one of insulators 250a to 250d. By having insulator 250 composed of one, two, or three layers of insulators 250a to 250d, the manufacturing process of semiconductor devices can be simplified, thereby improving productivity.

[0370] For example, such as Figure 10 As shown, the insulator 250 can also have a three-layer structure. In this case, the insulator 250 preferably has a stacked structure of insulator 250a, insulator 250b on insulator 250a, and insulator 250c on insulator 250b. In other words, from Figure 4A The structure shown has 250d of insulator removed.

[0371] When forming the insulator 250, it is preferable to perform the ALD process twice or more. For example, it is preferable that the insulator 250 has a laminated structure composed of multiple insulating films, and that two or more of the multiple insulating films are formed using the ALD process. By forming at least two insulating films using the ALD process, the coverage and thickness uniformity of the insulator 250 can be improved. In addition, by continuously forming two or more different films, such as two or more insulating films, using the ALD process, productivity can be improved.

[0372] In addition to the structure described above, it is preferable to also have a structure that suppresses hydrogen ingress into the transistor 200, etc. For example, it is preferable to provide an insulator with the function of suppressing hydrogen diffusion by covering one or both of the top and bottom of the transistor 200, etc. In the semiconductor device described in this embodiment, the insulator is, for example, insulator 283, insulator 282, insulator 222, and insulator 221, etc. In addition, the insulator 215 provided under the transistor 200 may also have the same structure as either or both of insulator 282 and insulator 283. In this case, the insulator 215 may adopt a stacked structure of insulator 282 and insulator 283, or it may adopt a structure in which insulator 282 is provided under insulator 283, or it may adopt a structure in which insulator 282 is provided on insulator 283.

[0373] One or more of insulators 283, 282, 222, and 221 are preferably used as barrier insulators to suppress the diffusion of impurities such as water and hydrogen from the substrate side or above the transistor 200. Therefore, one or more of insulators 283, 282, 222, and 221 preferably comprise an insulating material that functions to suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Additionally, it is preferable to include an insulating material that functions to suppress the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, making it difficult for the aforementioned oxygen to permeate).

[0374] Insulators 283, 282, 222, and 221 preferably all include insulators that suppress the diffusion of impurities such as water and hydrogen, as well as oxygen. Examples of suitable materials include alumina, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon oxynitride. For example, insulators 283 and 221 preferably use silicon nitride, which has higher hydrogen barrier properties. Additionally, insulator 282 preferably uses alumina, which has a high hydrogen trapping or fixing ability. Furthermore, insulator 222 has a high hydrogen trapping or fixing ability, and is preferably made of high-k hafnium oxide.

[0375] Alternatively, at least one of insulators 221 and 222 may also have a laminated structure of the aforementioned materials and silicon oxide or silicon oxynitride. For example, a laminated structure of silicon nitride and silicon oxide may also be used as insulator 221. Additionally, a laminated structure of hafnium oxide and silicon oxide may also be used as insulator 222.

[0376] By employing this structure, the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed on the upper side of insulator 283 to transistor 200 and the like can be suppressed. Furthermore, the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed on the lower side of insulator 221 to transistor 200 and the like can be suppressed. Additionally, hydrogen contained in insulators 280 and 250 can be captured and fixed to insulator 282 or insulator 222. Furthermore, by providing insulators 282 and 283, the diffusion of oxygen contained in insulator 280 to the top of transistor 200 and the like can be suppressed. Furthermore, by providing insulators 222 and 221, the diffusion of oxygen contained in oxide semiconductor 230 to the bottom of transistor 200 and the like can be suppressed. Thus, by employing a structure in which insulators with the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen, surround the top and bottom of transistor 200, excess oxygen and hydrogen diffusion to oxide semiconductor can be reduced. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0377] Furthermore, insulators 275 and 250d are preferably made of silicon nitride, which has higher hydrogen barrier properties. In addition, insulator 250a is preferably made of alumina, which has a high hydrogen trapping or fixing ability. Furthermore, insulator 250c is preferably made of hafnium oxide, which has a high hydrogen trapping or fixing ability.

[0378] Conductors 242a and 242b are disposed separately from each other, and conductors 242a1 and 242b1 are disposed in contact with the oxide semiconductor 230. For example, as Figure 4C As shown, the conductor 242 is disposed in a manner that covers the high aspect ratio oxide semiconductor 230. Additionally, as... Figure 2C As shown, the conductor 242a1 (conductor 242b1) preferably has a structure that contacts two or more finned oxide semiconductors 230 when viewed in cross-section.

[0379] Here, near the source or drain of transistor 200, such as Figure 4C As shown, the conductor 242a is arranged in a folded state, sandwiching the oxide semiconductor 230. Therefore, when viewed in cross-section along the channel width direction of the transistor 200, the conductor 242a1 contacts the oxide semiconductor 230 on each of the top surface, the side surface on the A3 side, and the side surface on the A4 side. Thus, compared to the case where the oxide semiconductor 230 is in a flat plate shape, the contact area between the conductor 242a1 and the oxide semiconductor 230 is increased on the A3 side and the A4 side of the oxide semiconductor 230. Furthermore, as... Figure 2C As shown, by employing a structure in which multiple finned oxide semiconductors 230 are in contact with the conductor 242a1, the contact area can be further increased. Note that in Figure 2C and Figure 4C The diagram shows the area near conductor 242a, and the same applies to conductor 242b. In other words, while the contact area between conductor 242a1 and oxide semiconductor 230 is the same, the contact area between conductor 242b1 and oxide semiconductor 230 is larger.

[0380] As described above, by increasing the contact area between the conductor 242 and the oxide semiconductor 230, the on-state current and frequency characteristics of the transistor 200 can be improved without increasing the occupied area of ​​the transistor 200. This provides a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using this semiconductor device can be increased. This enables miniaturization or high integration of the semiconductor device. Additionally, the storage capacity of a memory device using this semiconductor device can be increased.

[0381] Note that sometimes hydrogen contained in the oxide semiconductor 230 diffuses into the conductor 242a or conductor 242b. In particular, by using a tantalum-containing nitride as conductor 242a and conductor 242b, for example, hydrogen contained in the oxide semiconductor 230 may easily diffuse into the conductor 242a or conductor 242b, and the diffused hydrogen may bond with the nitrogen contained in the conductor 242a or conductor 242b. That is, for example, hydrogen contained in the oxide semiconductor 230 may sometimes be absorbed by the conductor 242a or conductor 242b. For example, when a tantalum-containing nitride is used as conductor 242a1 and conductor 242b1 in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 may sometimes be absorbed by conductor 242a1 and conductor 242b1.

[0382] Furthermore, to suppress the decrease in conductivity of conductors 242a and 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, a metal oxide comprising indium, zinc, and one or more selected from gallium, aluminum, and tin is preferred. By using CAAC-OS, oxygen extraction from the oxide semiconductor 230 by conductors 242a or 242b can be suppressed. For example, oxygen extraction from the oxide semiconductor 230 by conductors 242a1 or 242b1 can be suppressed. Additionally, the decrease in conductivity of conductors 242a and 242b can be suppressed.

[0383] like Figure 2B and Figure 3AAs shown, the conductor 260 is disposed inside the opening 201. When viewed in cross-section along the channel width direction of the transistor 200, the conductor 260 covers the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230, separated by the insulator 250. Furthermore, the top surface of the conductor 260 is positioned such that its height is the same as or approximately the same as the height of the uppermost part of the insulator 250 and the top surface of the insulator 280.

[0384] The sidewall of the opening 201 can be perpendicular or substantially perpendicular to the top surface of the insulator 222, or it can be conical. By having a conical sidewall, the coverage of the insulator 250 and the like provided in the opening 201 is improved, and defects such as voids can be reduced.

[0385] Conductor 260 is used as the first gate electrode of transistor 200. Here, as... Figure 2A and Figure 2B As shown, the conductor 260 is preferably provided extending in the channel width direction. By adopting this structure, the conductor 260 is used as wiring when multiple transistors are arranged.

[0386] A portion of the conductor 260 is arranged in a folded state, sandwiching the finned oxide semiconductor 230. Thus, as described above, when viewed in cross-section along the channel width direction of the transistor 200, the oxide semiconductor 230 and the conductor 260 are separated by the insulator 250 on the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. In other words, the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 are all used as channel formation regions. Therefore, compared to the case where the oxide semiconductor 230 is planar, the channel width of the transistor 200 is increased by the portion of the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0387] exist Figure 3A In this embodiment, the conductor 260 has a two-layer structure: a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is disposed in such a way that it contacts the insulator 250 inside the opening 201. Alternatively, the conductor 260b is disposed on the conductor 260a in such a way that it is embedded in the opening 201. In other words, the conductor 260a is disposed in such a way that it surrounds the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion as the conductor 260a.

[0388] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0389] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 280 from oxidizing the conductor 260b and causing a decrease in conductivity. For example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be used as conductive materials with the function of inhibiting oxygen diffusion.

[0390] Furthermore, the conductor 260b is preferably a conductor with high conductivity. For example, the conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main component. In addition, the conductor 260b can have a multilayer structure, for example, it can have a multilayer structure of titanium or titanium nitride with the aforementioned conductive material.

[0391] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by filling opening 201. Here, the side surface of insulator 280 in opening 201 coincides with or substantially coincides with the side surface of conductor 242a2 and conductor 242b2. Therefore, even without alignment, conductor 260 can be provided in a manner that overlaps with the area between conductor 242a2 and conductor 242b2.

[0392] The dielectric constants of insulators 216 and 280 are preferably lower than those of insulator 222. By using a material with a low dielectric constant for the interlayer film, parasitic capacitances generated between wirings (not shown) can be reduced, for example.

[0393] For example, insulator 216 and insulator 280 preferably each comprise one or more of silicon oxide, silicon oxynitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide.

[0394] In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. They are also preferred because materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released during heating.

[0395] In addition, the top surfaces of insulators 216 and 280 can also be flattened.

[0396] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, the insulator 280 preferably contains silicon oxides such as silicon oxide and silicon oxynitride.

[0397] Conductor 240a is disposed inside opening 202a. Conductor 240b is disposed inside opening 202b. The bottom surface of conductor 240a contacts the top surface of conductor 242a, and the bottom surface of conductor 240b contacts the top surface of conductor 242b. Here, the height of the top surface of conductor 240 is approximately the same as the height of the top surface of insulator 283.

[0398] The conductor 240 is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. Alternatively, the conductor 240 may also be a laminated structure in which a first conductor is disposed in contact with the side of the insulator 241 and a second conductor is disposed inside it. In this case, the aforementioned conductive material can be used as the second conductor. Here, the aforementioned first conductor corresponds to... Figure 4C The conductor 240a1 shown above corresponds to the second conductor mentioned above. Figure 4C The conductor shown is 240a2.

[0399] When a multilayer structure is adopted as the conductor 240, a conductive material with the function of suppressing the permeation of impurities such as water and hydrogen is preferably used as the first conductor disposed near insulators 283, 282, 280, and 275. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferred. The conductive material with the function of suppressing the permeation of impurities such as water and hydrogen can be used as a single layer or in a multilayer. By adopting this structure, impurities such as water and hydrogen contained in the layer above insulator 283 can be prevented from mixing into oxide semiconductor 230 through conductors 240a and 240b.

[0400] As described above, insulator 241a is provided in contact with the sidewall of opening 202a. Insulator 241b is provided in contact with the sidewall of opening 202b. The inner surface of insulator 241a is in contact with conductor 240a, and the inner surface of insulator 241b is in contact with conductor 240b.

[0401] As insulator 241, a barrier insulating film suitable for insulators such as 275 can be used. For example, silicon nitride, aluminum oxide, silicon oxynitride, etc., can be used as insulator 241. By providing insulator 241, impurities such as water and hydrogen contained in insulator 280 can be suppressed from entering oxide semiconductor 230 through conductors 240a and 240b. In particular, silicon nitride has high hydrogen barrier properties and is therefore preferred. In addition, oxygen contained in insulator 280 can be prevented from being absorbed by conductors 240a and 240b.

[0402] The insulator 241 may have a laminated structure. In this case, the insulator 241 may include a first insulator in contact with the sidewall of the opening 202 and a second insulator inside it. As the first insulator and the second insulator, the insulator 241 preferably uses, for example, a combination of an oxygen-barrier insulating film and a hydrogen-barrier insulating film.

[0403] For example, it is preferable to use alumina deposited by thermal ALD as the first insulator and silicon nitride deposited by PEALD as the second insulator. By employing such a structure, oxidation of the conductor 240 can be suppressed, and hydrogen ingress into the conductor 240 can be suppressed.

[0404] Furthermore, the insulator 241 may also have a stacked structure of three or more layers. Additionally, in the above structure, the conductor 240 has a two-layer stacked structure, but the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0405] For example, such as Figure 4C As shown, conductor 240a can also cover oxide semiconductor 230 and conductor 242a sandwiching oxide semiconductor 230 in a folded state. Therefore, when viewed in cross-section along the channel width direction of transistor 200, conductor 240a contacts conductor 242a on each of the top surface, the side surface on the A3 side, and the side surface on the A4 side of oxide semiconductor 230. Thus, compared to the case where oxide semiconductor 230 is in a flat plate shape, the contact area between conductor 240a and conductor 242a is increased on the A3 side and the A4 side of oxide semiconductor 230. Furthermore, as... Figure 2C As shown, by employing a structure in which conductor 240a covers multiple finned oxide semiconductors 230, the contact area between conductor 240a and conductor 242a can be further increased. Note that in Figure 2C and Figure 4C Conductors 240a and 242a are shown, and conductors 240b and 242b are also the same. In other words, while the contact area between conductors 240a and 242a is the same as that between conductors 240b and 242b, the contact area between conductors 240b and 242b is increased.

[0406] As described above, when the contact area between conductor 240 and conductor 242 increases, the contact resistance between conductor 240 and conductor 242 can be reduced. This improves the on-state current, frequency characteristics, etc., of transistor 200 without increasing the occupied area of ​​transistor 200. Consequently, a high-speed semiconductor device can be provided. Furthermore, the operating speed of memory devices using this semiconductor device can be increased. This enables miniaturization or high integration of semiconductor devices. Additionally, the storage capacity of memory devices using this semiconductor device can be increased.

[0407] <Structure Example of a Semiconductor Device 2> The following explanations are, for example, related to... Figures 1A to 3B The examples shown are of different structures of the semiconductor device according to one aspect of the present invention.

[0408] exist Figures 1A to 3B In this configuration, the insulator 224 is provided only in the region overlapping with the oxide semiconductor 230, but it is not limited to this. For example, as... Figures 11A to 11D As shown, in addition to the area overlapping with the oxide semiconductor 230, an insulator 224 can also be provided outside the opening 201. Here, Figures 11A to 11D Corresponding to Figure 2A , Figure 2B , Figure 2C and Figure 3A Therefore, the detailed structure can be found in the above description.

[0409] In one aspect of the semiconductor device of the present invention, in the region at least overlapping with the opening 201, the shape of the insulator 224 as viewed from a planar surface can be made consistent with or substantially consistent with the shape of the oxide semiconductor 230 as viewed from a planar surface. Additionally, as... Figures 11B to 11D As shown, an insulator 275 is disposed between insulator 224 and insulator 280. Additionally, as... Figure 11D As shown, conductors 242a and 242b are in contact with the top surface of insulator 224. Additionally, as... Figure 11B As shown, the insulator 255 is in contact not only with the side of the opening 201 of the insulator 275 and the side of the opening 201 of the insulator 280, but also with the side of the insulator 224.

[0410] Figures 12A to 12D An example of the structure of a semiconductor device without insulator 224 is shown. Figures 12A to 12D Corresponding to Figure 2A , Figure 2B , Figure 2C and Figure 3A .exist Figures 12A to 12D In the example shown, the bottom surface of the oxide semiconductor 230 is in contact with the top surface of the insulator 222. Alternatively, insulators 221 and 222 may not be provided. In this case, the bottom surface of the oxide semiconductor 230 is in contact with the insulator 216.

[0411] and Figures 1A to 3B Compared to the semiconductor device shown, Figures 12A to 12D The semiconductor device shown can simplify manufacturing processes and increase productivity. On the other hand, with Figures 12A to 12D Compared to the semiconductor device shown, Figures 1A to 3BThe semiconductor device shown makes it easier to apply a gate electric field to the lower end and vicinity of the oxide semiconductor 230. Therefore, the electrical characteristics of the transistor 200 can be improved.

[0412] Figure 13A This is a perspective view showing an example of the structure of a semiconductor device including a transistor 200. Figure 13A In addition to Figure 1A In addition to the insulator 224, oxide semiconductor 230, conductor 242a1, conductor 242a2, conductor 242b1, conductor 242b2 and conductor 260 shown, conductor 240a and conductor 240b are also shown. Figure 13B It is shown by dashed lines Figure 13A A perspective view of conductors 240a, 240b, and 260, with the shaded lines omitted. Figure 13C From Figure 13B Delete the 3D image of conductor 260.

[0413] Figure 14A For example, it is shown that includes Figure 13A A plan view of an example structure of the semiconductor device shown, transistor 200. Figure 14B It is along Figure 14A The cross-sectional view of the section with dotted lines A5-A6 in the figure. Figure 14C It is along Figure 14A A cross-sectional view of the section with dotted lines B1-B2 in the diagram. Figure 14D It is along Figure 14A The cross-sectional view of the section marked with dashed lines B3-B4. Note that... Figure 14A The cross-sectional view of the portion shown by the dashed lines A1-A2 in the figure can be referred to Figure 2B .in addition, Figure 14A The cross-sectional view of the portion shown by the dashed lines A3-A4 in the figure can be referred to Figure 2C .

[0414] Figures 13A to 14D An example is shown where a portion of the opening 202 (also referred to as a portion of the conductor 240) overlaps with the oxide semiconductor 230, while other portions of the opening 202 (also referred to as other portions of the conductor 240) do not overlap with the oxide semiconductor 230. Thus, by employing a structure where a portion of the conductor 240 overlaps with the oxide semiconductor 230 and other portions of the conductor 240 do not overlap with the oxide semiconductor 230, the arrangement space for the conductor 240 can be increased.

[0415] Figure 14A and Figure 14D An example is shown where the conductor 240 covers the entire region of the oxide semiconductor 230 parallel to the channel width direction, but the invention is not limited thereto. Figure 15A and Figure 15B As shown, a portion of the region of the oxide semiconductor 230 parallel to the channel width direction may also be left uncovered by the conductor 240. Here, Figure 15A Corresponding to Figure 14A , Figure 15B Corresponding to Figure 14D .

[0416] Figure 15A and Figure 15B An example is shown where the side of the conductor 260 in the region of the oxide semiconductor 230 parallel to the channel width direction is not covered by the conductor 240. Figure 15A and Figure 15B In the example shown, with Figure 14A and Figure 14D Compared to the example shown, the distance between conductor 240 and conductor 260 can be increased. Therefore, the parasitic capacitance between conductor 240 and conductor 260 can be reduced. On the other hand, in Figure 14A and Figure 14D In the example shown, with Figure 15A and Figure 15B Compared to the example shown, the contact resistance between conductor 240a and conductor 242a2 and the contact resistance between conductor 240b and conductor 242b2 can be reduced.

[0417] For example, Figure 14C An example is shown where the opening 202 and the conductor 240 are arranged in such a way that they overlap with the oxide semiconductor 230, but the present invention is not limited thereto. Figure 16A As shown, the opening 202 and the conductor 240 may not overlap with the oxide semiconductor 230. Figure 16A It is a cross-sectional view along the B1-B2 direction.

[0418] In addition, Figure 3A , Figure 14C and Figure 16A In the example, conductors 240a and 240b are symmetrically arranged with conductor 260 as the center, but the present invention is not limited thereto. For example, such as Figure 16B As shown, when viewed in cross-section along the channel length direction of transistor 200, a portion of conductor 240a can overlap with oxide semiconductor 230 without conductor 240b overlapping with oxide semiconductor 230. Additionally, for example, as... Figure 16C As shown, when viewed in cross-section along the channel length of transistor 200, a structure can also be adopted in which conductor 240a is disposed in the region overlapping with oxide semiconductor 230 and conductor 240b is disposed in the region not overlapping with oxide semiconductor 230. Figure 16B and Figure 16C It is a cross-sectional view along the B1-B2 direction.

[0419] Furthermore, the semiconductor device in this embodiment can also employ, for example... Figures 17A to 17D The structure shown has a conductor 205 disposed beneath the insulator 221. The conductor 205 has a region serving as the second gate electrode (lower gate electrode) of the transistor 200. Additionally, insulators 222 and 221 each have regions serving as the second gate insulator of the transistor 200. Figures 17A to 17D Corresponding to Figure 2A , Figure 2B , Figure 2C and Figure 3A Therefore, the detailed structure can be found in the above description.

[0420] In transistor 200, conductor 205 is disposed in a manner that overlaps with oxide semiconductor 230 and conductor 260. Here, conductor 205 is preferably disposed in a manner that embeds into opening 203 formed in insulator 216. Additionally, as... Figure 17A and Figure 17B As shown, the conductor 205 is preferably provided extending in the channel width direction. By adopting this structure, the conductor 205 is used as wiring when multiple transistors are arranged.

[0421] like Figure 17D As shown, the conductor 205 preferably includes conductor 205a and conductor 205b. Conductor 205a is disposed in contact with the bottom surface and sidewall of the opening 203. Conductor 205b is disposed in a recess formed along the opening 203 of conductor 205a. Here, the height of the top surface of conductor 205 is the same as or approximately the same as the height of the top surface of insulator 216.

[0422] Here, the conductor 205a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to include a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0423] By using a conductive material with hydrogen diffusion suppression function as conductor 205a, impurities such as hydrogen contained in conductor 205b can be prevented from diffusing to oxide semiconductor 230 through insulator 216, etc. Furthermore, by using a conductive material with oxygen diffusion suppression function as conductor 205a, oxidation of conductor 205b and subsequent decrease in conductivity can be prevented. Examples of conductive materials with oxygen diffusion suppression function include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Conductor 205a can have a single-layer structure or a multilayer structure of the aforementioned conductive materials. For example, conductor 205a preferably contains titanium nitride.

[0424] Furthermore, the conductor 205b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, the conductor 205b preferably contains tungsten.

[0425] Conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential applied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be further increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0426] Furthermore, the resistivity of conductor 205 is designed considering the potential applied to conductor 205, and the thickness of conductor 205 is set according to this resistivity. Additionally, the thickness of insulator 216 is approximately the same as that of conductor 205. Here, it is preferable to reduce the thickness of both conductor 205 and insulator 216 within the design limits of conductor 205. By reducing the thickness of insulator 216, the absolute amount of impurities such as hydrogen contained in insulator 216 can be reduced, thus suppressing the diffusion of these impurities into oxide semiconductor 230.

[0427] Note that the above structure shows a stacked structure of conductors 205a and 205b, but the present invention is not limited thereto. Conductor 205 can have a single-layer structure or a stacked structure of three or more layers. For example, when conductor 205 has a three-layer stacked structure, a conductor containing the same material as conductor 205a can be provided on conductor 205b in the stacked structure of conductors 205a and 205b. In this case, the top surface of conductor 205b can be lower than the uppermost part of conductor 205a, so that the conductor is embedded in the recess formed by conductors 205a and 205b.

[0428] <Example of a storage unit structure> The following describes a structural example of a memory cell including transistor 200.

[0429] like Figure 18 As shown, in addition to transistor 200, capacitor 460 and transistor 310 formed on a silicon substrate can also be used to use them as 2T (transistor) 1C (capacitor) type memory cells. Figure 18 As shown, a layer including transistor 200 and capacitor 460 can be disposed on a layer including transistor 310. Additionally, Figure 19A This shows a cross-sectional view of the transistor 200 along the channel width direction. Figure 19BA cross-sectional view including conductor 240a is shown in this direction. Figure 19C A cross-sectional view of capacitor 460 in this direction is shown. Figure 19D A cross-sectional view of transistor 310 in the channel width direction is shown.

[0430] Transistor 310 is disposed on substrate 311 and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 comprising a portion of substrate 311, a low-resistance region 314a serving as one of a source region and a drain region, and a low-resistance region 314b serving as the other of the source region and drain region. Transistor 310 can be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0431] like Figure 19D As shown, in transistor 310, the semiconductor region 313 (a portion of substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulator 315 in between. Alternatively, the conductor 316 can be made of a material with adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 310 is sometimes referred to as a finned transistor. Additionally, an insulator used to form a mask for the convex portion can be provided in contact with the upper surface of the convex portion. Although the case shown here is forming the convex portion by processing a portion of the semiconductor substrate, a semiconductor film with a convex shape can also be formed by processing an SOI (Silicon on Insulator) substrate.

[0432] Notice, Figure 18 The structure of transistor 310 shown is only an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0433] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be configured according to the design. Additionally, in this specification, wiring and plugs electrically connected to the wiring can also be considered as components. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0434] For example, in transistor 310, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Conductors 328 and the like are embedded in insulators 320 and 322. Conductors 330 and the like are embedded in insulators 324 and 326. Conductors 328 and 330 are used as contact plugs or wiring.

[0435] In addition, the insulator used as an interlayer film can also be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by using a planarization process such as chemical mechanical polishing (CMP).

[0436] A transistor 200 and a capacitor 460 are disposed on insulator 326. The structure of the layer on which the transistor 200 and capacitor 460 are disposed is the same as the structure described above, and is indicated by the same shading lines and symbols. Detailed structure can be found in the description above. Furthermore, an insulator 285 is disposed on insulator 283, and a conductor 413 electrically connected to conductor 240a is disposed on insulator 285. Insulator 285 can use an insulating material suitable for insulator 216. Furthermore, conductor 413 can use a conductive material suitable for conductor 242. Note that in… Figure 18 In the example shown, the opening 202a is provided not only in insulators 275, 280, 282 and 283, but also in insulator 285.

[0437] Capacitor 460 includes an oxide semiconductor 452, an oxide semiconductor 230, a conductor 242b1 on the oxide semiconductor 452, an insulator 454 on the conductor 242b1, and a conductor 456 on the insulator 454. For example... Figure 18 and Figures 19A to 19C As shown, oxide semiconductor 452 has the same structure as oxide semiconductor 230 and can be formed using the same process. Capacitor 460 and transistor 200 share conductor 242b1. Insulator 454 has the same structure as insulator 250 and can be formed using the same process. Conductor 456 has the same structure as conductor 260 and can be formed using the same process.

[0438] Here, capacitor 460 includes a conductor 242b1 serving as a first electrode, a conductor 456 serving as a second electrode, and an insulator 454 serving as a dielectric. In other words, capacitor 460 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0439] The capacitor 460 has a similar structure to the transistor 200 and can be fabricated simultaneously in the same layer as the transistor 200. Specifically, insulators 275 and 280 have openings 461 that overlap with the oxide semiconductor 452. Note that the difference between the capacitor 460 and the transistor 200 is that the conductor 242b1 is arranged to overlap with the opening 461. Therefore, the opening 461 extends to the conductor 242b1.

[0440] Insulator 454 and conductor 242b1 are disposed overlappingly inside opening 461. Here, inside opening 461, insulator 455 is disposed between the top surface of conductor 242b1, the side surface of conductor 242b2, the side surface of insulator 275, and the side surface of insulator 280 and insulator 454. Insulator 455 has the same structure as insulator 255 and can be formed using the same process.

[0441] Insulator 455 is in contact with the top surface of conductor 242b1 inside the opening 461. Insulator 454 is in contact with the top and side surfaces of insulator 455 inside the opening 461. Conductor 456 is disposed on insulator 454 inside the opening 461.

[0442] like Figure 19C As shown, the oxide semiconductor 452 of capacitor 460, like oxide semiconductor 230, has a high aspect ratio structure, and multiple oxide semiconductors 230 can be provided. Therefore, similar to oxide semiconductor 230, when viewed in cross-section in a predetermined direction, the height of oxide semiconductor 452 is greater than the width of oxide semiconductor 452. Furthermore, when viewed in planar view, one embodiment of the semiconductor device of the present invention has two or more regions where oxide semiconductor 452 and conductor 456 overlap. Therefore, the area of ​​the conductor 242b1, insulator 454, and conductor 456 disposed along the top and side surfaces of oxide semiconductor 452 can be increased. Thus, the electrostatic capacitance can be increased without increasing the occupied area of ​​capacitor 460.

[0443] like Figure 18 and Figures 19A to 19C As shown, insulator 424 has the same structure as insulator 224 and can be formed using the same process. Insulator 224 and insulator 424 are disposed on substrate 311, specifically on insulator 222. That is, insulator 224 and insulator 424 are disposed on the same formed surface of substrate 311. Furthermore, as described above, at least in the region overlapping with opening 201, the shape of insulator 224 as viewed from a planar surface is consistent with or substantially consistent with the shape of oxide semiconductor 230 as viewed from a planar surface.

[0444] The oxide semiconductor 452 is disposed in contact with the top surface of the insulator 424. In the region at least overlapping with the opening 461, the shape of the insulator 424 as viewed from a planar view is identical or substantially identical to the shape of the oxide semiconductor 452 as viewed from a planar view. The oxide semiconductor 452 overlaps with the insulator 424 as viewed from a planar view. The bottom surface of the insulator 424 contacts the insulator 222, the side surface of the insulator 424 contacts the conductor 242b1, and the top surface of the insulator 424 contacts the bottom surface of the oxide semiconductor 452.

[0445] As described above, the thickness of insulator 224 is preferably greater than the thickness of insulator 250 inside opening 201. Furthermore, insulator 424 has the same structure as insulator 224, and insulator 454 has the same structure as insulator 250. Therefore, the thickness of insulator 424 is preferably greater than the thickness of insulator 454. In this case, as... Figure 19C As shown, the bottom surface of the conductor 456 disposed inside the opening 461 can be positioned lower than the bottom surface of the oxide semiconductor 452.

[0446] Furthermore, it is preferable to provide a conductor 458 in the opening 462 formed in insulators 215, 216, 221, and 222. The conductor 458 may, for example, have the same structure as the conductor 240. The top surface of the conductor 458 contacts the bottom surface of the conductor 242b1 and can be electrically connected to the conductor 330. Note that in Figure 18 The diagram shows one conductor 458, but it is not limited to this; two or more conductors can be used to electrically connect conductor 242b1 and conductor 330. Alternatively, a structure in which a portion of conductor 242b1 is embedded in opening 462 can also be used.

[0447] By adopting the above structure, one of the source and drain electrodes of transistor 200, one electrode of capacitor 460, and the gate of transistor 310 can be electrically connected, thereby forming a 2T1C type memory cell. Alternatively, by adopting a structure without transistor 310, a 1T1C type memory cell can be formed. Furthermore, by adopting a structure without capacitor 460, a 2T0C type memory cell can also be formed.

[0448] Here, transistor 310 is preferably arranged to overlap with at least one of transistor 200 and capacitor 460. For example, a structure in which transistor 310 overlaps with transistor 200 is preferred. By adopting this structure, the occupied area of ​​the memory cell can be reduced.

[0449] Figure 20A This is a perspective view showing an example of the structure of a semiconductor device including transistors and capacitors. Figure 20B It is shown by dashed lines Figure 20A A perspective view of conductors 260 and 456, with the shaded lines omitted.

[0450] Figure 21A This is a plan view illustrating an example structure of a semiconductor device, which includes, as... Figure 20A and Figure 20B The transistor shown is transistor 200 and as a transistor Figure 20A and Figure 20B The capacitor shown has a capacitance of 460. Figure 21B It is along Figure 21A A cross-sectional view of the section marked by the dashed line C1-C2. Here, Figures 20A to 21B An example of the structure of a memory cell 100 including a transistor 200 and a capacitor 460 is shown. Figure 21A The cross-sectional views along the dashed lines D1-D2, D3-D4, and D5-D6 can be found by referring to [reference needed]. Figure 19A , Figure 19B and Figure 19C .

[0451] Figures 20A to 21B An example is shown where an oxide semiconductor 230 is disposed on an insulator 224, and insulators 255, 250, 260, 455, 454, and 456 are disposed on the oxide semiconductor 230. In other words, an example is shown where the oxide semiconductor 230 is used jointly by the transistor 200 and the capacitor 460. Furthermore, an example is shown where the insulator 224 overlaps not only with the transistor 200 but also with the capacitor 460. Therefore, it is not necessary to form patterns for the oxide semiconductor 230 and the insulator 224 for each of the transistor 200 and the capacitor 460, thus reducing the area occupied by the transistor 200 and the capacitor 460.

[0452] In addition, although Figure 18 The illustrated structure shows a transistor 310 formed on a silicon substrate, but the invention is not limited thereto. For example, as Figure 22A As shown, two transistors with the same structure (hereinafter referred to as transistor 200a and transistor 200b) can also be provided as transistor 200. Here, transistor 200a and transistor 200b are provided in the same layer and are arranged to cross each other in the channel length direction. Note that since transistor 200a and transistor 200b have the same structure as transistor 200, the constituent elements are shown with the same shading lines and symbols. Figure 22A Transistors 200a and 200b are shown to have the same characteristics as... Figure 2B and Figure 3A The transistor 200 shown is an example of the same structure.

[0453] In addition, Figure 22AIn the structure shown, a capacitor 400 is disposed on the insulator 285. The capacitor 400 includes a conductor 410 on the insulator 285, an insulator 430 on the conductor 410, and a conductor 420 on the insulator 430. Conductors 240b, insulator 241b, conductor 240c, and insulator 241c are disposed in contact with the bottom surface of conductor 410. Here, conductor 240c and insulator 241c are disposed in a manner that embeds them in the openings 202c of insulators 282, 283, and 285, and have the same structure as conductors 240b and insulator 241c. The bottom surface of conductor 240c is in contact with the top surface of conductor 260 of transistor 200b. By adopting this structure, one of the source and drain electrodes of transistor 200a, one electrode of capacitor 400, and the gate of transistor 200b are electrically connected.

[0454] The capacitor 400 includes a conductor 410 serving as a first electrode, a conductor 420 serving as a second electrode, and an insulator 430 serving as a dielectric. That is, the capacitor 400 constitutes a MIM capacitor.

[0455] Conductors 410 and 420 can be made of conductive materials suitable for conductor 260. For example, conductors 410 and 420 can be made of tungsten. Here, by employing a structure where conductor 420 covers conductor 410, conductor 420 can be used as a capacitor 400 on the side of conductor 410. This increases the electrostatic capacitance of capacitor 400. Additionally, conductor 413 can be formed simultaneously with conductor 410.

[0456] Conductors 410, 413, and 420 have a single-layer structure, but are not limited to this structure; they may also have a stacked structure of two or more layers. For example, a stacked structure of a barrier conductor and a highly conductive conductor may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0457] The insulator 430 included in the capacitor 400 is preferably made of a high-k material. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. By using such a high-k material, the thickness of the insulator 430 can be set to a level that suppresses leakage current, and the electrostatic capacitance of the capacitor 400 can be sufficiently ensured. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to deposit it using a deposition method with good coverage, such as ALD or CVD.

[0458] Alternatively, the insulator 430 may also have a multilayer structure. Preferably, a multilayer structure is used, consisting of a high-k material and a material with a higher dielectric strength than the high-k material. Materials with high dielectric strength (relatively low dielectric constant) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, and silicon oxide with both carbon and nitrogen. The insulator 430 may also have a multilayer structure consisting of a high-k aluminum oxide and a high-dielectric-strength silicon oxide layer on the aluminum oxide.

[0459] Alternatively, for example, an insulator 430 can be made by sequentially stacking zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, for example, an insulator sequentially stacked with zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film sequentially stacked with hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulator with high dielectric strength, such as aluminum oxide, the dielectric strength is increased, thereby suppressing electrostatic discharge damage to the capacitor 400.

[0460] Alternatively, insulator 430 can also be made of a material that is ferroelectric. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X Metal oxides such as (X is a real number greater than 0). Additionally, materials that can exhibit ferroelectric properties include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Furthermore, materials that can exhibit ferroelectric properties include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0461] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, indium, etc. Element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to element M2 can be appropriately set. Additionally, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. The ratio of the number of atoms of element M1, element M2, and element M3 can be appropriately set.

[0462] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0463] Note that while examples of metal oxides and metal nitrides are shown in the above description, the invention is not limited to these. For example, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal nitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0464] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Alternatively, the insulator 430 can have a multilayer structure composed of multiple materials selected from the above-mentioned materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0465] Note that in Figure 22A In the storage device shown, the capacitor 400 is planar in shape, but the storage device shown in this embodiment is not limited to this. For example, the capacitor 400 may also be cylindrical or columnar.

[0466] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. As the insulator 487, an insulator with the function of trapping or fixing hydrogen is preferably used. For example, alumina is preferably used for the insulator 487. As the insulator 488, an insulator with the function of inhibiting hydrogen diffusion is preferably used. For example, silicon nitride, which has higher hydrogen barrier properties, is preferably used for the insulator 488.

[0467] In addition, although Figure 22AThe diagram shows a structure in which transistors 200a and 200b are disposed in the same layer, but the invention is not limited thereto. For example, as Figure 22B As shown, a layer 401a including transistor 200a can also be stacked on a layer 401b including transistor 200b. Note that layers 401a and 401b have the same characteristics as... Figure 22A The layers of insulators 215 to 285 shown have the same structure.

[0468] like Figure 22B As shown, conductors 240c and insulators 241c can be formed in the openings 202c provided in the insulators 282 to 285 of layer 401b and insulators 215 to 285 of layer 401a. With this structure, conductor 410 of capacitor 400 can be electrically connected to conductor 260 of transistor 200b. Furthermore, conductor 410 and conductor 260 of transistor 200b do not need to be connected only by conductor 240c. Two or more conductors can also be used to electrically connect conductor 410 to conductor 260 of transistor 200b.

[0469] Here, transistor 200b is preferably arranged to overlap with at least one of transistor 200a and capacitor 400. For example, it is preferable that the oxide semiconductor 230 of transistor 200b overlaps with at least one of the oxide semiconductor 230 of transistor 200a and conductor 410 of capacitor 400. By adopting this structure, the occupied area of ​​the memory cell can be reduced.

[0470] Figure 23 It shows that Figure 21A The diagram shows an example of a matrix of storage cells 100 arranged in two rows and two columns. Figure 24A It is along Figure 23 A cross-sectional view of the section marked with dashed lines E1-E2. Figure 23 In the diagram, the storage units 100 in the first row and first column, the first row and second column, the second row and first column, and the second row and second column are respectively designated as storage unit 100_11, storage unit 100_12, storage unit 100_21, and storage unit 100_22. Note that in... Figure 23 In the image, oxide semiconductor 230, conductor 260, conductor 456 and conductor 413 are shaded.

[0471] In addition, Figure 23 and Figure 24AIn this document, the transistors 200 included in storage units 100_11, 100_12, 100_21, and 100_22 are respectively designated as transistor 200_11, transistor 200_12, transistor 200_21, and transistor 200_22. Furthermore, the capacitors 460 included in storage units 100_11, 100_12, 100_21, and 100_22 are respectively designated as capacitor 460_11, capacitor 460_12, capacitor 460_21, and capacitor 460_22. Furthermore, the conductors 242b included in storage units 100_11, 100_12, 100_21 and 100_22 are respectively referred to as conductors 242b_11, 242b_12, 242b_21 and 242b_22.

[0472] like Figure 23 As shown, when viewed from a planar perspective, conductor 260, insulator 250, and insulator 255 have regions extending in the row direction. Therefore, transistors 200 on the same row share conductor 260, insulator 250, and insulator 255. Consequently, the first gate electrodes of transistors 200 on the same row are electrically connected to each other.

[0473] Here, the conductor 260, insulator 250, and insulator 255 included in transistors 200_11 and 200_12 are respectively designated as conductor 260_1, insulator 250_1, and insulator 255_1. Furthermore, the conductor 260, insulator 250, and insulator 255 included in transistors 200_21 and 200_22 are respectively designated as conductor 260_2, insulator 250_2, and insulator 255_2. Moreover, in... Figure 24A In this context, the opening 201 containing conductor 260_1, insulator 250_1 and insulator 255_1 is referred to as opening 201_1, and the opening 201 containing conductor 260_2, insulator 250_2 and insulator 255_2 is referred to as opening 201_2.

[0474] In addition, such as Figure 23 As shown, when viewed from a planar perspective, conductor 456, insulator 454, and insulator 455 have regions extending in the row direction. Therefore, capacitors 460 in the same row share conductor 456, insulator 454, and insulator 455. Consequently, the second electrodes of capacitors 460 in the same row are electrically connected to each other. Furthermore, capacitors 460 in the same column can also share conductor 456, insulator 454, and insulator 455. Alternatively, for example, all capacitors 460 can also share conductor 456.

[0475] Here, the conductor 456, insulator 454, and insulator 455 included in capacitors 460_11 and 460_12 are respectively designated as conductor 456_1, insulator 454_1, and insulator 455_1. Furthermore, the conductor 456, insulator 454, and insulator 455 included in capacitors 460_21 and 460_22 are respectively designated as conductor 456_2, insulator 454_2, and insulator 455_2. Moreover, in... Figure 24A In this design, the opening 461 containing conductor 456_1, insulator 454_1, and insulator 455_1 is designated as opening 461_1, and the opening 461 containing conductor 456_2, insulator 454_2, and insulator 455_2 is designated as opening 461_2. Alternatively, conductor 456_1 and conductor 456_2 can also be electrically connected. In this case, conductor 456_1 and conductor 456_2 can be considered as a single conductor.

[0476] Storage cells 100_11 and 100_21 share an insulator 224 and an oxide semiconductor 230. Storage cells 100_12 and 100_22 also share an insulator 224 and an oxide semiconductor 230. Here, the insulator 224 and oxide semiconductor 230 included in storage cells 100_11 and 100_21 are respectively designated as insulator 224_1 and oxide semiconductor 230_1. Furthermore, the insulator 224 and oxide semiconductor 230 included in storage cells 100_12 and 100_22 are respectively designated as insulator 224_2 and oxide semiconductor 230_2.

[0477] Transistors 200_11 and 200_21 share conductor 242a. Additionally, transistors 200_12 and 200_22 also share conductor 242a. Here, the conductor 242a included in transistors 200_11 and 200_21 is designated as conductor 242a_1. Furthermore, the conductor 242a included in transistors 200_12 and 200_22 is designated as conductor 242a_2.

[0478] Conductors 242a_1, 242a_2, 242b_11, 242b_12, 242b_21, and 242b_22 may each have a two-layer stacked structure. The lower layer (equivalent to conductor 242a1) of conductors 242a_1 and 242a_2 respectively has a region that protrudes towards the opening 201 than the upper layer (equivalent to conductor 242a2) of conductors 242a_1 and 242a_2. The lower layer (equivalent to conductor 242b1) of conductors 242b_11, 242b_12, 242b_21 and 242b_22 has a region that protrudes toward the opening 201 from the upper layer (equivalent to conductor 242b2) of conductors 242b_11, 242b_12, 242b_21 and 242b_22.

[0479] When viewed in cross-section along the channel length of transistor 200_11, the distance between the lower layers of conductor 242a_1 and conductor 242b_11 is smaller than the distance between the upper layers of conductor 242a_1 and conductor 242b_11. Furthermore, when viewed in cross-section along the channel length of transistor 200_21, the distance between the lower layers of conductor 242a_1 and conductor 242b_21 is smaller than the distance between the upper layers of conductor 242a_1 and conductor 242b_21. Additionally, although in Figure 24A Although not shown in the diagram, when viewed in cross-section along the channel length of transistor 200_12, the distance between the lower layers of conductor 242a_2 and conductor 242b_12 is less than the distance between the upper layers of conductor 242a_2 and conductor 242b_12. Furthermore, when viewed in cross-section along the channel length of transistor 200_22, the distance between the lower layers of conductor 242a_2 and conductor 242b_22 is less than the distance between the upper layers of conductor 242a_2 and conductor 242b_22.

[0480] By adopting the above structure, the distance between the source and drain can be further shortened, and the channel length can be shortened accordingly. Therefore, as described above, the frequency characteristics of the transistor 200 can be improved. Thus, a semiconductor device with high operating speed can be provided.

[0481] Insulators 275, 280, 282, 283, and 285 are provided with openings 202a leading to conductors 242a_1 and 242a_2. Figure 24AIn this context, the opening 202a leading to the conductor 242a_1 is designated as opening 202a_1. Furthermore, the insulator 241a and conductor 240a disposed inside the opening 202a_1 are designated as insulator 241a_1 and conductor 240a_1, respectively. Moreover, in... Figure 23 In this context, the conductor 240a disposed inside the opening 202a that reaches the conductor 242a_2 is referred to as conductor 240a_2.

[0482] Viewed from a planar perspective, the conductor 413 has a region extending in the column direction. Thus, the conductors 242a included in the transistors 200 on the same column are electrically connected to each other. Here, in Figure 23 and Figure 24A In this context, the conductor 413, which is electrically connected to conductors 242a_1 and 240a_1, is denoted as conductor 413_1. Additionally, in... Figure 23 In this context, the conductor 413 that is electrically connected to conductor 242a_2 and conductor 240a_2 is referred to as conductor 413_2.

[0483] like Figure 23 and Figure 24A As shown, the oxide semiconductor 230 disposed in memory cell 100_11 and the oxide semiconductor 230 disposed in memory cell 100_21 are not separated but are configured as a single oxide semiconductor 230_1. Furthermore, as... Figure 23 As shown, the oxide semiconductor 230 disposed in memory cell 100_12 and the oxide semiconductor 230 disposed in memory cell 100_22 are not separated but are configured as a single oxide semiconductor 230_2. Thus, for example, when multiple memory cells 100 in adjacent rows share the oxide semiconductor 230, the memory cells 100 can be configured with high density. This enables high integration of the semiconductor device. Furthermore, it simplifies the manufacturing process of the semiconductor device.

[0484] Figure 24B It is shown Figure 24A The cross-sectional view shown is of an example of the oxide semiconductor 230_1 separated by memory cell 100. Figure 24B In this context, the oxide semiconductor 230 included in the storage unit 100_11 is denoted as oxide semiconductor 230_11, and the oxide semiconductor 230 included in the storage unit 100_21 is denoted as oxide semiconductor 230_21.

[0485] like Figure 24B As shown, when the oxide semiconductor 230 is separated according to the memory cell 100, and as... Figure 24ACompared to the case where multiple memory cells 100 share the oxide semiconductor 230, it is easier to independently drive the transistors of each memory cell. Furthermore, the reliability of each memory cell can be improved. On the other hand, as shown... Figure 24A As shown, in the case where multiple memory cells 100 share the oxide semiconductor 230, and as... Figure 24B Compared to the case where the oxide semiconductor 230 is separated according to the memory cell 100, the memory cells 100 can be configured with a high density.

[0486] Materials Constituting Semiconductor Devices The following describes the materials that can be used to construct semiconductor devices. Note that the layers constituting a semiconductor device can have a single-layer structure or a stacked structure.

[0487] <<Substrate>> Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Additionally, examples of substrates include substrates containing metal nitrides, substrates containing metal oxides, insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Alternatively, substrates on which one or more elements are disposed can also be used. Examples of components disposed on a substrate include capacitors, resistors, switches, light-emitting elements, and storage elements.

[0488] <<Insulators>> As an insulator that can be used in at least one of insulators 215, 216, 221, 222, 223, 224, 225, 241, 250, 255, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 424, 430, 454, 455, 487, and 488, examples of insulating oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides can be cited.

[0489] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the gate insulator, such as insulator 250, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a low relative permittivity as the insulator used as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0490] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0491] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0492] Furthermore, by surrounding a transistor using metal oxides with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of one or more insulators selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0493] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that has been removed by heating is contacted with an oxide semiconductor, the oxygen vacancies contained in the oxide semiconductor can be filled.

[0494] <<Conductors>> As a conductor that can be used in at least one of conductors 205, 240, 242, 260, 316, 328, 330, 410, 413, 420, 456, and 458, examples of conductors include metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the aforementioned metallic elements, or alloys combining the aforementioned metallic elements. Furthermore, examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred materials as they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicides can also be used.

[0495] When using a conductor with a multilayer structure, for example, a multilayer structure combining a material containing the aforementioned metal element and a conductive material containing oxygen, a multilayer structure combining a material containing the aforementioned metal element and a conductive material containing nitrogen, or a multilayer structure combining a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may also be used.

[0496] Furthermore, when using oxides in the channel formation region of a transistor, the conductor used as the gate electrode, such as conductor 260, preferably employs a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0497] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can also be used. Additionally, one or more of the following can be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon. Furthermore, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0498] <Examples of Semiconductor Device Manufacturing Methods> The following is for reference Figures 25A to 41D An example of a method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Here, manufacturing... Figures 1A to 3B The case of the semiconductor device shown will be used as an example for explanation.

[0499] exist Figures 25A to 41D Unless otherwise stated, A in each figure is a plan view. B in each figure is a cross-sectional view along the dashed line A1-A2 in figure A, which corresponds to a cross-sectional view along the channel width direction of transistor 200. C in each figure is a cross-sectional view along the dashed line A3-A4 in figure A, which corresponds to a cross-sectional view along the channel width direction of transistor 200. D in each figure is a cross-sectional view along the dashed line B1-B2 in figure A, which corresponds to a cross-sectional view along the channel length direction of transistor 200.

[0500] The insulating materials used to form insulators, the conductive materials used to form conductors, or the semiconductor materials used to form semiconductors can be deposited using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.

[0501] Note that examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing conductive metal films. Additionally, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0502] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0503] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the processed material can be reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage these components. On the other hand, since such plasma damage does not occur in thermal CVD, the yield of semiconductor devices can be improved. Additionally, since plasma damage during deposition is eliminated in thermal CVD, films with fewer defects can be obtained.

[0504] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0505] CVD and ALD methods differ from sputtering methods that deposit particles released from a target or similar material. Therefore, ALD is a deposition method that is less affected by the shape of the workpiece and exhibits good step coverage. In particular, ALD offers excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0506] Furthermore, when using CVD, films of arbitrary composition can be deposited by adjusting the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio simultaneously with deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple deposition chambers because the time required for transport or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0507] When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, films of arbitrary composition can be deposited.

[0508] First, prepare a substrate (not shown), and deposit an insulator 215 (see reference) on the substrate. Figures 25A to 25D As described above, insulator 215 can be the same insulator as any one or more of the laminated films of insulators 282 and 283. As a deposition method for insulator 215, sputtering, CVD, MBE, PLD, or ALD can be used, for example. Sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, reduces the hydrogen concentration in insulator 215, and is therefore preferred.

[0509] Next, insulator 216 is deposited on insulator 215. Insulator 216 is preferably deposited using a sputtering method. By using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in insulator 216 can be reduced. Note that the deposition of insulator 216 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used. In this embodiment, silicon oxide is deposited using a sputtering method as insulator 216.

[0510] Insulators 215 and 216 are preferably deposited continuously without exposure to the atmosphere. For example, a multi-chamber deposition apparatus is preferred. This reduces hydrogen in the film during deposition of insulators 215 and 216 and suppresses hydrogen incorporation into the film between deposition steps.

[0511] Here, by forming an opening 203 in the insulator 216 leading to the insulator 215 and forming a conductor 205 inside the opening 203, a conductor can be formed. Figures 17A to 17D The transistor 200 is shown. The conductor 205 can be formed by depositing a conductive film suitable for the conductor 205 in a manner that fills the opening 203, and then removing a portion of the conductive film by CMP treatment.

[0512] Next, insulator 221 is deposited on insulator 216 (see reference). Figures 25A to 25D ).

[0513] The insulator 221 is preferably an insulator that blocks oxygen, hydrogen, and water as described above. The insulator 221 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon nitride is deposited using the PEALD method as the insulator 221.

[0514] Next, insulator 222 is deposited on insulator 221 (see reference). Figures 25A to 25D ).

[0515] The insulator 222 is preferably deposited with an oxide containing one or both of aluminum and hafnium. For example, aluminum oxide, hafnium oxide, or hafnium aluminate are preferred as the insulator containing one or both of aluminum and hafnium. Alternatively, hafnium zirconium oxide is preferred. The insulator containing one or both of aluminum and hafnium oxide provides a barrier against oxygen, hydrogen, and water. When the insulator 222 provides a barrier against hydrogen and water, the diffusion of hydrogen and water from the structure surrounding the transistor through the insulator 222 to the inside of the transistor can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0516] The insulator 222 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using thermal ALD.

[0517] In this embodiment, silicon nitride is deposited using the PEALD method as insulator 221, and hafnium oxide is deposited using the thermal ALD method as insulator 222. Thus, by using silicon nitride, which has the function of suppressing hydrogen diffusion, as insulator 221, hydrogen diffusion from the lower layer of transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has the function of trapping or fixing hydrogen, as insulator 222, hydrogen contained in oxide semiconductor 230 can be trapped or fixed by insulator 222. This reduces the hydrogen concentration in and around oxide semiconductor 230.

[0518] Next, an insulating film 224f, which forms insulator 224, is deposited on insulator 222 (see reference). Figures 25A to 25D ).

[0519] As the insulating film 224f, it is preferable to deposit an insulating film that traps or immobilizes hydrogen. This suppresses the diffusion of hydrogen from the structure surrounding the transistor through the insulator 224 to the inside of the transistor, thereby reducing VoH in the channel formation region. Furthermore, a high-k material is preferably deposited as the insulating film 224f. This allows the insulator 224 to be easily used as the gate insulator, and the oxide semiconductor 230 can be used entirely as the channel formation region.

[0520] As the insulating film 224f, a metal oxide having an amorphous structure is preferably deposited. As the metal oxide, an oxide containing one or both of aluminum and hafnium is preferred, specifically hafnium silicate. The insulating film 224f can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods.

[0521] When depositing a hafnium silicate film as an insulating film 224f, the deposition method described above can use a deposition gas containing hafnium and silicon, or a deposition target. For example, a co-sputtering method using a silicon oxide target and a hafnium oxide target can be used. Alternatively, a thermal ALD method using hafnium tetrachloride and silicon tetrachloride as precursors can be used. Furthermore, for example, silicon can be added to a hafnium oxide film after deposition using the above methods to form a hafnium silicate film. As a method for adding silicon, for example, ion implantation, where the source gas is ionized and mass-separated to add the ions, or ion doping, where the source gas is ionized and the ions are added without mass separation, can be used.

[0522] Next, an insulating film is deposited on the insulating film 224f, and the insulating film is etched to form the insulator 223 (see reference). Figures 25A to 25D Insulator 223 is used as a template for forming oxide semiconductor 230. As insulator 223, for example, an insulator suitable for at least one of insulators 216, 221, and 222 can be used. As insulator 223, for example, aluminum oxide, silicon nitride, or silicon oxide can be used. In particular, when silicon nitride or silicon oxynitride is used as insulator 223, the diffusion of hydrogen from insulator 223 to oxide semiconductor film 230f and the diffusion of oxygen from oxide semiconductor film 230f to insulator 223 can be suppressed. Therefore, the reliability of transistor 200 can be improved, and it is preferred. Insulator 223 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods.

[0523] The insulator 223 can have a stacked structure of two or more layers. For example, a stacked structure of two or more layers formed using different deposition methods can be used. For example, a stacked structure of a layer formed by ALD and a layer formed by sputtering on that layer can be used. Thus, the processing of the insulating film 224f can sometimes be suppressed. Specifically, it can sometimes be suppressed that a portion of the region of the insulating film 224f overlapping with the insulator 223 is removed. In this case, in subsequent processes, the oxide semiconductor film 230f can cover the insulator 223 with high coverage.

[0524] When silicon nitride is used as insulator 223, silicon oxide or aluminum oxide can be used as insulator 222, and hafnium oxide can be used as insulating film 224f. Alternatively, hafnium oxide can be used as insulator 222, and silicon oxide or aluminum oxide can be used as insulating film 224f.

[0525] The insulator 223 is fabricated into an island shape, for example, using photolithography. This fabrication can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. In this embodiment, as... Figure 25A and Figure 25BAs shown, two columnar insulators 223 are arranged in the A1-A2 direction to form the structure.

[0526] like Figure 25B and Figure 25C As shown, the side surface of insulator 223 can also be perpendicular or substantially perpendicular to the top surface of insulator 222. By adopting this structure, a smaller area and higher density can be achieved when multiple transistors are arranged.

[0527] Next, an oxide semiconductor film 230f, which is formed as an oxide semiconductor 230, is deposited in a manner that covers the insulator 223 (see reference). Figures 26A to 26D The oxide semiconductor film 230f is a metal oxide film that becomes oxide semiconductor 230 in subsequent processes, and the aforementioned metal oxide film can be used. The oxide semiconductor film 230f can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0528] Since the oxide semiconductor film 230f is deposited along the insulator 223, it preferably has high coverage. Therefore, the oxide semiconductor film 230f is preferably deposited using a high-coverage ALD method or the like. The aspect ratio of the oxide semiconductor film 230 is preferably high. Therefore, the thickness of the oxide semiconductor film 230f is preferably small. Therefore, it is preferable to deposit the oxide semiconductor film 230f using an ALD method that allows for thickness adjustment with a small thickness. By depositing the oxide semiconductor film 230f in this way, the oxide semiconductor film 230f is formed in contact with the top and side surfaces of the insulator 223.

[0529] Here, the oxide semiconductor film 230f is preferably deposited using the same method as the oxide semiconductor 30 described above. By forming the oxide semiconductor film 230f in this way, for example, the oxide semiconductor film 230f and the oxide semiconductor 230 can be formed in a manner that effectively covers the insulator 223.

[0530] For example, such as Figure 4B and Figure 4CAs shown, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductor 230a to oxide semiconductor 230c, for example, films of oxide semiconductor 230a and oxide semiconductor 230c can be deposited using the ALD method, and a film of oxide semiconductor 230b can be deposited using the sputtering method. Specifically, the film of oxide semiconductor 230a can be deposited with an In:Zn ratio of 2:1 or a composition close to that of indium. Alternatively, indium oxide can be used to form the film of oxide semiconductor 230a. Furthermore, the film of oxide semiconductor 230b can be deposited using an oxide target with an In:Sn:Zn ratio of 4:0.1:1 or a composition close to that of indium. Similarly, the film of oxide semiconductor 230c can be deposited with an In:Zn ratio of 2:1 or a composition close to that of indium. Alternatively, indium oxide can be used to form the film of oxide semiconductor 230c.

[0531] Next, a heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range where the oxide semiconductor film 230f does not become polycrystalline. The heat treatment of the oxide semiconductor film 230f can be performed using the same method as the heat treatment of the oxide semiconductor 30 described above.

[0532] For example, as a heat treatment, it can be carried out for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 450°C.

[0533] By depositing oxide semiconductor 230 using the above method and then performing heat treatment, oxide semiconductor 230 can be made into AG CAAC. This improves the on-state current, S-value, field-effect mobility, and frequency characteristics of transistor 200, thus providing a semiconductor device with excellent electrical characteristics. Furthermore, a highly reliable semiconductor device can be provided.

[0534] The heat treatment is preferably carried out in a nitrogen atmosphere or an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can be carried out in a nitrogen atmosphere or an inert gas atmosphere, and then, to replenish the removed oxygen, the heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0535] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content in the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the oxide semiconductor film 230f can be prevented as much as possible. In addition, the high-purity gas can also be used for heat treatment before and after this process.

[0536] Furthermore, the aforementioned heat treatment containing oxygen gas reduces impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. By reducing impurities in the film, the crystallinity of the oxide semiconductor film 230f is improved, enabling a denser structure. Therefore, the crystalline region in the oxide semiconductor film 230f can be increased, and the in-plane non-uniformity of the crystalline region can be reduced. Consequently, the in-plane non-uniformity of the transistor's electrical characteristics can be reduced.

[0537] Furthermore, by performing a heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, thereby reducing oxygen vacancies in the oxide semiconductor film 230f. This improves the reliability of the transistor 200.

[0538] Furthermore, through heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulating film 224f and is absorbed by the insulating film 224f. In other words, hydrogen in the oxide semiconductor film 230f diffuses to the insulating film 224f. Therefore, although the hydrogen concentration in the insulating film 224f increases, the hydrogen concentration in the oxide semiconductor film 230f decreases. Additionally, by providing an insulator 221 under the insulating film 224f, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0539] In particular, the oxide semiconductor film 230f (the oxide semiconductor 230 in the following text) is used as the channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f with a reduced hydrogen concentration has high reliability and is therefore preferred.

[0540] Furthermore, it is preferable to perform a process to improve the crystallinity of the oxide semiconductor film 230f during or after deposition of the oxide semiconductor film 230f. Examples of processes to improve the crystallinity of the oxide semiconductor film 230f include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation. Alternatively, multiple of these processes may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0541] Furthermore, it is more preferable to perform multiple treatments to improve the crystallinity of the oxide semiconductor film 230f during deposition. For example, when forming the oxide semiconductor film 230f using the ALD method, it is preferable to perform microwave plasma treatment after each atomic layer is formed. Alternatively, by performing crystallinity-improving treatments after each oxide semiconductor film 230f with a predetermined thickness, productivity can be increased, which is therefore preferred. Specifically, it is preferable to form a first oxide semiconductor film of 1 nm or more and 10 nm or less as the oxide semiconductor film 230f, perform a first microwave plasma treatment, and then form a second oxide semiconductor film of 1 nm or more and 10 nm or less, and perform a second microwave plasma treatment. There are no particular limitations on the deposition methods of the first and second oxide semiconductor films; the ALD method or sputtering method can be used. In particular, by depositing the first oxide semiconductor film using the ALD method, it is preferable to prevent elements constituting the formed surface layer from mixing into the first and second oxide semiconductor films (also known as mixing). In particular, this method is suitable for cases where the element contained in the layer constituting the formed surface hinders the crystallization of the oxide semiconductor (e.g., the presence of silicon, carbon, etc.). Furthermore, the first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Additionally, a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is shown here, but the method is not limited to this. The same treatment can be applied even if the oxide semiconductor film 230f has a single-layer structure or a stacked structure of three or more layers.

[0542] Alternatively, a treatment to improve the crystallinity of the oxide semiconductor film 230f can be performed after deposition. Specifically, this treatment can be performed directly on the deposited oxide semiconductor film 230f, or it can be performed through another film, such as an insulating film, deposited on the oxide semiconductor film 230f. For example, microwave plasma treatment can be performed after deposition of the oxide semiconductor film 230f, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) can be deposited after deposition of the oxide semiconductor film 230f, and then the oxide semiconductor film 230f can be subjected to heat treatment or microwave plasma treatment through the insulating film.

[0543] The aforementioned treatment to improve the crystallinity of the oxide semiconductor film 230f can also serve as a treatment to remove impurities contained in the oxide semiconductor film 230f. For example, carbon, hydrogen, nitrogen, etc., contained in the oxide semiconductor film 230f can be appropriately removed. Alternatively, by performing the treatment to improve the crystallinity of the oxide semiconductor film 230f under an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor film 230f can be reduced.

[0544] When performing a process to improve the crystallinity of the oxide semiconductor film 230f, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower. Furthermore, the heat treatment temperature is preferably 100°C or higher and 700°C or lower, or 300°C or higher and 450°C or lower.

[0545] By improving the crystallinity of the oxide semiconductor film 230f, a transistor with high reliability can be realized.

[0546] In addition, such as Figure 27A As shown, an oxide semiconductor film 230f can also be formed on layer 231 after covering the insulator 223. This prevents the oxide semiconductor film 230f from contacting the insulator 223. This also prevents impurities from contaminating the oxide semiconductor film 230f. For example, it can suppress the contamination of constituent elements of the insulator 223 (such as silicon) and impurities contained in the insulator 223 (such as hydrogen) into the oxide semiconductor film 230f. Therefore, by forming layer 231, the reliability of the transistor 200 can sometimes be improved. Note that... Figure 27A It is a cross-sectional view along the A1-A2 direction.

[0547] Layer 231 preferably contains elements from the oxide semiconductor film 230f. For example, layer 231 preferably contains one or both of gallium and zinc. Alternatively, layer 231 preferably contains one or both of gallium oxide and zinc oxide. This suppresses variations in the electrical characteristics of the transistor 200 caused by impurities incorporating into the oxide semiconductor film 230f. For example, even when silicon oxide or silicon nitride is used as the insulator 223, the incorporation of silicon into the oxide semiconductor film 230f can be suppressed, preventing the formation of a CAAC structure within the oxide semiconductor film 230f. Therefore, the reliability of the transistor 200 can be improved.

[0548] Alternatively, a hydrogen barrier insulator can be used for layer 231. For example, silicon nitride or silicon oxynitride can be used as layer 231. Therefore, even if the insulator 223 contains impurities (such as hydrogen), hydrogen diffusion to the oxide semiconductor film 230f can be suppressed. Thus, the reliability of the transistor 200 can be improved.

[0549] When the thickness of layer 231 is less than or equal to the thickness of oxide semiconductor film 230f, transistor 200 can be miniaturized, which is therefore preferred. The thickness of layer 231 is preferably 0.01 nm or more and 100 nm or less, more preferably 0.01 nm or more and 50 nm or less, even more preferably 0.01 nm or more and 20 nm or less, even more preferably 0.01 nm or more and 10 nm or less, still more preferably 0.1 nm or more and 10 nm or less, and still more preferably 1 nm or more and 10 nm or less. For example, in order to form a layer 231 with such a small thickness in a way that provides high coverage over insulator 223, it is preferable to form layer 231 using the ALD method. Note that layer 231 can also be deposited, for example, using sputtering, CVD, MBE, or PLD methods.

[0550] Figure 27B An example is shown where layer 231 has a stacked structure of layer 231a and layer 231b on layer 231a. Layer 231a can be used for... Figure 27A The material of layer 231 shown. Layer 231a can be, for example, gallium oxide or zinc oxide.

[0551] Layer 231b preferably contains the metal element contained in the oxide semiconductor film 230f. As layer 231b, it is preferable to use an oxide containing a metal element that is contained in the oxide semiconductor film 230f but not in layer 231a. For example, if indium gallium zinc oxide is used as the oxide semiconductor film 230f and gallium oxide or zinc oxide is used as layer 231a, indium zinc oxide is preferably used as layer 231b. In this case, the composition of layer 231b can be set to In:Zn = 2:1 [atomic ratio] or close to it. Alternatively, the composition of layer 231b can be set to In:Zn = 1:1 [atomic ratio] or close to it, or In:Zn = 4:1 [atomic ratio] or close to it.

[0552] The thickness of layer 231a can be Figure 27A The thickness of layer 231a can be within a desirable range. For example, the thickness of layer 231a can be 0.01 nm or more and 100 nm or less, preferably 0.01 nm or more and 10 nm or less, more preferably 0.1 nm or more and 10 nm or more, even more preferably 0.1 nm or more and 5 nm or more, even more preferably 0.1 nm or more and 3 nm or more, even more preferably 0.1 nm or more and 2 nm or more, and even more preferably 0.1 nm or more and 1 nm or more.

[0553] The thickness of layer 231b can be greater than that of layer 231a. The thickness of layer 231b can be, for example, 0.1 nm or more and 200 nm or less, preferably 0.1 nm or more and 100 nm or less, more preferably 0.1 nm or more and 50 nm or less, more preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, more preferably 1 nm or more and 7 nm or less, more preferably 1 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less.

[0554] Layers 231a and 231b can be used for Figure 27A The method for forming layer 231 shown is described. In particular, when using the ALD method, layers 231a and 231b can be formed in a manner that provides high coverage over the insulator 223, which is therefore preferred.

[0555] Microwave plasma processing is preferably performed after forming layers 231a and 231b and before forming the oxide semiconductor film 230f. This allows the components contained in layer 231a and layer 231b to be alloyed. For example, when gallium oxide is used as layer 231a and indium zinc oxide as layer 231b, the alloyed region can contain indium gallium zinc oxide. This suppresses changes in the electrical characteristics of the transistor 200 caused by impurities infiltrating the oxide semiconductor film 230f. For example, with... Figure 27ACompared to the example shown, the incorporation of impurities into the oxide semiconductor film 230f is more likely to be suppressed. In this case, for example, even when silicon oxide or silicon nitride is used as the insulator 223, silicon incorporation into the oxide semiconductor film 230f can be further suppressed, making it less likely for a CAAC structure to form in the oxide semiconductor film 230f. Therefore, the reliability of the transistor 200 can be further improved.

[0556] A larger alloying region thickness tends to suppress the incorporation of impurities into the oxide semiconductor film 230f, which is preferable. The thickness of the alloying region is preferably 5% to 100% of the thickness of layer 231, more preferably 10% to 100%, further preferably 30% to 100%, and even more preferably 50% to 100%. The thickness of the alloying region can, for example, be 0.1 nm to 0.5 nm.

[0557] Note that layer 231b can sometimes be regarded as the oxide semiconductor 30a described above. In this case, the layer in oxide semiconductor film 230f that is in contact with layer 231b can be regarded as oxide semiconductor 30b.

[0558] When performing the microwave plasma treatment described above after forming layers 231a and 231b and before forming the oxide semiconductor film 230f, it is preferable to heat the substrate. The heating temperature of the substrate is room temperature (e.g., 25°C) or higher and 500°C or lower, preferably 100°C or higher and 500°C or lower, more preferably 200°C or higher and 500°C or lower, and even more preferably 250°C or higher and 450°C or lower. In addition, the power of the power supply for applying microwaves in the microwave plasma treatment apparatus is preferably 1000W or higher and 10000W or lower, more preferably 2000W or higher and 5000W or lower.

[0559] Next, a portion of the oxide semiconductor film 230f is removed by anisotropic etching (see reference). Figures 28A to 28D Specifically, for example, the oxide semiconductor film 230f is processed by anisotropic etching until the top surface of the insulator 223 is exposed, thereby removing a portion of the oxide semiconductor film 230f. In the oxide semiconductor film 230f, a region mainly parallel to the substrate surface is etched to form a sidewall-shaped oxide semiconductor 230 in contact with the side surface of the insulator 223. Note that when removing a portion of the oxide semiconductor film 230f by anisotropic etching, an insulator serving as a hard mask may also be provided in that portion. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, etc., can be suitable as this insulating film.

[0560] Anisotropic etching can form an oxide semiconductor 230 with a high aspect ratio. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupied area, thus improving the on-state current and frequency characteristics of the transistor 200. Furthermore, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupied area, thus improving the on-state current and frequency characteristics of the transistor 200.

[0561] In addition, such as Figure 28A As shown, the oxide semiconductor 230, when viewed from a planar perspective, has a ring shape with both ends being equal or substantially equal. The oxide semiconductor 230 can also be described as having a shape including an opening in its central portion. Furthermore, as described above, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, as a ring-shaped oxide semiconductor 230, oxide semiconductors 230a, 230b, and 230c are sequentially formed with the region where the insulator 223 is formed as the center. Therefore, as... Figure 9A As shown, when viewed in cross-section along the channel width direction of transistor 200, oxide semiconductors 230c, 230b, 230a, 230b, and 230c are arranged symmetrically in sequence.

[0562] Furthermore, while the above description describes a structure with two annular oxide semiconductors 230, the present invention is not limited thereto. For example, one or more annular oxide semiconductors 230 may be provided. Additionally, an oxide semiconductor 230 with a shape including multiple openings may be formed by combining the annular oxide semiconductors 230. For example, as... Figure 6A As shown, an oxide semiconductor 230 can also be formed with three openings arranged in the A1-A2 direction when viewed from a planar perspective. In this case, Figures 25A to 25D In the process shown, three insulators 223 are formed in a short, adjacent manner. Additionally, for example, as... Figure 6B As shown, an oxide semiconductor 230 that appears as a lattice when viewed from a planar surface can also be formed. At this time, in Figures 25A to 25D In the process shown, a grid-like groove is formed in the insulator 223.

[0563] In addition, Figure 28A In this process, the oxide semiconductor 230 appears ring-shaped when viewed from a planar perspective, and a portion of the oxide semiconductor 230 can be further removed by etching. For example, in Figure 28A In the structure shown, a portion of it can also be removed so that the oxide semiconductor 230 is a rectangle extending in the B1-B2 direction when viewed from the plane.

[0564] When performing anisotropic etching on the oxide semiconductor film 230f, dry etching is preferred.

[0565] As etching gases for dry etching, halogen-containing etching gases can be used. Specifically, etching gases containing one or more of fluorine, chlorine, and bromine can be used. For example, as etching gases, one or more of the following gases can be used: C4F6, C5F6, C4F8, CF4, SF6, CHF3, CH2F2, Cl2, BCl3, SiCl4, and BBr3. Additionally, oxygen, carbon dioxide, nitrogen, helium, argon, hydrogen, or hydrocarbon gases can be appropriately added to the above etching gases. Furthermore, depending on the material being processed in the dry etching process, gases containing hydrocarbon gases or hydrogen gases but not halogen gases can also be used as etching gases. As hydrocarbons used for etching gases, methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H4H6) can be used. 10 One or more of the following: ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4). Etching conditions can be appropriately set according to the object being etched.

[0566] Alternatively, a capacitively coupled plasma (CCP) etching apparatus, including parallel planar electrodes, can be used as a dry etching device. This apparatus can also employ a structure where a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure where a high-frequency voltage of the same frequency is applied to each of the parallel planar electrodes can be used. Furthermore, a structure where multiple different high-frequency voltages are applied to the parallel planar electrodes can also be used. This type of CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, for example, a structure where high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a structure where multiple different high-frequency voltages are applied to one of the parallel planar electrodes can also be used. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus with a high-density plasma source. The etching apparatus can be appropriately configured according to the object being etched. Note that in the aforementioned dry etching apparatus, reactive ion etching can be performed by generating a self-biased potential by applying a high-frequency voltage to an electrode on one side of the substrate. In reactive ion etching, etching is performed by accelerating ions in the plasma to collide with the workpiece, thus enabling highly anisotropic etching processes.

[0567] Note that, in such Figure 27A or Figure 27B When layer 231 is formed as shown, a portion of layer 231, in addition to a portion of the oxide semiconductor film 230f, is also removed by anisotropic etching. Specifically, for example, the oxide semiconductor film 230f and layer 231 are processed by anisotropic etching until the top surface of the insulator 223 is exposed, thereby removing a portion of the oxide semiconductor film 230f and a portion of layer 231. At this time, layer 231 has a sidewall-like structure in contact with the side surface of the insulator 223, and a sidewall-like oxide semiconductor 230 is formed on the outer side of layer 231.

[0568] Next, remove insulator 223 (refer to...) Figures 29A to 29D When removing insulator 223, dry etching or wet etching methods can be used. Wet etching is preferred, for example. Figure 29B and Figure 29CThe diagram shows that both sides of the top surface of the oxide semiconductor 230, on side A1 (A3) and side A2 (A4), are formed into a curved shape, but this is not a limitation. For example, sometimes only the oxide semiconductor 230... Figure 28B and Figure 28C The side that does not contact the insulator 223 is formed into a curved shape.

[0569] As described above, insulator 223 is removed during the manufacturing process of a semiconductor device according to one aspect of the present invention. Therefore, insulator 223 is also referred to as a sacrificial layer.

[0570] Next, the insulating film 224f is processed to form the insulator 224 (refer to...). Figures 30A to 30D For example, the oxide semiconductor 230 can be used as a mask to process the insulating film 224f. In this case, the region of the insulating film 224f that does not overlap with the oxide semiconductor 230 can be removed. Therefore, as... Figure 30A As shown, the insulator 224 can be formed in a manner that overlaps with the oxide semiconductor 230. Alternatively, the insulator 224 can be formed in a manner that is identical or substantially identical to the shape of the oxide semiconductor 230 when viewed from a planar surface. Note that in manufacturing... Figures 11A to 11D When using the semiconductor device shown, no process is performed. Figures 30A to 30D The process shown.

[0571] In the processing of the insulating film 224f, either dry etching or wet etching can be used. Dry etching is suitable for microfabrication. The conditions and apparatus for dry etching can be found above.

[0572] During the processing of insulating film 224f, the insulator 222 beneath insulating film 224f is sometimes also processed. In this case, the thickness of the region of insulator 222 that does not overlap with insulator 224 is sometimes smaller than the thickness of the region of insulator 222 that overlaps with insulator 224.

[0573] In addition, for example Figures 28A to 28C An example is shown of forming two insulators 223 and two oxide semiconductors 230 in a transistor 200, but the invention is not limited thereto. Figure 31A As shown in the cross-sectional view, each of the two transistors (transistor 200_1 and transistor 200_2) can also be formed with a structure of two insulators 223 and two oxide semiconductors 230. Additionally, as... Figure 31BAs shown in the cross-sectional view, insulators 223 of different widths can also be formed. When viewed in the A1-A2 direction, three fin-shaped oxide semiconductors 230 are formed for each of transistors 200_1 and 200_2. In this case, a portion of the oxide semiconductor 230 is removed so that the oxide semiconductor 230 of transistor 200_1 and the oxide semiconductor 230 of transistor 200_2 are divided in a straight line extending in the B1-B2 direction when viewed from the plane.

[0574] Alternatively, insulator 223 may not need to be removed. For example, as... Figure 32A As shown, a structure can also be adopted that leaves a portion of the insulator 223 remaining. For example, the insulator 223 can also remain in the region where the conductor 240 is disposed in a subsequent process. For example, in the above process, when the insulator 223 is removed, a mask is formed in the region where the conductor 240 is disposed using photolith...

Claims

1. A semiconductor device, comprising: transistor; First insulator; Second insulator; as well as Third insulator The transistor comprises an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fourth insulator. The first insulator is disposed on the substrate. The oxide semiconductor is disposed on the first insulator. Both the first conductor and the second conductor are disposed on the oxide semiconductor. The third conductor is in contact with the top surface of the first conductor. The fourth conductor is in contact with the top surface of the second conductor. The distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor. The second insulator is disposed on the third conductor and the fourth conductor. The second insulator includes an opening that overlaps with the region of the oxide semiconductor located between the third and fourth conductors when viewed from a plane. The third insulator is disposed inside the opening such that it has a region that contacts the top surface of the first conductor, a region that contacts the top surface of the second conductor, a region that contacts the side surface of the third conductor, a region that contacts the side surface of the fourth conductor, and a region that contacts the side surface of the second insulator. The fourth insulator is disposed inside the opening such that it has a region that contacts the oxide semiconductor, a region that contacts the side of the first conductor, and a region that contacts the side of the second conductor. The fifth conductor is disposed on the fourth insulator inside the opening. In the region at least overlapping with the opening, the shape of the first insulator as viewed from a plane is the same as or substantially the same as the shape of the oxide semiconductor as viewed from a plane. When viewed in cross-section along the channel width of the transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section along the channel width direction of the transistor, the height of the oxide semiconductor is greater than or equal to the width of the oxide semiconductor. Furthermore, when viewed from a planar perspective, the oxide semiconductor and the fifth conductor overlap in more than two regions.

2. The semiconductor device according to claim 1, The third insulator is less permeable to oxygen than the second insulator.

3. The semiconductor device according to claim 2, The third insulator comprises silicon nitride.

4. The semiconductor device according to claim 1, The first insulator comprises a metal oxide.

5. A semiconductor device, comprising: transistor; Capacitor; First insulator; Second insulator; as well as Third insulator The transistor comprises an oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and a fourth insulator. The capacitor includes the oxide semiconductor, the second conductor, the sixth conductor, and the fifth insulator. The first insulator is disposed on the substrate. The oxide semiconductor is disposed on the first insulator. Both the first conductor and the second conductor are disposed on the oxide semiconductor. The third conductor is in contact with the top surface of the first conductor. The fourth conductor is in contact with the top surface of the second conductor. The distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor. The second insulator is disposed on the third conductor and the fourth conductor. The second insulator includes a first opening that overlaps with the region of the oxide semiconductor located between the first conductor and the second conductor when viewed from a plane. The second insulator includes a second opening that overlaps with the oxide semiconductor and extends into the second conductor. The third insulator is disposed inside the first opening such that it has a region that contacts the top surface of the first conductor, a region that contacts the top surface of the second conductor, a region that contacts the side surface of the third conductor, a region that contacts the side surface of the fourth conductor, and a region that contacts the side surface of the second insulator. The fourth insulator is disposed inside the first opening such that it has a region that contacts the oxide semiconductor, a region that contacts the side of the first conductor, and a region that contacts the side of the second conductor. The fifth conductor is disposed on the fourth insulator inside the first opening. The fifth insulator is disposed inside the second opening in a manner that overlaps with the second conductor. The sixth conductor is disposed on the fifth insulator inside the second opening. In the region at least overlapping with the first opening, the shape of the first insulator as viewed from a plane is the same as or substantially the same as the shape of the oxide semiconductor as viewed from a plane. When viewed in cross-section along the channel width of the transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the oxide semiconductor. When viewed in cross-section along the channel width direction of the transistor, the height of the oxide semiconductor is greater than or equal to the width of the oxide semiconductor. Furthermore, when viewed from a planar perspective, the oxide semiconductor and the fifth conductor overlap in more than two regions.

6. The semiconductor device according to claim 5, The third insulator is less permeable to oxygen than the second insulator.

7. The semiconductor device according to claim 5, The third insulator comprises silicon nitride.

8. The semiconductor device according to claim 5, The first insulator comprises a metal oxide.

9. The semiconductor device according to claim 5, When viewed from a plane, the oxide semiconductor and the sixth conductor overlap in more than two regions.

10. The semiconductor device according to claim 9, The metal oxide described therein has the function of capturing or fixing hydrogen.

11. The semiconductor device according to claim 10, The metal oxide mentioned therein is a high-k material.

12. The semiconductor device according to claim 11, The metal oxide mentioned above is an oxide containing one or both of aluminum and hafnium.

13. The semiconductor device according to claim 12, The metal oxide mentioned therein is hafnium silicate.

14. The semiconductor device according to claim 1, When viewed from a plane, the oxide semiconductor appears as a ring with both ends aligned or substantially aligned.

15. The semiconductor device according to claim 1, When viewed from a plan view, the side of the opening is consistent with or substantially consistent with the side of the third conductor and the side of the fourth conductor.

16. The semiconductor device according to claim 1, When viewed in cross-section along the channel width direction of the transistor, the width of the oxide semiconductor is 5 nm or more and 50 nm or less. Furthermore, when viewed in cross-section along the channel width direction of the transistor, the height of the oxide semiconductor is at least 1.5 times and less than 10 times the width of the oxide semiconductor.

17. The semiconductor device according to any one of claims 1 to 4 and claims 14 to 16, The oxide semiconductor contains indium. The oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate. Furthermore, when observing the cross-section of the oxide semiconductor using a transmission electron microscope, it was confirmed that bright spots were arranged in layers in a direction perpendicular to the surface of the substrate.

18. The semiconductor device according to any one of claims 1 to 4 and claims 14 to 16, The oxide semiconductor contains indium. The oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate. The oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region. Furthermore, when observing the cross-section of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the substrate surface were confirmed in each of the first, second, and third regions.

19. The semiconductor device according to claim 18, The second region contains zinc. The second region includes crystals. Furthermore, the c-axis of the crystal is approximately parallel to the normal direction of the side surface of the oxide semiconductor.

20. The semiconductor device according to claim 18, The indium content in the first region is higher than that in the second region. Furthermore, the indium content in the third region is higher than that in the second region.

21. A method for manufacturing a semiconductor device, comprising the following steps: Deposit an insulating film on the substrate; A first insulator is formed on the insulating film; An oxide semiconductor film is deposited in a manner that covers the first insulator; The oxide semiconductor film is processed by anisotropic etching until the top surface of the first insulator is exposed, forming an oxide semiconductor that contacts the side surface of the first insulator. Remove the first insulator; A second insulator is formed by removing regions of the insulating film that do not overlap with the oxide semiconductor; A first conductor and a second conductor on the first conductor are formed in such a manner that the oxide semiconductor and the second insulator are covered; A third insulator is formed on the second conductor; A first opening overlapping the oxide semiconductor is formed in the third insulator by processing the third insulator. By processing the second conductor, a third conductor and a fourth conductor are formed so that they are sandwiched opposite the first opening when viewed from a planar perspective; A fourth insulator is formed in such a way that it is in contact with the first conductor, the third conductor, the fourth conductor, and the third insulator; A second opening is formed in the fourth insulator in such a manner that it overlaps with a portion of the first opening; By processing the first conductor, a fifth conductor and a sixth conductor are formed so that, when viewed from a plane, they sandwich the second opening and are opposite to each other; A fifth insulator is formed on the fourth insulator in such a way that it contacts the region of the oxide semiconductor that overlaps with the second opening; as well as A seventh conductor is formed on the fifth insulator by embedding it into the first opening.

22. The method for manufacturing a semiconductor device according to claim 21, Alumina or silicon nitride is used as the first insulator.

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