Array substrate and display device

Abstract

An array substrate including a plurality of pixel driving circuits is provided. Each pixel driving circuit comprises a driving transistor and a compensation transistor. An active layer of the compensation transistor includes a first portion and a second portion. The first portion and the second portion are spaced apart by an intermediate portion. And the orthographic projection of the middle part on the substrate is not overlapped with the orthographic projection of the grid electrode of the compensation transistor on the substrate. The array substrate comprises an anti-interference block. The anti-interference block is configured to be supplied with a first voltage signal that is supplied to a cathode of a light emitting element in the array substrate. And the orthographic projection of the anti-interference block on the substrate is at least partially overlapped with the orthographic projection of the middle part on the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit includes a driving transistor and a compensation transistor; a first electrode of the compensation transistor is connected to a second electrode of the driving transistor; the second electrode of the compensation transistor is connected to the gate of the driving transistor; the active layer of the compensation transistor includes a first portion and a second portion; the first portion and the second portion are spaced apart by an intermediate portion; and the orthographic projection of the intermediate portion on a substrate does not overlap with the orthographic projection of the gate of the compensation transistor on the substrate; wherein the array substrate includes an anti-interference block; the anti-interference block is configured to be provided with a first voltage signal, the first voltage signal being provided to the cathode of a light-emitting element in the array substrate; and the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the intermediate portion on the substrate.

[0004] Optionally, the orthographic projection of the anti-interference block on the substrate does not overlap at least partially with the orthographic projection of the first portion on the substrate; and the orthographic projection of the anti-interference block on the substrate does not overlap at least partially with the orthographic projection of the second portion on the substrate.

[0005] Optionally, the array substrate further includes a plurality of first voltage supply lines configured to provide the first voltage signal; wherein the anti-interference block is connected to a corresponding first voltage supply line among the plurality of first voltage supply lines.

[0006] Optionally, the interference prevention block is located in the second conductive layer; each of the first voltage supply lines is located in the first signal line layer; and the respective first voltage supply lines are connected to the interference prevention block through vias extending through at least one insulating layer.

[0007] Optionally, each of the first voltage supply lines includes a first main portion and a plurality of protruding portions projecting in a direction away from the first main portion; wherein the orthographic projection of each of the plurality of protruding portions on the substrate at least partially overlaps with the orthographic projection of the intermediate portion on the substrate.

[0008] Optionally, the orthographic projection of each protrusion on the substrate does not overlap at least partially with the orthographic projection of the first portion on the substrate; and the orthographic projection of each protrusion on the substrate does not overlap at least partially with the orthographic projection of the second portion on the substrate.

[0009] Optionally, the orthographic projection of each protrusion on the substrate overlaps at least partially with the orthographic projection of the anti-interference block on the substrate; and the orthographic projection of the first main portion on the substrate does not overlap at least partially with the orthographic projection of the anti-interference block on the substrate.

[0010] Optionally, the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the middle portion of the third transistor in the two adjacent pixel driving circuits in the two adjacent columns on the substrate.

[0011] Optionally, the orthographic projection of each protrusion onto the substrate at least partially overlaps with the orthographic projection of the middle portion of the third transistor in two adjacent pixel driving circuits in two adjacent columns onto the substrate.

[0012] Optionally, the array substrate includes a second signal line layer; wherein the second signal line layer includes a plurality of second voltage supply lines, a plurality of third voltage supply lines, a plurality of data lines, a plurality of third reset signal lines, and a plurality of dummy lines.

[0013] Optionally, multiple pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); each of the multiple third reset signal lines is located in the (4k-3)th column of the K columns; each of the multiple dummy lines is located in the (4k-1)th column of the K columns; and each of the multiple third voltage supply lines is located in the 4kth column or the (4k-2)th column of the K columns.

[0014] Optionally, in the (4k-3)th column of the K columns, the third reset signal line of the plurality of third reset signal lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines; in the (4k-2)th column of the K columns, the third voltage supply line of the plurality of third voltage supply lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines; in the (4k-1)th column of the K columns, the dummy line of the plurality of dummy lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines; and in the 4kth column of the K columns, the third voltage supply line of the plurality of third voltage supply lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines.

[0015] Optionally, the array substrate has a second signal line layer; wherein the second signal line layer includes a plurality of second voltage supply lines, a plurality of data lines, a plurality of third reset signal lines, and a plurality of fourth reset signal lines.

[0016] Optionally, multiple pixel driving circuits are arranged in K columns, where K is a positive integer; the K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); each of the multiple third reset signal lines is located between the 4kth column and the (4k-1)th column, or between the (4k-2)th column and the (4k-3)th column; and each of the multiple fourth reset signal lines is located between the (4k-1)th column and the (4k-2)th column.

[0017] Optionally, the third reset signal line of the plurality of third reset signal lines separates two adjacent data lines in two adjacent columns of the plurality of data lines; and the fourth reset signal line of the plurality of fourth reset signal lines separates two adjacent second voltage supply lines in two adjacent columns of the plurality of second voltage supply lines.

[0018] Optionally, the array substrate includes a plurality of first voltage supply lines and a plurality of third voltage supply lines; wherein the plurality of first voltage supply lines and the plurality of third voltage supply lines are interconnected to form an interconnected first voltage signal network; each of the plurality of third voltage supply lines is electrically connected to at least one of the plurality of first voltage supply lines; each of the plurality of first voltage supply lines is electrically connected to at least one of the plurality of third voltage supply lines; each first voltage supply line includes a first main portion and a plurality of first branches extending in a direction away from the first main portion; and each of the third voltage supply lines is connected to a first branch of the plurality of first branches through a via extending through at least one insulating layer.

[0019] Optionally, the array substrate includes a plurality of first reset signal lines, a plurality of third reset signal lines, and a first connection line; wherein the plurality of first reset signal lines and the plurality of third reset signal lines are interconnected to form an interconnected first reset signal network; each of the plurality of third reset signal lines is electrically connected to at least one of the plurality of first reset signal lines; each of the plurality of first reset signal lines is electrically connected to at least one of the plurality of third reset signal lines; each pixel driving circuit further includes a first transistor; and each of the first reset signal lines is connected to a first electrode of the first transistor via the first connection line.

[0020] Optionally, each of the first reset signal lines includes a second main portion and a plurality of second branches extending in a direction away from the second main portion; each of the third voltage supply lines is electrically connected to the first connection line via a via extending through at least one insulating layer; the first connection line is electrically connected to a second branch of the plurality of second branches via a via extending through at least one insulating layer; and at least one of the plurality of third reset signal lines is electrically connected to at least one of the plurality of first reset signal lines via the first connection line.

[0021] Optionally, the array substrate includes a plurality of second reset signal lines and a plurality of fourth reset signal lines, as well as a second connecting line; wherein the plurality of second reset signal lines and the plurality of fourth reset signal lines are interconnected to form an interconnected second reset signal network; each of the plurality of fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines; each of the plurality of second reset signal lines is electrically connected to at least one of the plurality of fourth reset signal lines; and each of the fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines via the second connecting line.

[0022] In another aspect, this disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 3B It is shown Figure 3A The diagram shows the structure of the light-shielding layer in the array substrate.

[0030] Figure 3C It is shown Figure 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0031] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0032] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0033] Figure 3F It is shown Figure 3A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate.

[0034] Figure 3G It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0035] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0036] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0037] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0038] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0039] Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram.

[0040] Figure 5 It is shown Figure 3A The diagram shows a schematic of the structure of the semiconductor material layer, the first planarization layer, and the second signal line layer in the array substrate.

[0041] Figure 6 It is shown Figure 3A The diagram shows a structure of multiple first voltage supply lines and multiple third voltage supply lines in the array substrate.

[0042] Figure 7 It is shown Figure 3A The diagram shows a schematic of the structure of multiple first reset signal lines, multiple third reset signal lines, and a first connecting line in the array substrate shown.

[0043] Figure 8A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 8B It is shown Figure 8A The diagram shows the structure of the light-shielding layer in the array substrate.

[0045] Figure 8C It is shown Figure 8A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0046] Figure 8D It is shown Figure 8A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0047] Figure 8E It is shown Figure 8A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0048] Figure 8F It is shown Figure 8A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate.

[0049] Figure 8G It is shown Figure 8A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0050] Figure 8H It is shown Figure 8A A schematic diagram of the structure of the first planarization layer in the array substrate shown.

[0051] Figure 8I It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0052] Figure 9A It is along Figure 8A A cross-sectional view of the D-D' line in the diagram.

[0053] Figure 9B It is along Figure 8A A cross-sectional view of the E-E' line in the diagram.

[0054] Figure 9C It is along Figure 8A A cross-sectional view of line F-F' in the diagram.

[0055] Figure 10 It is shown Figure 8A The diagram shows a schematic of the structure of the semiconductor material layer, the first planarization layer, and the second signal line layer in the array substrate.

[0056] Figure 11 It is shown Figure 8A The diagram shows a structure of multiple first voltage supply lines and multiple third voltage supply lines in the array substrate.

[0057] Figure 12 It is shown Figure 8AThe diagram shows a structure of multiple second voltage supply lines and multiple fourth voltage supply lines in the array substrate. Detailed Implementation

[0058] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0059] This disclosure particularly provides an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor and a compensation transistor. Optionally, a first electrode of the compensation transistor is connected to a second electrode of the driving transistor. Optionally, a second electrode of the compensation transistor is connected to the gate of the driving transistor. Optionally, the active layer of the compensation transistor includes a first portion and a second portion. Optionally, the first portion and the second portion are spaced apart by an intermediate portion. Optionally, the orthographic projection of the intermediate portion onto the substrate does not overlap with the orthographic projection of the gate of the compensation transistor onto the substrate. Optionally, the array substrate includes an anti-interference block. Optionally, the anti-interference block is configured to be provided with a first voltage signal, the first voltage signal being provided to the cathode of a light-emitting element in the array substrate. Optionally, the orthographic projection of the anti-interference block onto the substrate at least partially overlaps with the orthographic projection of the intermediate portion onto the substrate.

[0060] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0061] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The array substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and various second voltage supply lines (e.g., low voltage supply lines). Each subpixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding first voltage supply line among the plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0062] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) Figure 2AIn some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding first gate line among a plurality of first gate lines GL1, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding second gate line among a plurality of second gate lines GL2, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. The transistor T4 has a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 has a gate connected to a corresponding first light-emitting control signal line in a plurality of first light-emitting control signal lines em1, a first electrode connected to a corresponding first voltage supply line in a plurality of first voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding second light-emitting control signal line in a plurality of second light-emitting control signal lines em2, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to a corresponding first gate line in a plurality of first gate lines GL1, a first electrode connected to a corresponding second reset signal line in a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding first voltage supply line and the first electrode of the fourth transistor T4.

[0063] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (See reference...) Figure 2B In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0064] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0065] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0066] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figures 2A to 2C During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. In the initial sub-stage t0, each of the plurality of first gate lines GL1 is provided with a cutoff signal, therefore the second transistor T2 and the sixth transistor T6 are turned off. In the initial sub-stage t0, each of the plurality of second gate lines GL2 is provided with a cutoff signal, therefore the third transistor T3 is turned off.

[0067] In reset phase t1, a turn-on reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, thereby turning on the first transistor T1. This allows the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and sequentially to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, each first gate line in the plurality of first gate lines GL1 and each second gate line in the plurality of second gate lines GL2 are provided with a cutoff signal, thus turning off the second transistor T2, the third transistor T3, and the sixth transistor T6. Each of the multiple first light emission control signal lines em1 is provided with a high voltage signal to turn off the fourth transistor T4. Each of the multiple second light emission control signal lines em2 is provided with a high voltage signal to turn off the fifth transistor T5.

[0068] During reset phase t1, the first transistor T1 is turned on, and the initialization voltage signal from the corresponding first reset signal line among the plurality of first reset signal lines Vint1 is transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then sequentially to the gate of the driving transistor Td. In some embodiments, the initialization voltage signal from the corresponding first reset signal line has a voltage level in the range of -2V to -5V. In one example, an initialization voltage signal with a voltage level in the range of -2V to -5V is sufficient to turn on the driving transistor Td.

[0069] In data writing sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. A corresponding first gate line in the plurality of first gate lines GL1 is provided with a conduction signal, therefore the second transistor T2 and the sixth transistor T6 are turned on. A corresponding second gate line in the plurality of second gate lines GL2 is provided with a conduction signal, therefore the third transistor T3 is turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in data writing sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The second transistor T2 is turned on in data writing sub-stage t2. The data voltage signal transmitted through each data line in the plurality of data lines DL is received by the first electrode of the second transistor T2 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data write sub-stage t2, the voltage level at node N1 gradually rises to (Vdata + Vth), where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. Each of the multiple first light-emitting control signal lines em1 is provided with a high voltage signal to turn off the fourth transistor T4. Each of the multiple second light-emitting control signal lines em2 is provided with a high voltage signal to turn off the fifth transistor T5.

[0070] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 through a corresponding first gate line among the plurality of first gate lines GL1 to turn on the sixth transistor T6; this allows the initialization voltage signal from the corresponding second reset signal line among the plurality of second reset signal lines Vint2 to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and sequentially to node N4. The anode of the light-emitting element LE is initialized.

[0071] In the light-emitting stage t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, thereby turning off the first transistor T1. Each of the first gate lines in the plurality of first gate lines GL1 and each of the second gate lines in the plurality of second gate lines GL2 are provided with cutoff signals, thus turning off the second transistor T2, the third transistor T3, and the sixth transistor T6. Each of the first light-emitting control signal lines em1 is provided with a low voltage signal to turn on the fourth transistor T4. Each of the second light-emitting control signal lines em2 is provided with a low voltage signal to turn on the fifth transistor T5. In the light-emitting stage t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0072] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, S3 represents a corresponding third sub-pixel, and S4 represents a corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, C3 represents a corresponding third sub-pixel of a third color, and C4 represents a corresponding fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0073] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0074] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. The portion of the array substrate includes multiple pixel driving circuits. Figure 3A The corresponding pixel driving circuit RPDC is shown in the figure.

[0075] Figure 3B It is shown Figure 3A The diagram shows the structure of the light-shielding layer in the array substrate. Figure 3C It is shown Figure 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate shown. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate shown. Figure 3F It is shown Figure 3A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. Figure 3G It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate shown. Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram. Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram.

[0076] Reference Figures 3A to 3I as well as Figures 4A to 4CIn some embodiments, the display panel includes a substrate BS; a light-shielding layer LSL located on the substrate BS; a buffer layer BUF located on the side of the light-shielding layer LSL away from the substrate BS; a semiconductor material layer SML located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the substrate BS; an interlayer dielectric layer ILD located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2 located on the side of the interlayer dielectric layer ILD away from the substrate BS; a passivation layer PVX located on the side of the second conductive layer CT2 away from the substrate BS; a first signal line layer SL1 located on the side of the passivation layer PVX away from the substrate BS; a first planarization layer PLN1 located on the side of the first signal line layer SL1 away from the substrate BS; a second signal line layer SL2 located on the side of the first planarization layer PLN1 away from the substrate BS; and a second planarization layer PLN2 located on the side of the second signal line layer SL2 away from the substrate BS.

[0077] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3CEach pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number, which indicates the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. Second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. Driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, S7, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0078] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., a third transistor T3), the active layer refers to a portion of the transistor comprising a first portion of the semiconductor material layer, a second portion of the semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, the first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and the second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0079] Reference Figure 2A , Figure 2B , Figure 3A as well as Figure 3D In some embodiments, the first conductive layer includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of reset control signal lines rst, a first gate pad GP1, a second gate pad GP2, and a first capacitor electrode Ce1 of a storage capacitor Cst. The first gate pad GP1 includes the gate G4 of a fourth transistor T4. The second gate pad GP2 includes the gate G5 of a fifth transistor T5. Optionally, at least a portion of the first capacitor electrode Ce1 is the gate of a driving transistor Td. In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, conductive materials can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first gate lines GL1, multiple second gate lines GL2, multiple reset control signal lines rst, first gate pad GP1, second gate pad GP2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located on the same layer.

[0080] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines GL1 and first capacitor electrodes Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed in the same material layer. In another example, multiple first gate lines GL1 and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines GL1 and forming the first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0081] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3E In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, the anti-interference block IPB, and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0082] Figure 3F The text describes vias extending through the interlayer dielectric layer (ILD).

[0083] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3GIn some embodiments, the first signal line layer includes a node connection line Cln, a voltage signal connection pad VCP, a data signal connection pad DCP, a relay electrode RE, a first connection line Cl1, a second connection line Cl2, a third connection line Cl3, a plurality of first voltage supply lines Vss1, a plurality of first light emission control signal lines em1, and a plurality of second light emission control signal lines em2. In some embodiments, the plurality of first voltage supply lines Vss1 are configured to provide a low voltage signal, for example, a voltage signal provided to the cathode of a light-emitting element in the array substrate. The data signal connection pad DCP is configured to connect a corresponding data line among the plurality of data lines to the first electrode of a second transistor T2. The voltage signal connection pad VCP is configured to connect a corresponding second voltage supply line among the plurality of second voltage supply lines to the second capacitor electrode Ce2 of a storage capacitor Cst. The relay electrode RE is configured to connect an anode connection pad located in the second signal line layer SL2 to the second electrodes of a fifth transistor T6 and a sixth transistor T6. The first connection line Cl1 is configured to connect a corresponding first reset signal line among the plurality of first reset signal lines Vint1 to the first electrode S1 of a first transistor T1. The second connection line Cl2 is configured to connect a corresponding second reset signal line among a plurality of second reset signal lines Vint2 to the first electrode S6 of the sixth transistor T6. The third connection line Cl3 is configured to connect the second capacitor electrode Ce2 to the first electrode S4 of the fourth transistor T4. The second capacitor electrode Ce2 is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines and is configured to supply a second voltage signal to the first electrode S4 of the fourth transistor T4. The node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit and the second electrode D3 of the third transistor T3 together. Optionally, the plurality of first voltage supply lines Vss1, the plurality of first light emission control signal lines em1, and the plurality of second light emission control signal lines em2 extend in a direction substantially parallel to the first direction DR1. As used herein, the term "substantially parallel" means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0084] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, node connection lines Cln, voltage signal connection pads VCP, data signal connection pads DCP, relay electrodes RE, first connection lines Cl1, second connection lines Cl2, third connection lines Cl3, multiple first voltage supply lines Vss1, multiple first light emission control signal lines em1, and multiple second light emission control signal lines em2 are located in the same layer.

[0085] Figure 3H The vias extending through the first planarization layer PLN1 are shown.

[0086] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3IIn some embodiments, the second signal line layer includes multiple second voltage supply lines Vdd, multiple third voltage supply lines Vss2, multiple data lines DL, multiple third reset signal lines Vint3, multiple dummy lines DUL, and an anode connection pad ACP. The anode connection pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit. The anode connection pad ACP is also electrically connected to the anode in each sub-pixel. A corresponding second voltage supply line among the multiple second voltage supply lines Vdd is electrically connected via a voltage signal connection pad VCP to the second capacitor electrode Ce2 of the storage capacitor Cst. A corresponding data line among the multiple data lines DL is electrically connected via a data signal connection pad to the first electrode of the second transistor T2. Each third reset signal line among the multiple third reset signal lines Vint3 is electrically connected to at least one of the multiple first reset signal lines Vint1 to form an interconnected first reset signal network. Optionally, a corresponding third reset signal line is electrically connected to at least one of the multiple first reset signal lines Vint1 via a first connection line in the pixel driving circuit. A corresponding third voltage supply line among the plurality of third voltage supply lines Vss2 is electrically connected to at least one of the plurality of first voltage supply lines Vss1 to form an interconnected first voltage signal network. In some embodiments, the plurality of first voltage supply lines Vss1 and the plurality of third voltage supply lines Vss2 are configured to provide a first voltage signal, such as a voltage signal provided to the cathode of a light-emitting element in an array substrate. In some embodiments, the plurality of second voltage supply lines Vdd are configured to provide a second voltage signal, such as a voltage signal provided to the first electrode S4 of a fourth transistor T4. Optionally, the voltage level of the second voltage signal is higher than the voltage level of the first voltage signal. Optionally, each dummy line among the plurality of dummy lines DUL is electrically isolated from the pixel driving circuitry.

[0087] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer comprises multiple sublayers stacked together. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines Vdd, multiple third voltage supply lines Vss2, multiple data lines DL, multiple third reset signal lines Vint3, multiple dummy lines DUL, and an anode connection pad ACP are located on the same layer.

[0088] In some embodiments, the array substrate includes pixel driving circuits arranged in K columns, where K is a positive integer. In some embodiments, the K columns include the (4k-3)th column C(4k-3), the (4k-2)th column C(4k-2), the (4k-1)th column C(4k-1), and the 4kth column C(4k) of the K columns, where k is a positive integer, 1≤k≤(K / 4). In one example, each of the plurality of third reset signal lines Vint3 is located in the (4k-3)th column C(4k-3) of the K columns; each of the plurality of dummy lines DUL is located in the (4k-1)th column C(4k-1) of the K columns; and each of the plurality of third voltage supply lines Vss2 is located in the 4kth column C(4k) or the (4k-2)th column C(4k-2) of the K columns.

[0089] In another example, in column (4k-3) of K columns C(4k-3), the third reset signal lines of multiple third reset signal lines Vint3 space the second voltage supply lines of multiple second voltage supply lines Vdd with the data lines of multiple data lines DL; in column (4k-2) of K columns C(4k-2), the third voltage supply lines of multiple third voltage supply lines Vss2 space the second voltage supply lines of multiple second voltage supply lines Vdd with the data lines of multiple data lines DL; in column (4k-1) of K columns C(4k-1), the dummy lines of multiple dummy lines DUL space the second voltage supply lines of multiple second voltage supply lines Vdd with the data lines of multiple data lines DL; and in column (4k) of K columns C(4k), the third voltage supply lines of multiple third voltage supply lines Vss2 space the second voltage supply lines of multiple second voltage supply lines Vdd with the data lines of multiple data lines DL.

[0090] In another example, the third reset signal lines Vint3 in the (4k-3)th column C(4k-3) of the K columns, the third voltage supply lines Vss2 in the (4k-2)th column C(4k-2) of the K columns, the dummy lines DUL in the (4k-1)th column C(4k-1) of the K columns, and the third voltage supply lines Vss2 in the 4kth column C(4k) of the K columns are arranged in sequence.

[0091] As used herein, the terms "column (4k-3)," "column (4k-2)," "column (4k-1)," and "column (4k)" are used in the case of K columns. The array substrate may or may not include additional columns preceding the first column of the K columns and / or additional columns following the last column of the K columns. In the case of an array substrate, the terms "column (4k-3)" or "column (4k-1)" do not necessarily indicate an odd-numbered column, and the terms "column (4k-2)" or "column (4k)" do not necessarily indicate an even-numbered column. In one example, column (4k-3) is an odd-numbered column in the case of K columns, but may be an even-numbered column in the case of an array substrate. In another example, column (4k-3) is an odd-numbered column in the case of K columns, and is also an odd-numbered column in the case of an array substrate. In one example, column (4k-2) is an even-numbered column in the case of K columns, but may be an odd-numbered column in the case of an array substrate. In another example, column (4k-2) is an even column in the case of K columns, and also an even column in the case of an array substrate. In one example, column (4k-1) is an odd column in the case of K columns, but can be an even column in the case of an array substrate. In another example, column (4k-1) is an odd column in the case of K columns, and also an odd column in the case of an array substrate. In one example, column (4k) is an even column in the case of K columns, but can be an odd column in the case of an array substrate. In another example, column (4k) is an even column in the case of K columns, and also an even column in the case of an array substrate.

[0092] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3D , Figure 3E and Figure 4A In some embodiments, except for the hole region H where a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the passivation layer PVX away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as the voltage signal connection pad VCP, the data signal connection pad DCP, the relay electrode RE, the first connection line Cl1, the second connection line Cl2, the third connection line Cl3, a plurality of first voltage supply lines Vss1, a plurality of first light emission control signal lines em1, and a plurality of second light emission control signal lines em2.

[0093] In some embodiments, the second capacitor electrode Ce2 is located on the side of the interlayer dielectric layer ILD away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the passivation layer PVX. The second via v2 extends through the insulating layer IN, the passivation layer PVX, and the interlayer dielectric layer ILD. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor T3, such as... Figure 4A As shown.

[0094] Reference Figure 2A , Figure 2B , Figures 3A to 3I as well as Figure 4A In some embodiments, the array substrate further includes a third via v3 extending through the passivation layer PVX. Each of the plurality of first voltage supply lines Vss1 is connected to the anti-interference block IPB.

[0095] Figure 5 It is shown Figure 3A This is a schematic diagram of the structure of the semiconductor material layer, the first planarization layer, and the second signal line layer in the array substrate shown. (Refer to...) Figure 2A , Figure 2B , Figures 3A to 3I , Figures 4A to 4B as well as Figure 5 In some embodiments, the third transistor T3 is a dual-gate transistor, and the active layer ACT3 of the third transistor T3 includes a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 are separated by an intermediate portion INP. The orthographic projection of the intermediate portion INP on the substrate BS does not overlap with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS. The orthographic projection of the first portion P1 on the substrate BS overlaps with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS. The orthographic projection of the second portion P2 on the substrate BS overlaps with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS.

[0096] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the first portion P1 on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS does not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the first portion P1 on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS and the orthographic projection of the second part P2 on the substrate BS are at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) non-overlapping.

[0097] In some embodiments, each of the plurality of first voltage supply lines Vss1 includes a first main portion MP1 and a plurality of protruding portions PP projecting in a direction away from the first main portion MP1. Optionally, the first main portion MP1 extends along a direction substantially parallel to a first direction DR1. Optionally, each of the plurality of protruding portions PP extends in a direction substantially parallel to a second direction DR2 in a direction away from the first main portion MP1.

[0098] In some embodiments, the orthographic projections of the respective protrusions on the substrate BS at least partially overlap with the orthographic projections of the intermediate portion INP on the substrate BS (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the orthographic projections of the respective protrusions on the substrate BS at least partially overlap with the orthographic projections of the first portion P1 on the substrate BS (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the orthographic projection of each protrusion on the substrate BS and the orthographic projection of the second portion P2 on the substrate BS do not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%).

[0099] In some embodiments, the orthographic projection of each protrusion on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the anti-interference block IPB on the substrate BS. Optionally, the orthographic projection of the first major portion MP1 on the substrate BS does not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the anti-interference block IPB on the substrate BS.

[0100] Reference Figure 2A , Figure 2B , Figures 3A to 3I as well as Figure 4B In some embodiments, the array substrate further includes a fourth via v4, a fifth via v5, and a sixth via v6. The fourth via v4 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the gate insulating layer GI. The fifth via v5 extends through the passivation layer PVX. The sixth via v6 extends through the passivation layer PVX and the interlayer dielectric layer ILD. The third connection line Cl3 is connected to the first electrode S4 of the fourth transistor T4 via the fourth via v4 and to the second capacitor electrode Ce2 via the fifth via v5. Each of the plurality of first light-emitting control signal lines em1 is connected to the first gate pad GP1 via the sixth via v6.

[0101] Reference Figure 2A , Figure 2B , Figures 3A to 3I as well as Figure 4C In some embodiments, the array substrate further includes a seventh via v7, an eighth via v8, and a ninth via v9. The seventh via v7 extends through the passivation layer PVX and the interlayer dielectric layer ILD. The eighth via v8 extends through the first planarization layer PLN1. The ninth via v9 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the gate insulating layer GI. Each of the plurality of second light-emitting control signal lines em2 is connected to the second gate pad GP2 via the seventh via v7. The anode connection pad ACP is connected to the relay electrode via the eighth via v8. The relay electrode RE is connected to the second electrode D5 of the fifth transistor T5 and the second electrode D6 of the sixth transistor T6 via the ninth via v9.

[0102] Figure 6 It is shown Figure 3A A schematic diagram of the structure of multiple first voltage supply lines and multiple third voltage supply lines in the array substrate shown. (Refer to...) Figure 2A , Figure 2B , Figures 3A to 3I , Figures 4A to 4C and Figure 6 In some embodiments, the array substrate includes a plurality of first voltage supply lines Vss1 and a plurality of third voltage supply lines Vss2. Each of the first voltage supply lines Vss1 extends along a direction substantially parallel to a first direction DR1. Each of the third voltage supply lines Vss2 extends along a direction substantially parallel to a second direction DR2. The plurality of first voltage supply lines Vss1 and the plurality of third voltage supply lines Vss2 are interconnected to form an interconnected first voltage signal network. In some embodiments, each of the third voltage supply lines Vss2 is electrically connected to at least one of the plurality of first voltage supply lines Vss1, and each of the first voltage supply lines Vss1 is electrically connected to at least one of the plurality of third voltage supply lines Vss2.

[0103] In some embodiments, each of the plurality of first voltage supply lines Vss1 includes a first main portion MP1 and a plurality of first branches BH1 extending in a direction away from the first main portion MP1. Optionally, the first main portion MP1 extends in a direction substantially parallel to a first direction DR1. Optionally, each of the plurality of first branches BH1 extends in a direction substantially parallel to a second direction DR2 in a direction away from the first main portion MP1. Each of the plurality of third voltage supply lines Vss2 is connected to a first branch of the plurality of first branches BH1 via a via extending through at least one insulating layer (e.g., a first planarization layer PLN1).

[0104] Figure 7 It is shown Figure 3A The diagram shows a schematic representation of the structure of multiple first reset signal lines, multiple third reset signal lines, and a first connection line in the array substrate. (Refer to...) Figure 2A , Figure 2B , Figures 3A to 3I , Figures 4A to 4C and Figure 7In some embodiments, the array substrate includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3. Each of the first reset signal lines Vint1 extends in a direction substantially parallel to a first direction DR1. Each of the third reset signal lines Vint3 extends in a direction substantially parallel to a second direction DR2. The plurality of first reset signal lines Vint1 and the plurality of third reset signal lines Vint3 are interconnected to form an interconnected first reset signal network. In some embodiments, each of the third reset signal lines Vint3 is electrically connected to at least one of the plurality of first reset signal lines Vint1, and each of the first reset signal lines Vint1 is electrically connected to at least one of the plurality of third reset signal lines Vint3. Optionally, in a pixel driving circuit, each of the third reset signal lines is electrically connected to at least one of the plurality of first reset signal lines Vint1 via a first connection line Cl1.

[0105] In some embodiments, each of the plurality of first reset signal lines Vint1 includes a second main portion MP2 and a plurality of second branches BH2 extending in a direction away from the second main portion MP2. Optionally, the second main portion MP2 extends in a direction substantially parallel to the first direction DR1. Optionally, each of the plurality of second branches BH2 extends in a direction substantially parallel to the second direction DR2 in a direction away from the second main portion MP2. Each of the plurality of third voltage supply lines Vint3 is electrically connected to a first connection line Cl1 via a via extending through at least one insulating layer (e.g., a first planarization layer PLN1). The first connection line Cl1 is electrically connected to a second branch of the plurality of second branches BH2 via a via extending through at least one insulating layer (e.g., a passivation layer PVX).

[0106] Figure 8A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. The portion of the array substrate includes multiple pixel driving circuits. Figure 8A The corresponding pixel driving circuit RPDC is shown in the figure.

[0107] Figure 8B It is shown Figure 8A The diagram shows the structure of the light-shielding layer in the array substrate. Figure 8C It is shown Figure 8A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. Figure 8D It is shown Figure 8A A schematic diagram of the structure of the first conductive layer in the array substrate shown. Figure 8E It is shown Figure 8AA schematic diagram of the structure of the second conductive layer in the array substrate shown. Figure 8F It is shown Figure 8A The diagram shows a schematic of the structure of the interlayer dielectric layer in the array substrate. Figure 8G It is shown Figure 8A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 8H It is shown Figure 8A A schematic diagram of the structure of the first planarization layer in the array substrate shown. Figure 8I It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 9A It is along Figure 8A A cross-sectional view of the D-D' line in the diagram. Figure 9B It is along Figure 8A A cross-sectional view of the E-E' line in the diagram. Figure 9C It is along Figure 8A A cross-sectional view of line F-F' in the diagram.

[0108] Reference Figures 8A to 8I as well as Figures 9A to 9C In some embodiments, the display panel includes a substrate BS; a light-shielding layer LSL located on the substrate BS; a buffer layer BUF located on the side of the light-shielding layer LSL away from the substrate BS; a semiconductor material layer SML located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the substrate BS; an interlayer dielectric layer ILD located on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2 located on the side of the interlayer dielectric layer ILD away from the substrate BS; a passivation layer PVX located on the side of the second conductive layer CT2 away from the substrate BS; a first signal line layer SL1 located on the side of the passivation layer PVX away from the substrate BS; a first planarization layer PLN1 located on the side of the first signal line layer SL1 away from the substrate BS; a second signal line layer SL2 located on the side of the first planarization layer PLN1 away from the substrate BS; and a second planarization layer PLN2 located on the side of the second signal line layer SL2 away from the substrate BS.

[0109] Reference Figure 2A , Figure 2B , Figure 8A and Figure 8CEach pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number, which indicates the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. Second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. Driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, S7, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0110] Reference Figure 2A , Figure 2B , Figure 8A as well as Figure 8DIn some embodiments, the first conductive layer includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of reset control signal lines rst, a first gate pad GP1, a second gate pad GP2, and a first capacitor electrode Ce1 of the storage capacitor Cst. The first gate pad GP1 includes the gate G4 of the fourth transistor T4. The second gate pad GP2 includes the gate G5 of the fifth transistor T5. Optionally, at least a portion of the first capacitor electrode Ce1 is the gate of the driving transistor Td. In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, the plurality of first gate lines GL1, the plurality of second gate lines GL2, the plurality of reset control signal lines rst, the first gate pad GP1, the second gate pad GP2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located on the same layer.

[0111] Reference Figure 2A , Figure 2B , Figure 8A and Figure 8E In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst.

[0112] Figure 8F The text describes vias extending through the interlayer dielectric layer (ILD).

[0113] Reference Figure 2A , Figure 2B , Figure 8A and Figure 8GIn some embodiments, the first signal line layer includes a node connection line Cln, a voltage signal connection pad VCP, a data signal connection pad DCP, a relay electrode RE, a first connection line Cl1, a second connection line Cl2, a third connection line Cl3, a plurality of first voltage supply lines Vss1, a plurality of first light emission control signal lines em1, and a plurality of second light emission control signal lines em2. In some embodiments, the plurality of first voltage supply lines Vss1 are configured to provide a low voltage signal, for example, a voltage signal provided to the cathode of a light-emitting element in the array substrate. The data signal connection pad DCP is configured to connect a corresponding data line among the plurality of data lines to the first electrode of a second transistor T2. The voltage signal connection pad VCP is configured to connect a corresponding second voltage supply line among the plurality of second voltage supply lines to the second capacitor electrode Ce2 of a storage capacitor Cst. The relay electrode RE is configured to connect an anode connection pad located in the second signal line layer SL2 to the second electrodes of a fifth transistor T6 and a sixth transistor T6. The first connection line Cl1 is configured to connect a corresponding first reset signal line among the plurality of first reset signal lines Vint1 to the first electrode S1 of a first transistor T1. The second connection line Cl2 is configured to connect a corresponding second reset signal line among the plurality of second reset signal lines Vint2 to the first electrode S6 of the sixth transistor T6. The third connection line Cl3 is configured to connect the second capacitor electrode Ce2 to the first electrode S4 of the fourth transistor T4. The second capacitor electrode Ce2 is connected to a corresponding second voltage supply line among the plurality of second voltage supply lines and is configured to supply a second voltage signal to the first electrode S4 of the fourth transistor T4. The node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit and the second electrode D3 of the third transistor T3 together. Optionally, the plurality of first voltage supply lines Vss1, the plurality of first light emission control signal lines em1, and the plurality of second light emission control signal lines em2 extend in a direction substantially parallel to the first direction DR1.

[0114] Figure 8H The vias extending through the first planarization layer PLN1 are shown.

[0115] Reference Figure 2A , Figure 2B , Figure 8A and Figure 8IIn some embodiments, the second signal line layer includes a plurality of second voltage supply lines Vdd, a plurality of data lines DL, a plurality of third reset signal lines Vint3, a plurality of fourth reset signal lines Vint4, and an anode connection pad ACP. The anode connection pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit. The anode connection pad ACP is also electrically connected to the anode in each sub-pixel. A corresponding second voltage supply line among the plurality of second voltage supply lines Vdd is electrically connected via a voltage signal connection pad VCP to the second capacitor electrode Ce2 of the storage capacitor Cst. A corresponding data line among the plurality of data lines DL is electrically connected via a data signal connection pad to the first electrode of the second transistor T2. Each third reset signal line among the plurality of third reset signal lines Vint3 is electrically connected to at least one of the plurality of first reset signal lines Vint1 to form an interconnected first reset signal network. Each fourth reset signal line among the plurality of fourth reset signal lines Vint4 is electrically connected to at least one of the plurality of second reset signal lines Vint2 to form an interconnected second reset signal network. Optionally, in the pixel driving circuit, each of the fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines Vint2 via a second connection line. In some embodiments, the plurality of first voltage supply lines Vss1 are configured to provide a first voltage signal, for example, a voltage signal provided to the cathode of the light-emitting element in the array substrate. In some embodiments, the plurality of second voltage supply lines Vdd are configured to provide a second voltage signal, for example, a voltage signal provided to the first electrode S4 of the fourth transistor T4. Optionally, the voltage level of the second voltage signal is higher than the voltage level of the first voltage signal.

[0116] In some embodiments, the array substrate includes pixel driving circuits arranged in K columns, where K is a positive integer. In some embodiments, the K columns include the (4k-3)th column C(4k-3), the (4k-2)th column C(4k-2), the (4k-1)th column C(4k-1), and the 4kth column C(4k) of the K columns, where k is a positive integer, 1≤k≤(K / 4). In one example, each of the plurality of third reset signal lines Vint3 is located between the 4kth column C(4k) and the (4k-1)th column C(4k-1) of the K columns, or between the (4k-2)th column C(4k-2) and the (4k-3)th column C(4k-3) of the K columns. In another example, each of the multiple fourth reset signal lines Vint4 is between column (4k-1) C(4k-1) and column (4k-2) C(4k-2) of the K columns.

[0117] In another example, the third reset signal line in the plurality of third reset signal lines Vint3 separates two adjacent data lines in two adjacent columns in the plurality of data lines DL, and the fourth reset signal line in the plurality of fourth reset signal lines Vint4 separates two adjacent second voltage supply lines in two adjacent columns in the plurality of second voltage supply lines Vdd.

[0118] In another example, multiple third reset signal lines Vint3 and multiple fourth reset signal lines Vint4 are arranged alternately along the first direction DR1.

[0119] Reference Figure 2A , Figure 2B , Figure 8A , Figure 8D , Figure 8E and Figure 9A In some embodiments, except for the hole region H where a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the passivation layer PVX away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as the voltage signal connection pad VCP, the data signal connection pad DCP, the relay electrode RE, the first connection line Cl1, the second connection line Cl2, the third connection line Cl3, a plurality of first voltage supply lines Vss1, a plurality of first light emission control signal lines em1, and a plurality of second light emission control signal lines em2.

[0120] In some embodiments, the second capacitor electrode Ce2 is located on the side of the interlayer dielectric layer ILD away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the passivation layer PVX. The second via v2 extends through the insulating layer IN, the passivation layer PVX, and the interlayer dielectric layer ILD. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor T3, such as... Figure 9A As shown.

[0121] Reference Figure 2A , Figure 2B , Figures 8A to 8I as well as Figure 9A In some embodiments, the array substrate further includes a third via v3 extending through the passivation layer PVX. Each of the plurality of first voltage supply lines Vss1 is connected to the anti-interference block IPB.

[0122] Figure 10 It is shown Figure 8A This is a schematic diagram of the structure of the semiconductor material layer, the first planarization layer, and the second signal line layer in the array substrate shown. (Refer to...) Figure 2A , Figure 2B , Figures 8A to 8I , Figures 9A to 9B as well as Figure 10 In some embodiments, the third transistor T3 is a dual-gate transistor, and the active layer ACT3 of the third transistor T3 includes a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 are separated by an intermediate portion INP. The orthographic projection of the intermediate portion INP on the substrate BS does not overlap with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS. The orthographic projection of the first portion P1 on the substrate BS overlaps with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS. The orthographic projection of the second portion P2 on the substrate BS overlaps with the orthographic projection of the gate G3 of the third transistor T3 on the substrate BS.

[0123] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the first portion P1 on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS does not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the first portion P1 on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS and the orthographic projection of the second part P2 on the substrate BS are at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) non-overlapping.

[0124] In some embodiments, each of the plurality of first voltage supply lines Vss1 includes a first main portion MP1 and a plurality of protruding portions PP projecting in a direction away from the first main portion MP1. Optionally, the first main portion MP1 extends along a direction substantially parallel to a first direction DR1. Optionally, each of the plurality of protruding portions PP extends in a direction substantially parallel to a second direction DR2 in a direction away from the first main portion MP1.

[0125] In some embodiments, the orthographic projections of the respective protrusions on the substrate BS at least partially overlap with the orthographic projections of the intermediate portion INP on the substrate BS (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the orthographic projections of the respective protrusions on the substrate BS at least partially overlap with the orthographic projections of the first portion P1 on the substrate BS (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). Optionally, the orthographic projection of each protrusion on the substrate BS and the orthographic projection of the second portion P2 on the substrate BS do not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%).

[0126] In some embodiments, the orthographic projection of each protrusion on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the anti-interference block IPB on the substrate BS. Optionally, the orthographic projection of the first major portion MP1 on the substrate BS does not overlap at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the anti-interference block IPB on the substrate BS.

[0127] Reference Figure 2A , Figure 2B , Figures 8A to 8I as well as Figure 9B In some embodiments, the array substrate further includes a fourth via v4, a fifth via v5, and a sixth via v6. The fourth via v4 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the gate insulating layer GI. The fifth via v5 extends through the passivation layer PVX. The sixth via v6 extends through the passivation layer PVX and the interlayer dielectric layer ILD. The third connection line Cl3 is connected to the first electrode S4 of the fourth transistor T4 via the fourth via v4 and to the second capacitor electrode Ce2 via the fifth via v5. Each of the plurality of first light-emitting control signal lines em1 is connected to the first gate pad GP1 via the sixth via v6.

[0128] Reference Figure 2A , Figure 2B , Figures 8A to 8I as well as Figure 9C In some embodiments, the array substrate further includes a seventh via v7, an eighth via v8, and a ninth via v9. The seventh via v7 extends through the passivation layer PVX and the interlayer dielectric layer ILD. The eighth via v8 extends through the first planarization layer PLN1. The ninth via v9 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the gate insulating layer GI. Each of the plurality of second light-emitting control signal lines em2 is connected to the second gate pad GP2 via the seventh via v7. The anode connection pad ACP is connected to the relay electrode via the eighth via v8. The relay electrode RE is connected to the second electrode D5 of the fifth transistor T5 and the second electrode D6 of the sixth transistor T6 via the ninth via v9.

[0129] Figure 11 It is shown Figure 8A A schematic diagram of the structure of multiple first reset signal lines and multiple third reset signal lines in the array substrate shown. (Refer to...) Figure 2A , Figure 2B , Figures 8A to 8I , Figures 9A to 9C and Figure 11 In some embodiments, the array substrate includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3. Each of the first reset signal lines Vint1 extends in a direction substantially parallel to a first direction DR1. Each of the third reset signal lines Vint3 extends in a direction substantially parallel to a second direction DR2. The plurality of first reset signal lines Vint1 and the plurality of third reset signal lines Vint3 are interconnected to form an interconnected first reset signal network. In some embodiments, each of the third reset signal lines Vint3 is electrically connected to at least one of the plurality of first reset signal lines Vint1, and each of the first reset signal lines Vint1 is electrically connected to at least one of the plurality of third reset signal lines Vint3.

[0130] In some embodiments, each of the plurality of first reset signal lines Vint1 includes a second main portion MP2 and a plurality of second branches BH2 extending in a direction away from the second main portion MP2. Optionally, the second main portion MP2 extends in a direction substantially parallel to the first direction DR1. Optionally, each of the plurality of second branches BH2 extends in a direction substantially parallel to the second direction DR2 in a direction away from the second main portion MP2. Each of the plurality of third voltage supply lines Vint3 is electrically connected to the second branches of the plurality of second branches BH2 via vias extending through at least one insulating layer (e.g., a first planarization layer PLN1 and a passivation layer PVX).

[0131] Figure 12 It is shown Figure 8A This is a schematic diagram of the structure of multiple first reset signal lines, multiple third reset signal lines, and a second connection line in the array substrate shown. (Refer to...) Figure 2A , Figure 2B , Figures 8A to 8I , Figures 9A to 9C and Figure 12 In some embodiments, the array substrate includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4. Each of the second reset signal lines Vint2 extends in a direction substantially parallel to a first direction DR1. Each of the fourth reset signal lines Vint4 extends in a direction substantially parallel to a second direction DR2. The plurality of second reset signal lines Vint2 and the plurality of fourth reset signal lines Vint4 are interconnected to form an interconnected second reset signal network. In some embodiments, each of the fourth reset signal lines Vint4 is electrically connected to at least one of the plurality of second reset signal lines Vint2, and each of the second reset signal lines Vint2 is electrically connected to at least one of the plurality of fourth reset signal lines Vint4. Optionally, in a pixel driving circuit, each of the fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines Vint2 via a second connection line Cl2.

[0132] In some embodiments, refer to Figures 8A to 8I , Figures 9A to 9CThe active layer of the transistors of two adjacent pixel driving circuits in two adjacent columns (for example, in the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) in the K columns, or in the (4k-3)th column C(4k-3) and the (4k-4)th column in the K columns, or in the 4kth column C(4k) and the (4k+1)th column C(4k+1) in the K columns) are part of the overall structure. In some embodiments, the active layer, first electrode, and second electrode of the transistors in two adjacent pixel driving circuits in two adjacent columns (e.g., in the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) of the K columns; or in the (4k-3)th column C(4k-3) and the (4k-4)th column of the K columns; or in the 4kth column C(4k) and the (4k+1)th column C(4k+1) of the K columns) are part of the overall structure. In some embodiments, the first electrodes of the sixth transistors in two adjacent pixel driving circuits in two adjacent columns (e.g., the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) in the K columns; or the (4k-3)th column C(4k-3) and the (4k-4)th column in the K columns; or the 4kth column C(4k) and the (4k+1)th column C(4k+1)th column in the K columns) are directly connected and are part of the overall structure.

[0133] In some embodiments, the gates of the fifth transistors in two adjacent pixel driving circuits in two adjacent columns (e.g., in the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) of the K columns; or in the (4k-3)th column C(4k-3) and the (4k-4)th column of the K columns; or in the 4kth column C(4k) and the (4k+1)th column C(4k+1) of the K columns) are directly connected and are part of the overall structure (e.g., part of the second gate pad GP2).

[0134] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the middle portion of the third transistor in two adjacent pixel driving circuits in two adjacent columns (e.g., the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) of the K columns; or the (4k-3)th column C(4k-3) and the (4k-4)th column of the K columns; or the 4kth column C(4k) and the (4k+1)th column C(4k+1) of the K columns).

[0135] In some embodiments, the orthographic projection of each protrusion on the substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) with the orthographic projection of the middle portion of the third transistor in two adjacent pixel driving circuits in two adjacent columns (e.g., the (4k-1)th column C(4k-1) and the (4k-2)th column C(4k-2) of K columns; or the (4k-3)th column C(4k-3) and the (4k-4)th column of K columns; or the 4kth column C(4k) and the (4k+1)th column C(4k+1)th column of K columns).

[0136] In some embodiments, the corresponding layers of the first pixel driving circuit and the corresponding layers of the second pixel driving circuit that are directly adjacent to each other and in the current level (e.g., in the same row) are, for example, about the main surface perpendicular to the array substrate and substantially parallel to the main surface of the array substrate. Figure 9AThe planes of the data lines are substantially mirror-symmetrical with respect to each other (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%). As used herein, the terms "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" are not intended to include layers that are not part of the pixel driving circuit. For example, the terms "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" do not include an anode layer or a pixel defining layer. In one example, the terms "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" refer to the conductive layer of the first pixel driving circuit and the conductive layer of the second pixel driving circuit. In a particular example, "corresponding layer" includes at least one of a semiconductor material layer SML, a first conductive layer CT1, a second conductive layer CT2, a first signal line layer SL1, or a second signal line layer SL2. In another particular example, "corresponding layer" also includes at least one of a buffer layer, a gate insulating layer, an interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer.

[0137] In the array substrate according to this disclosure, in some embodiments, the anti-interference block IPB is located in the second conductive layer CT2 and is configured to be provided with a first voltage signal, for example, a voltage signal provided to the cathode of the light-emitting element in the array substrate. Various alternative embodiments can be practiced. In some alternative embodiments, the anti-interference block IPB is configured to be provided with a reset signal. In some alternative embodiments, the anti-interference block IPB is configured to be provided with a second voltage signal, for example, a voltage signal provided to the first electrode S4 of the fourth transistor T4.

[0138] In some embodiments, each pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0139] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0140] Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0141] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes forming a driving transistor and a compensation transistor. Optionally, a first electrode of the compensation transistor is connected to a second electrode of the driving transistor. Optionally, the second electrode of the compensation transistor is connected to the gate of the driving transistor. Optionally, the active layer forming the compensation transistor includes forming a first portion and forming a second portion. Optionally, the first portion and the second portion are spaced apart by an intermediate portion. Optionally, the orthographic projection of the intermediate portion on the substrate does not overlap with the orthographic projection of the gate of the compensation transistor on the substrate. Optionally, the method further includes forming an anti-interference block. Optionally, the anti-interference block is configured to be provided with a first voltage signal, the first voltage signal being provided to the cathode of a light-emitting element in the array substrate. Optionally, the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the intermediate portion on the substrate.

[0142] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising multiple pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor and a compensation transistor. The first electrode of the compensation transistor is connected to the second electrode of the driving transistor; The second electrode of the compensation transistor is connected to the gate of the driving transistor; The active layer of the compensation transistor includes a first part and a second part; The first part and the second part are separated by a middle part; as well as The orthographic projection of the middle portion on the substrate does not overlap with the orthographic projection of the gate of the compensation transistor on the substrate. The array substrate includes an anti-interference block; The anti-interference block is configured to be provided with a first voltage signal, which is provided to the cathode of the light-emitting element in the array substrate; as well as The orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the middle portion on the substrate.

2. The array substrate according to claim 1, wherein, The orthographic projection of the anti-interference block on the substrate does not overlap with the orthographic projection of the first portion on the substrate at least partially; as well as The orthographic projection of the anti-interference block on the substrate does not overlap at least partially with the orthographic projection of the second part on the substrate.

3. The array substrate of claim 1, further comprising a plurality of first voltage supply lines configured to provide the first voltage signal; in, The anti-interference block is connected to the corresponding first voltage supply line among the plurality of first voltage supply lines.

4. The array substrate according to claim 3, wherein, The interference prevention block is located in the second conductive layer; Each first voltage supply line is located on the first signal line layer; and The corresponding first voltage supply line is connected to the anti-interference block via a via extending through at least one insulating layer.

5. The array substrate according to claim 3, wherein, Each first voltage supply line includes a first main portion and a plurality of protruding portions protruding in a direction away from the first main portion; Wherein, the orthographic projection of each of the plurality of protruding portions on the substrate overlaps at least partially with the orthographic projection of the intermediate portion on the substrate.

6. The array substrate according to claim 5, wherein, The orthographic projection of each of the protruding portions on the substrate does not at least partially overlap with the orthographic projection of the first portion on the substrate; as well as The orthographic projection of each of the protruding portions on the substrate does not at least partially overlap with the orthographic projection of the second portion on the substrate.

7. The array substrate according to claim 5, wherein, The orthographic projection of each protruding portion on the substrate at least partially overlaps with the orthographic projection of the anti-interference block on the substrate; as well as The orthographic projection of the first main portion on the substrate does not overlap at least partially with the orthographic projection of the anti-interference block on the substrate.

8. The array substrate according to any one of claims 1 to 7, wherein, The orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the middle portion of the third transistor in the two adjacent pixel driving circuits in the two adjacent columns on the substrate.

9. The array substrate according to any one of claims 5 to 7, wherein, The orthographic projection of each protrusion onto the substrate at least partially overlaps with the orthographic projection of the middle portion of the third transistor in the two adjacent pixel driving circuits in the two adjacent columns onto the substrate.

10. The array substrate according to any one of claims 1 to 9, comprising a second signal line layer; in, The second signal line layer includes multiple second voltage supply lines, multiple third voltage supply lines, multiple data lines, multiple third reset signal lines, and multiple dummy lines.

11. The array substrate according to claim 10, wherein, The plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; The K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); Each of the plurality of third reset signal lines is located in the (4k-3)th column of the K columns; Each of the plurality of dummy lines is located in the (4k-1)th column of the K columns; and Each of the plurality of third voltage supply lines is located in the 4kth column of the K columns or the (4k-2)th column of the K columns.

12. The array substrate according to claim 11, wherein, In the (4k-3)th column of the K columns, the third reset signal line of the plurality of third reset signal lines separates the second voltage supply line of the plurality of second voltage supply lines from the data line of the plurality of data lines; In the (4k-2)th column of the K columns, the third voltage supply line of the plurality of third voltage supply lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines; In the (4k-1)th column of the K columns, the dummy lines among the plurality of dummy lines separate the second voltage supply lines among the plurality of second voltage supply lines from the data lines among the plurality of data lines; as well as In the 4kth column of the K columns, the third voltage supply line of the plurality of third voltage supply lines separates the second voltage supply line of the plurality of second voltage supply lines from the data lines of the plurality of data lines.

13. The array substrate according to any one of claims 1 to 9, comprising a second signal line layer; in, The second signal line layer includes multiple second voltage supply lines, multiple data lines, multiple third reset signal lines, and multiple fourth reset signal lines.

14. The array substrate according to claim 13, wherein, The plurality of pixel driving circuits are arranged in K columns, where K is a positive integer; The K columns include the (4k-3)th column, the (4k-2)th column, the (4k-1)th column, and the 4kth column, where k is a positive integer, 1≤k≤(K / 4); Each of the plurality of third reset signal lines is located between the 4kth column and the (4k-1)th column of the K columns, or between the (4k-2)th column and the (4k-3)th column of the K columns; and Each of the plurality of fourth reset signal lines is located between the (4k-1)th column and the (4k-2)th column in the K columns.

15. The array substrate according to claim 14, wherein, The third reset signal line of the plurality of third reset signal lines separates two adjacent data lines in two adjacent columns of the plurality of data lines; and The fourth reset signal line of the plurality of fourth reset signal lines separates two adjacent second voltage supply lines in two adjacent columns of the plurality of second voltage supply lines.

16. The array substrate according to claim 1, comprising a plurality of first voltage supply lines and a plurality of third voltage supply lines; in, The plurality of first voltage supply lines and the plurality of third voltage supply lines are interconnected to form an interconnected first voltage signal network; Each of the plurality of third voltage supply lines is electrically connected to at least one of the plurality of first voltage supply lines; Each of the plurality of first voltage supply lines is electrically connected to at least one of the plurality of third voltage supply lines; Each of the first voltage supply lines includes a first main portion and a plurality of first branches extending in a direction away from the first main portion; and Each of the third voltage supply lines is connected to the first branch of the plurality of first branches via a via extending through at least one insulating layer.

17. The array substrate according to claim 1, comprising a plurality of first reset signal lines, a plurality of third reset signal lines, and a first connection line; in, The plurality of first reset signal lines and the plurality of third reset signal lines are interconnected to form an interconnected first reset signal network; Each of the plurality of third reset signal lines is electrically connected to at least one of the plurality of first reset signal lines; Each of the plurality of first reset signal lines is electrically connected to at least one of the plurality of third reset signal lines; Each pixel driving circuit further includes a first transistor; and Each of the first reset signal lines is connected to the first electrode of the first transistor via the first connection line.

18. The array substrate according to claim 17, wherein, Each of the first reset signal lines includes a second main portion and a plurality of second branches extending in a direction away from the second main portion; Each of the third voltage supply lines is electrically connected to the first connection line via a via extending through at least one insulating layer. The first connecting line is electrically connected to the second branch of the plurality of second branches through a via extending through at least one insulating layer; as well as At least one of the plurality of third reset signal lines is electrically connected to at least one of the plurality of first reset signal lines via the first connection line.

19. The array substrate according to claim 1, comprising a plurality of second reset signal lines and a plurality of fourth reset signal lines, and a second connection line; in, The plurality of second reset signal lines and the plurality of fourth reset signal lines are interconnected to form an interconnected second reset signal network; Each of the plurality of fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines; Each of the plurality of second reset signal lines is electrically connected to at least one of the plurality of fourth reset signal lines; as well as Each of the fourth reset signal lines is electrically connected to at least one of the plurality of second reset signal lines via the second connection line.

20. A display device comprising an array substrate according to any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.

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