Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: patterning the upper part of a device wafer to form a plurality of bonding protrusions, and enabling grooves to be formed between the bonding protrusions; a patterned first photoresist layer is formed on the device wafer, the first photoresist layer is a photoetching negative photoresist layer, the patterned first photoresist layer is located in the groove, and the thickness of the first photoresist layer is larger than the depth of the groove; forming a first bonding metal layer on the first photoresist layer and the bonding bulge; and removing the first photoresist layer and the first bonding metal layer on the first photoresist layer. According to the semiconductor structure and the preparation method thereof, the thickness uniformity and the surface flatness of a device wafer can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] The device layer is a core structure layer of a MEMS (Micro-Electro-Mechanical System) inertial device, contains key structures such as an output structure, and the mechanical properties thereof directly determine the sensitivity, noise characteristics and reliability of the MEMS inertial device, and the thickness uniformity, side wall morphology and roughness, surface flatness and the like of the device layer need to be precisely controlled.

[0003] The preparation process of the bonding metal layer on the device layer will directly affect the structural integrity of the device layer. In the prior art, the bonding metal layer on the device layer is usually formed by deposition and dry etching. However, the etching residue of the dry etching bonding metal layer will cause a micro-masking effect in the subsequent etching process, resulting in local etching stagnation, such as over-etching or uneven in-die etching, which will seriously affect the thickness uniformity of the device layer, and further affect the performance and long-term reliability of the MEMS inertial device.

[0004] Therefore, improvements need to be made to at least partially solve the above problems. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, and even less to determine the protection scope of the claimed technical solution.

[0006] In order to at least partially solve the above problems, according to a first aspect of the present application, a preparation method of a semiconductor structure is provided, comprising: patterning an upper portion of a device wafer to form a plurality of bonding protrusions, wherein the plurality of bonding protrusions have a groove therebetween; forming a patterned first photoresist layer on the device wafer, wherein the first photoresist layer is a negative photoresist layer, the patterned first photoresist layer is located in the groove, and the thickness of the first photoresist layer is greater than the depth of the groove; forming a first bonding metal layer on the first photoresist layer and the bonding protrusions; removing the first photoresist layer and the first bonding metal layer located thereon.

[0007] Exemplarily, the patterning of the upper portion of the device wafer to form a plurality of bonding protrusions comprises: forming a patterned second photoresist layer on the device wafer; etching the device wafer with the second photoresist layer as a mask to form the trenches; removing the second photoresist layer.

[0008] Exemplarily, the second photoresist layer is a photoresist positive layer.

[0009] Exemplarily, the first photoresist layer and the second photoresist layer are patterned by the same mask.

[0010] Exemplarily, before forming the plurality of bonding bumps on the upper part of the patterned device wafer, the preparation method further comprises: bonding a cap wafer with the lower side of the device wafer and thinning the device wafer.

[0011] Exemplarily, the cap wafer has a plurality of cavities between the cap wafer and the device wafer; The plurality of cavities respectively correspond to positions of the plurality of trenches; The preparation method further comprises: forming a comb structure on the bottom of the trench corresponding to the position of the cavity.

[0012] Exemplarily, the preparation method further comprises: providing a wiring wafer, the surface of the wiring wafer having a second metal bonding layer corresponding to the first bonding metal layer; metal bonding the wiring wafer and the device wafer through the first bonding metal layer and the second metal bonding layer.

[0013] Exemplarily, the material of the first bonding metal layer and / or the second bonding metal layer comprises at least one of aluminum, germanium, copper, tin, gold and silver.

[0014] According to a second aspect of the present application, a semiconductor structure is provided, which is prepared by the preparation method as described above.

[0015] According to the semiconductor structure and the preparation method thereof, by forming a patterned photoresist negative layer first, then forming a first bonding metal layer, and finally removing the photoresist negative layer and the first bonding metal layer thereon to form a patterned first bonding metal layer on the device wafer, on the one hand, without using dry etching process, the etching residue can be effectively avoided to affect the subsequent etching process, and the thickness uniformity and surface flatness of the device wafer are improved, on the other hand, after the photoresist negative layer is patterned, an undercut is formed, which can effectively prevent the sidewall from depositing metal material, thereby effectively improving the peeling success rate of the first bonding metal layer. BRIEF DESCRIPTION OF DRAWINGS

[0016] The following drawings for the present application are hereby incorporated into this application as part of the present application for understanding the present application. The embodiments of the present application and its description shown in the drawings are used to explain the devices and principles of the present application. In the drawings, Figure 1 A flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application; Figures 2-9 A cross-sectional view of a structure corresponding to each step of a method for preparing a semiconductor structure according to an embodiment of the present application.

[0017] Explanation of reference signs: 100 - device wafer, 110 - bonding bump, 120 - trench, 130 - comb structure, 200 - cap wafer, 210 - substrate, 220 - dielectric layer, 230 - cavity, 300 - second photoresist layer, 400 - first photoresist layer, 500 - first bonding metal layer, 600 - wiring wafer, 610 - second bonding metal layer. DETAILED DESCRIPTION

[0018] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known

[0019] It should be understood that the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals in the figures denote like elements throughout.

[0020] It should be understood that although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in use, a downward

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a device and are not intended to limit the scope of the application.

[0024] Reference is made to the drawings of the accompanying Figure 1 A method for fabricating a semiconductor structure according to an embodiment of the present application is exemplarily illustrated. The method comprises the following steps: S10: patterning an upper portion of a device wafer to form a plurality of bonding bumps, wherein the plurality of bonding bumps have a trench therebetween; S20: forming a patterned first photoresist layer on the device wafer, wherein the first photoresist layer is a negative photoresist layer, the patterned first photoresist layer is located in the trench, and a thickness of the first photoresist layer is greater than a depth of the trench; S30: forming a first bonding metal layer on the first photoresist layer and on the bonding bumps; S40: removing the first photoresist layer and the first bonding metal layer located on the first photoresist layer.

[0025] According to the method for manufacturing the semiconductor structure, the first bonding metal layer is formed on the device wafer by forming a patterned photoresist layer first, and then removing the photoresist layer and the first bonding metal layer thereon, so that the first bonding metal layer is patterned. On one hand, the dry etching process is not needed, and the etching residue can be effectively avoided from affecting the subsequent etching process, so that the thickness uniformity and the surface flatness of the device wafer are improved. On the other hand, the undercut is formed after the photoresist layer is patterned, so that the metal material is effectively prevented from being deposited on the sidewall, and the peeling success rate of the first bonding metal layer is effectively improved.

[0026] Referring to the drawings Figure 2 - the drawings Figure 7 The method for manufacturing the semiconductor structure according to an embodiment of the present application (including the steps S10-S40) is described in detail. In this embodiment, the semiconductor structure is a structure in a MEMS device.

[0027] For example, referring to the drawings Figure 2 Before the step S10, the cap wafer 200 is bonded to the lower side of the device wafer 100, and the device wafer 100 is thinned. In this embodiment, the cap wafer 200 includes a substrate 210 and a dielectric layer 220 on the substrate 210. The upper part of the substrate 210 has a plurality of grooves, and the dielectric layer 220 covers the upper surface of the substrate 210 and the sidewall and bottom wall of the grooves. The part of the grooves not covered by the dielectric layer 220 becomes the cavity 230 between the cap wafer 200 and the device wafer 100 after the cap wafer 200 is bonded to the device wafer 100. For example, the substrate 210 can be a silicon substrate, and the dielectric layer 220 can be a silicon dioxide layer. In this embodiment, the device wafer 100 is a silicon wafer. The device wafer 100 is used to be processed by subsequent processes to form microstructures (such as cantilever beams, comb electrodes, etc.) on it to realize the specific functions of the MEMS device. In this step, the upper side of the cap wafer 200 (i.e., the upper surface of the dielectric layer 220) is bonded to the lower side of the device wafer 100 (i.e., the lower surface of the device wafer 100) by a bonding process. After the bonding is completed, the upper surface of the device wafer 100 is polished by a CMP (Chemical-mechanical Polishing) process to thin the device wafer 100 to a predetermined thickness range. The device wafer 100 is bonded with a relatively large thickness, which can ensure that the device wafer 100 has sufficient mechanical strength before and during the bonding process, so as to avoid the device wafer 100 from being broken during the transportation and bonding process. The device wafer 100 is thinned after the bonding, which can reduce the volume and improve the heat dissipation efficiency.

[0028] In the step S10, the upper part of the device wafer 100 is patterned to form a plurality of bonding protrusions 110. First, referring to the drawingsFigure 3 A patterned second photoresist layer 300 is formed on the device wafer 100. Specifically, a single layer of second photoresist layer 300 is first formed on the upper surface of the device wafer 100 by a method such as spin coating; then, a photomask (i.e., a mask) is used to pattern the second photoresist layer 300, that is, the second photoresist layer 300 is exposed using a photomask, followed by development, hardening, and other steps to form the patterned second photoresist layer 300. In this embodiment, the second photoresist layer 300 is a positive photoresist layer. The exposed areas of the positive photoresist layer have increased solubility due to chemical structure decomposition (and are removed by the developer during development), while the unexposed areas are retained. Using a positive photoresist layer for the second photoresist layer 300 can achieve higher resolution and better pattern fidelity, effectively reducing dimensional distortion. In some other embodiments, the second photoresist layer 300 can also be a negative photoresist layer. In this embodiment, some openings in the patterned second photoresist layer 300 correspond to the position of the cavity 230. That is, some openings are located above the cavity 230, and their projections in the vertical direction at least partially coincide with the cavity 230.

[0029] Then, see appendix. Figure 4 Using the second photoresist layer 300 as a mask, the device wafer 100 is etched to form trenches 120, and then the second photoresist layer 300 is removed. Specifically, the device wafer 100 is first etched using an etching process such as dry etching, using the second photoresist layer 300 as a mask, to form multiple trenches 120 on the device wafer 100; then, the second photoresist layer 300 is removed using a dry or wet stripping process. This forms multiple bonding bumps 110 on the upper part of the device wafer 100, with trenches 120 between the multiple bonding bumps 110. The bonding bumps 110 may include anchor points and bonding rings, and their upper surfaces are used to form a first bonding metal layer 500 to achieve bonding between the device wafer 100 and a substrate or other wafers. In this embodiment, there are multiple cavities 230 between the cap wafer 200 and the device wafer 100. The multiple cavities 230 correspond to the positions of multiple trenches 120, that is, the multiple trenches 120 are located above the multiple cavities 230, and their projections in the vertical direction at least partially coincide with the multiple cavities 230.

[0030] In step S20, see Appendix Figure 5A first photoresist layer 400 is formed on the device wafer 100. Specifically, a whole layer of the first photoresist layer 400 is first formed on the upper surface of the device wafer 100 by a method such as spin coating. Then, the first photoresist layer 400 is patterned by using a photomask (i.e. a mask plate). Specifically, the first photoresist layer 400 is exposed by using the photomask, and then developed, hardened, and the like to form the patterned first photoresist layer 400. In this embodiment, the first photoresist layer 400 is a negative photoresist layer, the patterned first photoresist layer 400 is located in the trench 120, the opening of the patterned first photoresist layer 400 exposes the upper surface of the bonding bump 110, and the thickness of the first photoresist layer 400 is greater than the depth of the trench 120. The exposed area of the negative photoresist layer is insoluble due to cross-linking reaction (retained during development), and the unexposed area is removed during development. Due to the light scattering during exposure and the difference in dissolution rate during development, the negative photoresist layer will form an undercut after patterning, which can prevent the sidewall from depositing metal material to some extent, thereby improving the success rate of subsequent first bonding metal layer 500 peeling. In this embodiment, the first photoresist layer 400 and the second photoresist layer 300 are patterned by the same photomask, i.e. the first photoresist layer 400 and the second photoresist layer 300 are exposed by the same photomask, so that one photomask can be used to expose both photoresist layers, which can effectively reduce production cost.

[0031] In step S30, referring to FIG. 4, a second photoresist layer 300 is formed on the device wafer 100. Specifically, a whole layer of the second photoresist layer 300 is first formed on the upper surface of the device wafer 100 by a method such as spin coating. Then, the second photoresist layer 300 is patterned by using a photomask (i.e. a mask plate). Specifically, the second photoresist layer 300 is exposed by using the photomask, and then developed, hardened, and the like to form the patterned second photoresist layer 300. In this embodiment, the second photoresist layer 300 is a positive photoresist layer, the patterned second photoresist layer 300 is located in the trench 120, the opening of the patterned second photoresist layer 300 exposes the upper surface of the bonding bump 110, and the thickness of the second photoresist layer 300 is greater than the depth of the trench 120. The exposed area of the positive photoresist layer is insoluble due to cross-linking reaction (retained during development), and the unexposed area is removed during development. Due to the light scattering during exposure and the difference in dissolution rate during development, the positive photoresist layer will form an undercut after patterning, which can prevent the sidewall from depositing metal material to some extent, thereby improving the success rate of subsequent second bonding metal layer 600 peeling. Figure 6 A first bonding metal layer 500 is formed on the first photoresist layer 400 and the bonding bump 110. Specifically, the first bonding metal layer 500 can be formed on the first photoresist layer 400 and the bonding bump 110 by a deposition process such as PVD process. Exemplarily, the material of the first bonding metal layer 500 includes at least one of aluminum, germanium, copper, tin, gold, and silver, as long as it can be bonded to other wafers or substrates by eutectic bonding. In this embodiment, since the patterned first photoresist layer 400 forms an undercut, the first bonding metal layer 500 is formed not only on the upper surface of the bonding bump 110, but also on the sidewall of the bonding bump 110 (i.e. the sidewall of the trench 120).

[0032] In step S40, referring to FIG. 5, a second bonding metal layer 600 is formed on the second photoresist layer 300 and the bonding bump 110. Specifically, the second bonding metal layer 600 can be formed on the second photoresist layer 300 and the bonding bump 110 by a deposition process such as PVD process. Exemplarily, the material of the second bonding metal layer 600 includes at least one of aluminum, germanium, copper, tin, gold, and silver, as long as it can be bonded to other wafers or substrates by eutectic bonding. In this embodiment, since the patterned second photoresist layer 300 forms an undercut, the second bonding metal layer 600 is formed not only on the upper surface of the bonding bump 110, but also on the sidewall of the bonding bump 110 (i.e. the sidewall of the trench 120). Figure 7, removing the first photoresist layer 400 and the first bonding metal layer 500 on the first photoresist layer 400. Specifically, the first photoresist layer 400 is dissolved by using a chemical solvent, so that it is separated from the surface of the device wafer 100. At the same time, the first bonding metal layer 500 on the first photoresist layer 400 loses support and is taken away by the solvent with the dissolved first photoresist layer 400, and finally the first bonding metal layer 500 deposited on the bonding bump 110 is reserved. In this way, the patterned first bonding metal layer 500 is formed on the device wafer 100.

[0033] The preparation method of the embodiment of the application does not need to use a dry etching process to etch the first bonding metal layer 500, which can effectively avoid uneven etching loss of the device wafer 100, and the thickness uniformity and surface roughness of the device wafer 100 are better, which provides a stable prerequisite for the preparation of the comb structure. On the other hand, it can effectively improve the side wall morphology of the first bonding metal layer 500 by avoiding the etching residues / side wall polymers that may be caused by dry etching.

[0034] For example, referring to FIG. 6, the device wafer 100 is provided, and the first photoresist layer 400 is formed on the surface of the device wafer 100. Figure 7 In this embodiment, the preparation method of the semiconductor structure further includes: S50: forming a comb structure 130 on the bottom of the trench 120 corresponding to the position of the cavity 230.

[0035] Specifically, the device wafer 100 part on the bottom of the trench 120 corresponding to the position of the cavity 230 can be etched by an etching process to form the comb structure 130 thereon. For example, the comb structure 130 can include movable mass blocks, elastic beams, and combs, and other key structures for realizing the function of the MEMS device. The cavity 230 can be used to provide movement space for the comb structure 130. For example, the comb structure 130 can be electrically connected with the first bonding metal layer 500. The specific structure form and etching method of the comb structure 130 are well known to those skilled in the art, which will not be described here. Since the thickness uniformity and surface roughness of the device wafer 100 of the embodiment of the application are relatively thick, a comb structure 130 with high quality can be formed, and thus the sensitivity, noise characteristics, and reliability of the finally formed MEMS device can be significantly improved.

[0036] For example, referring to FIG. 6, the device wafer 100 is provided, and the first photoresist layer 400 is formed on the surface of the device wafer 100. Figure 8 In this embodiment, the preparation method of the semiconductor structure further includes: S60: providing a wiring wafer 600, the surface of the wiring wafer 600 having a second metal bonding layer 610 corresponding to the first bonding metal layer 500; and metal bonding the wiring wafer 600 and the device wafer 100 through the first bonding metal layer 500 and the second metal bonding layer 610.

[0037] Specifically, the wiring wafer 600 is a functional wafer integrated with an electrical interconnection network, which plays a core role in efficiently leading out electrical signals (e.g., driving signals, detection signals, ground, etc.) of the device wafer 100 to an external circuit, while providing mechanical support and packaging basis for the device wafer 100. The wiring wafer 600 has a second metal bonding layer 610 corresponding to the first bonding metal layer 500 on the surface, and has a wiring layer electrically connected to the second metal bonding layer 610 in the wiring wafer 600. Exemplarily, the material of the second bonding metal layer 610 can include at least one of aluminum, germanium, copper, tin, gold, and silver, as long as it can be bonded with the first bonding metal layer 500 through eutectic bonding. The specific structural form and forming method of the wiring wafer 600 are known to those skilled in the art, and will not be described here. Exemplarily, in step S60, the wiring wafer 600 can be aligned with the structure formed in step S50, so that the first bonding metal layer 500 and the second metal bonding layer 610 are oppositely arranged and positionally corresponding, and then the first bonding metal layer 500 and the second metal bonding layer 610 are bonded through a metal bonding process such as thermal compression bonding, so that the wiring wafer 600 and the device wafer 100 are bonded together through the first bonding metal layer 500 and the second metal bonding layer 610, and the electrical signals of the device wafer 100 can be led out to the external circuit through the wiring wafer 600.

[0038] So far, the related steps of the preparation method of the semiconductor structure of the embodiment of the present application have been introduced. In addition to the above steps, the preparation method of the embodiment can also include other steps in the above steps or between different steps, which can be realized by various processes in the prior art, and will not be described here.

[0039] The present application also provides a semiconductor structure prepared by the preparation method as described above.

[0040] Although the example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

[0041] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the above-described device embodiments are only illustrative, for example, the division of the units is only a logical functional division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0042] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0043] Similarly, it is to be understood that the various features of the application can be used alone or in any combination depending on the embodiment of the application being used. It is therefore contemplated to this effect that the application can be practiced otherwise than is specifically explained in the detailed description and illustrations, without parting from the scope of the application. It is to be noted that the use of particular descriptive terms in the description is solely for the purpose of providing a clear and complete description of the application and should not be regarded as a limitation of the application. The use of the term "comprising" or "containing" means that other elements can also be present. The use of the term "including" means that other elements can also be present. The use of the term "consisting essentially of means that other elements can also be present, but only if the other elements do not materially alter the basic and novel characteristics of the described application. The use of the term "consisting of means that no other elements can be present.

[0044] Those skilled in the art will appreciate that all features described in this specification (including the summary of the application, abstract, and the claims) together with the drawings also form part of the original disclosure and that the disclosure of all features and all steps of any method or apparatus described herein, which follows from this original disclosure, can be performed by any combination of features other than those specifically stated in the specification (including the summary of the application, abstract, and the claims) again following the original disclosure. Except where expressly described otherwise, each feature disclosed in this specification (including the summary of the application, abstract, and the claims) can be replaced by alternative features serving the same, equivalent or a similar purpose to provide the same, equivalent or similar result.

[0045] Furthermore, those skilled in the art will recognize that references in the specification to "one embodiment", "an embodiment", "an example embodiment", means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily referring to a single embodiment. Furthermore, the terms "comprises", "comprising", "includes", "including", or the like, means "including but not limited to" or "comprising but not limited to". It is further noted that the claims can be drafted to exclude any or all embodiments that such terms can convey.

[0046] It is to be understood that the embodiments and variations thereof described herein are merely illustrative of the principles of the application and that numerous modifications may be devised by those skilled in the art without departing from the scope of the application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: The upper part of the patterned device wafer is used to form a plurality of bonding bumps, wherein the plurality of bonding bumps have trenches between them; A patterned first photoresist layer is formed on the device wafer, wherein the first photoresist layer is a photoresist negative layer, the patterned first photoresist layer is located in the trench, and the thickness of the first photoresist layer is greater than the depth of the trench. A first bonding metal layer is formed on the first photoresist layer and on the bonding protrusion; Remove the first photoresist layer and the first bonding metal layer located on the first photoresist layer.

2. The preparation method according to claim 1, characterized in that, The upper part of the patterned device wafer is used to form multiple bonding bumps, including: A patterned second photoresist layer is formed on the device wafer; The device wafer is etched using the second photoresist layer as a mask to form the trench; Remove the second photoresist layer.

3. The preparation method according to claim 2, characterized in that, The second photoresist layer is a positive photoresist layer.

4. The preparation method according to claim 3, characterized in that, The first photoresist layer and the second photoresist layer are patterned using the same photomask.

5. The preparation method according to claim 1, characterized in that, Before forming multiple bonding bumps on the upper part of the patterned device wafer, the fabrication method further includes: The cap wafer is bonded to the underside of the device wafer, and the device wafer is thinned.

6. The preparation method according to claim 5, characterized in that, There are multiple cavities between the cap wafer and the device wafer; The plurality of cavities correspond to the positions of the plurality of grooves respectively; The preparation method further includes: A comb-like structure is formed at the bottom of the groove corresponding to the cavity location.

7. The preparation method according to claim 1, characterized in that, The preparation method further includes: A wiring wafer is provided, the surface of which has a second metal bonding layer corresponding to the first bonding metal layer; The wiring wafer and the device wafer are metal-bonded through the first bonding metal layer and the second metal bonding layer.

8. The preparation method according to claim 7, characterized in that, The material of the first bonding metal layer and / or the second bonding metal layer includes at least one of aluminum, germanium, copper, tin, gold and silver.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method according to any one of claims 1-8.

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