Self-calibration measuring device and self-calibration measuring method for stray capacitance
By using a parasitic capacitance self-calibration measurement device and method, the problem of inaccurate capacitance measurement in the test path of ATE testers was solved, and the accurate measurement of the capacitance value of the device under test and the automated processing of wafer inspection were realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2026-03-27
AI Technical Summary
In the existing technology, the capacitance measurement of the test path of the ATE tester is inaccurate, which affects the accuracy of the capacitance measurement of the test device.
A parasitic capacitance self-calibration measurement device is adopted, including a parasitic capacitance measurement module and an error compensation module. By measuring the parasitic capacitance of the test circuit with and without the device under test, it is determined whether the first parasitic capacitance is within the preset range, and the measured capacitance value of the device under test is calculated.
This improves the accuracy and stability of capacitance measurement of test devices, avoids measurement errors caused by circuit connection problems, and enhances the automation efficiency of wafer inspection.
Smart Images
Figure CN121741302A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor testing, and in particular to a self-calibration measurement device and method for parasitic capacitance. BACKGROUND
[0002] In the current field of automatic test equipment (ATE), the method for measuring the capacitance of the test channel and the load board mainly uses the specification parameters of the ATE tester itself as an important reference. The ATE tester is equipped with a corresponding specification manual when it is shipped, which explicitly indicates the specific size of the capacitive load of the test component module of the ATE tester. Generally, this capacitive load size data can be used as a reference value for the test channel capacitance. However, it should be noted that this data only reflects the size of the load capacitance of the ATE tester itself.
[0003] In actual testing work, the test channel not only includes the ATE tester itself, but also includes other connected components. For example, when testing a silicon wafer, the ATE tester needs to be connected to the device under test on the wafer through an adapter structure; the adapter structure includes a device interface board (DIB), a spring adapter board (Pogo Tower), and a probe card (Probe Card) to establish a connection relationship. In this process, the adapter structure itself and the connections between the components will increase the load capacitance on the test channel on the original basis. Therefore, if the specification parameters of the ATE tester itself are simply used as the capacitance value on the test channel, it will lead to inaccurate measurement of the capacitance on the test channel. This inaccurate capacitance measurement problem will have a chain reaction and negatively affect the final measurement accuracy of the device under test, greatly reducing the accuracy of the measurement results.
[0004] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a self-calibration measurement device and method for parasitic capacitance, which solves the problem of inaccurate measurement of the test channel in the prior art, which ultimately affects the measurement of the capacitance value of the device under test.
[0006] To achieve the above-mentioned and other related purposes, the present application provides a self-calibration measurement device for parasitic capacitance, comprising:
[0007] a parasitic capacitance measurement module and an error compensation module;
[0008] The parasitic capacitance measuring module is connected to both ends of the test line, and is configured to measure a first parasitic capacitance of the test line without the device under test, and measure a second parasitic capacitance of the test line with the device under test.
[0009] The error compensation module is connected to the parasitic capacitance measuring module, and is configured to determine whether the first parasitic capacitance is within a preset capacitance range, and obtain a measured capacitance value of the device under test based on a difference between the second parasitic capacitance and the first parasitic capacitance when the first parasitic capacitance is within the preset capacitance range.
[0010] Optionally, the error compensation module includes a determination unit, a calculation unit, and a storage unit.
[0011] The storage unit is configured to provide the determination unit with a preset capacitance range of the first parasitic capacitance.
[0012] The determination unit is connected to the storage unit, and receives the first parasitic capacitance, and is configured to determine whether the first parasitic capacitance is within the preset capacitance range and output a control calculation signal when the first parasitic capacitance is within the preset capacitance range.
[0013] The calculation unit is connected to the determination unit, and receives the first parasitic capacitance and the second parasitic capacitance, and is configured to perform a subtraction operation on the second parasitic capacitance and the first parasitic capacitance based on the control calculation signal and output a measured capacitance value of the device under test.
[0014] Optionally, the parasitic capacitance self-calibration measuring device further includes a preset capacitance range calculation module; the preset capacitance range calculation module is arranged between the parasitic capacitance measuring module and the storage unit.
[0015] The preset capacitance range calculation module is configured to measure a parasitic capacitance value of the test line without the device under test in advance, and output the processed preset capacitance range to the storage unit for storage.
[0016] Optionally, the error compensation module further includes an error reporting unit.
[0017] The determination unit outputs an error reporting signal when the first parasitic capacitance is outside the preset capacitance range; and the error reporting unit is connected to the determination unit, and is configured to report an error based on the error reporting signal and stop the parasitic capacitance self-calibration measuring device.
[0018] To achieve the above object and other related objects, the present application provides a parasitic capacitance self-calibration measuring method, which includes:
[0019] S1, measuring a first parasitic capacitance of a test line without a device under test;
[0020] S2, judging whether the first parasitic capacitance is within a preset capacitance range, and measuring a second parasitic capacitance of a test circuit after a device under test is arranged when the first parasitic capacitance is within the preset capacitance range;
[0021] S3, obtaining a measured capacitance value of the device under test based on a difference between the second parasitic capacitance and the first parasitic capacitance.
[0022] Optionally, the first parasitic capacitance comprises a parasitic capacitance of the test circuit; and the second parasitic capacitance comprises the parasitic capacitance of the test circuit and the measured capacitance value of the device under test.
[0023] The parasitic capacitance of the test circuit comprises a parasitic capacitance of a measurement machine and a parasitic capacitance of a switching structure; and the switching structure is arranged between the measurement machine and the device under test.
[0024] Optionally, the preset capacitance range is set within a range of 95% to 105% of a preset value.
[0025] Optionally, the parasitic capacitance self-calibration measurement method further comprises a preset value acquisition step before step S1; and the preset value acquisition step comprises:
[0026] A1, measuring a parasitic capacitance value of a test circuit without arranging a device under test to obtain corresponding parasitic capacitance data;
[0027] A2, performing a data preprocessing algorithm on each parasitic capacitance data to remove abnormal data in each parasitic capacitance data;
[0028] A3, obtaining a preset value based on each parasitic capacitance data after the abnormal data is removed and storing the preset value.
[0029] Optionally, whether the first parasitic capacitance is within the preset capacitance range is judged, and when the first parasitic capacitance is outside the preset capacitance range, the parasitic capacitance self-calibration measurement method is stopped from being executed and the test circuit is powered on again.
[0030] Optionally, after the test circuit is powered on, step S1 is executed again.
[0031] As described above, the parasitic capacitance self-calibration measurement device and the self-calibration measurement method have the following beneficial effects:
[0032] The present application judges whether the parasitic capacitance test of the test circuit without arranging the device under test is normal through the error compensation module, and then tests the parasitic capacitance value of the test circuit with the device under test arranged, which avoids inaccurate test of the test circuit and finally affects the capacitance value measurement of the device under test. At the same time, the present application can facilitate the automatic test of wafer devices. BRIEF DESCRIPTION OF DRAWINGS
[0033] Figure 1 A frame diagram of a parasitic capacitance self-calibration measurement device according to the present application is shown.
[0034] Figure 2 A structure diagram of a parasitic capacitance self-calibration measurement device according to the present application is shown.
[0035] Figure 3 A step diagram of a parasitic capacitance self-calibration measurement method according to the present application is shown.
[0036] Figure 4 A step diagram of preset value collection according to the present application is shown.
[0037] Element number explanation
[0038] 1 parasitic capacitance self-calibration measurement device
[0039] 101 test line
[0040] 102 device to be measured
[0041] 11 parasitic capacitance measurement module
[0042] 12 error compensation module
[0043] 121 judging unit
[0044] 122 calculating unit
[0045] 123 storing unit
[0046] 124 error reporting unit
[0047] 13 preset capacitance range calculating module DETAILED DESCRIPTION
[0048] The present application is described in greater detail by the following specific examples. Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure herein. The present application can be implemented or applied in other different specific embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0049] Reference is made to Figures 1-4 It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application rather than the number, shape and size of the components in actual implementation. The shape, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complicated.
[0050] As shown in Figures 1-2 The embodiment provides a self-calibration measurement device for parasitic capacitance 1, which comprises a parasitic capacitance measurement module 11 and an error compensation module 12.
[0051] As shown in Figures 1-2 The parasitic capacitance measurement module 11 is connected to both ends of the test line 101, and is used for measuring a first parasitic capacitance C1 of the test line 101 without the to-be-tested device, and measuring a second parasitic capacitance C2 of the test line 101 with the to-be-tested device 102.
[0052] Specifically, in the embodiment, the parasitic capacitance measurement module 11 is set as a measurement machine, and the parasitic capacitance is measured by the measurement machine. Therefore, the parasitic capacitance value obtained by measuring the test line 101 at least includes a parasitic capacitance value of the measurement machine (not shown in the figure) and a parasitic capacitance value of a switching structure (not shown in the figure) connected between the measurement machine and the to-be-tested device 102. In the embodiment, the switching structure at least includes a wafer equipment interface board (DIB), a spring switching board (Pogo Tower) and a probe card (Probe Card), and therefore the parasitic capacitance value of the switching structure can be regarded as the sum of the parasitic capacitance values of the wafer equipment interface board, the spring switching board and the probe card.
[0053] It should be noted that the test line 101 in the first parasitic capacitance C1 and the second parasitic capacitance C2 is the same test line, and therefore the parasitic capacitance value of the test line 101 theoretically does not change.
[0054] As shown in Figures 1-2 The error compensation module 12 is connected to the parasitic capacitance measurement module 11, and is used for judging whether the first parasitic capacitance C1 is in a preset capacitance range, and obtaining a measured capacitance value C of the to-be-tested device 102 based on a difference between the second parasitic capacitance C2 and the first parasitic capacitance C1 (C=C2-C1) when the first parasitic capacitance C1 is in the preset capacitance range.
[0055] Specifically, as shown in Figure 2 The error compensation module 12 comprises a judging unit 121, a calculating unit 122 and a storage unit 123.
[0056] As an example, the storage unit 123 is used for providing the judging unit 121 with a preset capacitance range of the first parasitic capacitance C1.
[0057] As an example, the judging unit 121 is connected to the storage unit 123, receives the first parasitic capacitance C1, and is used for judging whether the first parasitic capacitance is in the preset capacitance range and outputting a control calculation signal when the first parasitic capacitance C1 is in the preset capacitance range.
[0058] In the embodiment, the judging unit 121 judges whether the value of the first parasitic capacitance C1 meets the preset capacitance range. Compared with the arrangement of directly measuring the capacitance value of the device under test 102 by using the parasitic capacitance measurement module 11 and directly calculating the capacitance value, the embodiment can effectively avoid problems such as that the parasitic capacitance measurement is abnormal and the capacitance value of the device under test 102 cannot be correctly measured due to a connection problem between the parasitic capacitance measurement module 11 and the test line 101 or a problem in the parasitic capacitance measurement module 11 and the test line 101.
[0059] For example, the calculating unit 122 is connected to the judging unit 121 and receives the first parasitic capacitance C1 and the second parasitic capacitance C2. Based on the control calculation signal, the calculating unit 122 performs subtraction operation on the second parasitic capacitance C2 and the first parasitic capacitance C1 and outputs the measured capacitance value of the device under test 102.
[0060] In the embodiment, the judging unit 121 first judges whether the first parasitic capacitance C1 measured currently meets the preset condition, so that the calculating step is started to calculate the measured capacitance value C of the device under test 102 under the preset condition. Since the preset capacitance range has been set in the storage unit 123 in the embodiment, the judging unit 121 and the calculating unit 122 in the embodiment can perform capacitance measurement on different devices under test on a wafer. Therefore, the parasitic capacitance self-calibration measurement device in the embodiment can be better applied to the field of wafer detection automation.
[0061] Specifically, the error compensation module 12 further includes an error reporting unit 124. When the first parasitic capacitance C1 is outside the preset capacitance range, the judging unit 121 outputs an error reporting signal. The error reporting unit 124 is connected to the judging unit 121 and reports an error based on the error reporting signal and stops the parasitic capacitance self-calibration measurement device 1.
[0062] For example, the error reporting unit 124 stops the parasitic capacitance self-calibration measurement device 1 after receiving the error reporting signal so as to subsequently manually check the error. In the embodiment, the error reporting unit 124 issues an error reporting sound after receiving the error reporting signal to remind that the parasitic capacitance self-calibration measurement device 1 has an error.
[0063] In the embodiment, the error reporting unit 124 further comprises a self-detection program which starts to detect each position of the parasitic capacitance self-calibration measurement device 1 after receiving the error reporting signal and stopping the parasitic capacitance self-calibration measurement device 1. For example, if there is a poor contact between the parasitic capacitance measurement module 11 and the test line 101, resulting in that the first parasitic capacitance C1 is not within the preset capacitance range, the judging unit 121 sends an error reporting signal, at this time, the error reporting unit 124 will stop the parasitic capacitance self-calibration measurement device 1 and start the self-detection program, detect the hardware inside the parasitic capacitance measurement module 11 of the test line 101, and detect the connection between the test line 101 and the parasitic capacitance measurement module 11 to determine whether there is a short circuit, a short circuit, or other connection problems and try to recover by re-powering; when re-powering still does not recover, the error is checked by manual intervention.
[0064] In the embodiment, the parasitic capacitance self-calibration measurement device 1 further comprises a preset capacitance range calculation module 13.
[0065] Specifically, the preset capacitance range calculation module 13 is arranged between the parasitic capacitance measurement module 11 and the storage unit 123. The preset capacitance range calculation module 13 is used to measure the parasitic capacitance value of the test line 101 without setting the device under test 102 in advance and output the processed preset capacitance range to the storage unit 123 for storage. By measuring the parasitic capacitance value of the test line 101 without setting the device under test 102 multiple times in advance, the preset value of the first parasitic capacitance C1 under the theoretical condition is obtained, and a certain fluctuation range of the preset value is taken as the preset capacitance range.
[0066] As shown in FIG. 1, Figure 3 The embodiment also provides a parasitic capacitance self-calibration measurement method, which comprises:
[0067] S1, measuring the first parasitic capacitance C1 of the test line 101 without setting the device under test 102.
[0068] Specifically, the first parasitic capacitance C1 includes the parasitic capacitance of the test line 101. The parasitic capacitance of the test line 101 includes the parasitic capacitance of the measurement machine and the parasitic capacitance of the adapter structure; the adapter structure is arranged between the measurement machine and the device under test.
[0069] In the embodiment, the adapter structure at least includes a wafer device interface board (DIB), a spring adapter board (Pogo Tower), and a probe card (Probe Card), so the parasitic capacitance value of the adapter structure can be regarded as the sum of the parasitic capacitance values of the wafer device interface board, the spring adapter board, and the probe card.
[0070] S2, judge whether the first parasitic capacitance C1 is in the preset capacitance range, and when the first parasitic capacitance C1 is in the preset capacitance range, measure the second parasitic capacitance C2 of the test circuit 101 in which the device under test 102 is arranged.
[0071] Specifically, the second parasitic capacitance C2 includes the parasitic capacitance of the test circuit and the measured capacitance value of the device under test. In this embodiment, it is first judged whether the first parasitic capacitance C1 is in the preset capacitance range, and after judging that the parasitic capacitance measurement module 11, the internal hardware of the test circuit 101 and the connection relationship are normal at this time, the device under test 102 is loaded, and the device under test 102 and the test circuit 101 are detected as a whole. By pre-verifying whether the measurement conditions are normal, on the one hand, the accuracy of detecting the measured capacitance value of the device under test can be improved; on the other hand, the efficiency of detection can also be improved, and problems such as repeated measurement and repeated calibration can be avoided.
[0072] Specifically, the preset capacitance range is set in the range of 95% to 105% of the preset value. For example, the preset capacitance value measured is 100pF, and the first parasitic capacitance C1 is in the range of 95pF to 105pF, and the subsequent second parasitic capacitance C2 measurement can be performed. Preferably, in this embodiment, the difference between the first parasitic capacitance C1 and the preset value is ±1nF.
[0073] Specifically, it is judged whether the first parasitic capacitance C1 is in the preset capacitance range, and when the first parasitic capacitance C1 is out of the preset capacitance range, the parasitic capacitance self-calibration measurement method is stopped.
[0074] As an example, after stopping the execution of the parasitic capacitance self-calibration measurement method, the self-detection program is started, and after the self-detection program is completed, the test circuit 101 is powered again. After the test circuit 101 is powered on, step S1 is executed again. It should be noted that after stopping the parasitic capacitance self-calibration measurement method, the hardware problems or connection problems in the connection circuit 101 and the parasitic capacitance measurement module 102 can also be checked by manual checking, and after checking, the power is turned on and step S1 is executed again.
[0075] S3, based on the difference between the second parasitic capacitance C2 and the first parasitic capacitance C1, the measured capacitance value C of the device under test 102 is obtained.
[0076] Specifically, after judging that the first parasitic capacitance C1 meets the preset capacitance range, the second parasitic capacitance C2 is measured. At this time, the second parasitic capacitance C2 is measured in the same parasitic capacitance measurement module 11 and test circuit 101, and the difference between the first parasitic capacitance C1 and the second parasitic capacitance C2 is whether the device under test 102 is arranged, so the measured capacitance value C of the device under test 102 is obtained by subtracting the first parasitic capacitance C1 from the second parasitic capacitance C2.
[0077] Specifically, the parasitic capacitance self-calibration measurement method further comprises a preset value acquisition step before step S1; the preset value acquisition step comprises:
[0078] A1, multiple measurements of the parasitic capacitance value of the test line 101 without setting the device under test 102 obtain corresponding parasitic capacitance data.
[0079] A2, a data preprocessing algorithm is performed on each parasitic capacitance data to remove abnormal data in each parasitic capacitance data.
[0080] A3, based on each parasitic capacitance data after removing abnormal data, a preset value is processed and stored.
[0081] In this embodiment, the average number of each parasitic capacitance data after removing abnormal data is calculated, and the preset value can also be obtained by median calculation and other methods.
[0082] It should be noted that the specific acquisition steps of the preset value are not limited to this embodiment, and a preset value can also be obtained by graph fitting and other methods.
[0083] It should be further noted that the parasitic capacitance self-calibration test method of the present embodiment is preferably set to detect at the product debugging stage, which is convenient for subsequent engineering production stage based on the obtained preset value to detect each measurement. In fact, as long as the range of the obtained preset value can be used as a setting to determine whether the first parasitic capacitance C1 is in the normal connection circuit, it is within the protection scope of the present embodiment.
[0084] In addition, the parasitic capacitance self-calibration measurement device and the self-calibration measurement method of the present embodiment need to test the parasitic capacitance of the test line 101 without setting the device under test 102 (i.e. the first parasitic capacitance C1) before each test loads the parasitic capacitance of the test line 101 of the device under test 102 (i.e. the second parasitic capacitance C2), which avoids the change of the parasitic capacitance value of the test line 101 that should be an invariant due to line connection and other reasons, thereby affecting the actual capacitance value of the device under test 102 obtained finally, improving the stability and accuracy of the capacitance value of the device under test 102 at each position of the test machine, and improving the test yield of the capacitance on the wafer.
[0085] In summary, the present application provides a kind of parasitic capacitance self-calibration measuring device and self-calibration measuring method, wherein parasitic capacitance self-calibration measuring device includes: parasitic capacitance measuring module and error compensation module;Parasitic capacitance measuring module is connected to the two ends of test circuit, for measuring the first parasitic capacitance of the test circuit without setting the device to be measured, and measuring the second parasitic capacitance of the test circuit after setting the device to be measured;Error compensation module is connected with parasitic capacitance measuring module, for judging whether the first parasitic capacitance is in the preset capacitance range, and when the first parasitic capacitance is in the preset capacitance range, the second parasitic capacitance is subtracted from the first parasitic capacitance, to obtain the measured capacitance value of the device to be measured.The present application first judges whether the parasitic capacitance test of test circuit is normal, and then tests the parasitic capacitance value of the test circuit after setting the device to be tested, which avoids the problem of inaccurate test of test circuit, and finally affects the capacitance value measurement of the device to be tested and other problems.Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0086] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.
Claims
1. A parasitic capacitance self-calibration measuring device, characterized in that, The parasitic capacitance self-calibration measurement device includes at least: a parasitic capacitance measurement module and an error compensation module; The parasitic capacitance measurement module is connected to both ends of the test circuit and is used to measure the first parasitic capacitance of the test circuit without the device under test and the second parasitic capacitance of the test circuit with the device under test. The error compensation module is connected to the parasitic capacitance measurement module and is used to determine whether the first parasitic capacitance is within a preset capacitance range. When the first parasitic capacitance is within the preset capacitance range, the measured capacitance value of the device under test is obtained based on the difference between the second parasitic capacitance and the first parasitic capacitance.
2. The parasitic capacitance self-calibration measuring device according to claim 1, characterized in that: The error compensation module includes a judgment unit, a calculation unit, and a storage unit; The storage unit is used to provide the determination unit with a preset capacitance range of the first parasitic capacitance; The judgment unit is connected to the storage unit and receives the first parasitic capacitance. It is used to determine whether the first parasitic capacitance is within a preset capacitance range and outputs a control calculation signal when the first parasitic capacitance is within the preset capacitance range. The calculation unit is connected to the judgment unit and receives the first parasitic capacitance and the second parasitic capacitance. Based on the control calculation signal, it performs a subtraction operation on the second parasitic capacitance and the first parasitic capacitance and outputs the measured capacitance value of the device under test.
3. The parasitic capacitance self-calibration measuring device according to claim 2, characterized in that: The parasitic capacitance self-calibration measurement device further includes a preset capacitance range calculation module; the preset capacitance range calculation module is disposed between the parasitic capacitance measurement module and the storage unit; The preset capacitance range calculation module is used to pre-measure the parasitic capacitance value of the test circuit without the device under test and output the processed preset capacitance range to the storage unit for storage.
4. The parasitic capacitance self-calibration measuring device according to claim 1, characterized in that: The error compensation module also includes an error reporting unit; When the first parasitic capacitance is outside the preset capacitance range, the judgment unit outputs an error signal; the error reporting unit is connected to the judgment unit, and reports an error and stops the parasitic capacitance self-calibration measurement device based on the error signal.
5. A method for self-calibrating parasitic capacitance measurement, characterized in that, The parasitic capacitance self-calibration measurement method includes at least the following: S1. Measure the first parasitic capacitance of the test circuit where no device under test is installed; S2. Determine whether the first parasitic capacitance is within the preset capacitance range, and when the first parasitic capacitance is within the preset capacitance range, measure the second parasitic capacitance of the test circuit after setting the device under test. S3. The measured capacitance value of the device under test is obtained based on the difference between the second parasitic capacitance and the first parasitic capacitance.
6. The parasitic capacitance self-calibration measurement method according to claim 5, characterized in that: The first parasitic capacitance includes the parasitic capacitance of the test circuit; the second parasitic capacitance includes the parasitic capacitance of the test circuit and the measured capacitance value of the device under test. The parasitic capacitance of the test circuit includes the parasitic capacitance of the measuring instrument and the parasitic capacitance of the adapter structure. The adapter structure is disposed between the measuring machine and the device under test.
7. The parasitic capacitance self-calibration measurement method according to claim 5, characterized in that: The preset capacitance range is set within the range of 95% to 105% of the preset value.
8. The parasitic capacitance self-calibration measurement method according to claim 7, characterized in that: The parasitic capacitance self-calibration measurement method also includes a preset value acquisition step before step S1; The preset value acquisition step includes: A1. Measure the parasitic capacitance of the test circuit without the device under test multiple times to obtain the corresponding parasitic capacitance data. A2. Perform a data preprocessing algorithm on each parasitic capacitance data to remove abnormal data from each parasitic capacitance data. A3. Based on the parasitic capacitance data after removing abnormal data, obtain preset values and store them.
9. The parasitic capacitance self-calibration measurement method according to claim 5, characterized in that: Determine whether the first parasitic capacitance is within a preset capacitance range. If the first parasitic capacitance is outside the preset capacitance range, stop executing the parasitic capacitance self-calibration measurement method and re-power the test circuit.
10. The parasitic capacitance self-calibration measurement method according to claim 9, characterized in that: After the test circuit is powered on, step S1 is executed again.