Method and apparatus for providing electronic device

Abstract

The invention relates to a method and an apparatus for providing an electronic device. The apparatus for providing an electronic device includes: a connection portion including a terminal at which the apparatus is connected to a display panel of the electronic device; a circuit board from which an electrical signal is supplied to the display panel, and to which the electrical signal generated from the display panel is supplied; and connection members each electrically connecting the connection portion to the circuit board. The connecting member includes a first connecting member having a first wiring through which a first electrical signal is transmitted, and a second connecting member having a second wiring through which a second electrical signal is transmitted. The first connecting member, the second connecting member, and the circuit board overlap each other in a thickness direction of the circuit board to define an overlapping region. In the overlapping region, the first wiring and the second wiring do not overlap.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0131091, filed on September 26, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to methods and apparatus. More specifically, one or more embodiments relate to methods and apparatus for manufacturing (or providing) electronic or display devices. Background Technology

[0004] Mobile electronic devices are already widely used. In addition to small electronic devices such as mobile phones, tablet PCs have recently become widely used as mobile electronic devices.

[0005] To support various functions, this mobile electronic device includes a display panel for providing users with visual information such as images or videos. As other components used to drive the display panel become smaller, the proportion of the electronic device's volume occupied by the display panel gradually increases, and structures capable of bending from a flat state to an angle have also been developed. Summary of the Invention

[0006] Typically, various tests can be performed to check the operation of a display panel, such as during methods of providing (or manufacturing) an electronic device including a display panel. In this regard, electrical signals applied to the display panel can be in the form of direct current (DC) and alternating current (AC), and therefore can influence or interact with each other. Consequently, at least one of the electrical signals applied to the display panel may include noise, or at least one of the electrical signals generated from the display panel may include noise, which may hinder accurate measurement of the display panel's operation. One or more embodiments include methods and apparatus for manufacturing (or providing) an electronic device or display device including a display panel, thereby allowing for accurate measurement and inspection thereon.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one or more embodiments, an apparatus for manufacturing (or providing) a display device and / or a display panel includes a connection portion including a plurality of terminals connected to a display panel, a first connection member connected to the connection portion and including a plurality of first wirings through which a signal applied to the display panel or a signal generated from the display panel is transferred, and a second connection member connected to the connection portion and including a plurality of second wirings through which the signal applied to the display panel or the signal generated from the display panel is transferred, wherein at least a portion of the first connection member and at least a portion of the second connection member overlap each other in a plan view, and a portion of at least one of the plurality of first wirings and a portion of at least one of the plurality of second wirings are disposed at different positions.

[0009] In an embodiment, a first width of a planar shape of the first connection member can be greater than a second width of a planar shape of the second connection member.

[0010] In an embodiment, the signal transferred through the first wirings can be in the form of an alternating current, and the signal transferred through the second wirings can be in the form of a direct current.

[0011] In an embodiment, a width of at least a portion of the planar shape of the first connection member can vary according to a length direction of the first connection member.

[0012] In an embodiment, at least one of the plurality of first wirings can be at least partially bent.

[0013] In an embodiment, at least one of the plurality of first wirings can include a 1-1 wiring inclined in a direction away from a center of the first connection member, a 1-2 wiring connected to the 1-1 wiring and disposed parallel to a length direction of the first connection member, and a 1-3 wiring connected to the 1-2 wiring and inclined in a different direction from the 1-1 wiring.

[0014] In an embodiment, the first connection member can further include an opening between some of the plurality of first wirings and other of the plurality of first wirings.

[0015] In an embodiment, in a plan view, the plurality of second wirings can be disposed between some of the plurality of first wirings and other of the plurality of first wirings.

[0016] In an embodiment, a distance between one of the plurality of second wirings and another of the plurality of second wirings adjacent to each other can be 20 µm or more.

[0017] In an embodiment, the first connection member can further include a shielding layer on a surface of the first connection member facing the second connection member.

[0018] According to one or more embodiments, a method of manufacturing a display apparatus includes: transmitting a first signal and a second signal to a display panel through a plurality of first wirings of a first connection member and a plurality of second wirings of a second connection member; and receiving a signal generated from the display panel through the plurality of second wirings, wherein at least a portion of the first connection member and at least a portion of the second connection member overlap each other in a plan view, and a portion of at least one of the plurality of first wirings and a portion of at least one of the plurality of second wirings are arranged at different positions in the plan view.

[0019] In an embodiment, a first width of a planar shape of the first connection member can be greater than a second width of a planar shape of the second connection member.

[0020] In an embodiment, the signal transmitted through the first wiring can be in the form of an alternating current, and the signal transmitted through the second wiring can be in the form of a direct current.

[0021] In an embodiment, a width of at least a portion of a planar shape of the first connection member can vary according to a length direction of the first connection member.

[0022] In an embodiment, at least one of the plurality of first wirings can be at least partially bent.

[0023] In an embodiment, at least one of the plurality of first wirings can include: a 1-1 wiring inclined in a direction away from a center of the first connection member; a 1-2 wiring connected to the 1-1 wiring and arranged parallel to a length direction of the first connection member; and a 1-3 wiring connected to the 1-2 wiring and inclined in a different direction from the 1-1 wiring.

[0024] In an embodiment, the first connection member can include an opening between some of the plurality of first wirings and other of the plurality of first wirings.

[0025] In an embodiment, in a plan view, the plurality of second wirings can be arranged between some of the plurality of first wirings and other of the plurality of first wirings.

[0026] In an embodiment, a distance between one of the plurality of second wirings and another of the plurality of second wirings adjacent to each other can be 20 µm or more.

[0027] In an embodiment, the first connection member can include a shielding layer on a surface of the first connection member facing the second connection member.

[0028] These general and specific embodiments can be implemented using a system, a method, a computer program, or any combination thereof. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic perspective view of an apparatus for manufacturing (or providing) an electronic device or a display device according to an embodiment; Figure 2 is a schematic perspective view of an apparatus for manufacturing (or providing) an electronic device or a display device according to an embodiment; Figure 1 is a schematic cross-sectional view of a probe terminal of a probe block shown in FIG. 1A; Figure 3 is a schematic plan view of a first connection member and a second connection member shown in FIG. 1A; Figure 1 is a schematic plan view of a first connection member and a second connection member shown in FIG. 1A; Figure 4 Figure 3 is a schematic cross-sectional view of a first connection member and a second connection member shown in FIG. 1A; Figure 5 is a schematic plan view of a first connection member of an apparatus for manufacturing a display device according to an embodiment; Figure 6 is a schematic plan view of a first connection member of an apparatus for manufacturing a display device according to an embodiment; Figure 7 is a schematic plan view of a first connection member of an apparatus for manufacturing a display device according to an embodiment; Figure 8A and Figure 8B is a schematic plan view of a display panel according to an embodiment; Figure 9 is an equivalent circuit diagram illustrating a pixel according to an embodiment; Figure 10 is an enlarged cross-sectional view of the display panel taken along line A-A' of Figure 8A or Figure 8B Figure 11 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and Figure 12 is a perspective view of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects of the present description.

[0031] ​​As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0032] Since the present description allows various changes and multiple embodiments, certain embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of one or more embodiments and methods of achieving the same will become apparent by the following detailed description of one or more embodiments in conjunction with the accompanying drawings.

[0033] One or more embodiments will be described in greater detail below with reference to the accompanying drawings. For those elements that are the same or correspond to one another, regardless of whether they are denoted by the same reference numerals, the same reference numerals are assigned and redundant descriptions thereof are omitted. In the drawings and the text of the disclosure, a reference numeral denoting a singular element can also be used to denote a plurality of elements.

[0034] Although terms such as "first" and "second" can be used to describe various elements, the elements should not be limited by the above terms. The above terms are used only to distinguish one element from another element. For example, 1-1, 1-2, 1-3, etc. can be used to index the first, second, third, etc. occurrence of an element.

[0035] The terms used herein are only for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise.

[0036] It will be understood that the terms "including," "comprising," and "having," as used herein, specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0037] It will also be understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly or indirectly on the other layer, region, or element. That is, for example, a layer, region, or element can exist between the layers, regions, or elements. In contrast, when a layer, region, or element is referred to as being "directly on" another layer, region, or element, there are no intervening layers, regions, or elements between them.

[0038] For ease of explanation, the size of the elements in the drawings can be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the purpose of facilitating the description, the following embodiments are not limited thereto.

[0039] The X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0040] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or another's relationship to another element as illustrated in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can therefore encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The terms "below" or "beneath" can therefore encompass both an orientation of above and below, depending on the particular orientation of the figure.

[0041] "about" or "approximately" as used herein includes the recited value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] While implementations can be described differently, a particular order in described processes can be performed differently. For example, two consecutively described processes can be performed at substantially the same time, or in an order opposite to the described order.

[0044] Figure 1 is a schematic perspective view of an apparatus 20 for manufacturing (or providing) an electronic device or a display device according to an embodiment. Figure 2 is Figure 1 is a schematic cross-sectional view of a probe terminal of a probe block 23 shown in FIG. 8. The apparatus 20 can be an inspection tool that measures or verifies an operation of an electronic device or a display device.

[0045] refer to Figure 1 The apparatus 20 for manufacturing a display device may include a test circuit board 21 as a circuit board, a connecting member 22, and a probe block 23 as a connecting portion of the apparatus 20.

[0046] Test board 21 can be connected to a signal generator (not shown) that is separate from test board 21 and configured to generate signals (e.g., electrical signals, test signals), wherein the signals are provided to test, for example, display panel 10 (see...). Figure 8A The electronic device is a signal generator, and the test circuit board 21 can be connected to a signal analyzer (not shown) configured to analyze signals generated from the display panel 10 to determine the operation or function of the display panel 10. In an embodiment, the signal generator and the signal analyzer can be integrally formed with the test circuit board 21.

[0047] The connecting member 22 can connect the test circuit board 21 and the probe block 23 to each other (e.g., electrically). In this respect, the connecting member 22 may include multiple connecting members 22, and the multiple connecting members 22 may be in a third direction or thickness direction of the device 20 (e.g., Figure 1 The multiple connecting members 22 are spaced apart from each other in the Z direction. The multiple connecting members 22 may be spaced apart from each other in a direction along the test circuit board 21 (such as a planar direction defined by directions that intersect each other and intersect with the thickness direction). Each connecting member 22 may be configured to transmit various signals such as electrical signals, test signals, etc. For example, one of the multiple connecting members 22 may be configured to transmit an alternating current (AC) signal. Furthermore, another of the multiple connecting members 22 may be configured to transmit a direct current (DC) signal.

[0048] For convenience, the following description will primarily focus on the configuration of multiple connecting members 22, which sequentially include a first connecting member 22-1, a second connecting member 22-2, ..., and an Nth connecting member 22-N, in the direction from the outside to the inside of the test circuit board 21. Here, N is a natural number of 3 or greater. Furthermore, the first connecting member 22-1 can be configured to transmit AC signals, and the second connecting members 22-2, ..., and the Nth connecting member 22-N can be configured to transmit DC signals.

[0049] Considering the third direction, the first connection member 22-1 can be disposed at the outermost side (or upper side) of the test circuit board 21. The second connection member 22-2 can be disposed between the first connection member 22-1 and the test circuit board 21. Also, the Nth connection member 22-N can be disposed between the second connection member 22-2 and the test circuit board 21. In the above case, each of the first connection member 22-1, the second connection member 22-2, …, and the Nth connection member 22-N can extend longitudinally from the probe block 23 and can be at least partially bent along the length direction. Accordingly, the space (or volume) occupied by each of the first connection member 22-1, the second connection member 22-2, …, and the Nth connection member 22-N within the device 20 can be reduced, so that the probe block 23 and the test circuit board 21 can be kept connected to each other even when the height in the third direction between the probe block 23 and the test circuit board 21 is not the same.

[0050] In this regard, the first connection member 22-1, the second connection member 22-2, …, and the Nth connection member 22-N can be flexible printed circuit boards (FPCBs) each as a flexible circuit board. Also, the first connection member 22-1, the second connection member 22-2, …, and the Nth connection member 22-N can each and separately have a first connection member connector 22-1e, a second connection member connector 22-2e, …, and an Nth connection member connector 22-Ne, respectively and separately at one end of the respective connection member, which is connected to the test circuit board 21, respectively. The connection member connectors can be provided at the distal end of the respective connection member. In this regard, the first connection member connector 22-1e, the second connection member connector 22-2e, …, and the Nth connection member connector 22-Ne can be arranged in a row along the direction of the test circuit board 21, such as along the length direction thereof. For example, the first connection member connector 22-1e, the second connection member connector 22-2e, …, and the Nth connection member connector 22-Ne can be arranged in a row in the second direction (e.g., Y direction of FIG. 1) in the planar direction. In this case, in a plan view, the first connection member 22-1, the second connection member 22-2, …, and the Nth connection member 22-N can overlap each other in the third direction. Figure 1

[0051] ​The probe block 23 can include a first body 23-1, a second body 23-2, and a probe terminal portion 23-3. The first body 23-1 and the second body 23-2 can be connected to each other to provide a single body, and can provide a space for connecting the probe terminal portion 23-3 to each connection member 22. For example, a separate wiring (not shown) can be arranged between the first body 23-1 and the second body 23-2 to connect the probe terminal portion 23-3 to each connection member 22, respectively. In an embodiment, a separate connection film (not shown) can be arranged between the first body 23-1 and the second body 23-2, and the connection film can also connect the probe terminal portion 23-3 to each connection member 22, respectively. In this case, the connection film can be provided in correspondence with the number of connection members 22. For convenience, hereinafter, a case in which the probe terminal portion 23-3 is connected to each connection member 22 by a separate wiring arranged within the first body 23-1 and the second body 23-2 will be mainly described.

[0052] The second body 23-2 can be arranged in correspondence with a pad portion (not shown) of a display panel 10, a display device, an electronic device, etc. (not shown). In this regard, the second body 23-2 can be coupled (e.g., electrically, physically, mechanically, etc.) to the pad portion of the display panel 10, or can be arranged on the pad portion. In an embodiment, the display panel 10 can have a pad portion connected to a separate FPCB different from the device 20, and can be arranged on the separate FPCB in correspondence with the separate FPCB, and connected to the probe terminal portion 23-3 of the device 20. In an embodiment, the display panel 10 can have a pad portion connected to a display circuit board described below, and the probe terminal portion 23-3 can be connected to the display circuit board. That is, the device 20 can be connected to an electronic device to be tested at a pad portion of the electronic device to be tested in this regard.

[0053] The probe terminal portion 23-3 can include a plurality of contact portions (not shown). In this regard, each of the contact portions can have a needle-shaped probe terminal and / or a recess shape or be defined by a needle-shaped probe terminal and / or a recess shape, and thus can be electrically connected to the display panel 10 at a pad portion such as the display panel 10. For convenience, hereinafter, a case in which the contact portions include probe terminals will be mainly described.

[0054] The plurality of probe terminals 23-3a and 23-3b can be arranged in the probe terminal portion 23-3, such as along the second body 23-2. In this regard, the plurality of probe terminals 23-3a and 23-3b can be divided into two regions (e.g., planar regions) along the length of the probe block 23, and arranged therein. For example, the plurality of probe terminals 23-3a and 23-3b can include first probe terminals 23-3a arranged in a first region 1A and second probe terminals 23-3b arranged in a second region 2A, where the second region 2A is adjacent to the first region 1A along the length of the probe block 23. In this regard, the alternating current signal can be transmitted through the first probe terminals 23-3a arranged in the first region 1A. The direct current signal can be transmitted through the second probe terminals 23-3b arranged in the second region 2A. That is, the first probe terminals 23-3a of the plurality of probe terminals 23-3a and 23-3b through which the alternating current signal is transmitted can be arranged at the periphery of the probe terminal portion 23-3, and the second probe terminals 23-3b through which the direct current signal is transmitted can be arranged in a central region of the probe terminal portion 23-3, which is distanced from the end (e.g., periphery) of the second body 23-2. Accordingly, when the signals are transmitted through each of the probe terminals 23-3a and 23-3b, such as simultaneously or synchronously, the influence of the alternating current signal on the direct current signal can be reduced.

[0055] According to the above operations of the apparatus 20 for manufacturing (or providing) a display device or an electronic device, the probe terminal portion 23-3 can be connected to a display panel 10 of such a display device or an electronic device. In this regard, the probe terminal portion 23-3 can be connected to the display panel 10 in various ways. For example, the probe terminal portion 23-3 can be arranged on a position changing apparatus for changing its position (e.g., raising or lowering the probe terminal portion 23-3), and the probe terminal portion 23-3 can selectively come into contact with a pad portion of the display panel 10 according to the operation of the position changing apparatus. In an embodiment, the second body 23-2 can be coupled to the pad portion of the display panel 10. In this regard, the pad portion can include a separate structure (not shown) at which the display panel 10 is coupled to the second body 23-2. In an embodiment, a separate adhesive member including a conductive material can be arranged between the second body 23-2 and the pad portion, and the probe terminal portion 23-3 and the pad portion can be connected to each other by the adhesive member. In an embodiment, the display panel 10 can be connected to a display controller (not shown) including a separate display circuit board, and the probe terminal can be connected to the display controller. In this regard, the method in which the probe terminal is connected to the display controller can be similar to the above method in which the probe terminal is connected to the pad portion of the display panel 10.

[0056] For convenience, a case in which the probe terminals directly contact the pad portions will be mainly described below. In this regard, the terminals (e.g., test terminals provided to include a plurality of test terminals) are arranged in the pad portions of the electronic device to be inspected or tested, and each probe terminal of the device 20 can directly contact each of the test terminals. When contacted, the elements can form an interface (e.g., a physical interface) therebetween.

[0057] When each probe terminal of the device 20 contacts each of the (test) terminals of the corresponding electronic device (e.g., the display panel 10), the signal generator can be configured to generate a signal and apply the signal to the display panel 10. In this regard, the signal can include at least one of various signals such as a bias control signal, an emission control signal, a clock signal, a data signal, a bias voltage, an initialization voltage, and a driving voltage for driving the display panel 10. In this regard, the bias control signal, the emission control signal, and the clock signal can be alternating current signals, and the data signal, the bias voltage, the initialization voltage, and the driving voltage can be direct current signals. In this case, the bias control signal, the emission control signal, and the clock signal can be transmitted through the first connection member 22-1, and the data signal, the bias voltage, the initialization voltage, and the driving voltage can be transmitted through one of the second connection member 22-2 to the Nth connection member 22-N. In this regard, each of the data signal, the bias voltage, the initialization voltage, and the driving voltage can be transmitted through each of the second connection member 22-2 to the Nth connection member 22-N.

[0058] In the above case, the signal generator can change a level of a first initialization voltage among the initialization voltages. Accordingly, a change in a second initialization voltage among the initialization voltages can be detected by the signal analyzer, and thus, it can be determined whether there is an abnormality in the operation of the display panel 10. In particular, the signal analyzer can detect a change in the amount of current of the first transistor of each sub-pixel of the display panel 10 by analyzing the change in the second initialization voltage.

[0059] In this case, the device 20 for manufacturing (or providing) a display device or an electronic device can reduce the influence of the alternating current signal on the direct current signal. In particular, the influence of the change in the alternating current signal on the slight change in the second initialization voltage can be reduced, and thus, the degree of change in the second initialization voltage can be accurately measured. In particular, in the above case, the change in the current that can be measured by the change in the second initialization voltage can be extended to the range of pico-ampere (pA).

[0060] Accordingly, the device 20 for manufacturing a display device and the method of manufacturing a display device using the device 20 can allow the display panel 10 to be accurately tested. Furthermore, the device 20 for manufacturing a display device and the method of manufacturing a display device using the device 20 can allow a small change in the current to be accurately detected.

[0061] Figure 3 is a schematic plan view of the first connection member 22-1 and the second connection member 22-2 shown in FIG. 1. Figure 1 Figure 4 is a schematic cross-sectional view of the first connection member 22-1 and the second connection member 22-2 shown in FIG. 1. Figure 3 Referring to

[0062] and Figure 3 , the first connection member 22-1 and the second connection member 22-2 can be stacked with each other, i.e., along a thickness direction of the test circuit board 21. In this regard, the first connection member 22-1 can include a first wiring 22-1a through which a signal is transmitted, and the second connection member 22-2 can include a second wiring 22-2a through which a signal is transmitted. In this regard, the first wiring 22-1a can include a first resin layer BD1, a first metal layer MT1, and a first cover layer RZ1. A shield layer IS1 can be provided on the first connection member 22-1. Figure 4 Within the first connection member 22-1, the first resin layer BD1 and the first metal layer MT1 can be provided as a single layer (e.g., in a single number) or as a plurality of layers (e.g., in a plurality of numbers). When one single first resin layer BD1 and one single first metal layer MT1 are provided, the first metal layer MT1 can be disposed on the first resin layer BD1, and the first metal layer MT1 can constitute the first wiring 22-1a. In an embodiment, when a plurality of first resin layers BD1 and a plurality of first metal layers MT1 are provided, the plurality of first resin layers BD1 and the plurality of first metal layers MT1 can be alternately stacked with each other, and each first metal layer MT1 can constitute one first wiring 22-1a. Further, because the first metal layers MT1 adjacent to each other in a thickness direction of the first resin layer BD1 are connected to each other, each first metal layer MT1 can constitute the first wiring 22-1a. In this regard, the first metal layers MT1 can be connected to each other through first vias TH1 that penetrate the first resin layer BD1. A separate metal can be filled in the first vias TH1, or a portion of the first metal layer MT1 can extend into the first vias TH1. For convenience, the following will mainly describe a case in which the first metal layer MT1 and the first resin layer BD1 are provided in a plurality of numbers and some of the plurality of first metal layers MT1 are connected to each other to constitute one first wiring 22-1a.

[0063]

[0064] ​​The shield layer IS1 can be disposed under the first connection member 22-1. The first cover layer RZ1 can shield the first metal layer MT1. In this regard, the first cover layer RZ1 can be disposed at the top and bottom of the first connection member 22-1. The shield layer IS1 can be disposed between the second connection member 22-2 and a portion of the first connection member 22-1, and thus a signal transmitted through the first wiring 22-1a can not affect a signal transmitted through the second wiring 22-2a. The shield layer IS1 can include an electromagnetic interference (EMI) shielding material. Here, along the thickness direction, the first connection member 22-1 includes the shield layer IS1 between the second connection member 22-2 and the remaining thickness portion of the first connection member 22-1.

[0065] The second connection member 22-2 can include a second resin layer BD2, a second metal layer MT2, a second cover layer RZ2, and a second via hole TH2. In this regard, the second resin layer BD2, the second metal layer MT2, the second cover layer RZ2, and the second via hole TH2 are the same as or similar to the above-described first resin layer BD1, the first metal layer MT1, the first cover layer RZ1, and the first via hole TH1, and thus a detailed description thereof is omitted.

[0066] The first connection member 22-1 and the second connection member 22-2 can be separated and spaced apart from each other along the thickness direction of the connection member. In this regard, the above-described alternating current signal can be transmitted through the first wiring 22-1a, and a direct current signal can be transmitted through the second wiring 22-2a. In this regard, the second connection member 22-2 can be provided in a plurality to include a plurality of second connection members 22-2. All of the plurality of second connection members 22-2 can be disposed under the first connection member 22-1. Thus, when a signal transmitted through the first wiring 22-1a changes over time, a change in a signal transmitted through the second wiring 22-2a due to the signal transmitted through the first wiring 22-1a can be reduced.

[0067] The first wiring 22-1a and the second wiring 22-2a can each be provided in a plurality to respectively include a plurality of first wirings 22-1a and a plurality of second wirings 22-2a. In this regard, a (first) portion of at least one of the plurality of first wirings 22-1a and a (first) portion of at least one of the plurality of second wirings 22-2a can not overlap each other. For example, another portion of the first wiring 22-1a and another portion of the second wiring 22-2a can cross or overlap each other. In this regard, the overlapping portion of the first wiring 22-1a and the second wiring 22-2a can have a minimum overlapping area so as to form a point in a plan view, or can be very short or small in a plan dimension.

[0068] In an embodiment, in a plan view, the plurality of first wirings 22-1a and the plurality of second wirings 22-2a can not overlap each other at all. For example, the plurality of second wirings 22-2a can be arranged between some of the plurality of first wirings 22-1a and other of the plurality of first wirings 22-1a. That is, the plurality of first wirings 22-1a can be divided into two groups, and the plurality of second wirings 22-2a can be arranged between the two groups of first wirings 22-1a. For example, Figure 3 A first group of the plurality of first wirings 22-1a and a second group of the plurality of first wirings 22-1a are shown, and a group of the plurality of second wirings 22-2a is arranged between the two groups of first wirings along the width direction of the connection member. Here, the first connection member 22-1 includes the first wirings 22-1a that are provided to include the plurality of first wirings 22-1a at opposite sides (e.g., opposite sides along the X direction) of the first connection member 22-1, and the second wirings 22-2a are between the first wirings 22-1a.

[0069] In a plan view, one of the plurality of first wirings 22-1a can be at least partially curved, in other words, can have at least one bend along the length of the first wiring 22-1a. For example, the first wiring 22-1a can include a 1-1 wiring 22-1aa (e.g., a first wiring portion or a 1-1 wiring portion) that is arranged diagonally along the longitudinal direction with respect to the length direction of the second wiring 22-2a and connected to the first probe terminal. The first wiring 22-1a can include a 1-2 wiring 22-1ab (e.g., a second wiring portion or a 1-2 wiring portion) connected to the 1-1 wiring 22-1aa that is arranged parallel to the length direction of the second wiring 22-2a along the longitudinal direction and is straight or linear in shape. The first wiring 22-1a can include a 1-3 wiring 22-1ac (e.g., a third wiring portion or a 1-3 wiring portion) connected to the 1-2 wiring 22-1ab and arranged diagonally along the longitudinal direction with respect to the length direction of the second wiring 22-2a. In this regard, the extension direction of the 1-3 wiring 22-1ac can be different from the extension direction of the 1-1 wiring 22-1aa. The 1-3 wiring 22-1ac can be connected to a corresponding connection member connector arranged at one end of the first connection member 22-1.

[0070] Each second wiring 22-2a can be straight, in other words, can not include a bend. The plurality of second wirings 22-2a can be spaced apart from each other by a distance. In this regard, a distance W1, which is a distance between each second wiring 22-2a and another second wiring 22-2a, can be about 20 micrometers (μm) or more, that is, equal to or greater than about 20 micrometers. When the distance W1 between the second wirings 22-2a adjacent to each other is about 20 μm, a leakage current between the adjacent second wirings 22-2a or between the outermost wiring of the second wirings 22-2a and the first wiring 22-1a adjacent to the outermost wiring can be the minimum. Accordingly, an influence between a signal transmitted through the second wiring 22-2a and a signal transmitted through the first wiring 22-1a can be minimized. On the other hand, when the distance W1 between each second wiring 22-2a and another second wiring 22-2a is less than 20 μm, a leakage current between the adjacent second wirings 22-2a or between the first wiring 22-1a and the outermost second wiring 22-2a can undesirably gradually increase.

[0071] In an embodiment, an apparatus 20 for providing an electronic device includes a connection portion (e.g., a probe block 23) including a probe terminal at which the apparatus 20 is connected to a display panel 10 of the electronic device, a circuit board (e.g., a test circuit board 21) from which an electrical signal is provided to the display panel 10 and an electrical signal generated from the display panel 10 is provided to the circuit board, and connection members each electrically connecting the connection portion to the circuit board, the connection members including a first connection member 22-1 including first wirings 22-1a through which a first electrical signal is transmitted between the connection portion and the circuit board and second connection members 22-2 through 22-N including second wirings 22-2a through which a second electrical signal is transmitted between the connection portion and the circuit board. Referring to Figure 1 and Figure 3 For example, the first connection member 22-1, the second connection members 22-2 through 22-N, and the circuit board overlap each other along a thickness direction (e.g., a Z direction) of the circuit board to define an overlapping region (e.g., a planar region common to each of the first connection member 22-1, the second connection members 22-2 through 22-N, and the circuit board). Within the overlapping region, the first wirings 22-1a and the second wirings 22-2a do not overlap.

[0072] In an embodiment, the first electrical signal includes an alternating current and the second electrical signal includes a direct current.

[0073] The first width L1 of the first connection member 22-1 and the second width L2 of the second connection member 22-2 can be different from each other. For example, the first width L1 can be greater than the second width L2. In this regard, the first width L1 and the second width L2 can be measured in a width direction perpendicular to a length direction of the first connection member 22-1 or a length direction of the second connection member 22-2. Here, the connection members each extend from the connection portion to the circuit board in one direction (Y direction), and in a direction (X direction) crossing the length direction, the width of the first connection member 22-1 is greater than the width of the second connection member 22-2.

[0074] Figure 5 is a schematic plan view of the first connection member 22-1 of the apparatus 20 for manufacturing a display device according to an embodiment.

[0075] Reference Figure 5 The apparatus 20 for manufacturing a display device can be the same as or similar to the apparatus 20 described above with reference to Figure 1 and Figure 2 For convenience, the first connection member 22-1 of the apparatus 20 for manufacturing a display device will be described in more detail below.

[0076] The first connection member 22-1 can include a first portion 22-1b, a second portion 22-1c, and a third portion 22-1d. Each of the portions can be a planar area of the first connection member 22-1, such as having a width along the X direction and a length along the Y direction. In this regard, the width of the first portion 22-1b can be different from the width of the second portion 22-1c. Further, the width of the second portion 22-1c can be different from the width of the third portion 22-1d. For example, the width of the first portion 22-1b and the width of the third portion 22-1d can be less than the width of the second portion 22-1c. In this regard, the width of the first portion 22-1b and the width of the third portion 22-1d can be the same as each other. Further, the width of the first connection member 22-1 can increase in a direction from the first portion 22-1b to the second portion 22-1c, and can decrease in a direction from the second portion 22-1c to the third portion 22-1d. In the above case, the first connection member connector 22-1e can be connected to the first connection member 22-1 at the third portion 22-1d, and the first connection member connector 22-1e can be connected to the test circuit board 21.

[0077] The first connection member 22-1 can include a first wiring 22-1a. In this regard, the first wiring 22-1a is the same as or similar to the first wiring 22-1a described above with reference to Figure 3 and Figure 4 and thus, a detailed description thereof is omitted.

[0078] Referring to Figure 4 The stack within the respective connection member can form a body of such connection member. One or more layers can define a portion (or entirety) of an outer edge of the body.

[0079] In Figure 5 , for example, the outer edge of the body of the first connection member 22-1 can extend in parallel to the wiring portion of the first wiring 22-1a. The extension direction of the outer edge can change direction along the Y direction at the bend of the body. Such a bend or change in direction can occur at a corner or a point, without being limited thereto. Although not shown, at least one of the portion where the first portion 22-1b and the second portion 22-1c are connected (e.g., bent) to each other and the portion where the second portion 22-1c and the third portion 22-1d are connected (e.g., bent) to each other can be rounded, rather than a corner or a point where the direction changes. Here, the connection members each extend in a direction from the connection portion to the circuit board, and the width of the first connection member 22-1 in a direction crossing the length direction varies along the length direction of the first connection member 22-1.

[0080] Figure 6 is a schematic plan view of the first connection member 22-1 of the apparatus 20 for manufacturing a display device according to an embodiment.

[0081] Referring to Figure 6 , the apparatus 20 for manufacturing a display device can be the same as or similar to the apparatus 20 described above with reference to Figure 1 and Figure 2 For convenience, the first connection member 22-1 of the apparatus 20 for manufacturing a display device will be described in more detail below.

[0082] The first connection member 22-1 can include the first wiring 22-1a and an opening 22-1f defined within a body of the first connection member 22-1. The first wiring 22-1a is the same as or similar to the first wiring 22-1a described above with reference to Figure 3 and Figure 4 , and thus a detailed description thereof is omitted.

[0083] The openings 22-1f can be disposed in a central portion of the first connection member 22-1. The openings 22-1f can be spaced apart from each other in the width direction with outer edges opposite each other. In this regard, the openings 22-1f can be in the form of holes that completely penetrate the body, or can be in the form of grooves that are partially recessed into the body such that the body has a minimum thickness at the openings 22-1f. The planar shape of the openings 22-1f can be a closed shape to provide a closed opening defined by portions of the body. Here, the first connection member 22-1 includes the first wiring 22-1a disposed to include a plurality of first wirings 22-1a and the openings 22-1f defined in the first connection member 22-1 and between the first wirings 22-1a.

[0084] The openings 22-1f can not only reduce the load on the first connection member 22-1, but also increase the flexibility of the first connection member 22-1. Although not shown, the openings 22-1f can at least partially overlap the second wirings 22-2a shown in FIG. 2B. Figure 3 That is, the width of the openings 22-1f can be the same as, or can be greater than, the width of the region in which the plurality of second wirings 22-2a are disposed.

[0085] Although not shown, the width of the first connection member 22-1 can be similar to the width shown in FIG. 2B. Figure 5

[0086] Figure 7 is a schematic plan view of a first connection member 22-1 of an apparatus 20 for manufacturing a display device according to an embodiment.

[0087] Referring to Figure 7 , the apparatus 20 for manufacturing a display device can be the same as or similar to the apparatus 20 described above with reference to Figure 1 and Figure 2 For convenience, the first connection member 22-1 of the apparatus 20 for manufacturing a display device will be described in more detail below.

[0088] The first connection member 22-1 can include a plurality of first wirings 22-1a. Two groups of the first wirings 22-1a can be respectively disposed at opposite sides of the body of the first connection member 22-1. Instead of linearly extending, the planar shape of at least one of the plurality of first wirings 22-1a can be rounded or curved along the length direction of the body. In this regard, the curved first wiring 22-1a can have one or more radii of curvature along the length direction of the body. The plurality of radii of curvature can include more than one inflection point at which the extension direction of the first wiring 22-1a changes. The plurality of first wirings 22-1a can not overlap the second wirings 22-2a as shown in Figure 3 .​

[0089] Although not shown, the width of the first connecting member 22-1 can be similar to the width shown in Figure 5 .

[0090] Figure 8A and Figure 8B is a schematic plan view of a display panel 10 according to an embodiment.

[0091] Referring to Figure 8A , a display device (or an electronic device) can include the display panel 10, and a cover window (not shown) for protecting the display panel 10 can be further disposed on the display panel 10, and an image generated by the display panel 10 can be seen through the cover window.

[0092] In a plan view, the display panel 10 can have a rectangular shape as shown in Figure 8A . Among two pairs of sides of the rectangle, one pair of sides can be longer than the other pair of sides. In the display panel 10 shown in Figure 8A , a first direction (X direction, row direction) indicates a direction along which a long side extends, a second direction (Y direction, column direction) indicates a direction along which a short side extends, and a direction perpendicular to the extension directions of the long side and the short side is indicated as a third direction (Z direction, e.g., thickness direction). At least one corner of the display panel 10 can have a rounded shape.

[0093] Referring to Figure 8A , the display panel 10 can include a display area DA in which a plurality of pixels PX are disposed and a peripheral area PA outside the display area DA. The peripheral area PA can be a non-display area in which the pixels PX are not disposed. The display area DA can be completely surrounded by the peripheral area PA. Various elements constituting the display panel 10 are disposed on the substrate 100. Accordingly, the substrate 100 can be considered to include the display area DA and the peripheral area PA.

[0094] The display panel 10 can provide a certain image by using light emitted from the plurality of pixels PX disposed in the display area DA. The pixels PX can emit, for example, red light, green light, or blue light. Alternatively, the pixels PX can emit red light, green light, blue light, or white light. The pixels PX can include display elements, and the display elements can include organic light emitting diodes. The display elements can be connected to a pixel circuit configured to drive the display elements. A certain image can be provided by light emitted from the pixels PX.

[0095] Various wirings configured to transmit electrical signals to be applied to the display area DA via the pixel circuit, terminals PAD connected to the wirings to transmit signals applied from the outside of the display panel 10 to the wirings, and the driver DRV can be arranged in the peripheral area PA. The various wirings configured to transmit electrical signals can include a drive voltage supply line 11, a common voltage supply line 13, a first initialization voltage supply line 15, a second initialization voltage supply line 17, and a bias voltage supply line 19.

[0096] Electrical signals such as control signals, test signals, and the like can be received by the display panel 10 at one or more of the terminals PAD. The terminals PAD of the display panel 10 can represent a pad portion at which a test device is connected to the display panel 10. In an embodiment, the probe terminal portion 23-3 can be connected to the display panel 10 at the terminals PAD of the display panel 10. For example, the terminals PAD can be physically exposed to the outside of the display panel 10 such that external elements such as a test device, an electronic component, and the like can be in electrical contact with the terminals PAD.

[0097] The drive voltage supply line 11 can include a first drive voltage supply line 11a and a second drive voltage supply line 11b. The common voltage supply line 13 can include a first common voltage supply line 13a and a second common voltage supply line 13b. The first drive voltage supply line 11a can be connected to the terminals PAD through a connection line 11c and can extend in the X direction at a first planar area below the display area DA. The second drive voltage supply line 11b extending in the X direction can also be provided in a second area above the display area DA and opposite the first planar area. The first common voltage supply line 13a can be connected to the terminals PAD through a connection line 13c and can extend in the X direction at the first planar area below the display area DA. The second common voltage supply line 13b can be connected to the terminals PAD and can have a ring shape with one side open and partially surrounding the display area DA in a plan view.

[0098] The first initialization voltage supply line 15 can be connected to the terminal PAD through a connection line 15c and can extend in the X direction at the first planar area below the display area DA. The second initialization voltage supply line 17 can be connected to the terminal PAD through a connection line 17c and can extend in the X direction at the first planar area below the display area DA. The bias voltage supply line 19 can be connected to the terminal PAD through a connection line 19c and can have a ring shape and surround the display area DA. The bias voltage supply line 19 can be connected to a plurality of bias voltage lines BL and a plurality of vertical bias voltage lines BLv arranged in the display area DA. Accordingly, the bias voltage lines BL can have a mesh structure in the display area DA. In an embodiment, the bias voltage supply line 19 can have a ring shape with the upper side open.

[0099] The driver DRV can be in the form of one or more integrated circuit chips and mounted on the substrate 100. The driver DRV can be configured to generate a data signal, and the data signal can be transmitted to the pixel circuit of the pixel PX through a data line of the display area DA. The driver DRV can be configured to generate a control signal, which is transmitted to a scan driving circuit (not shown) arranged in the peripheral area PA. The scan driving circuit can be arranged in the peripheral area PA on the left side and / or the right side of the substrate 100, with the display area DA between them, that is, the display area DA between them in the X direction. The scan driving circuit can overlap some of the wirings arranged in the peripheral area PA. The scan driving circuit can be configured to generate a scan signal, and the scan signal can be transmitted to the pixel circuit through a scan line of the display area DA.

[0100] Although the organic light emitting display apparatus will be described below as an example of the display apparatus according to an embodiment, the display apparatus described herein is not limited thereto. In an embodiment, the display apparatus described herein can be a display apparatus such as an inorganic light emitting display (or inorganic electroluminescent (EL) display) or a quantum dot light emitting display. For example, an emission layer of a display element included in the display apparatus can include an organic material or an inorganic material. Alternatively, the display apparatus can include an emission layer and a quantum dot on a path of light emitted from the emission layer.

[0101] Reference Figure 8B , Figure 8B The display panel 10a shown in FIG. 1A is different from the display panel 10b shown in FIG. 1B in that the display panel 10a includes the bias voltage supply line 19 and the bias voltage lines BL and BLv, and the display panel 10b does not include the bias voltage supply line 19 and the bias voltage lines BL and BLv. Figure 8AThe display panel 10 shown in FIG. 1 differs in that, in a plan view, the second direction (Y direction) has a long side, and the first direction (X direction) has a short side. A display circuit board 30 on which a display driver 32 is arranged can be connected to one side of the display panel 10a. The display driver 32 can be configured to generate a control signal that is transmitted to a scan driving circuit (not shown) of the peripheral area PA. The display driver 32 can be configured to generate a data signal and transmit the data signal to the pixel circuit of the display area DA.

[0102] Figure 9 is an equivalent circuit diagram showing a pixel PX according to an embodiment.

[0103] Reference Figure 9 The pixel PX includes a pixel circuit PC and an organic light emitting diode OLED as a display element, which is connected to the pixel circuit PC and a common voltage supply line that supplies a common voltage ELVSS to the organic light emitting diode OLED. The pixel circuit PC can include a first to eighth transistors T1 to T8, a capacitor Cst, and signal lines connected thereto. The signal lines can include a data line DL, a first gate line GWL, a second gate line GCL, a third gate line GIL, an emission control line EML, a bias control line EBL, a first and second initialization voltage lines VL1 and VL2, a driving voltage line PL, and a bias voltage line BL.

[0104] The first to third gate lines GWL, GCL, and GIL, the emission control line EML, and the bias control line EBL can be gate control lines to which a gate signal for controlling the on and off of the transistors is applied. The driving voltage line PL can be configured to transmit a driving voltage ELVDD to the first transistor T1. The driving voltage ELVDD can be a high voltage supplied to a pixel electrode (first electrode or anode) of the organic light emitting diode OLED included in each pixel PX. The first initialization voltage line VL1 can be configured to transmit a first initialization voltage Vint for initializing the first transistor T1 to the pixel PX. The second initialization voltage line VL2 can be configured to transmit a second initialization voltage Vaint for initializing the organic light emitting diode OLED to the pixel PX. The bias voltage line BL can be configured to transmit a bias voltage Vbias to the first transistor T1.

[0105] The first transistor T1 can be a driving transistor, and the second transistor T2 to the eighth transistor T8 can be switching transistors. According to the type (N-type or P-type) and / or operating conditions of the transistors, the first terminal of each of the first transistor T1 to the eighth transistor T8 can be a source terminal or a drain terminal, and the second terminal can be a terminal different from the first terminal. For example, when the first terminal is a source terminal, the second terminal can be a drain terminal. In an embodiment, the source terminal and the drain terminal can be interchangeably referred to as a source electrode and a drain electrode, respectively.

[0106] The first transistor T1 can be connected between a driving voltage line PL and an organic light emitting diode OLED. The first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and can be electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 includes a gate connected to a second node N2, a first terminal connected to a first node N1, and a second terminal connected to a third node N3. The first transistor T1 can be configured to receive a data signal according to a switching operation of the second transistor T2, and to supply a driving current to the organic light emitting diode OLED.

[0107] The second transistor T2 (data write transistor) can be connected between a data line DL and the first node N1, and can be connected to the driving voltage line PL via the fifth transistor T5. The first node N1 can be a node to which the first transistor T1 and the fifth transistor T5 are connected. The second transistor T2 includes a gate connected to a first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1 (or the first terminal of the first transistor T1). The second transistor T2 can be turned on according to a first gate signal GW received through the first gate line GWL to perform a switching operation for transmitting a data signal DATA transmitted through the data line DL to the first node N1.

[0108] The third transistor T3 (compensation transistor) can be connected between the second node N2 and the third node N3. The third transistor T3 can be connected to the organic light emitting diode OLED via the sixth transistor T6. The second node N2 can be a node to which the gate of the first transistor T1 is connected, and the third node N3 can be a node to which the first transistor T1 and the sixth transistor T6 are connected. The third transistor T3 includes a gate connected to a second gate line GCL, a first terminal connected to the second node N2 (or the gate of the first transistor T1), and a second terminal connected to the third node N3 (or the second terminal of the first transistor T1). The third transistor T3 can be turned on according to a second gate signal GC received through the second gate line GCL to diode-connect the first transistor T1, thereby compensating for a threshold voltage of the first transistor T1.

[0109] The fourth transistor T4 (first initialization transistor) can be connected between the second node N2 and the first initialization voltage line VL1. The fourth transistor T4 includes a gate connected to the third gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1. The fourth transistor T4 can be turned on according to the third gate signal GI received through the third gate line GIL to transmit the first initialization voltage Vint to the gate of the first transistor T1 and initialize the gate of the first transistor T1.

[0110] The fifth transistor T5 (first emission control transistor) can be connected between the driving voltage line PL and the first node N1. The sixth transistor T6 (second emission control transistor) can be connected between the third node N3 and the organic light emitting diode OLED. The fifth transistor T5 includes a gate connected to the emission control line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 includes a gate connected to the emission control line EML, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EM received through the emission control line EML, and thus a driving current flows through the organic light emitting diode OLED.

[0111] The seventh transistor T7 (second initialization transistor) can be connected between the organic light emitting diode OLED and the second initialization voltage line VL2. The seventh transistor T7 can include a gate connected to the bias control line EBL, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to the second initialization voltage line VL2. The seventh transistor T7 can be turned on according to the bias control signal EB received through the bias control line EBL to transmit the second initialization voltage Vaint to the pixel electrode of the organic light emitting diode OLED and initialize the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 can be omitted.

[0112] The eighth transistor T8 (bias transistor) can be connected between the first node N1 and the bias voltage line BL. The eighth transistor T8 can include a gate connected to the bias control line EBL, a first terminal connected to the bias voltage line BL, and a second terminal connected to the first node N1. The eighth transistor T8 can be turned on according to the bias control signal EB received through the bias control line EBL to apply the bias voltage Vbias to the first terminal of the first transistor T1 and to pre-set the first terminal to a voltage suitable for a subsequent operation of the first transistor T1.

[0113] In Figure 9In the embodiment, the pixel circuit PC in which the first to eighth transistors T1 to T8 are implemented as p-channel MOSFETs (PMOS) is shown, but one or more embodiments are not limited thereto. In the pixel circuit PC, the third and fourth transistors T3 and T4 among the first to eighth transistors T1 to T8 can be implemented as n-channel MOSFETs (NMOS), and the remaining transistors can be implemented as p-channel MOSFETs (PMOS).

[0114] The apparatus 20 for manufacturing a display device can measure at least one of a transfer curve, a hysteresis, a leakage current, and a driving range of the first transistor T1. In particular, the apparatus 20 for manufacturing a display device can detect a defect in the display panel 10 through a color deviation test and a residual image test by measuring a current for each driving range portion of the first transistor T1.

[0115] Figure 10 is a cross-sectional view of the display panel 10 or 10a taken along a line A-A' of Figure 8A or Figure 8B .

[0116] Referring to Figure 10 , the display panel 10 or 10a can include a substrate 100, a pixel circuit layer PCL, and a light emitting diode layer DEL as a display element layer.

[0117] Elements within the pixel circuit layer PCL can define a pixel circuit. The pixel circuit layer PCL can include elements of transistors and capacitors, and insulating layers arranged below and / or above the elements. In this regard, Figure 10 The first transistor T1, the third transistor T3, and the capacitor Cst among the transistors and capacitors included in the pixel circuit are shown. In addition, the pixel circuit layer PCL can include an inorganic insulating layer IIL and an organic insulating layer OIL. For example, as shown in Figure 10 , the inorganic insulating layer IIL can include a buffer layer 111, a first gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a second gate insulating layer 115, and a third interlayer insulating layer 116. The organic insulating layer OIL can include a first organic insulating layer 121 and a second organic insulating layer 123.

[0118] The substrate 100 can include a glass material, a ceramic material, a metal material, a plastic, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 can include a polymer resin such as polyether sulfone (PES), polyacrylate, polyether imide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, cellulose acetate propionate (CAP), or the like.

[0119] The substrate 100 can have a single-layer structure or a multi-layer structure including the above materials. In the multi-layer structure, the substrate 100 can further include an inorganic layer. For example, the substrate 100 can include a first organic base layer 101, a first inorganic barrier layer 102, a second organic base layer 103, and a second inorganic barrier layer 104. Each of the first and second organic base layers 101 and 103 can include a polymer resin. The first and second inorganic barrier layers 102 and 104 are barrier layers that prevent external foreign substances from penetrating, and can include a single layer or a plurality of layers including an inorganic insulating material such as silicon nitride and / or silicon oxide.

[0120] A bottom metal layer BML can be disposed on the substrate 100. The bottom metal layer BML can include one or more materials selected from among aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the bottom metal layer BML can include a single molybdenum layer, can have a two-layer structure in which a molybdenum layer and a titanium layer are stacked, or can have a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0121] A buffer layer 111 can be disposed on the bottom metal layer BML. The buffer layer 111 can be an inorganic insulating layer including an inorganic insulating material such as silicon nitride and / or silicon oxide, and can have a single-layer structure or a multi-layer structure including the above materials.

[0122] A silicon semiconductor layer of a silicon-based transistor can be disposed on the buffer layer 111. In this regard, Figure 10 A semiconductor layer A1 corresponding to a portion of the silicon semiconductor pattern SACT of the first transistor T1 is illustrated. The semiconductor layer A1 can include a channel region C1 and impurity regions disposed on both sides of the channel region C1 and doped with impurities, and Figure 10 A second region D1 disposed on one side of the channel region C1, which is one of the impurity regions, is illustrated.

[0123] A first gate insulating layer 112 can be disposed on the silicon semiconductor pattern SACT. The first gate insulating layer 112 can be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can have a single-layer structure or a multi-layer structure including the above materials.

[0124] A gate electrode G1 and a first capacitor electrode CE1 can be disposed on the first gate insulating layer 112. Figure 10The gate electrode G1 is shown to be formed integrally with the first capacitor electrode CE1 as a single continuous body. In other words, the gate electrode G1 can function as the first capacitor electrode CE1, or the first capacitor electrode CE1 can function as the gate electrode G1.

[0125] The gate electrode G1 and / or the first capacitor electrode CE1 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or a plurality of layers including the above materials.

[0126] The first interlayer insulating layer 113 can be arranged over the gate electrode G1 and / or the first capacitor electrode CE1. The first interlayer insulating layer 113 can be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can have a single-layer structure or a multi-layer structure including the above materials.

[0127] The second capacitor electrode CE2 can be arranged on the first interlayer insulating layer 113. The second capacitor electrode CE2 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or a plurality of layers including the above materials. The second capacitor electrode CE2 can overlap the gate electrode G1 and / or the first capacitor electrode CE1. The second capacitor electrode CE2 can include an opening SOP so that the connection electrode 161 electrically connected to the first end of the first connection electrode 171 can also be connected to the gate electrode G1. The opening SOP can overlap a portion of the gate electrode G1. Although not shown, the other end of the first connection electrode 171 can be electrically connected to the source region of the third transistor T3.

[0128] The second interlayer insulating layer 114 can be arranged over the second capacitor electrode CE2. The second interlayer insulating layer 114 can be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can have a single-layer structure or a multi-layer structure including the above materials.

[0129] The oxide semiconductor layer can be arranged on the second interlayer insulating layer 114. In this regard, Figure 10 A portion of the semiconductor layer A3 of the third transistor T3 corresponding to the oxide semiconductor pattern OACT is shown. The semiconductor layer A3 can include a channel region C3 and conductive regions arranged on both sides of the channel region C3, and Figure 10A second region D3 arranged on one side of the channel region C3 is shown as one of the conductive regions. A vertical distance from the substrate 100 to the semiconductor layer A3 can be greater than a vertical distance from the substrate 100 to the semiconductor layer Al. That is, along a thickness direction of the display panel 10, the semiconductor layer A3 can be farther from the substrate 100 than the semiconductor layer Al.

[0130] The gate electrode G3 can include portions arranged below and / or above the semiconductor layer A3, respectively. Figure 10 The gate electrode G3 is shown to include a bottom gate electrode G3a arranged below the semiconductor layer A3 and a top gate electrode G3b arranged above the semiconductor layer A3. In an embodiment, one of the bottom gate electrode G3a and the top gate electrode G3b can be omitted.

[0131] The bottom gate electrode G3a can include the same material as that of the second capacitor electrode CE2, and can be arranged on a layer (e.g., the first interlayer insulating layer 113) on which the second capacitor electrode CE2 is arranged. That is, the bottom gate electrode G3a and the second capacitor electrode CE2 can be in the same layer. Because in the same layer, the elements can be formed in the same process and / or include the same material as each other, the elements can be respective portions of the same material layer, the elements can be on the same layer by forming an interface with the same underlying or overlying layer, the elements can be coplanar with each other or disposed with the same thickness, and the like, without being limited thereto.

[0132] The top gate electrode G3b can be arranged above the semiconductor layer A3 with the second gate insulating layer 115 therebetween. The top gate electrode G3b can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or a plurality of layers including the above materials.

[0133] Figure 10 The second gate insulating layer 115 is shown as a pattern arranged only between the top gate electrode G3b and the semiconductor layer A3, but one or more embodiments are not limited thereto. In an embodiment, the second gate insulating layer 115 can completely cover the substrate 100 as another insulating layer, such as the first gate insulating layer 112, for example. The second gate insulating layer 115 can be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can have a single layer structure or a multi-layer structure including the above materials.

[0134] A third interlayer insulating layer 116 can be disposed on the top gate electrode G3b and the connection electrode 161. The third interlayer insulating layer 116 can be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and can have a single-layer structure or a multi-layer structure including the above materials.

[0135] The first connection electrode 171 and the second connection electrode 172 can be disposed on the third interlayer insulating layer 116. The first connection electrode 171 and the second connection electrode 172 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or a plurality of layers including the above materials. For example, the first connection electrode 171 and the second connection electrode 172 can include a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0136] The second connection electrode 172 can electrically connect the semiconductor layer A1 and the semiconductor layer A3 to each other. The second connection electrode 172 can be connected to a portion (e.g., a second region D1 of the semiconductor layer A1) of the semiconductor layer A1 through a contact hole that penetrates an inorganic insulating layer disposed between the semiconductor layer A1 and the second connection electrode 172, for example, the first gate insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116. The second connection electrode 172 can be connected to a portion (e.g., a second region D3 of the semiconductor layer A3) of the semiconductor layer A3 through a contact hole that penetrates the third interlayer insulating layer 116 disposed between the semiconductor layer A3 and the second connection electrode 172. Figure 10 Figure 10 The second connection electrode 172 can electrically connect the semiconductor layer A1 and the semiconductor layer A3 to each other. The second connection electrode 172 can be connected to a portion (e.g., a second region D1 of the semiconductor layer A1) of the semiconductor layer A1 through a contact hole that penetrates an inorganic insulating layer disposed between the semiconductor layer A1 and the second connection electrode 172, for example, the first gate insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 116. The second connection electrode 172 can be connected to a portion (e.g., a second region D3 of the semiconductor layer A3) of the semiconductor layer A3 through a contact hole that penetrates the third interlayer insulating layer 116 disposed between the semiconductor layer A3 and the second connection electrode 172.

[0137] The bottom metal layer BML can have a voltage level of a constant voltage. The bottom metal layer BML can prevent or reduce the occurrence of afterimage due to (-) charges by preventing (-) charges from being concentrated at a lower portion of the semiconductor layer A1 of the first transistor T1.

[0138] The first organic insulating layer 121 can be formed on the second connection electrode 172 and the first connection electrode 171. The first organic insulating layer 121 can include an organic material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0139] ​A driving voltage line PL can be disposed on the first organic insulating layer 121. A second organic insulating layer 123 can be disposed on the driving voltage line PL. The driving voltage line PL can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), and / or tungsten (W). In some embodiments, the driving voltage line PL can include a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0140] The second organic insulating layer 123 can include an organic material such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0141] A light emitting diode layer DEL can be disposed on the pixel circuit layer PCL. The light emitting diode layer DEL can include a light emitting diode. For example, the light emitting diode layer DEL can include an organic light emitting diode OLED. The organic light emitting diode OLED can include a pixel electrode 210, an emission layer 220, and an opposite electrode 230.

[0142] The pixel electrode 210 of the organic light emitting diode OLED can be on the second organic insulating layer 123. The emission layer 220 can include a low-molecular-weight organic material or a polymer organic material. At least one layer selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) can also be disposed between the pixel electrode 210 and the opposite electrode 230.

[0143] An edge of the pixel electrode 210 can be covered by the solid material portion of the bank layer 140, and an inner portion of the pixel electrode 210 can overlap the emission layer 220 through the opening 140OP of the bank layer 140. The opposite electrode 230 can be formed (or provided) corresponding to a plurality of organic light emitting diodes OLED when the pixel electrode 210 is formed (or provided) for each of the organic light emitting diodes OLED, respectively. In other words, the plurality of organic light emitting diodes OLED can share the opposite electrode 230, and a stack structure of a portion of the opposite electrode 230, the emission layer 220, and the pixel electrode 210 can correspond to the organic light emitting diode OLED.

[0144] An encapsulation layer 300 can be disposed on the organic light emitting diode OLED. The encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 10 An embodiment in which the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 is shown. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include silicon oxide, silicon nitride, and / or silicon oxynitride, and the organic encapsulation layer 320 can include an organic insulating material.

[0145] The display panel 10 or 10a can be applied to various electronic devices (or display modules or display devices). The electronic device according to the embodiment of the disclosure can include the display panel 10 or 10a described above, and in addition to the display panel 10 or 10a, a module or a device having an additional function can be included.

[0146] Figure 11 FIG. 1 is a block diagram illustrating an electronic device 1000 according to an embodiment of the disclosure.

[0147] Referring to Figure 11 The electronic device 1000 can include a display module 1010, a processor 1020, a memory 1030, and a power module 1040.

[0148] The processor 1020 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0149] The memory 1030 can store data information required for the operation of the processor 1020 or the display module 1010. When the processor 1020 executes an application stored in the memory 1030, an image data signal and / or an input control signal can be transmitted to the display module 1010, and the display module 1010 can process the received signal and output image information through a display screen.

[0150] The power module 1040 can include a power supply module such as a power adapter, a battery device, etc., and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device 1000.

[0151] At least one of the components of the electronic device 1000 described above can be included in a display device (or a display panel) according to the above-described embodiments. In addition, some of the respective modules functionally included in one module can be included in the display device, and the other modules can be provided separately from the display device. For example, the display device can include the display module 1010, and the processor 1020, the memory 1030, and the power module 1040 can be provided in the electronic device 1000 in the form of other devices other than the display device.

[0152] Figure 12 FIG. 2 is a schematic view of an electronic device according to an embodiment of the disclosure.

[0153] Referring to Figure 12, various electronic devices applying the display apparatus according to the embodiments of the disclosure can not only include image display electronic devices, but also include wearable electronic devices including display modules, vehicle electronic devices 1000_3 including display modules, etc. The image display electronic devices can be a smart phone 1000_1a, a tablet computer 1000_1b, a laptop computer 1000_1c, a TV 1000_1d, a desktop monitor 1000_1e, etc. The wearable electronic devices can be smart glasses 1000_2a, a head-mounted display 1000_2b, a smart watch 1000_2c, etc. The vehicle electronic devices 1000_3 can be a central information display (CID) provided on a dashboard and a center console of a vehicle, an interior mirror display, etc.

[0154] The method and apparatus 20 for manufacturing (or providing) a display apparatus according to one or more of the above embodiments can allow accurate testing of the operation of the display apparatus.

[0155] The method and apparatus for manufacturing (or providing) a display apparatus according to one or more of the above embodiments can allow detection of an electrical signal having reduced electrical noise.

[0156] In an embodiment, a method of providing an electronic device includes providing an electrical signal from a circuit board to a display panel 10, and providing an electrical signal generated by the display panel 10 to the circuit board, and transmitting first and second electrical signals between the display panel 10 and the circuit board through first and second wirings of first and second connection members 22-1 and 22-2, respectively. Here, the first and second connection members 22-1 and 22-2 and the circuit board overlap each other along a thickness direction of the circuit board to define an overlapping region, and within the overlapping region, the first and second wirings do not overlap.

[0157] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached drawings, it will be evident for those skilled in the art that various changes can be made in form and details without departing from the spirit and scope of the disclosure as defined by the following claims.

Claims

1. An apparatus for providing an electronic device, the apparatus comprising: The connection portion includes terminals, at which the device is connected to the display panel of the electronic device; A circuit board that provides electrical signals to the display panel, and provides electrical signals generated from the display panel to the circuit board; as well as Each of the connecting members electrically connects the connecting portion to the circuit board, the connecting member comprising: A first connecting member includes a first wiring, through which a first electrical signal is transmitted between the connecting portion and the circuit board; and The second connecting member includes a second wiring, through which a second electrical signal is transmitted between the connecting portion and the circuit board. in, The first connecting member and the second connecting member overlap each other along the thickness direction of the circuit board to define an overlap area, and Within the overlapping area, the first wiring and the second wiring do not overlap.

2. The apparatus according to claim 1, wherein, Each of the connecting members extends from the connecting portion to the circuit board in a first direction, and In a second direction intersecting the first direction, the width of the first connecting member is greater than the width of the second connecting member.

3. The apparatus according to claim 1, wherein, The first electrical signal includes alternating current, and The second electrical signal includes direct current.

4. The apparatus according to claim 1, wherein, Each of the connecting members extends from the connecting portion to the circuit board in a first direction, and The width of the first connecting member in the second direction, which intersects the first direction, varies along the first direction.

5. The apparatus according to claim 1, wherein, The first wiring is bent along the length of the first connecting member.

6. The apparatus according to claim 1, wherein, The first wiring includes: The first-1 wiring portion is inclined in a direction away from the center of the first connecting member; The first-2 wiring portion extends from the first-1 wiring portion and is parallel to the length direction of the first connecting member; and The first-third wiring portion extends from the first-second wiring portion and is inclined in a different direction than the first-first wiring portion.

7. The apparatus according to claim 1, wherein, The first connecting member includes: The first wiring is configured to include a plurality of first wirings; and An opening is defined in the first connecting member and between the plurality of first wirings.

8. The apparatus according to claim 1, wherein, The first connecting member includes: The first wiring is configured to include a plurality of first wirings on opposite sides of the first connecting member, and The second wiring is between the plurality of first wirings.

9. The apparatus according to claim 1, wherein, The second connecting member includes: The second wiring is configured to include a plurality of second wirings, and The distance between the plurality of second wirings is equal to or greater than 20 micrometers.

10. The apparatus according to claim 1, wherein, Along the thickness direction, the first connecting member further includes a shielding layer between the second connecting member and the remaining thickness portion of the first connecting member.

11. A method of providing an electronic device, the method comprising: The circuit board provides electrical signals to the display panel, and the display panel provides electrical signals generated by the display panel to the circuit board. as well as A first electrical signal and a second electrical signal are transmitted between the display panel and the circuit board via a first wiring of a first connecting member and a second wiring of a second connecting member, respectively. in, The first connecting member and the second connecting member overlap each other along the thickness direction of the circuit board to define an overlap area, and Within the overlapping area, the first wiring and the second wiring do not overlap.

12. The method according to claim 11, wherein, Each of the first connecting member and the second connecting member has a planar shape, the planar shape having a length from the circuit board to the display panel and a width less than the length, and The width of the first connecting member is greater than the width of the second connecting member.

13. The method according to claim 11, wherein, The first electrical signal includes alternating current, and The second electrical signal includes direct current.

14. The method according to claim 11, wherein, The first connecting member has a planar shape, the planar shape having a length from the circuit board to the display panel and a width less than the length, and The width of the first connecting member varies along the length of the first connecting member.

15. The method according to claim 11, wherein, The first wiring is bent along the length of the first connecting member.

16. The method according to claim 11, wherein, The first wiring includes: The first-1 wiring portion is inclined in a direction away from the center of the first connecting member; The first-2 wiring portion extends from the first-1 wiring portion and is arranged parallel to the length direction of the first connecting member; and The first-third wiring portion extends from the first-second wiring portion and is inclined in a different direction than the first-first wiring portion.

17. The method according to claim 11, wherein, The first connecting member includes: The first wiring is configured to include a plurality of first wirings; and An opening is defined in the first connecting member and between the plurality of first wirings.

18. The method according to claim 11, wherein, The first connecting member includes: The first wiring is configured to include a plurality of first wirings on opposite sides of the first connecting member, and The second wiring is between the plurality of first wirings.

19. The method according to claim 11, wherein, The second connecting member includes: The second wiring is configured to include a plurality of second wirings, and The distance between the plurality of second wirings is equal to or greater than 20 micrometers.

20. The method according to claim 11, wherein, Along the thickness direction, the first connecting member includes a shielding layer between the second connecting member and the remaining thickness portion of the first connecting member.

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