Control method and system for reducing dead time in waveform switching process of signal generator

Abstract

The invention discloses a control method and system for reducing dead zone time in a waveform switching process of a signal generator, and the method comprises the steps: starting a delay window through detecting a user parameter modification operation, and resetting timing if an operation is detected in the window again; after the window is finished, generating a first check code based on the to-be-updated parameter, and comparing the first check code with a second check code in a previous stable state; and if not, an updating instruction is sent to the waveform generation unit. And after the waveform generation unit receives the instruction, when the current waveform period is ended, the waveform is controlled to sequentially pass through the falling edge transition section, the low level holding section, the rising edge transition section and the high level holding section to form a complete transition period, and the waveform is switched to a target waveform parameter after the period is ended. According to the method, near-real-time, continuous and burr-free switching of various waveforms is realized, and the system response speed, the switching fluency and the reliability and efficiency of an automatic test process are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of electronic test and measurement technology, and in particular to a control method and system for reducing the dead time during waveform switching in a signal generator. Background Technology

[0002] In existing signal generator designs, a combination of MCU, FPGA, DAC, and multi-stage gain circuits is typically used to generate sine waves, square waves, pulse waves, and arbitrary waveforms. However, when the device switches between different waveforms or jumps between different output amplitude ranges, a significant dead time often occurs. Because the DAC output buffer, the mode update of the FPGA's internal logic, and the analog gain switching all require a certain transition process, a brief DC flat or discontinuous level signal appears at the output during the switching instant. Furthermore, when a DDS directly generates a square wave, the overflow point of the phase accumulator is not distributed consistently across different periods, causing the rising and falling edges of the square wave to shift in position during some periods, resulting in abnormal waveforms such as ghosting, glitches, and steps, affecting waveform continuity. These abnormal outputs may be directly transmitted to the instrument under test in automated or unmanned testing equipment, causing false triggering, overvoltage, or even damage, posing potential risks. Simultaneously, testing processes often require uninterrupted waveform switching, but traditional architectures cannot guarantee true zero dead time, affecting the stability and efficiency of automated processes. Therefore, an improved scheme is needed that can maintain continuity, avoid dead zones, and eliminate ghosting during waveform switching without relying on additional analog devices, so as to achieve high-quality and high-reliability signal switching control. Summary of the Invention

[0003] The purpose of this invention is to provide a control method and system for reducing the dead time during waveform switching in a signal generator, so as to solve the problems of dead time and waveform distortion during waveform switching.

[0004] The technical solution adopted in this invention is: A control method for reducing the dead time during waveform switching in a signal generator includes the following steps: Detect user parameter modification operations and respond to the modification operation by starting a delayed window; If a parameter modification operation is detected again within the delay window, the timer of the delay window is reset and the sending of the update command is postponed. If no new parameter modification operation is detected when the delay window ends, a first checksum is generated based on the current set of parameters to be updated. The first check code is compared with the second check code of the previous stable output state of the signal generator; When the first check code and the second check code are inconsistent, an update command containing the parameter set is sent to the waveform generation unit; otherwise, no update is pushed. The waveform generation unit receives the update command and performs a waveform switching operation after the current waveform cycle ends. The waveform switching operation includes controlling the waveform output to pass through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1 in sequence to form a complete transition cycle, and switching the waveform parameters to the target parameters to be updated after the transition cycle ends.

[0005] Furthermore, the counting duration of the delay window is 200ms.

[0006] Furthermore, the first checksum is generated using the CRC32 algorithm based on the current set of parameters to be updated.

[0007] Furthermore, the waveform generation unit is an FPGA, and the waveform output by the waveform generation unit is a square wave.

[0008] Furthermore, the waveforms of the falling edge transition segment (T2) and the rising edge transition segment (T4) are formed by continuously changing transition waveforms generated by direct digital frequency synthesis (DDC) technology.

[0009] This invention also discloses a control system for reducing the dead time during waveform switching in a signal generator, comprising a microcontroller and a waveform generation unit. The microcontroller detects and responds to user parameter modification operations to initiate a delay window. When another parameter modification operation is detected within the delay window, the delay window timer is continuously reset. Until the delay window timer expires without detecting a new parameter modification operation, a first checksum is generated based on the current set of parameters to be updated. The first checksum is then compared with a second checksum from the previous stable output state of the signal generator. If the first checksum and the second checksum are inconsistent, an update command is sent to the waveform generation unit. The waveform generation unit is used to receive update instructions and, based on the update instructions, after the current waveform cycle ends, control the waveform output to pass through a complete transition cycle in sequence through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1. After the transition cycle ends, the waveform parameters are switched to the target parameters to be updated.

[0010] Furthermore, the microcontroller is configured to set the timing duration of the delay window to 200ms.

[0011] Furthermore, the microcontroller uses the CRC32 algorithm to generate the first checksum of the parameter set to be updated.

[0012] Furthermore, the waveform generation unit is an FPGA.

[0013] Furthermore, the system also includes a digital-to-analog converter for converting the digital signals generated by the waveform generation unit into analog signals for output.

[0014] The present invention adopts the above technical solution, and the beneficial effects are as follows: 1) Eliminates waveform switching dead time: The delay window and verification mechanism on the MCU side avoid output jitter caused by frequent parameter sending; the forced transition period on the FPGA side ensures that the output signal changes continuously, achieving true zero-dead-time switching. 2) Completely solves waveform distortion problems: By reconstructing waveforms such as square waves into segmented structures (especially fixed transition segments), the generation of waveform edges no longer depends on the random overflow point of the DDS phase accumulator, thus completely eliminating ghosting, glitches, and edge misalignment, resulting in high-quality output waveforms. 3) Improves system reliability and safety: Eliminates random abnormal levels during switching, effectively preventing accidental triggering or damage to the device under test, making it particularly suitable for high-reliability automated testing scenarios. 4) Low implementation cost: This invention is implemented entirely through improved internal logic algorithms of the MCU and FPGA, without adding additional analog switches, comparators, or shaping circuits, thus not increasing hardware costs and facilitating software upgrades on existing equipment models.

[0015] This invention employs an improved DDS-based segmented output algorithm to ensure that the waveform maintains continuous level changes during switching, without generating excessively high or low levels or interruptions. Attached Figure Description

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments; Figure 1 This is a schematic flowchart of the control method for reducing the dead time during waveform switching in a signal generator according to the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0018] like Figure 1 As shown, this invention discloses a control method for reducing the dead time during waveform switching in a signal generator, which includes the following steps: Detect user parameter modification operations and respond to the modification operation by starting a delayed window; If a parameter modification operation is detected again within the delay window, the timer of the delay window is reset and the sending of the update command is postponed. If no new parameter modification operation is detected when the delay window ends, a first checksum is generated based on the current set of parameters to be updated. The first check code is compared with the second check code of the previous stable output state of the signal generator; When the first check code and the second check code are inconsistent, an update command containing the parameter set is sent to the waveform generation unit; otherwise, no update is pushed. The waveform generation unit receives the update command and performs a waveform switching operation after the current waveform cycle ends. The waveform switching operation includes controlling the waveform output to pass through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1 in sequence to form a complete transition cycle, and switching the waveform parameters to the target parameters to be updated after the transition cycle ends.

[0019] Furthermore, the counting duration of the delay window is 200ms.

[0020] Furthermore, the first checksum is generated using the CRC32 algorithm based on the current set of parameters to be updated.

[0021] Furthermore, the waveform generation unit is an FPGA, and the waveform output by the waveform generation unit is a square wave.

[0022] Furthermore, the waveforms of the falling edge transition segment (T2) and the rising edge transition segment (T4) are formed by continuously changing transition waveforms generated by direct digital frequency synthesis (DDC) technology. In the falling edge transition segment (T2) and the rising edge transition segment (T4), the level is gradually switched from high to low or from low to high according to the new parameters.

[0023] This invention also discloses a control system for reducing the dead time during waveform switching in a signal generator, comprising a microcontroller and a waveform generation unit. The microcontroller detects and responds to user parameter modification operations to initiate a delay window. When another parameter modification operation is detected within the delay window, the delay window timer is continuously reset. Until the delay window timer expires without detecting a new parameter modification operation, a first checksum is generated based on the current set of parameters to be updated. The first checksum is then compared with a second checksum from the previous stable output state of the signal generator. If the first checksum and the second checksum are inconsistent, an update command is sent to the waveform generation unit. The waveform generation unit is used to receive update instructions and, based on the update instructions, after the current waveform cycle ends, control the waveform output to pass through a complete transition cycle in sequence through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1. After the transition cycle ends, the waveform parameters are switched to the target parameters to be updated.

[0024] Furthermore, the microcontroller is configured to set the timing duration of the delay window to 200ms.

[0025] Furthermore, the microcontroller uses the CRC32 algorithm to generate the first checksum of the parameter set to be updated.

[0026] Furthermore, the waveform generation unit is an FPGA.

[0027] Furthermore, the system also includes a digital-to-analog converter for converting the digital signals generated by the waveform generation unit into analog signals for output.

[0028] The specific principles of this invention will be explained in detail below: When the MCU detects a parameter change, it first executes a delay-wait mechanism to avoid discontinuous waveform output caused by frequent parameter issuance. Simultaneously, the FPGA's internal DDS generator is redesigned to output a structurally optimized waveform signal. Its output logic employs a segmented structure, combined with digitally controlled edge transition waveforms, to achieve smooth waveform switching without dead zones.

[0029] Specifically, when the user changes the parameters of the signal generator, the MCU starts a 200ms timer. If the parameters are adjusted via knobs or buttons during this period, the timer is continuously reset until the user operation is paused for a predetermined time to prevent frequent parameter sending from causing intervals in the waveform output. After the 200ms timer expires, the MCU aggregates all parameters that may affect the signal generator output into a memory block and calculates a checksum using the CRC32 algorithm, comparing it with the CRC32 value of the device in its current stable state. Only when the checksums are inconsistent is a parameter update signal sent to the FPGA, thus eliminating the problem of discontinuous output levels caused by continuous switching from the top level. Through this parameter change aggregation and verification mechanism, the DAC output gaps or jitter caused by continuous and rapid parameter sending can be avoided from the source, ensuring continuous and stable waveform output. When the FPGA receives the update signal, it performs a smooth switching of waveform parameters according to the aforementioned DDS segmented transition algorithm, ensuring zero-dead-zone switching from both hardware and software perspectives.

[0030] Building upon this, the FPGA utilizes its internal DDS generator to implement the square wave output logic as a four-segment structure: T1 high-level hold segment, T2 falling edge transition segment, T3 low-level hold segment, and T4 rising edge transition segment. Stages T1 and T3 use the FPGA's fixed clock as a reference, maintaining extremely high time consistency. Stages T2 and T4 use a smooth, continuously changing high-frequency transition waveform from the DDS output to gradually transition the level from high to low or from low to high, achieving a gradual rise and fall effect. When switching waveforms, the system does not directly change the DAC's output state. Instead, it first enters a complete transition band process, sequentially executing stages T2→T3→T4→T1, and only switches to the new waveform parameters after completing a full cycle. In this way, the generation of waveform edges no longer depends on the DDS phase accumulator, thus avoiding waveform ghosting problems caused by inconsistent overflow distribution of the phase accumulator. With this design, the rising and falling edges of each square wave cycle always appear at fixed positions, no longer affected by the inconsistent distribution of overflow points in the DDS phase accumulator, thus completely eliminating abnormal waveforms such as ghosting, glitches, and steps during square wave switching. During waveform switching, the FPGA triggers a transition sequence (T2→T3→T4→T1) at the end of the current cycle and switches to new waveform parameters after the complete cycle, ensuring waveform continuity and strict edge alignment.

[0031] By simultaneously performing data smoothing and buffering processing in both top-level parameter control and bottom-level waveform synthesis, a near-perceptible parameter operation experience is achieved on the user side. The waveform output remains responsive and significantly reduces the system load on the MCU and FPGA resources during continuous knob operation, thus giving the system a more stable and smoother operating performance.

[0032] The advantages of this invention, employing the above technical solution, are as follows: By using an improved DDS-based segmented output algorithm, the waveform maintains continuous level changes during switching, preventing excessively high or low levels or interruptions. It completely avoids ghosting and edge misalignment during waveform switching and resolves the edge drift phenomenon caused by inconsistencies in traditional DDS phase overflow. No additional analog shaping, comparators, or switching circuits are required; the entire solution is based entirely on improvements to the MCU control logic and changes to the digital logic of the FPGA's internal output method. No additional BOM or components are needed, allowing for upgrades even for older machines. It improves the safety of automated testing processes; after eliminating switching dead zones, random levels no longer occur, thus avoiding the risk of damage to external devices. This invention enhances system response speed and switching smoothness. With the improved algorithm, various waveforms can achieve near real-time, continuous, and glitch-free switching, facilitating more efficient and stable automated processes.

[0033] This invention employs an improved DDS-based segmented output algorithm to ensure that the waveform maintains continuous level changes during switching, without generating excessively high or low levels or interruptions.

[0034] Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Without conflict, the embodiments and features in the embodiments of this application can be combined with each other. The components of the embodiments of this application described and illustrated herein can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

Claims

1. A control method for reducing the dead time during waveform switching in a signal generator, characterized in that: It includes the following steps: Detect user parameter modification operations and respond to the modification operation by starting a delayed window; If a parameter modification operation is detected again within the delay window, the timer of the delay window is reset and the sending of the update command is postponed. If no new parameter modification operation is detected when the delay window ends, a first checksum is generated based on the current set of parameters to be updated. Compare the first check code with the second check code of the previous stable output state of the signal generator; When the first check code and the second check code are inconsistent, an update command containing the parameter set is sent to the waveform generation unit. Otherwise, no updates will be pushed. The waveform generation unit receives the update command and performs a waveform switching operation after the current waveform cycle ends. The waveform switching operation includes controlling the waveform output to pass through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1 in sequence to form a complete transition cycle, and switching the waveform parameters to the target parameters to be updated after the transition cycle ends.

2. The control method for reducing the dead time during waveform switching in a signal generator according to claim 1, characterized in that: The counting duration of the delay window is 200ms.

3. The control method for reducing the dead time during waveform switching in a signal generator according to claim 1, characterized in that: The first checksum is generated using the CRC32 algorithm based on the current set of parameters to be updated.

4. The control method for reducing the dead time during waveform switching in a signal generator according to claim 1, characterized in that: The waveform generation unit is an FPGA, and the waveform output by the waveform generation unit is a square wave.

5. The control method for reducing the dead time during waveform switching in a signal generator according to claim 1, characterized in that: The waveforms of the falling edge transition segment and the rising edge transition segment are formed by continuously changing transition waveforms generated by direct digital frequency synthesis technology.

6. A control system for reducing the dead time during waveform switching in a signal generator, comprising the control method for reducing the dead time during waveform switching in a signal generator as described in any one of claims 1 to 5, characterized in that: The system includes a microcontroller and a waveform generation unit; the microcontroller is used to detect and respond to user parameter modification operations in order to start a delay window, and when another parameter modification operation is detected within the delay window, the timer of the delay window is continuously reset; If no new parameter modification operation is detected until the delay window expires, a first checksum is generated based on the current set of parameters to be updated; the first checksum is then compared with the second checksum of the previous stable output state of the signal generator; if the first checksum and the second checksum do not match, an update command is sent to the waveform generation unit. The waveform generation unit is used to receive update instructions and, based on the update instructions, after the current waveform cycle ends, control the waveform output to pass through a complete transition cycle in sequence through the falling edge transition segment T2, the low level holding segment T3, the rising edge transition segment T4, and the high level holding segment T1. After the transition cycle ends, the waveform parameters are switched to the target parameters to be updated.

7. The control system for reducing the dead time during waveform switching in a signal generator according to claim 6, characterized in that: The microcontroller is configured with a delay window duration of 200ms.

8. The control system for reducing the dead time during waveform switching in a signal generator according to claim 6, characterized in that: The microcontroller uses the CRC32 algorithm to generate the first checksum of the parameter set to be updated.

9. The control system for reducing the dead time during waveform switching in a signal generator according to claim 6, characterized in that: The waveform generation unit is an FPGA.

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