High-reliability configuration system and method
By using an FPGA configuration scheme with a separate main control chip and programmable logic unit, the problems of slow configuration speed, large resource consumption and insufficient reliability in the existing technology are solved, realizing efficient and reliable FPGA configuration, which is suitable for high-reliability applications such as aerospace.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-27
AI Technical Summary
Existing FPGA configuration solutions are insufficient in terms of configuration speed, resource utilization and reliability, making it difficult to meet the needs of high-reliability applications such as aerospace, especially in terms of long configuration time, large resource consumption and insufficient identification of false completion signals.
It adopts a separate structure of main control chip and programmable logic unit, and writes the data into a first-in-first-out buffer in blocks through a four-wire serial peripheral interface and an advanced scalable interface bus. It combines a sixteen-bit parallel configuration interface for data transmission, and performs validity detection and retransmission control on the completion signal to achieve efficient transmission and reliable guarantee of configuration data.
It significantly improves configuration speed, reduces reliance on DDR storage resources, increases system resource utilization and configuration success rate, and enhances reliability and stability in harsh environments.
Smart Images
Figure CN121742928A_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of FPGA configuration technology, and specifically to a high-reliability configuration system and method. Background Technology
[0002] With the rapid development of key fields such as aerospace and defense, unprecedented demands have been placed on the localization of components used in electronic systems and their high reliability under extreme environments. Field Programmable Gate Arrays (FPGAs) have become one of the core components in highly reliable embedded systems, and the reliability of FPGA configuration schemes is directly related to whether electronic systems can start up normally and operate continuously.
[0003] In the existing technology, there are two main types of configuration methods for domestic FPGA devices: one is that an independent processor sends configuration data directly to the FPGA device through a serial peripheral interface (SPI); the other is to use a system-on-chip field-programmable gate array (SoC FPGA) as the main control chip, and the SoC FPGA's processing system reads the configuration data from external non-volatile memory through the peripheral interface, caches it through dynamic random access memory (DDR), and then sends the configuration data to the FPGA device being configured.
[0004] However, the existing configuration schemes mentioned above have significant shortcomings in engineering applications: First, relying solely on general-purpose processors for configuration via slow serial interfaces such as SPI is limited by interface bandwidth and clock frequency, resulting in long configuration times. This makes it difficult to meet the rapid loading requirements of large-capacity FPGA devices during startup and also results in poor flexibility. Second, in schemes using SoC FPGAs as the main control chip, the complete configuration data file is typically cached in off-chip DDR memory. This method occupies a large amount of DDR space for a long time, severely encroaching on the storage resources required for system operation. Third, existing schemes generally only determine whether the configuration is successful by monitoring the FPGA's configuration completion signal (DONE). There is a lack of an effective mechanism for identifying false DONE signals. When interference or anomalies cause DONE to be falsely triggered before the configuration data is fully transmitted, the system cannot detect and take corrective measures in a timely manner. After configuration failure, there is often a lack of a unified and systematic automatic retry strategy, and the overall configuration reliability is difficult to meet the engineering requirements of high-reliability applications such as aerospace. Summary of the Invention
[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a high-reliability configuration system and method to solve the problem of balancing FPGA configuration speed and system resource utilization, while ensuring the overall reliability of the configuration.
[0006] This application provides a high-reliability configuration system, the system including a main control chip, a target configuration chip, and a storage unit, wherein the main control chip integrates a processing unit and a programmable logic unit. The processing unit is configured to obtain a binary configuration file from the storage unit through a four-wire serial peripheral interface, and write the binary configuration file into blocks into a first-in-first-out buffer in the programmable logic unit through an advanced extensible interface bus. The programmable logic unit is used to send the configuration data in the first-in-first-out buffer to the target configuration chip through a 16-bit parallel configuration interface; detect the completion signal of the target configuration chip; and control the configuration process of the target configuration chip according to the detection result. The target configuration chip is used to perform configuration processing based on the configuration data, and after the configuration processing is completed, it configures the completion signal as a first level signal.
[0007] According to the technical solution provided in the embodiments of this application, the processing unit is specifically used for: The binary configuration file is divided into blocks based on a preset data length to obtain at least one data block; For each data block, if the state information of the first-in-first-out buffer meets the preset write conditions, the data block is transmitted to the first-in-first-out buffer.
[0008] According to the technical solution provided in the embodiments of this application, the programmable logic unit is specifically used for: A reset control signal is sent to the target configuration chip to control the target configuration chip to perform initialization processing; Configure the configuration selection input signal as a second-level signal; latch the configuration data bit by bit onto the sixteen-bit parallel data lines at each rising edge of the configuration clock signal; perform bit order adjustment processing on the configuration data on the sixteen-bit parallel data lines; configure the read / write selection signal as a write operation signal.
[0009] According to the technical solution provided in the embodiments of this application, the programmable logic unit is specifically used for: If the completion signal is detected as the first level signal before all the configuration data is sent to the target configuration chip; or if the duration of the completion signal being the first level signal is less than a preset duration, then the completion signal is determined to be an invalid signal.
[0010] According to the technical solution provided in the embodiments of this application, the programmable logic unit is further used for: If the completion signal is found to be invalid after all the data has been sent to the target configuration chip, a reset control signal is sent to the target configuration chip, and the data in the first-in-first-out buffer is resent to the target configuration chip through the sixteen-bit parallel configuration interface; If the number of times the data is sent is greater than or equal to a preset number, then the sending of the data to the target configuration chip is terminated.
[0011] According to the technical solution provided in the embodiments of this application, the target configuration chip is further used for: After receiving the configuration data, the integrity of the configuration data is verified. If the verification fails, the completion signal is determined to be invalid, and the next round of configuration data is received again.
[0012] According to the technical solution provided in the embodiments of this application, the target configuration chip is further used for: Upon receiving the reset control signal from the programmable logic unit, the initialization completion indicator pin of the target configuration chip is configured to the second level signal, the register contents are cleared, and the initialization state is entered. If the initialization completion indicator pin of the target configuration chip changes from a second level signal to a first level signal, it indicates that the target configuration chip has completed the initialization process.
[0013] This application provides a high-reliability configuration method, the method comprising: The binary configuration file is obtained from the storage unit through the four-wire serial peripheral interface of the processing unit, and the binary configuration file is written into the first-in-first-out buffer in the programmable logic unit in blocks through the advanced extensible interface bus. The configuration data in the first-in-first-out buffer is sent to the target configuration chip through a 16-bit parallel configuration interface; the completion signal of the target configuration chip is detected, and the configuration process of the target configuration chip is controlled according to the detection result; The target configuration chip is configured based on the configuration data, and the completion signal is configured as a first level signal after the configuration process is completed.
[0014] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement a high-reliability configuration method as described above.
[0015] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a high-reliability configuration method as described above.
[0016] Compared with the prior art, the beneficial effects of this application are as follows: This application uses the processing unit in the main control chip to write the binary configuration file into the first-in-first-out (FIFO) buffer of the programmable logic unit (PLU), and the PLU sends the configuration data to the target configuration chip through a 16-bit parallel configuration interface. Compared with the existing technology where the processor directly configures via slow serial interfaces such as SPI, this significantly improves the configuration bandwidth and overall loading speed, increases the configuration rate, and solves the bottleneck problem of traditional SPI configuration speed. This application adopts a separate structure of processing unit and PLU, writing configuration data into the FIFO in blocks, without preloading the complete configuration file into the external DDR memory of the main control chip. This fundamentally solves the problem of configuration files occupying a large amount of DDR space and affecting the operation of other system tasks in the prior art, achieving high efficiency and controllability of resource utilization. This application can detect the completion signal of the target configuration chip, thereby ensuring that the system still has strong reliability and configuration success rate in harsh environments. Attached Figure Description
[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This application provides a schematic diagram of the structure of a high-reliability configuration system; Figure 2 An architecture diagram of a high-reliability configuration system provided in this application; Figure 3 A timing diagram of the target configuration chip configuration process provided in this application; Figure 4 This application provides a state transition diagram for the configuration process of the target configuration chip. Figure 5 A flowchart illustrating a high-reliability configuration method provided in this application; Figure 6 A block diagram of an electronic device provided in this application.
[0018] Icon labels: 600. Electronic device; 601. Processor; 602. Input device; 603. Output device; 604. Memory; 605. Communication bus. Detailed Implementation
[0019] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0021] Please refer to Figure 1 This application provides a schematic diagram of a high-reliability configuration system. The high-reliability configuration system may include a main control chip, a target configuration chip, and a storage unit. The main control chip may integrate a processing unit and a programmable logic unit.
[0022] Can be combined Figure 2 , Figure 2 The diagram illustrates the architecture of a high-reliability configuration system. The main control chip can be a SoCFPGA (System-on-Chip Field-Programmable Gate Array). The processing unit (PS) retrieves the binary configuration file corresponding to the target configuration chip from the storage unit via a four-wire serial peripheral interface (QSPI), and writes this binary configuration file in blocks into a first-in-first-out buffer within the programmable logic unit via an Advanced eXtensible Interface (AXI) bus. This storage unit can be an external serial flash memory (SPIFlash).
[0023] The programmable logic unit (PL) can be used to transmit data blocks in the first-in first-out (FIFO) buffer to the target configuration chip through the 16-bit parallel configuration interface (SelectMap x16), and to detect the validity of the completion signal of the target configuration chip, and control the configuration process of the target configuration chip based on the detection result.
[0024] The target configuration chip can be the FPGA (Field-Programmable Gate Array) to be configured. It can be used to acquire configuration data sent by the programmable logic units and perform configuration processing based on this data. After the configuration processing is complete, it configures the completion signal to a first-level signal. Specifically, in... Figure 2 In the interaction between the programmable logic unit and the target configuration chip, D[15:0] represents the data corresponding to the sixteen-bit parallel data lines. The CSI_B (Configuration Select Input) signal indicates whether configuration data transmission is enabled or disabled during the configuration process. If the CSI_B signal is the second level signal, i.e., a low level signal, it indicates that configuration data transmission is enabled; if the CSI_B signal is the first level signal, i.e., a high level signal, it indicates that configuration data transmission is disabled. The RWDR_B (Read Write Select) signal is used to specify whether the current bus transmits a read operation signal or a write operation signal. The CCLK (Configuration Clock) signal is used to represent the main clock signal of the target configuration chip during the configuration process. The PROGRAM_B (Program Load Control) signal is used to indicate that the target configuration chip has entered the configuration mode. The INIT_B (Initialization) signal is used to indicate whether the target configuration chip has completed the initialization process. The DONE signal is used to indicate whether the target configuration chip has correctly completed the configuration. As an example, the timing diagram of the target configuration chip configuration process is as follows: Figure 3 As shown. In the initial power-on state, all signals are in an idle state. The PROGRAM_B signal is pulled low, indicating that the target configuration chip has entered the configuration mode. The INIT_B signal is first pulled low and then pulled high, indicating that the target configuration chip has completed initialization and is ready to receive configuration data. In the configuration preparation stage, the CSI_B signal is pulled low, indicating that the transmission of configuration data is valid. The RDWR_B signal is pulled low, indicating that the write operation has begun and data is ready to be written. In the configuration data transmission stage, valid data begins to appear on the D[15:0] signals. Each rising edge of CCLK triggers a data latch once, and the programmable logic unit writes each data word after the configuration file is divided into blocks into D[15:0] bit by bit. In the configuration completion detection stage, waiting for the target chip to pull the DONE signal high indicates that the configuration is successful.
[0025] By adopting a separate structure for the processing unit and the programmable logic unit, the PS reads the configuration file from the external SPI Flash at high speed via QSPI and writes it to the FIFO buffer in the PL in blocks via the AXI bus. The PL then efficiently loads the data to the target configuration chip via the SelectMap x16 parallel interface, significantly improving the overall configuration speed and avoiding the bottleneck caused by traditional serial loading. The FIFO buffer decouples data processing from caching, so even if there are fluctuations in PS processing or external SPI Flash reading, it will not directly affect the continuous transmission of data at the PL end, ensuring that there will be no sudden interruption during the configuration process and improving system stability.
[0026] In some embodiments, when the processing unit writes the binary configuration file into blocks and into the first-in-first-out (FIFO) buffer in the programmable logic unit via the AXI bus, it can divide the binary configuration file into blocks based on a preset data length to obtain at least one data block. For each data block, if the status information corresponding to the FIFO buffer meets the preset write conditions, the data block can be transferred to the FIFO buffer. The preset data length can be determined according to actual conditions, such as 512 bytes. The status information can include the remaining capacity of the FIFO buffer, a write enable flag, and a full flag. The write enable flag indicates whether the current write operation is allowed; if the write enable flag is valid, the current write operation is allowed. The full flag indicates whether the FIFO buffer is full; if the full flag is invalid, the FIFO buffer is not currently full. The preset write conditions can be: the current remaining capacity is not less than the byte length of the data block, the write enable flag is valid, and the full flag is invalid.
[0027] By improving the architecture by writing configuration data to the PL-side FIFO in blocks via the AXI bus instead of relying on the entire DDR cache, the dependence on off-chip DDR resources can be significantly reduced, improving the system resource utilization and flexibility of configuration processing. The use of fixed block length transmission simplifies the cache control logic and improves the configuration rate. By judging based on preset write conditions, write conflicts and data loss are effectively avoided.
[0028] In some embodiments, when the programmable logic unit sends the configuration data in the first-in-first-out buffer to the target configuration chip via SelectMap x16, it can perform the following timing control operations: The programmable logic unit (PLU) can send a reset control signal to the target configuration chip to control it to perform initialization. For example, it can pull the PROGRAM_B pin signal low in the target configuration chip to clear its internal configuration registers and enter the initialization state. Once the target configuration chip completes its initialization, its corresponding INIT_B signal changes from a second-level signal to a first-level signal and is sent to the PLU. The first-level signal is higher than the second-level signal; the first level can represent a high-level signal, and the second level can represent a low-level signal. The transition from a low level to a high level in the target configuration chip indicates that the initialization process is complete.
[0029] After sending the reset control signal, the programmable logic unit can configure the CSI_B signal as the second level signal and send it to the target configuration chip. On each rising edge of the CCLK signal, the configuration data is latched bit by bit into the pins of the 16-bit parallel data line. The data corresponding to the 16-bit parallel data line can be represented as D[15:0], that is, the configuration data is transmitted to the 16-bit parallel data line. The bit order of the configuration data on the 16-bit parallel data line is adjusted. The read / write selection signal is configured as the write operation signal. The bit order adjustment method can be determined based on the preset bit order corresponding to the target configuration chip. For example, if the preset bit order is high bit first, the data in the 16-bit parallel data line can be adjusted in the manner of high bit first and low bit last to meet the internal parsing logic of the target configuration chip. During the entire data transmission process, the RWDR_B signal can be configured as the write selection signal to ensure that the data is stably written to the target configuration chip. By performing initialization control and bit order adjustment on the target configuration chip during the configuration process, the configuration data can be transmitted stably according to the timing and format requirements of the target configuration chip. Through unified management of read / write selection signals and configuration selection signals, it can be ensured that data will not be written incorrectly, omitted, or out of sequence, thereby improving the reliability of the configuration process.
[0030] In some embodiments, the programmable logic unit (PLU) can monitor the completion signal of the target configuration chip. If the completion signal is a first-level signal received before all configuration data is sent to the target configuration chip, or if the duration of the completion signal is less than a preset duration after receiving the first-level signal, the completion signal can be determined to be invalid. The preset duration can be determined according to actual conditions, such as being configurable as the duration corresponding to 10 clock signals. If the completion signal is determined to be invalid, it indicates that the received completion signal was a false signal, and configuration data can continue to be sent to the target configuration chip until the configuration data is sent completely and a new completion signal from the target configuration chip is detected. By monitoring the validity of the completion signal of the target configuration chip, false judgments of configuration failure are avoided, configuration reliability and success rate are improved, and fault tolerance to signal anomalies is enhanced.
[0031] In some embodiments, the programmable logic unit can also be used to: if an invalid completion signal is detected after all data has been sent to the target configuration chip, then send a reset control signal to the target configuration chip again, and resend the data in the first-in-first-out buffer to the target configuration chip through a 16-bit parallel configuration interface; if sending the data is greater than or equal to a preset number of times, then the sending of the data to the target configuration chip can be terminated. The preset number of times can be determined as needed, such as three times. If three consecutive configuration attempts fail to complete, a loading failure flag can be fed back to the processing unit. This failure status flag can include the number of times the data was repeatedly sent and the current working status of the target configuration chip, and the above failure status information can be stored in a local log buffer for subsequent diagnostic analysis.
[0032] After all the configuration data is sent to the target configuration chip, if the received completion signal is a first-level signal, it is determined to be a valid signal, and a loading completion flag is fed back to the processing unit.
[0033] When the completion signal received by the target configuration chip is determined to be invalid, a reset control signal and data retransmission are automatically triggered, implementing closed-loop recovery control logic for configuration failures and improving system reliability. Terminating data transmission after multiple consecutive configuration failures avoids resource consumption and time waste caused by repeated attempts, ensuring system operating efficiency.
[0034] In some embodiments, the target configuration chip is further configured to: after receiving the configuration data, perform integrity verification on the configuration data, such as performing segment-by-segment verification on the received data to determine whether errors or loss occurred during data transmission; if the configuration data passes the integrity verification, the completion signal can be determined as a first level signal; if the verification fails, the completion signal is determined to be an invalid signal, and the next round of configuration data is restarted; when the completion signal is detected to be an invalid signal, the chip can continue to prepare to receive the next round of configuration data.
[0035] By adding an integrity verification mechanism inside the target configuration chip, erroneous configuration caused by transmission interference, timing errors or data corruption can be effectively prevented, ensuring the reliable and error-free operation of the chip. When the verification fails, it can be identified as a configuration failure of the target configuration chip and enter the next round of data reception process, avoiding stagnation due to a one-time error and realizing a highly reliable automatic retransmission mechanism. The whole process does not require manual intervention and can be handled automatically by the target configuration chip.
[0036] In some embodiments, after the target configuration chip receives a reset control signal from the programmable logic unit, the PROGRAM_B pin of the target configuration chip can be configured to a second level to trigger a reset process, clear the register contents, and initialize the state. If the INIT_B pin of the target configuration chip changes from the second level to the first level, it indicates that the target configuration chip has completed the initialization process and can receive new configuration data. As an example, the second level is lower than the first level; the second level can represent a low level, and the first level can represent a high level.
[0037] By performing a reset, residual data can be prevented from interfering with the next configuration process, improving the consistency of system initialization. By reading the level change of the initialization completion indicator pin, it can be determined whether the initialization process is complete, ensuring that the target configuration chip is always configured in a controlled and stable state, significantly improving the reliability of the configuration system.
[0038] See Figure 4 , Figure 4 This application provides a state transition diagram for the target configuration chip process, which describes the state change process of the logic state machine in the programmable logic unit during the process of the main control chip loading the configuration file to the target configuration chip.
[0039] The idle state indicates that the system is in an initial idle state after power-on and the configuration process for the target configuration chip has not yet begun. If a signal corresponding to the power-on of the loading device is detected, the system will proceed to the next state. The preparation state indicates the preparatory state before the actual start of the configuration process. In this state, it waits for a reset control signal. If the reset control signal is ready, it enters the initialization state. In the initialization state, the programmable logic unit sends a reset control signal to the target configuration chip, clearing the target configuration chip's configuration and starting initialization processing. If the INIT_B signal of the target configuration chip jumps from low to high (i.e., the target configuration chip changes from a second-level signal to a first-level signal), it indicates that initialization is complete, and it enters the data transmission state. In the data transmission state, configuration data is sent to the target configuration chip through the SelectMap x16 parallel interface. If the DONE signal is abnormal during this process, such as the DONE signal being a first-level signal but data transmission not complete, or the duration of the DONE signal being a first-level signal being less than a preset duration, then the DONE signal is determined to be invalid, and it enters the completion confirmation waiting state. If the data transmission is complete and the DONE signal is valid, it jumps to the configuration completion state. In the completion confirmation waiting state, if the DONE signal is valid and data transmission is confirmed to be complete, it jumps to the configuration completion state, which indicates that the configuration has been successfully completed. If the DONE signal fails, the system will return to the idle state and wait for the next configuration process.
[0040] By dividing the configuration process into stages and managing its states through state machine logic, the system achieves automatic control and state identification of the configuration process, enabling the main control chip to automatically control the configuration process of the target configuration chip. By monitoring and judging the transition states and durations of the INIT_B and DONE signals, the system can effectively identify false completion signals, prevent erroneous loading, and improve system reliability. When an anomaly occurs during the configuration process, the system can promptly enter a waiting confirmation state and decide whether to retry or terminate based on the judgment result, which helps to enhance the self-recovery capability under abnormal conditions. Each state configuration process is controllable and measurable, facilitating subsequent maintenance and fault location.
[0041] S501 retrieves the binary configuration file from the storage unit through the four-wire serial peripheral interface of the processing unit, and writes the binary configuration file into blocks into the first-in-first-out buffer in the programmable logic unit through the advanced extensible interface bus.
[0042] In this embodiment, the processing unit can be the processing system in the main control chip, used to read the binary configuration file from the external memory. Specifically, the processing unit can read the binary configuration file corresponding to the target configuration chip segment by segment from the storage unit through a four-wire serial peripheral interface, and divide the read binary configuration file into blocks according to a preset data length, such as 512 bytes, to obtain multiple data blocks.
[0043] After a data block is generated, the processing unit can write data to the programmable logic unit (PLU) via the Advanced Scalable Interface (ALI) bus. Before writing each data block, the processing unit obtains the status information of the first-in-first-out (FIFO) buffer, including the remaining capacity, write enable flag, and full flag. If the status information meets the preset write conditions, such as the remaining capacity of the FIFO buffer is not less than the length of the current data block, the write enable flag is valid, and the full flag is invalid, the processing unit writes the data block to the FIFO buffer within the PLU for subsequent data transmission.
[0044] By combining block writing with a FIFO caching mechanism, the efficiency of data management and transmission stability during the configuration process are improved.
[0045] S502: The configuration data in the first-in-first-out buffer is sent to the target configuration chip through the 16-bit parallel configuration interface; the completion signal of the target configuration chip is detected, and the configuration process of the target configuration chip is controlled according to the detection result.
[0046] In this embodiment, the programmable logic unit (PLU) can be used to control the transmission of configuration data to the target configuration chip and detect the configuration completion signal. Specifically, the PLU can write the configuration data in the first-in-first-out buffer into the data input port of the target configuration chip in 16-bit units, based on a 16-bit parallel configuration interface. During data transmission, the PLU can execute preset timing control operations, including: initialization control: by outputting a reset control signal to the target configuration chip, its internal configuration register is cleared and enters the initialization state. After the initialization completion indication signal of the target configuration chip changes from low to high, the next stage is entered; configuration data latching: at the rising edge of each configuration clock signal, the configuration data is latched bit by bit onto the 16-bit parallel data lines; bit order adjustment processing: based on the bit order requirements of the target configuration chip, the bit order of the data on the parallel data lines is adjusted, such as performing high-bit-first or low-bit-first rearrangement processing, thereby satisfying the internal parsing logic of the target configuration chip; write operation holding: the write control signal is continuously held as a write operation to ensure that the configuration data is stably written to the target configuration chip.
[0047] During the data transmission phase, the programmable logic unit (PLU) simultaneously monitors the completion signal of the target configuration chip. If the PLU detects that the completion signal is set to a high level before all data has been transmitted, or if the duration of the completion signal is less than a preset duration, such as 10 clock cycles, the PLU determines the completion signal as invalid and, depending on the situation, continues to transmit the remaining data or initiates the next round of configuration.
[0048] High-speed data transmission is achieved through a 16-bit parallel configuration interface, combined with a completion signal detection mechanism, which enhances the configuration success rate of the target configuration chip and the timing control accuracy of data transmission, significantly improving the overall configuration reliability of the system.
[0049] S503: Configure the target configuration chip based on the configuration data, and configure the completion signal as the first level signal after the configuration processing is completed.
[0050] In this embodiment, after receiving all configuration data, the target configuration chip can perform configuration processing of its internal logic resources based on the configuration data, including loading the configuration bit stream, initializing internal modules, and restoring normal operating status. Once the target configuration chip completes the above configuration processing, it can set its completion signal to a first-level signal, i.e., a high-level signal, to report the successful completion of the configuration to the main control chip. Upon receiving this valid completion signal, the processing unit can generate a corresponding completion flag and end the current configuration process.
[0051] If the target configuration chip fails to output a valid completion signal within the preset time limit, the system can trigger an automatic retry mechanism, send a reset signal to the target configuration chip again through the programmable logic unit, and re-execute the data transmission operation until the maximum number of retries is reached or the configuration is successful.
[0052] Confirming configuration completion by pulling the signal high helps to achieve final confirmation of the configuration process, ensuring that the target configuration chip has successfully completed configuration initialization and entered a stable operating state, thereby improving the reliability and controllability of system operation.
[0053] See Figure 6 , Figure 6 This is a schematic block diagram of an electronic device provided according to an embodiment of this application. Figure 6 The electronic device 600 in this embodiment may include one or more processors 601, one or more input devices 602, one or more output devices 603, and one or more memories 604. The processors 601, input devices 602, output devices 603, and memories 604 communicate with each other via a communication bus 605. The memories 604 store computer programs, including program instructions. The processors 601 execute the program instructions stored in the memories 604. The processors 601 are configured to invoke the program instructions to perform the functions of each module / unit in the above system embodiments.
[0054] It should be understood that, in the embodiments of this application, the processor 601 may be a central processing unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0055] Input device 602 may include a touchpad, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint orientation information), a microphone, etc., and output device 603 may include a display (LCD, etc.), a speaker, etc.
[0056] The memory 604 may include read-only memory and random access memory, and provides instructions and data to the processor 601. A portion of the memory 604 may also include non-volatile random access memory. For example, the memory 604 may also store device type information.
[0057] In specific implementations, the processor 601, input device 602, and output device 603 described in the embodiments of this application can execute the implementation methods described in the embodiments of the high reliability configuration method provided in this application, or they can execute the implementation methods of the electronic devices described in the embodiments of this application, which will not be repeated here.
[0058] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to complete the process. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.
[0059] The computer-readable storage medium can be an internal storage unit of the electronic device in any of the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device. Furthermore, the computer-readable storage medium can include both internal and external storage units of the electronic device. The computer-readable storage medium is used to store computer programs and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.
[0060] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
[0061] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. A high-reliability configuration system, characterized in that, The system includes a main control chip, a target configuration chip, and a storage unit. The main control chip integrates a processing unit and a programmable logic unit. The processing unit is configured to obtain a binary configuration file from the storage unit through a four-wire serial peripheral interface, and write the binary configuration file into blocks into a first-in-first-out buffer in the programmable logic unit through an advanced extensible interface bus. The programmable logic unit is used to send the configuration data in the first-in-first-out buffer to the target configuration chip through a 16-bit parallel configuration interface; detect the completion signal of the target configuration chip; and control the configuration process of the target configuration chip according to the detection result. The target configuration chip is used to perform configuration processing based on the configuration data, and after the configuration processing is completed, it configures the completion signal as a first level signal.
2. The system according to claim 1, characterized in that, The processing unit is specifically used for: The binary configuration file is divided into blocks based on a preset data length to obtain at least one data block; For each data block, if the state information of the first-in-first-out buffer meets the preset write conditions, then the data block is transmitted to the first-in-first-out buffer.
3. The system according to claim 1, characterized in that, The programmable logic unit is specifically used for: A reset control signal is sent to the target configuration chip to control the target configuration chip to perform initialization processing; Configure the configuration selection input signal to a second level signal; at each rising edge of the configuration clock signal, latch the configuration data bit by bit onto a 16-bit parallel data line; perform bit order adjustment processing on the configuration data on the 16-bit parallel data line; Configure the read / write select signal as a write operation signal.
4. The system according to claim 1, characterized in that, The programmable logic unit is specifically used for: If the completion signal is detected as the first level signal before all the configuration data is sent to the target configuration chip; or if the duration of the completion signal being the first level signal is less than a preset duration, then the completion signal is determined to be an invalid signal.
5. The system according to claim 1, characterized in that, The programmable logic unit is also used for: If the completion signal is found to be invalid after all the data has been sent to the target configuration chip, a reset control signal is sent to the target configuration chip, and the data in the first-in-first-out buffer is resent to the target configuration chip through the sixteen-bit parallel configuration interface; If the number of times the data is sent is greater than or equal to a preset number, then the sending of the data to the target configuration chip is terminated.
6. The system according to claim 1, characterized in that, The target configuration chip is also used for: After receiving the configuration data, the integrity of the configuration data is verified. If the verification fails, the completion signal is determined to be invalid, and the next round of configuration data is received again.
7. The system according to claim 1, characterized in that, The target configuration chip is also used for: Upon receiving the reset control signal from the programmable logic unit, the initialization completion indicator pin of the target configuration chip is configured to the second level signal, the register contents are cleared, and the initialization state is entered. If the initialization completion indicator pin of the target configuration chip changes from a second level signal to a first level signal, it indicates that the target configuration chip has completed the initialization process.
8. A high-reliability configuration method, characterized in that, The method includes: The binary configuration file is obtained from the storage unit through the four-wire serial peripheral interface of the processing unit, and the binary configuration file is written into the first-in-first-out buffer in the programmable logic unit in blocks through the advanced extensible interface bus. The configuration data in the first-in-first-out buffer is sent to the target configuration chip through a 16-bit parallel configuration interface; the completion signal of the target configuration chip is detected, and the configuration process of the target configuration chip is controlled according to the detection result; The target configuration chip is configured based on the configuration data, and the completion signal is configured as a first level signal after the configuration process is completed.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements a high-reliability configuration method as described in claim 8.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a high-reliability configuration method as described in claim 8.