Real-time task processing method and related device

Abstract

A real-time task processing method is applied to a real-time operating system. According to the real-time task processing method, when an executable file of a real-time task is loaded, codes and data, used for achieving a process with an execution duration requirement, in the executable file are loaded to a first memory area of a memory; and caching codes and data on the first memory region to a first cache region with a higher reading speed based on a mapping relationship between the memory and the cache. The first cache region is only used for caching the content on the first memory region, so that the cached content in the first cache region can be ensured to be used for realizing a process with an execution time length requirement, the first cache region is prevented from being preempted by other data contents, the cache hit rate when a real-time task is executed is improved, and the execution efficiency of the real-time task is improved. And therefore, the real-time task can be completed within the specified time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a real-time task processing method and related device. BACKGROUND

[0002] A real-time operating system (RTOS) is an operating system specially used for running real-time tasks. The real-time operating system can ensure that the real-time tasks are completed within a specific time by managing limited hardware resources. In simple terms, the real-time operating system is an operating system that guarantees to complete a specific function within a certain time limit.

[0003] The real-time tasks running on the real-time operating system usually include hard real-time tasks and soft real-time tasks. The hard real-time tasks require that the tasks must be completed within a specified time, otherwise, it may cause serious consequences. The soft real-time tasks require that the tasks can be completed as soon as possible, and are not forced to be completed within a specified time.

[0004] At present, in the real-time operating system, the hard real-time tasks can usually be completed within the specified time. However, in some extreme cases, part of the hard real-time tasks in the real-time operating system may not be completed within the specified time, so that the real-time operating system cannot meet the time requirement of the hard real-time tasks, which is easy to cause serious consequences. SUMMARY

[0005] The present application provides a real-time task processing method and related device, which can improve the cache hit rate when executing real-time tasks, and further ensure that the real-time tasks can be completed within a specified time.

[0006] In a first aspect, a real-time task processing method is provided, which is applied to a real-time operating system. The real-time task processing method specifically includes: in the process of loading an executable file of a real-time task, a first code and a first data used for implementing a key process in the executable file are loaded onto a first memory area of a memory by an execution device, and the key process includes a process in the real-time task that needs to meet an execution time requirement. The first code can be a binary instruction in the executable file, and the first data can be a variable or a constant in the executable file.

[0007] Then, based on a mapping relationship between the first memory area and a first cache area on a cache, the execution device copies the first code and the first data from the first memory area to the first cache area. The mapping relationship is used to indicate that the first cache area is only used to cache the content stored in the first memory area, and the reading speed of the cache is higher than that of the memory.

[0008] Secondly, in response to obtaining the instruction of executing the critical process, the execution device obtains the first code and the first data from the first cache area without obtaining the first code and the first data from the memory, and executes the critical process.

[0009] In the present scheme, when loading the executable file of the real-time task, the code and the data for implementing the process with the execution time requirement in the executable file are loaded onto the first memory area of the memory, and then the code and the data on the first memory area are cached onto the first cache area with higher reading speed based on the mapping relationship between the memory and the cache. Since the first cache area is only used to cache the content on the first memory area, it can be ensured that the content cached in the first cache area is all for implementing the process with the execution time requirement, avoiding the first cache area being occupied by other data content, improving the cache hit rate when executing the real-time task, and then ensuring that the real-time task can be completed within the specified time.

[0010] In a possible implementation, the capacity of the first cache area is the same as that of the first memory area. In this way, all the content stored in the first memory area can be cached in the first cache area and will not be replaced out.

[0011] In the present scheme, by setting the first cache area and the first memory area with the same capacity, the first cache area can cache all the content in the first memory area at the same time, so that the first code and the first data cached in the first cache area will not be replaced out due to insufficient storage space of the first cache area, thereby ensuring that the first code and the first data can be cached in the first cache area all the time. In this way, the execution device can have a 100% hit rate when reading the first code and the first data in the cache, and then ensure that the reading speed of the code and the data when the execution device executes the critical process is deterministic and highest.

[0012] In a possible implementation, in the process of loading the real-time operating system, the execution device loads the second code and the second data for implementing the interrupt processing process and the task scheduling process onto the first memory area. And based on the mapping relationship between the first memory area and the first cache area, the execution device copies the second code and the second data from the first memory area to the first cache area. Secondly, in response to obtaining the interrupt request, the execution device obtains the second code and the second data from the first cache area, and executes the interrupt processing process and the task scheduling process to schedule the execution of the critical process.

[0013] The second code includes the code for implementing the interrupt processing process and the code for implementing the task scheduling process. The second data includes the data for implementing the interrupt processing process and the data for implementing the task scheduling process.

[0014] In the scheme, in addition to storing the code and data for implementing the key process in the first memory region corresponding to the first cache region, the code and data for implementing the interrupt processing process and the task scheduling process in the real-time operating system are also stored in the first memory region corresponding to the first cache region, so that all the code and data related to the key process are cached in the first cache region, and the interrupt processing process and the task scheduling process which may affect the execution efficiency of the key process can also be quickly executed, thereby improving the execution efficiency of the key process and ensuring that the key process can be completed within a limited time.

[0015] In a possible implementation, when loading the executable file of the real-time task, the execution device loads the code and data in the executable file which are not used for implementing the key process on the second memory region of the memory. The first memory region and the second memory region do not have a coincident memory region, and the content stored on the second memory region cannot be copied to the first cache region.

[0016] In the scheme, by storing the code and data for implementing the key process and the code and data not used for implementing the key process in the executable file of the real-time task in different memory regions of the memory, the code and data for executing different processes can be isolated in the memory, the pollution and interference between the memory regions where the code and data for executing different processes in the same real-time task are located can be avoided, and the high hit rate of the code and data for implementing the key process in the cache can be ensured.

[0017] In a possible implementation, in the process of loading the executable file of the non-real-time task, the execution device loads the code and data in the executable file of the non-real-time task on the second memory region. That is, since all the code and data in the executable file of the non-real-time task do not participate in the key process, all the code and data in the executable file of the non-real-time task are loaded on the second memory region, so as to ensure that all the code and data corresponding to the non-real-time task are not cached in the first cache region.

[0018] In a possible implementation, during the running of the execution device, the execution device copies the content in the second memory region to the second cache region based on the mapping relationship between the second memory region and the second cache region in the cache, and the first cache region and the second cache region do not have a coincident cache region.

[0019] In the scheme, on the basis of the first cache region which is specially used for caching the code and data related to the key process in the cache, the second cache region which is used for caching the code and data related to other processes is also provided, so that the execution efficiency of the key process is not affected, and the high reading speed of the cache is used to improve the efficiency of the CPU when executing other processes as much as possible.

[0020] In a possible implementation, the first code and the first data have target marks in the executable file. When the executable file of the real-time task is loaded, the execution device first determines the first code and the first data with the target marks in the executable file, and then loads the first code and the first data onto the first memory region.

[0021] In a possible implementation, the executable file indicates storage addresses of the first code and the first data, and the storage addresses are located on the first memory region. When the executable file of the real-time task is loaded, the execution device loads the first code and the first data onto the storage addresses of the first memory region according to the storage addresses of the first code and the first data indicated in the executable file.

[0022] In a possible implementation, the execution duration of the critical process is less than or equal to a preset duration.

[0023] In a second aspect, a processing apparatus of a real-time task is provided. The processing apparatus is applied to a real-time operating system, and includes a loading module configured to load first code and first data for implementing a critical process in an executable file of the real-time task onto a first memory region of a memory during loading of the executable file, the critical process including a process in the real-time task that needs to meet an execution duration requirement; and a processing module configured to copy the first code and the first data from the first memory region to a first cache region on a cache based on a mapping relationship between the first memory region and the first cache region, the mapping relationship being used to indicate that the first cache region is used only to cache content stored in the first memory region, and a reading speed of the cache being higher than a reading speed of the memory, and the processing module being further configured to, in response to obtaining an instruction to execute the critical process, obtain the first code and the first data from the first cache region and execute the critical process.

[0024] In a possible implementation, the capacity of the first cache region is the same as the capacity of the first memory region.

[0025] In a possible implementation, the loading module is further configured to load second code and second data for implementing an interrupt processing process and a task scheduling process onto the first memory region during loading of the real-time operating system; and the processing module is further configured to copy the second code and the second data from the first memory region to the first cache region based on the mapping relationship, and in response to obtaining an interrupt request, obtain the second code and the second data from the first cache region and execute the interrupt processing process and the task scheduling process to schedule execution of the critical process.

[0026] In a possible implementation, the loading module is further configured to: load the code and the data in the executable file that are not used to implement the critical process onto a second memory region of the memory, the first memory region and the second memory region do not have a coincident memory region, and the content stored on the second memory region cannot be copied to the first cache region.

[0027] In a possible implementation, the loading module is further configured to: load the code and the data in the executable file of the non-real-time task onto a second memory region in the process of loading the executable file of the non-real-time task.

[0028] In a possible implementation, the processing module is further configured to: copy the content in the second memory region to a second cache region on the cache based on a mapping relationship between the second memory region and the second cache region, the first cache region and the second cache region do not have a coincident cache region.

[0029] In a possible implementation, the first code and the first data have a target mark in the executable file, and the loading module is further configured to: determine the first code and the first data with the target mark in the executable file; and load the first code and the first data onto the first memory region.

[0030] In a possible implementation, the executable file indicates a storage address of the first code and the first data, and the storage address is located on the first memory region; and the loading module is further configured to: load the first code and the first data to the storage address of the first memory region according to the storage address indicated in the executable file.

[0031] In a possible implementation, the execution duration of the critical process is less than or equal to a preset duration.

[0032] The third aspect of the present application provides a real-time task processing apparatus, which can include a processor, the processor and a memory are coupled, and the memory stores program instructions, when the program instructions stored in the memory are executed by the processor, the method of the first aspect or any implementation manner of the first aspect is implemented. For the processor to execute the steps in each possible implementation manner of the first aspect, specific details can be referred to the first aspect, and will not be described here.

[0033] The fourth aspect of the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, when the computer program is run on a computer, the computer executes the method of any implementation manner of the first aspect.

[0034] The fifth aspect of the present application provides a circuit system, and the circuit system includes a processing circuit, the processing circuit is configured to execute the method of any implementation manner of the first aspect.

[0035] The sixth aspect of this application provides a computer program product that, when run on a computer, causes the computer to perform any implementation of the first aspect described above.

[0036] A seventh aspect of this application provides a chip system including a processor for supporting a server in implementing the functions involved in any implementation of the first aspect described above, such as processing data and / or information involved in the methods described above. In one possible design, the chip system further includes a memory for storing necessary program instructions and data for the server. This chip system may be composed of chips or may include chips and other discrete devices.

[0037] The beneficial effects of the second to seventh aspects mentioned above can be referred to the introduction of the first aspect above, and will not be repeated here. Attached Figure Description

[0038] Figure 1 A schematic diagram of a system architecture provided for this application;

[0039] Figure 2 A flowchart illustrating a real-time task processing method provided in this application;

[0040] Figure 3 A schematic diagram illustrating the mapping relationship between memory and cache provided in this application;

[0041] Figure 4 A schematic diagram illustrating another mapping relationship between memory and cache provided in this application;

[0042] Figure 5 This application provides a schematic diagram of task processing timing in a hard real-time task scenario;

[0043] Figure 6 A schematic diagram of a real-time task and a non-real-time task processing flow provided for this application;

[0044] Figure 7 A schematic diagram of another real-time task and non-real-time task processing flow provided for this application;

[0045] Figure 8 A schematic diagram illustrating a cache supporting group-associative mode provided in this application;

[0046] Figure 9 A schematic diagram of the structure of a real-time task processing device provided in this application;

[0047] Figure 10 A schematic diagram of the structure of an electronic device provided in this application;

[0048] Figure 11A structural schematic diagram of a computer readable storage medium provided in the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0050] The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0051] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units does not necessarily limit to those clearly listed steps or units, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] (1) Real-time operating system

[0053] The real-time operating system refers to an operating system that schedules all available resources to complete real-time tasks and controls all real-time tasks to run in coordination.

[0054] (2) Real-time task

[0055] In a real-time system, there are usually multiple real-time tasks running. These real-time tasks are usually related to some external devices and can react or control the corresponding external devices, thus having a certain degree of urgency. Generally, real-time tasks can be classified from different perspectives.

[0056] According to whether the task execution presents periodic changes:

[0057] a. Periodic real-time task

[0058] The external device periodically sends an excitation signal to the computer, requiring the computer to execute in a specified cycle to periodically control some external device.

[0059] b. Non-periodic real-time task

[0060] The excitation signal sent by the external device has no obvious periodicity, but must be associated with a deadline. The deadline can be divided into a start deadline (i.e., the task must start execution before a certain time) and a completion deadline (i.e., the task must be completed before a certain time).

[0061] According to the requirements of the task on the deadline, real-time tasks can be divided into hard real-time tasks and soft real-time tasks. Among them, the hard real-time task requires that the task must be completed within a specified time, otherwise it may cause serious consequences. The soft real-time task requires that the task can be completed as soon as possible, and does not require that the task must be completed within a specified time.

[0062] (3) Interrupt

[0063] An interrupt refers to a situation that occurs during the operation of a computer that requires intervention by the computer. The computer can automatically stop the program being run and switch to processing a new program, and after processing is complete, it returns to the paused program to continue running.

[0064] In the specific implementation of the interrupt, the hardware device or program in the computer can send an interrupt request to the central processing unit (CPU) to interrupt the normal execution flow of the CPU, thereby triggering the CPU to execute a specific interrupt service program.

[0065] (4) Cache

[0066] Cache refers to a memory that can exchange data at high speed. Generally, the read speed of the cache will be higher than that of the memory, so the cache will exchange data with the CPU before the memory. That is, when the CPU needs to access data, it will first search for the data in the cache. If the CPU can find the data in the cache (i.e., cache hit), the CPU directly reads the data from the cache without accessing the memory; if the CPU cannot find the data in the cache (i.e., cache miss), the CPU continues to search for and read the data in the memory.

[0067] Currently, in real-time operating systems, hard real-time tasks can often be completed within a specified time. However, in some extreme cases, there may be situations where some hard real-time tasks cannot be completed within a specified time in the real-time operating system, making the real-time operating system unable to meet the time requirements of hard real-time tasks, which can easily lead to serious consequences.

[0068] The applicant's research revealed that the primary reason hard real-time tasks fail to complete within the allotted time is the uncontrolled data access latency caused by cache misses when the CPU accesses the data required for the task. Simply put, when the CPU needs to execute a hard real-time task, it first searches for the necessary data in the cache. If the data is not found in the cache, the CPU continues searching and reading the data from memory. In extreme cases, if the cache does not contain any of the data required for the hard real-time task (e.g., the cache is preempted by other data), the CPU must search and read all the necessary data from memory, resulting in prolonged data access latency and ultimately preventing the hard real-time task from completing within the allotted time.

[0069] This application provides a method for processing real-time tasks. When loading the executable file of a real-time task, the code and data in the executable file used to implement processes with execution time requirements are loaded into a first memory region. Then, based on the mapping relationship between memory and cache, the code and data in the first memory region are cached into a first cache region with higher read speed. Since the first cache region is only used to cache the content in the first memory region, it can be ensured that the content cached in the first cache region is used to implement processes with execution time requirements, preventing the first cache region from being preempted by other data content, improving the cache hit rate when executing real-time tasks, and thus ensuring that real-time tasks can be completed within the specified time.

[0070] Please see Figure 1 , Figure 1 This is a schematic diagram of a system architecture provided for this application. (For example...) Figure 1 As shown, in the system architecture, the execution device 101 can be, for example, a physical host or a physical server. The execution device 101 includes a CPU 1011, memory 1012, and cache 1013. Memory 1012 is used to store the code and data of real-time tasks running on the execution device 101, while cache 1013 is used to cache a portion of the code and data already stored in memory.

[0071] Further, the execution device 101 is communicatively connected with the data storage system 102 for obtaining the program code stored in the data storage system 102 to implement the real-time task processing method provided in the present application. The data storage system 102 may, for example, be implemented by a storage device deployed on the execution device 101, for example, the execution device 101 is a physical server, and the data storage system 102 is a hard disk deployed on the physical server. The data storage system 102 may, for example, also be implemented by a storage device independent of the execution device, for example, the execution device 101 is a computing server, and the data storage system 102 is a data server specially storing program code.

[0072] During the operation of the execution device 101, the program code and the related data required for the execution of the real-time task processing method can be obtained from the data storage system 102, and the efficiency of the thread calling system service provided on the execution device 101 can be improved based on the real-time task processing method provided in the present application.

[0073] The execution device 101 runs a real-time operating system, which is used to control all real-time tasks to run coordinately based on the real-time operating system. Specifically, the execution device 101 running the real-time operating system may, for example, be a device in the fields of aerospace, military, medical treatment, industry, consumer electronics, automotive electronics, energy, high-end manufacturing, Internet of Things, etc., such as a computer, an Internet of Things device, or a wireless control device.

[0074] For example, please refer to Figure 2 , Figure 2 for a flowchart of the real-time task processing method provided in the present application. As shown in Figure 2 , the real-time task processing method is applied to a real-time operating system, and the real-time task processing method includes the following steps 201-203.

[0075] In step 201, during the loading of the executable file of the real-time task, the first code and the first data in the executable file for implementing a critical process are loaded onto a first memory area of the memory, and the critical process includes a process with an execution time requirement in the real-time task.

[0076] During the operation of the execution device, in order to execute the real-time task, the execution device often needs to load the executable file of the real-time task first, i.e., load the executable task of the real-time task from the hard disk to the memory. The execution device may, for example, trigger the loading of the executable file of the real-time task at the start; or may, for example, trigger the loading of the executable file of the real-time task after receiving a corresponding instruction or external input signal after the start, and the present application does not make a specific limitation in this regard.

[0077] When loading the executable file of the real-time task, the execution device loads different codes and data in the executable file into different memory regions in the memory. Specifically, the execution device loads first codes and first data in the executable file for implementing a critical process into a first memory region in the memory, and loads other codes and other data in the executable file which are not for implementing the critical process into a memory region other than the first memory region in the memory, so that the codes and data for implementing the critical process are isolated from the codes and data which are not for implementing the critical process in the memory. The first codes can be binary instructions in the executable file, and the first data can be variables or constants in the executable file. During the running of the first codes, the first data can be read or modified. Based on the first codes and the first data, a specific process in the real-time task can be implemented.

[0078] The critical process can include processes in the real-time task that have execution time length requirements. For example, the critical process can include only processes in the current real-time task that have execution time length requirements, or can include processes in the current real-time task and other real-time tasks (i.e., multiple real-time tasks) that have execution time length requirements. That is, the first codes and the first data in the executable file can be used to implement the entire critical process, or can be used to implement only part of the critical process.

[0079] Optionally, the execution time length of the critical process is less than or equal to a preset time length, which is determined or adjusted according to the type of the critical process itself in the actual application scenario, which is not limited here. Therefore, in the case where the first codes and the first data in the executable file are used to implement the entire critical process, the execution time length requirement can be that the execution time length is less than or equal to the preset time length. In the case where the first codes and the first data in the executable file are used to implement part of the critical process, the execution time length requirement can be that the execution time length is less than or equal to a specified time length (where the specified time length is less than the preset time length), or the execution time length of the process implemented by the first codes and the first data and the execution time length of other processes are less than or equal to the preset time length.

[0080] In general, the process implemented based on the first codes and the first data needs to be completed within a certain time length, so as to meet the time length requirement of the real-time task.

[0081] In step 202, the first codes and the first data are copied from the first memory region to the first cache region based on a mapping relationship between the first memory region and the first cache region on the cache. The mapping relationship is used to indicate that the first cache region is only used to cache the content stored in the first memory region, and the reading speed of the cache is higher than that of the memory.

[0082] Exemplarily, please refer to Figure 3 , Figure 3 A schematic diagram of a mapping relationship established between a memory and a cache is provided in the present application. As shown in Figure 3 , in the present application, a mapping relationship is established between a first memory region on the memory and a first cache region on the cache, which indicates that the first cache region is only used to cache the content stored in the first memory region. That is, the first cache region will not cache the content outside the first memory region on the memory. In this way, based on the mapping relationship between the first memory region and the first cache region, the execution device can copy the first code and the first data from the first memory region to the first cache region, so as to improve the speed of the CPU in subsequently reading the first code and the first data.

[0083] It can be understood that in the execution device, the reading speed of the cache is usually much higher than that of the memory, but due to cost constraints, the capacity of the cache is usually much smaller than that of the memory. Therefore, in this step, by establishing the mapping relationship between the first memory region and the first cache region, the first cache region is only used to cache the content in the first memory region, and will not cache other content outside the first memory region. Moreover, the first memory region is used to store the code and data in the executable file for implementing the process with time requirement, so as to ensure that other code and data in the executable file which are not used to implement the process with time requirement will not be cached on the first cache region, thereby ensuring that the first code and the first data will not be replaced out of the first cache region due to the occupation of other code or data, effectively ensuring the hit rate of the CPU in searching for the first code and the first data in the cache.

[0084] Optionally, in order to ensure the hit rate of the cache, the capacity of the first cache region is the same as that of the first memory region. Therefore, in the case that the capacity of the first cache region is the same as that of the first memory region, all the content stored in the first memory region can be cached in the first cache region and will not be replaced out. That is, since the first cache region can simultaneously cache all the content in the first memory region, the first code and the first data cached in the first cache region will not be replaced out due to insufficient storage space of the first cache region, thereby ensuring that the first code and the first data can be always cached in the first cache region, ensuring that the CPU of the execution device can have a 100% hit rate in reading the first code and the first data in the cache, and further ensuring that the speed of the CPU in reading the code and the data when executing the critical process is deterministic and highest.

[0085] Of course, in some scenarios (such as the capacity of the first memory region is large), the capacity of the first cache region can also be smaller than that of the first memory region, which is not limited in the present application.

[0086] It can be understood that in an executable file of a real-time task, a large amount of code and data are often included. However, usually only a small part of the code and data is used to implement a process with an execution time requirement, and most of the code and data is used to implement a process without an execution time requirement. Therefore, when the first memory region stores the first code and the first data used to implement the process with the execution time requirement, the first memory region itself can also be a memory region with a small capacity, such as a first memory region with a size of 1 megabyte (MB), because the first code and the first data occupy a small storage space. In this way, when the first memory region has a small capacity, the first cache region with the same capacity as the first memory region can be ensured to be divided in the cache although the cache itself has a small capacity.

[0087] In step 203, in response to obtaining the instruction to execute the critical process, the first code and the first data are obtained from the first cache region, and the critical process is executed.

[0088] After the first code and the first data are copied to the first cache region, if the CPU in the execution device obtains an instruction to execute the critical process, the CPU in the execution device can obtain the first code and the first data from the first cache region without obtaining the first code and the first data from the memory, and execute the critical process based on the first code and the first data. Of course, if the first code and the first data are only used to implement part of the critical process, the CPU in the execution device also needs to obtain other code and data to implement the entire critical process.

[0089] In the real-time operating system, because the critical process related to the real-time task can be periodically triggered for execution or triggered for execution by an external signal, in order to ensure that the critical process can be completed within a preset time period after being triggered for execution, some corresponding software modules are often deployed in the real-time operating system to ensure the execution of the critical process. Specifically, the real-time operating system can be deployed with an interrupt processing module and a task scheduling module to ensure the smooth execution of the critical process by executing an interrupt processing process and a task scheduling process by the interrupt processing module and the task scheduling module respectively. That is, when the critical process is executed, the execution device often needs to execute the corresponding interrupt processing process and the task scheduling process. Therefore, in order to improve the execution efficiency of the critical process, the related code and data of the interrupt processing process and the task scheduling process in the real-time operating system that affect the execution efficiency of the critical process can also be loaded onto the first memory region.

[0090] Exemplarily, in the process of loading the real-time operating system, the execution device loads second code and second data for implementing an interrupt processing flow and a task scheduling flow onto the first memory region.

[0091] After the second code and the second data are loaded onto the first memory region, based on the mapping relationship between the first memory region and the first cache region, the execution device copies the second code and the second data from the first memory region to the first cache region.

[0092] Then, in response to obtaining an interrupt request, the execution device can obtain the second code and the second data from the first cache region, and execute the interrupt processing flow and the task scheduling flow to schedule the execution of the critical flow.

[0093] The second code includes code for implementing the interrupt processing flow and code for implementing the task scheduling flow. The second data includes data for implementing the interrupt processing flow and data for implementing the task scheduling flow. The interrupt processing flow is a flow triggered when a CPU in the execution device obtains a signal sent by a timer or an external device signal, and is mainly used to make the CPU pause the currently executed flow and switch to the execution of the critical flow. The task scheduling flow is a flow executed after the CPU executes the interrupt processing flow or after the CPU finishes executing part of the critical flow, and is mainly used to schedule the execution of real-time tasks to complete the entire critical flow. For example, when the critical flow includes a flow composed of multiple real-time tasks, the CPU continues to execute the task scheduling flow after executing the interrupt processing flow to schedule the execution of the first real-time task. After the CPU finishes a real-time task in the critical flow, the CPU continues to execute the task scheduling flow to schedule the execution of the next real-time task in the critical flow.

[0094] In this scheme, in addition to storing code and data for implementing the critical flow in the first memory region corresponding to the first cache region, code and data for implementing the interrupt processing flow and the task scheduling flow in the real-time operating system are also stored in the first memory region corresponding to the first cache region, so that all code and data related to the critical flow are cached in the first cache region, ensuring that the interrupt processing flow and the task scheduling flow, which may affect the execution efficiency of the critical flow, can also be quickly executed, thereby improving the execution efficiency of the critical flow and ensuring that the critical flow can be completed within a limited time.

[0095] The above describes loading code and data related to the critical flow into the first memory region corresponding to the first cache region, so that the code and data related to the critical flow can finally be cached in the first cache region. The following describes how to load code and data not related to the critical flow.

[0096] Exemplarily, in the process of loading the executable file of the real-time task, the execution device loads the code and data in the executable file of the real-time task which are not used for implementing the critical process onto the second memory region of the memory. The first memory region and the second memory region do not have a coincident memory region, and the content stored on the second memory region cannot be copied to the first cache region. That is, the second memory region is another region on the memory other than the first memory region. And since the first cache region only corresponds to the first memory region, the content stored on the second memory region will not be copied to the first cache region.

[0097] In this way, by storing the code and data for implementing the critical process and the code and data not used for implementing the critical process in the executable file of the real-time task in different memory regions of the memory respectively, the code and data for implementing different processes can be isolated on the memory, the pollution and interference between the memory regions where the code and data for implementing different processes in the same real-time task are located can be avoided, and the high hit rate of the code and data for implementing the critical process on the cache can be ensured.

[0098] Optionally, in the process of loading the executable file of the non-real-time task, the execution device loads the code and data in the executable file of the non-real-time task onto the second memory region. That is, since all the code and data in the executable file of the non-real-time task do not participate in the critical process, all the code and data in the executable file of the non-real-time task are loaded onto the second memory region to ensure that all the code and data corresponding to the non-real-time task will not be cached into the first cache region.

[0099] Optionally, in the execution device, a mapping relationship between the second memory region and a second cache region on the cache is established in advance. In this way, during the running of the execution device, based on the mapping relationship between the second memory region and the second cache region, the execution device can copy the content in the second memory region onto the second cache region. The first cache region and the second cache region do not have a coincident cache region. For example, the execution device copies the code and data in the executable file of the real-time task which are not used for implementing the critical process from the second memory region to the second cache region; or the execution device copies the code and data in the executable file of the non-real-time task from the second memory region to the second cache region.

[0100] In general, in the case that the mapping relationship between the second memory region and the second cache region is established, the CPU of the execution device can copy the code and / or data in the second memory region to the second cache region according to the requirement of reading the code and / or data in the actual running process. Moreover, since the capacity of the second cache region is generally less than that of the second memory region, the content cached in the second cache region can be frequently replaced according to the running condition of the CPU. However, the replacement of the content cached in the second cache region does not affect the content cached in the first cache region, so that the CPU can quickly read the required code and data from the first cache region when executing the critical process, ensuring the execution efficiency of the critical process.

[0101] In the present scheme, on the basis of the first cache region specially used for caching the code and data related to the critical process in the cache, the second cache region used for caching the code and data related to other processes is further provided, so that the higher reading speed of the cache can be utilized to improve the efficiency of the CPU when executing other processes as much as possible without affecting the execution efficiency of the critical process.

[0102] Exemplarily, please refer to Figure 4 , Figure 4 Another schematic diagram of the mapping relationship between the memory and the cache provided in the present application. As shown in Figure 4 , the memory includes a first memory region and a second memory region, and the cache includes a first cache region and a second cache region.

[0103] Among them, the first memory region and the first cache region have a mapping relationship, the capacity of the first memory region is the same as that of the first cache region, and the first memory region is used for storing the code and data for implementing the critical process, the code and data for implementing the interrupt processing process and the task scheduling process in the real-time task. Therefore, based on the mapping relationship between the first memory region and the first cache region, the first cache region is also used for caching only the code and data for implementing the critical process, the code and data for implementing the interrupt processing process and the task scheduling process in the real-time task.

[0104] In addition, the second memory region and the second cache region have a mapping relationship, the capacity of the second memory region is greater than that of the second cache region, and the second memory region is used for storing the code and data for implementing the non-critical process in the real-time task and the code and data of the non-real-time task. Therefore, based on the mapping relationship between the second memory region and the second cache region, the second cache region is used for caching the code and data for implementing the non-critical process in the real-time task and the code and data of the non-real-time task.

[0105] In the process of loading the executable file of the real-time task, in order to accurately store the first code and the first data in the executable file in the first memory region, the present application provides a plurality of possible implementation manners.

[0106] In a possible implementation manner, the first code and the first data have target marks in the executable file.

[0107] When loading the executable file of the real-time task, the execution device first determines the first code and the first data having target marks in the executable file; then, the execution device loads the first code and the first data to the first memory region.

[0108] That is, the first code and the first data in the executable file are pre-marked with target marks, and the execution device can identify the code and the data having target marks in the executable file when loading the executable file, and then store the first code and the first data having target marks to the first memory region. For the code and the data in the executable file not having target marks, the execution device stores these code and data to other memory regions (such as the second memory region described above) in the memory.

[0109] It should be noted that the developer can add target marks to the code and the data for implementing the critical process when writing the source code of the real-time task, so that when the source code of the real-time task is compiled into an executable file, the executable file including the first code and the first data can be obtained, and the first code and the first data have target marks.

[0110] Alternatively, after the developer writes the source code of the real-time task, the source code can be first compiled into an executable file, and the executable file is tested and run to determine the hot code and the hot data in the process of running the executable file. Specifically, in the process of running the executable file, if some code and some data are run every time the critical process is executed, these code and data can be considered as hot code and hot data, and then target marks can be added to these hot code and hot data. For example, after determining the hot code and the hot data in the executable file, target marks can be added to these hot code and hot data in the executable file; or target marks can be added to the original code and the original data corresponding to the hot code and the hot data in the source code of the executable file, and finally the executable file is compiled, and the hot code and the hot data in the executable file have target marks.

[0111] In another possible implementation manner, the executable file indicates the storage addresses of the first code and the first data, and the storage addresses of the first code and the first data are located on the first memory region.

[0112] When loading the executable file of a real-time task, the execution device loads the first code and the first data into the storage address of the first memory region according to the storage address of the first code and the first data indicated in the executable file.

[0113] In other words, the execution device can pre-allocate a first memory region in memory and establish a mapping relationship between the first memory region and the first cache region. Furthermore, the executable file directly indicates the storage address of the first code and first data in memory, and this storage address is located within the first memory region. Thus, when the executable file is loaded, based on the instructions in the executable file, the execution device can load the first code and first data into the specified storage address within the first memory region.

[0114] Similarly, developers can pre-add target tags to the code and data that implement the critical processes in the source code of a real-time task, and then allocate storage addresses in the first memory region for the code and data with target tags when compiling the source code, so that the code and data that implement the critical processes can be stored in the first memory region.

[0115] The above describes a real-time task processing method provided in this application. For ease of understanding, the execution process of this real-time task processing method will be explained in detail below with specific examples.

[0116] Please see Figure 5 , Figure 5 This application provides a schematic diagram of the task processing timing in a hard real-time task scenario. For example... Figure 5 As shown, in a task execution scenario, a cycle requires the execution of real-time task 1, real-time task 2, non-real-time task, and background task. First, at the start of a cycle, a high-precision timer triggers an interrupt request to the CPU, initiating the task processing flow for the current cycle. After the CPU executes the interrupt handling flow, it proceeds to the task scheduling flow, initially scheduling the high-priority real-time task 1. After the CPU completes real-time task 1, it continues the task scheduling flow, scheduling the next-priority real-time task 2. After the CPU completes real-time task 2, it continues the task scheduling flow, scheduling the even lower-priority non-real-time task. After the CPU completes the non-real-time task, it continues the task scheduling flow, scheduling the lowest-priority background task, finally awaiting the next cycle.

[0117] The processes involved in executing real-time tasks 1 and 2 constitute the critical processes, and these critical processes must be completed before the next cycle begins. Therefore, the execution latency of these critical processes must be extremely low and deterministic. Furthermore, by... Figure 5It can be seen that the execution latency of critical processes is actually affected by interrupt handling processes and task scheduling processes. Therefore, the latency of interrupt handling processes and task scheduling processes must also be low enough to avoid affecting the normal execution of critical processes.

[0118] This application supports using software to isolate and centralize the code and data that implement the critical process from the code and data that are not used to implement the critical process, and to allocate cache resources in memory for the code and data used to implement the critical process and to make separate mappings.

[0119] Specifically, as real-time tasks, Real-Time Task 1 and Real-Time Task 2 will be isolated in memory from the code and data of non-real-time tasks and background tasks. Furthermore, as real-time tasks, the code and data used to implement critical processes within Real-Time Task 1 and Real-Time Task 2 will also be isolated in memory from the code and data not used to implement critical processes.

[0120] Please see Figure 6 , Figure 6 This application provides a schematic diagram of the processing flow for both real-time and non-real-time tasks. Figure 6 As shown, in a real-time operating system, real-time tasks and non-real-time tasks run, and the key processes in real-time tasks have real-time requirements, while non-real-time tasks do not. To improve the execution efficiency of key processes in real-time tasks, the processing flow for real-time and non-real-time tasks in this application includes the following three stages: 1. Collaborative task scheduling and cache replacement orchestration; 2. Independent mapping of memory and cache partitions; 3. Deterministic cache replacement. These three stages will be described in detail below.

[0121] Phase 1: Collaboration of task scheduling and cache replacement orchestration.

[0122] In Phase 1, to ensure that the code and data used to implement interrupt handling, task scheduling, and critical processes reside in a cache area that will not be replaced by other data, the orchestration of cache replacement can be coordinated with the task scheduling situation during real-time task execution. That is, the code and data used to implement interrupt handling, task scheduling, and critical processes are orchestrated into a cache area that will not be replaced by other data, while the code and data used to implement other processes are orchestrated into a cache area where data replacement will occur.

[0123] For example, the real-time operating system can be compiled and linked uniformly with real-time tasks and non-real-time tasks, sharing an address space to generate an original image. This original image is an executable file that includes the code and data of the real-time operating system, real-time tasks, and non-real-time tasks. Of course, in some embodiments, the real-time operating system, real-time tasks, and non-real-time tasks can also be compiled separately and independently; this is not specifically limited here.

[0124] To identify the code and data used to implement critical processes in a real-time task, the original image can be tested. During the test run of the original image, hotspot code and data in the real-time task execution process can be identified through methods such as memory access record analysis, memory access pattern modeling, and prediction. Then, based on the original image, the identified hotspot code and data can be marked, resulting in a marked image. Alternatively, after identifying hotspot code and data, the source code of the original image can also be marked with the corresponding code and data. This allows the source code to be loaded with the marked code and data at addresses in the real-time memory region (i.e., the first memory region mentioned above) during compilation, thus obtaining a marked image.

[0125] Furthermore, the interrupt handling and task scheduling processes that can be executed in a real-time operating system are processes with high real-time requirements. Therefore, the code and data used to implement the interrupt handling and task scheduling processes in the real-time operating system can also be marked as hot code and hot data, so that the code and data used to implement the interrupt handling and task scheduling processes can be loaded into the real-time memory area.

[0126] In this way, by marking the original image or the source code corresponding to the original image, it can be ensured that when the execution device loads the marked image, it can load the code and data used to implement the critical processes, as well as the code and data used to implement the interrupt handling process and the task scheduling process, into the real-time memory area.

[0127] The memory is divided into a real-time memory area and a non-real-time memory area (i.e., the second memory region mentioned above), and these two areas are completely separated in address space for subsequent cache resource mapping. When loading the marked image, code and data in the real-time operating system that are not used to implement interrupt handling and task scheduling processes are loaded into the non-real-time memory area. Similarly, code and data in real-time tasks that are not used to implement critical processes are also loaded into the non-real-time memory area, as are code and data in non-real-time tasks.

[0128] For example, please refer to Figure 7 , Figure 7This application provides another schematic diagram illustrating the processing flow of real-time and non-real-time tasks. For example... Figure 7 As shown, the original image can be divided into code and data segments. The code segment, specifically the `.text` file, is used to store code. The data segment includes `.rodata`, `.data`, `.bss`, and `.stack`. `.rodata` stores read-only data, `.data` stores regular readable and writable data, `.bss` stores data initialized to 0, and `.stack` stores the program's execution stack. All code and data segments can be marked as described above to load marked code and data into the real-time memory area. Unmarked code and data are loaded into the non-real-time memory area.

[0129] Phase 2: Independent mapping between memory and cache partitions.

[0130] After stage 1 processing, the memory has been separated into a real-time memory area and a non-real-time memory area. Therefore, this stage can perform segment alignment and page allocation according to the hardware specifications of the execution device and the Memory Management Unit (MMU). For example, if the execution device supports 4K page mapping, then the real-time memory area will be mapped according to 4K pages.

[0131] The cache in the execution device also allocates resources according to the cache's specifications. For example, for a 4-way set-associative cache with a size of 2MB, the number of page resources that can be allocated to the cache is: 2MB / 4KB / 4 = 128. For an example, please refer to... Figure 8 , Figure 8 This is a schematic diagram illustrating a cache supporting group-associative mode provided in this application. Figure 8 As shown, when the cache supports set-associative mode, the cache region can be divided into multiple groups (e.g., group 1 and group 2), and different groups include different cache regions. For a given address in memory (e.g., ... Figure 8 The cache addresses (0-11) correspond to a fixed group within the cache. This means that data at a given address will only be cached within the corresponding group. For example, data at addresses 1, 3, 5, 7, 9, and 11 will only be cached within group 1; data at addresses 0, 2, 4, 6, 8, and 10 will only be cached within group 2.

[0132] Specifically, caching can be divided into a real-time cache area and a non-real-time cache area. The real-time cache area is mapped to the real-time memory area, while the non-real-time cache area is mapped to the real-time memory area. This ensures that the real-time cache area only caches code and data from the real-time memory area, and not code and data from the non-real-time memory area. This guarantees that code and data from the real-time memory area will be cached in the real-time cache area, while code and data from the non-real-time memory area will not enter the real-time cache area.

[0133] Phase 3, deterministic cache replacement.

[0134] After completing the two stages described above, deterministic cache replacement can be performed during the execution of the program on the execution device. Specifically, the code and data stored in the real-time memory area are strictly determined according to real-time requirements, and the real-time cache area can only cache the code and data stored in the real-time memory area. Therefore, it can be ensured that the real-time cache hit rate is 100% when the execution device is executing critical processes. That is, the code and data required by the execution device to execute critical processes can all be found in the real-time cache area, thereby ensuring that the latency of code execution and data access is within a defined range, completely eliminating uncontrollable latency factors caused by cache misses, and achieving the goal of ensuring that real-time tasks meet deadline requirements under a real-time operating system with hard real-time requirements.

[0135] Furthermore, since code and data in the non-real-time memory area never enter the real-time cache area, cache replacement only occurs in the non-real-time cache area. That is, the non-real-time cache area will replace code or data based on the code or data accessed by the execution device in real time.

[0136] The method provided in this application has been described in detail above. Next, the device provided in this application for performing the above method will be described.

[0137] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a real-time task processing device provided in this application. Figure 9As shown, the real-time task processing device is applied to a real-time operating system, and the real-time task processing device includes: a loading module 901, used to load the first code and first data used to implement the key process in the executable file of the real-time task into a first memory area in memory during the loading process of the executable file of the real-time task, the key process including the process in the real-time task that needs to meet the execution time requirement; a processing module 902, used to copy the first code and first data from the first memory area to the first cache area based on the mapping relationship between the first memory area and the first cache area on the cache, wherein the mapping relationship is used to indicate that the first cache area is only used to cache the content stored in the first memory area, and the cache read speed is higher than the memory read speed; the processing module 902 is also used to retrieve the first code and first data from the first cache area and execute the key process in response to obtaining the instruction to execute the key process.

[0138] In one possible implementation, the capacity of the first cache region is the same as the capacity of the first memory region.

[0139] In one possible implementation, the loading module 901 is further configured to load the second code and the second data used to implement the interrupt handling process and the task scheduling process into the first memory area during the loading of the real-time operating system; the processing module 902 is further configured to copy the second code and the second data from the first memory area to the first cache area based on the mapping relationship; the processing module 902 is further configured to, in response to the acquisition of an interrupt request, retrieve the second code and the second data from the first cache area and execute the interrupt handling process and the task scheduling process to schedule the execution of the critical process.

[0140] In one possible implementation, the loading module 901 is further configured to: load code and data in the executable file that are not used to implement the critical process into a second memory region, wherein the first memory region and the second memory region do not overlap, and the contents stored in the second memory region cannot be copied to the first cache region.

[0141] In one possible implementation, the loading module 901 is further configured to: load the code and data in the executable file of the non-real-time task into a second memory region during the loading process of the executable file of the non-real-time task.

[0142] In one possible implementation, the processing module 902 is further configured to: copy the contents of the second memory region to the second cache region based on the mapping relationship between the second memory region and the second cache region on the cache, wherein the first cache region and the second cache region do not have overlapping cache regions.

[0143] In one possible implementation, the first code and the first data have target tags in the executable file, and the loading module 901 is further configured to: determine the first code and the first data with target tags in the executable file; and load the first code and the first data into a first memory region.

[0144] In one possible implementation, the executable file indicates the storage address of the first code and the first data, and the storage address is located in the first memory region; the loading module 901 is further configured to: load the first code and the first data into the storage address of the first memory region according to the storage address indicated in the executable file.

[0145] In one possible implementation, the execution time of the critical process must be less than or equal to the preset time.

[0146] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of an electronic device provided in this application. Figure 10 As shown, electronic device 1000 can specifically be a server, but this is not limited here. Specifically, electronic device 1000 includes: receiver 1001, transmitter 1002, processor 1003, and memory 1004 (wherein the number of processors 1003 in electronic device 1000 can be one or more). Figure 10 (Taking a processor as an example), processor 1003 may include application processor 10031 and communication processor 10032. In some embodiments of this application, receiver 1001, transmitter 1002, processor 1003 and memory 1004 may be connected via a bus or other means.

[0147] Memory 1004 may include read-only memory and random access memory, and provides instructions and data to processor 1003. A portion of memory 1004 may also include non-volatile random access memory (NVRAM). Memory 1004 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0148] Processor 1003 controls the operation of electronic devices. In specific applications, the various components of electronic devices are coupled together through a bus system, which may include not only data buses but also power buses, control buses, and status signal buses. However, for clarity, all buses in the diagram are referred to as a bus system.

[0149] The methods disclosed in the embodiments of this application described above can be applied to processor 1003, or implemented by processor 1003. Processor 1003 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of processor 1003 or by instructions in the form of software. The processor 1003 described above can be a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0150] The processor 1003 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 1004. The processor 1003 reads information from memory 1004 and, in conjunction with its hardware, completes the steps of the above methods.

[0151] Receiver 1001 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of electronic devices. Transmitter 1002 can be used to output digital or character information through the first interface; transmitter 1002 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1002 may also include a display device such as a display screen.

[0152] The electronic device provided in this application embodiment can specifically be a chip, which includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip in the execution device to execute the methods described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. The storage unit can also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, such as random access memory (RAM).

[0153] Please refer to Figure 11 , Figure 11 This is a schematic diagram of a computer-readable storage medium provided in this application. This application also provides a computer-readable storage medium in some embodiments, wherein the above-described... Figure 2 The disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0154] Figure 11 A conceptual partial view of an example computer-readable storage medium arranged according to at least some of the embodiments shown herein is illustrated schematically. The example computer-readable storage medium includes a computer program for executing computer processes on a computing device.

[0155] In one embodiment, the computer-readable storage medium 1100 is provided using a signal bearer medium 1101. The signal bearer medium 1101 may include one or more program instructions 1102, which, when executed by one or more processors, can provide the above-mentioned... Figure 2 The described function or part of the function.

[0156] In some examples, the signal carrying medium 1101 may include a computer-readable medium 1103, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital magnetic tape, a memory, ROM, or RAM, etc.

[0157] In some embodiments, the signal carrying medium 1101 may comprise a computer-recordable medium 1104, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, etc. In some embodiments, the signal carrying medium 1101 may comprise a communication medium 1105, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.). Therefore, for example, the signal carrying medium 1101 may be transmitted by a wireless form of communication medium 1105 (e.g., a wireless communication medium conforming to the IEEE 802.X standard or other transmission protocols).

[0158] One or more program instructions 1102 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 1102 conveyed to the computing device via a computer-readable medium 1103, a computer-recordable medium 1104, and / or a communication medium 1105.

[0159] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0160] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods of the various embodiments of this application.

[0161] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0162] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, computer instructions may be transferred from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method for processing real-time tasks, characterized in that, The method is applied to a real-time operating system, and the method includes: During the loading of the executable file of the real-time task, the first code and first data used to implement the key process in the executable file are loaded into the first memory area of ​​the memory. The key process includes the process in the real-time task that needs to meet the execution time requirement. Based on the mapping relationship between the first memory region and the first cache region on the cache, the first code and the first data are copied from the first memory region to the first cache region, wherein the mapping relationship is used to indicate that the first cache region is only used to cache the content stored in the first memory region, and the read speed of the cache is higher than the read speed of the memory. In response to receiving an instruction to execute the critical process, the first code and the first data are retrieved from the first cache area, and the critical process is executed.

2. The method according to claim 1, characterized in that, The capacity of the first cache region is the same as the capacity of the first memory region.

3. The method according to claim 1 or 2, characterized in that, The method further includes: During the loading of the real-time operating system, the second code and the second data used to implement the interrupt handling process and the task scheduling process are loaded into the first memory area; Based on the mapping relationship, the second code and the second data are copied from the first memory area to the first cache area; In response to receiving an interruption request, the second code and the second data are retrieved from the first cache area, and the interrupt handling process and task scheduling process are executed to schedule the execution of the critical process.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: The code and data in the executable file that are not used to implement the key process are loaded into a second memory region of the memory. The first memory region and the second memory region do not overlap, and the content stored in the second memory region cannot be copied to the first cache region.

5. The method according to claim 4, characterized in that, The method further includes: During the loading of the executable file for a non-real-time task, the code and data in the executable file for the non-real-time task are loaded into the second memory region.

6. The method according to claim 4 or 5, characterized in that, The method further includes: Based on the mapping relationship between the second memory region and the second cache region on the cache, the content of the second memory region is copied to the second cache region, wherein the first cache region and the second cache region do not have overlapping cache regions.

7. The method according to any one of claims 1-6, characterized in that, The first code and the first data have target markers in the executable file. Loading the first code and first data from the executable file, used to implement the key process, into a first memory region includes: The first code and the first data with the target marker are determined in the executable file; Load the first code and the first data into the first memory region.

8. The method according to any one of claims 1-6, characterized in that, The executable file indicates the storage address of the first code and the first data, and the storage address is located in the first memory region; The step of loading the first code and first data used to implement the key process in the executable file into a first memory region includes: The first code and the first data are loaded into the storage address of the first memory region according to the storage address indicated in the executable file.

9. The method according to any one of claims 1-8, characterized in that, The execution time of the key process must be less than or equal to the preset time.

10. A real-time task processing apparatus, characterized in that, The device is used in a real-time operating system, and the device includes: The loading module is used to load the first code and first data used to implement the key process in the executable file of the real-time task into the first memory area of ​​the memory during the loading process of the executable file of the real-time task. The key process includes the process in the real-time task that needs to meet the execution time requirement. The processing module is configured to copy the first code and the first data from the first memory region to the first cache region based on the mapping relationship between the first memory region and the first cache region on the cache, wherein the mapping relationship is used to indicate that the first cache region is only used to cache the content stored in the first memory region, and the read speed of the cache is higher than the read speed of the memory. The processing module is further configured to, in response to receiving an instruction to execute the key process, retrieve the first code and the first data from the first cache area and execute the key process.

11. The apparatus according to claim 10, characterized in that, The capacity of the first cache region is the same as the capacity of the first memory region.

12. The apparatus according to claim 10 or 11, characterized in that, The loading module is also used to load the second code and the second data used to implement the interrupt handling process and the task scheduling process into the first memory area during the loading of the real-time operating system. The processing module is further configured to copy the second code and the second data from the first memory area to the first cache area based on the mapping relationship; The processing module is further configured to, in response to receiving an interrupt request, retrieve the second code and the second data from the first cache area, and execute the interrupt handling process and the task scheduling process to schedule the execution of the critical process.

13. The apparatus according to any one of claims 10-12, characterized in that, The loading module is also used for: The code and data in the executable file that are not used to implement the key process are loaded into a second memory region of the memory. The first memory region and the second memory region do not overlap, and the content stored in the second memory region cannot be copied to the first cache region.

14. The apparatus according to claim 13, characterized in that, The loading module is also used for: During the loading of the executable file for a non-real-time task, the code and data in the executable file for the non-real-time task are loaded into the second memory region.

15. The apparatus according to claim 13 or 14, characterized in that, The processing module is further configured to: Based on the mapping relationship between the second memory region and the second cache region on the cache, the content of the second memory region is copied to the second cache region, wherein the first cache region and the second cache region do not have overlapping cache regions.

16. The apparatus according to any one of claims 10-15, characterized in that, The first code and the first data have target tags in the executable file, and the loading module is further configured to: The first code and the first data with the target marker are determined in the executable file; Load the first code and the first data into the first memory region.

17. The apparatus according to any one of claims 10-15, characterized in that, The executable file indicates the storage address of the first code and the first data, and the storage address is located in the first memory region; The loading module is also used for: The first code and the first data are loaded into the storage address of the first memory region according to the storage address indicated in the executable file.

18. The apparatus according to any one of claims 10-17, characterized in that, The execution time of the key process must be less than or equal to the preset time.

19. A real-time task processing apparatus, characterized in that, The device includes a memory and a processor; the memory stores code, and the processor is configured to execute the code, wherein when the code is executed, the device performs the method as described in any one of claims 1 to 9.

20. A computer storage medium, characterized in that, The computer storage medium stores instructions that, when executed by the computer, cause the computer to perform the method according to any one of claims 1 to 9.

21. A computer program product, characterized in that, The computer program product stores instructions that, when executed by a computer, cause the computer to perform the method according to any one of claims 1 to 9.

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