Banded matrix LU decomposition fusion optimization method and system
By adopting a block partitioning strategy based on a right-looking structure and a fusion kernel execution mechanism, the problems of computational redundancy and low parallel efficiency in the LU decomposition of strip matrices are solved, achieving efficient GPU resource utilization and performance improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-27
AI Technical Summary
Existing LU decomposition algorithms struggle to effectively utilize the sparse structure of banded matrices, resulting in high computational redundancy, low parallel efficiency, and poor GPU architecture adaptability, thus failing to fully leverage the parallel advantages of GPUs.
A block partitioning strategy based on a right-looking structure is adopted. By generating a block partitioning strategy and integrating the kernel execution mechanism, the scope of iterative computation is limited, global memory access is reduced, panel decomposition and GER operations are optimized, thread resources are dynamically configured, and auxiliary buffers are used to process data outside the bandwidth.
It significantly improves the computational performance and resource utilization of LU decomposition of striped matrices on GPU platforms, with a performance increase of 20 to 40 times, a reduction in runtime of 2 to 2.8 times, and optimization of computational processes and memory access efficiency.
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Figure CN121743652A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computing platform optimization technology, and in particular to a method and system for optimizing the decomposition and fusion of strip matrix LU. Background Technology
[0002] Striped matrices are a class of matrices with a specific sparse structure, where non-zero elements are concentrated along the main diagonal and within a few adjacent bandwidths. They have wide applications in engineering calculations, physical modeling, and numerical analysis. With the rapid development of computer technology, Graphics Processing Units (GPUs), due to their powerful parallel computing capabilities, have been widely used in scientific computing, significantly improving the efficiency of large-scale numerical calculations. Especially in numerical linear algebra, GPUs have become an important tool for accelerating matrix operations and are widely used in signal processing, image analysis, and information security, among other fields.
[0003] Existing optimization research on matrix factorization mainly focuses on the LU (Lower-Upper Decomposition) algorithm for dense matrices, and various parallelization schemes have been implemented on GPU platforms. For example, heterogeneous computing allows the highly serialized panel decomposition to be executed on the CPU, while the parallelizable tail matrix update is handled by the GPU to hide data transfer overhead. In addition, right-looking decomposition strategies based on block algorithms (a specific computational order and data access pattern) and dynamic task scheduling mechanisms are also widely used to improve the parallel efficiency of LU decomposition of dense matrices. However, most of these methods are designed for dense matrices and fail to effectively adapt to the sparse structure and locally non-zero distribution characteristics of banded matrices.
[0004] Although some studies have attempted to transfer the block algorithm concept of dense matrices to strip matrix factorization, such as the block LU decomposition routine based on Level 3 BLAS provided in LAPACK, and the GPU-oriented strip matrix factorization prototype frameworks that have emerged in recent years, these methods have improved computational efficiency to some extent, but still have the following limitations: First, traditional methods often treat strip matrices as dense matrices, resulting in a large number of zero elements participating in the calculation, which wastes computational and storage resources; second, the implementation of existing strip matrix factorization algorithms on GPUs is still relatively preliminary, failing to fully utilize its thread hierarchy structure, making it difficult to achieve high parallel efficiency and bandwidth utilization.
[0005] Currently, most existing LU decomposition algorithms are designed for dense matrices, making it difficult to effectively utilize the sparse structure of banded matrices. This leads to computational redundancy and storage waste in practical applications. Especially in solving banded matrices, traditional methods cannot fully leverage the parallel advantages of GPUs, thus limiting performance. The main problems and drawbacks are as follows:
[0006] (1) Dense matrix algorithms are not well adapted to banded structures. Most existing LU decomposition algorithms are based on dense matrix design and fail to fully consider the sparsity and locality of data distribution of banded matrices. In the decomposition process, traditional methods often calculate all matrix elements, including zero elements, resulting in a large number of redundant operations. Especially on GPU platforms, this redundancy not only increases the computational burden but also wastes memory bandwidth, limiting the improvement of overall performance.
[0007] (2) Parallel computing strategies fail to effectively utilize the characteristics of strip matrix structures. Although GPUs possess powerful parallel processing capabilities, existing strip matrix decomposition methods still employ strategies for dense matrices in terms of task partitioning and thread scheduling, without specifically optimizing for the bandwidth characteristics and data locality of strip matrices. For example, during Panel decomposition and Schur complement (submatrix update after block elimination), traditional methods struggle to achieve efficient fine-grained parallelism while maintaining numerical stability, resulting in insufficient utilization of GPU computing resources. Specifically, on the one hand, existing task partitioning strategies fail to fully consider the distribution characteristics of non-zero elements in strip matrices, leading to unbalanced thread loads, with some threads processing valid data while others remain idle; on the other hand, during the Schur complement update stage, traditional parallel modes cannot fully utilize the limited range characteristics of the strip matrix update region, causing unnecessary synchronization overhead and memory contention. This low parallel efficiency is particularly pronounced when processing medium-bandwidth matrices, failing to fully leverage the large-scale parallel advantages of GPUs and hindering the achievement of ideal computational throughput.
[0008] (3) Fragmentation of computational process and excessive kernel function scheduling overhead. Existing implementations typically break down the various steps of LU decomposition of striped matrices (such as intra-block decomposition, column vector scaling, and trailing matrix updates) into multiple independent GPU kernel functions that are executed sequentially. This coarse-grained task partitioning leads to severe fragmentation of the computational process, resulting in frequent kernel function startup and synchronization overhead. Especially when processing small- to medium-sized or medium-bandwidth striped matrices, the actual effective computational load of each kernel function is often low, causing kernel function scheduling overhead to account for a significant proportion of the total time, making it impossible to fully utilize the GPU's streaming processing and computation-transfer overlap capabilities. In addition, global memory synchronization points between kernel functions also disrupt the continuity of computation, limiting further improvements in overall performance. Summary of the Invention
[0009] To address the problems of high computational redundancy, low parallel efficiency, and poor GPU architecture adaptability in traditional LU decomposition algorithms when processing striped matrices, this invention proposes a fusion optimization method and system for striped matrix LU decomposition. By combining block partitioning with computational operation fusion, the method fully adapts to the sparse structure of striped matrices and the characteristics of GPU hardware, significantly improving the computational performance and resource utilization of striped matrix LU decomposition on GPU platforms.
[0010] To achieve the above-mentioned technical effects, on the one hand, this invention provides a method for LU decomposition and fusion optimization of a strip matrix, comprising the following steps:
[0011] S1. Based on the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix, a block partitioning strategy based on a right-looking structure is generated; the block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size; and the data outside the bandwidth involved in the update is transferred and calculated through an auxiliary buffer.
[0012] S2. The SCAL and GER operations of the Panel decomposition stage in each iteration are integrated into a single GPU kernel function for execution. The execution of the integrated kernel function includes: the first thread block performs the SCAL operation on the pivot column in parallel, and then multiple thread blocks execute the GER operation in parallel to update the tail submatrix, wherein each thread block is responsible for updating one column in the tail submatrix. During the execution, the intermediate results generated by the SCAL operation are temporarily stored in a register and used for subsequent GER update calculations to reduce global memory access.
[0013] S3. Based on the block partitioning strategy and the fusion kernel function, generate and execute the LU decomposition process of the strip matrix; the execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, uniformly calling the fusion kernel to complete the panel decomposition, and calling the optimized matrix update kernel to complete the tail matrix update based on the block partitioning strategy; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed.
[0014] Furthermore, the block partitioning strategy also includes: during the block decomposition phase, a fine-grained thread allocation rule is adopted to dynamically configure thread resources according to the size of the currently processed column block; for strip matrix structures, by analyzing the distribution of elements to be calculated, only the corresponding number of threads are started for the regions containing non-zero elements, and each thread is responsible for processing the calculation task of one valid matrix element.
[0015] Furthermore, the block partitioning strategy also includes: in the tail matrix update stage, using coarse-grained parallel rules to divide the update region into several sub-blocks, with each thread block responsible for solving the triangular matrix or general matrix of one sub-block.
[0016] Furthermore, the step of transferring and calculating the out-of-bandwidth data involved in the update through the auxiliary buffer specifically includes:
[0017] Data outside the bandwidth that cannot be directly accessed due to the compressed storage format is copied to the workspaces work13 and work31, and the results are written back to the main matrix after the calculation is completed. Furthermore, the update scope of each iteration is restricted to the strip region, specifically: in each iteration, only the submatrix located in the lower right corner of the current processing block and within the strip region is updated.
[0018] Furthermore, step S2 also includes: before performing the GER operation, the fusion kernel function dynamically calculates the number of columns of the tail submatrix that needs to be updated to determine the actual execution range.
[0019] Furthermore, when the total size of the matrix is less than 2048, the block size is 16; when the total size of the matrix is greater than or equal to 2048, the block size is 32.
[0020] Furthermore, the optimized matrix update kernel described in step S3 includes a TRSM kernel for trigonometric solving and a GEMM kernel for general matrix multiplication.
[0021] On the other hand, based on the same inventive structure, the present invention also provides a strip matrix LU decomposition and fusion optimization system for implementing the method described above, comprising:
[0022] The block partitioning strategy generation module is used to generate a block partitioning strategy based on a right-looking structure according to the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix. The block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size. Furthermore, an auxiliary buffer is used to transfer and calculate the out-of-bandwidth data involved in the update.
[0023] The fusion kernel execution module is used to integrate the SCAL and GER operations of the Panel decomposition phase in each iteration into a single GPU kernel function. The execution of the fusion kernel function includes: the first thread block performs the SCAL operation on the pivot column in parallel, and then multiple thread blocks execute the GER operation in parallel to update the tail submatrix, where each thread block is responsible for updating one column in the tail submatrix. During the execution, the intermediate results generated by the SCAL operation are temporarily stored in registers and used for subsequent GER update calculations to reduce global memory access.
[0024] The process execution control module is used to generate and execute the LU decomposition process of the strip matrix based on the block partitioning strategy and the fusion kernel function. The execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, uniformly calling the fusion kernel to complete the panel decomposition, and calling the optimized matrix update kernel to complete the tail matrix update based on the block partitioning strategy; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed.
[0025] The method and system for fusion optimization of strip matrix LU decomposition described in this invention first generates a block partitioning strategy based on a right-looking structure, strictly limiting the computational scope of each iteration to the strip region, and handling out-of-bandwidth data through an auxiliary buffer. Then, the SCAL and GER operations in panel decomposition are fused into a single kernel function. After the first thread block completes SCAL, multiple thread blocks execute GER in parallel, and intermediate results are reused through registers to reduce global memory access. Finally, based on the above strategy and kernel assembly execution flow, the block size is dynamically determined, and the fusion kernel and the optimized matrix update kernel are called sequentially in each iteration, progressing along the main diagonal until decomposition is complete. This invention effectively solves the computational redundancy and parallel efficiency bottleneck problems of strip matrix LU decomposition on GPU platforms. Attached Figure Description
[0026] Figure 1 This is a flowchart illustrating the steps of the LU decomposition and fusion optimization method for a strip matrix provided in an embodiment of the present invention.
[0027] Figure 2 This is a schematic diagram of the structure of the strip matrix LU decomposition and fusion optimization system provided in an embodiment of the present invention. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0029] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.
[0030] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.
[0031] In recent years, LU decomposition of striped matrices has demonstrated increasingly important application value in engineering computing and scientific simulations. However, traditional LU decomposition algorithms are mainly designed for dense matrices, and when ported to GPU platforms to process striped matrices, they face multiple challenges such as computational redundancy, low parallel efficiency, and memory access mismatch. Existing methods cannot fully utilize the sparsity characteristics of striped matrices and the massively parallel architecture of GPUs, resulting in low utilization of computing resources and limited performance improvement. To address this, this invention provides a fusion optimization method and system for LU decomposition of striped matrices. By introducing a block partitioning strategy based on a right-looking structure, the block size can be adjusted according to the matrix size and bandwidth characteristics, improving data locality while avoiding redundant computation of zero elements. In the execution phase, by merging the column vector scaling and rank-1 update key operations into a single GPU kernel function, the number of kernel function launches and global memory access overhead are effectively reduced, achieving full scheduling of GPU computing resources.
[0032] To enable those skilled in the art to reproduce and implement the present invention, the method and system for LU decomposition and fusion optimization of the strip matrix will be described in detail below with reference to the accompanying drawings and specific embodiments. These embodiments are specific illustrations of the present invention, and their descriptions are helpful in understanding the present invention, but should not be construed as limiting the present invention.
[0033] Figure 1This invention illustrates a method for optimizing the LU decomposition of striped matrices using an embodiment of the present invention. This method addresses issues such as high computational redundancy, low parallel efficiency, and poor storage access in striped matrix LU decomposition on GPU platforms. The overall process includes three core steps: block partitioning strategy generation, computational operation fusion, and execution plan generation and performance evaluation. This ensures that striped matrix LU decomposition achieves high performance under different matrix sizes and bandwidth configurations. The method steps are as follows:
[0034] S1: Based on the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix, a block partitioning strategy based on a right-looking structure is generated; the upper and lower bandwidths specifically include the lower bandwidth kl and the upper bandwidth ku; the block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size; and the data outside the bandwidth involved in the update is transferred and calculated through an auxiliary buffer.
[0035] The target graphics processor is a GPU, and the key hardware characteristics of the target graphics processor include the number of computing units, the capacity of shared memory, the size of the register file, and the memory hierarchy.
[0036] This embodiment restricts the update scope of each iteration to a strip region. Specifically, in each iteration, only the submatrix located in the lower right corner of the current processing block and within the strip region is updated. The process of transferring and calculating the out-of-bandwidth data involved in the update through the auxiliary buffer specifically involves using the work13 and work31 buffers for temporary data storage, calculation, and write-back.
[0037] The block partitioning strategy further includes: in the intra-block decomposition stage, using fine-grained thread allocation rules to dynamically configure thread resources according to the size of the currently processed column block; for strip matrix structures, by analyzing the distribution of elements to be calculated, starting only the corresponding number of threads for regions containing non-zero elements, and each thread is responsible for processing the calculation task of one valid matrix element; and in the tail matrix update stage, using coarse-grained parallel rules to divide the update region into several sub-blocks, with each thread block responsible for the triangular matrix solution or general matrix solution calculation of one sub-block.
[0038] The process of transferring and calculating the out-of-bandwidth data involved in the update through the auxiliary buffer is as follows: the out-of-bandwidth data that cannot be directly accessed due to the compressed storage format is copied to the work13 and work31 work areas, and after the calculation is completed, the result is written back to the main matrix.
[0039] This embodiment analyzes the number of GPU cores, memory capacity at each level, and matrix size, combined with the inherent lower bandwidth kl and upper bandwidth ku of the striped matrix, to determine a basic computing unit size, i.e., the block size, that is adapted to the hardware's parallel capabilities. Based on this, a "right-looking" computing framework is adopted to generate a block partitioning strategy: the entire decomposition process is organized as an iteration along the main diagonal of the matrix, with the block size as the step size. In each iteration, the system strictly updates only the submatrix in the lower right corner of the current processing block that is within the bandwidth range of [kl, ku], eliminating invalid operations on out-of-band zero elements from the algorithm's root. To achieve this precise update, for out-of-band data that is discontinuous under the striped compressed storage format and exceeds the direct access range, the relevant data can be copied to buffers work13 and work31 for calculation, and then written back to the corresponding position in the original matrix, thus ensuring the correctness of the calculation without destroying the compressed storage.
[0040] In the specific implementation process, it is first necessary to conduct an in-depth analysis of the hardware characteristics of the target GPU platform, including key parameters such as the number of computing units, shared memory capacity, register file size, and memory hierarchy. Based on these hardware characteristics, a block partitioning strategy library suitable for strip matrix factorization is constructed to provide basic support for subsequent parallel computing.
[0041] This embodiment employs a block partitioning algorithm based on a right-looking structure. The core idea of this algorithm is to divide the strip matrix into multiple computational blocks along the main diagonal, with each block's processing affecting only a limited number of adjacent regions. The optimization of this scheme is mainly reflected in three aspects:
[0042] Firstly, regarding data update range control, the system controls the data update range by dividing the strip matrix into blocks, avoiding updating the matrix globally in each iteration. This improves overall computational efficiency and data locality. Specifically, for a matrix with upper and lower bandwidths of kl and ku respectively, its non-zero elements are restricted to the main diagonal and its vicinity within the strip region. When implementing the block partitioning algorithm based on the right-looking structure, the system updates only the sub-matrix located within the strip region to the lower right of the current processing block in each iteration. This is achieved by directly introducing the kl and ku parameters when calculating the cycle boundary, thus fundamentally avoiding any access to or calculation of zero elements outside the strip region at the algorithm level.
[0043] Secondly, regarding the hierarchical thread scheduling strategy, the system designs differentiated parallel schemes for different stages of LU decomposition of strip matrices. Specifically, in the panel factorization stage, a fine-grained thread allocation strategy is adopted, dynamically configuring thread resources according to the current column block size. The SIMD (Single Instruction, Multiple Data) characteristics within the thread bundle are utilized to achieve efficient vector processing. For the special structure of strip matrices, the system analyzes the actual distribution of elements to be calculated and allocates an appropriate number of threads to each effective computation region. Taking a column block with NB (Block size) = 32 as an example, the system starts the corresponding number of threads only for regions containing non-zero elements based on the bandwidth characteristics of the strip matrix. Each thread is responsible for processing the computation task of one effective matrix element. This dynamic thread allocation mechanism ensures a precise match between computing resources and actual computing needs, avoiding the waste of thread resources and guaranteeing the optimization of computing density. In the tail matrix update stage, a coarse-grained parallel strategy is adopted, dividing the update region into several sub-blocks. Each thread block is responsible for the TRSM (triangular matrix solving) / GEMM (generic matrix multiplication) calculation of one sub-block. This hybrid scheduling mechanism enables the full utilization of the GPU's parallel computing capabilities in the computationally intensive stage and maximizes memory bandwidth utilization in the data-intensive stage.
[0044] Finally, in terms of data layout optimization, a suitable data layout for the strip matrix is designed. By arranging data reasonably, global memory access conflicts are reduced, ensuring that GPU threads can achieve efficient and continuous access to global memory during critical decomposition and update calculations. Specifically, this solution adjusts the data alignment method and access mode so that multiple threads within the same thread bundle can merge reading or writing to contiguous memory blocks at once, significantly reducing the number of memory accesses and access conflicts.
[0045] S2: The SCAL and GER operations of the Panel decomposition phase in each iteration are integrated into a single GPU kernel function for execution. The execution of the integrated kernel function includes: the first thread block performs the SCAL operation on the pivot column in parallel, and then multiple thread blocks execute the GER operation in parallel to update the tail submatrix, where each thread block is responsible for updating one column in the tail submatrix. During execution, the intermediate results generated by the SCAL operation are temporarily stored in a register and used for subsequent GER update calculations to reduce global memory access.
[0046] Step S2 further includes: before performing the GER operation, the fusion kernel function dynamically calculates the number of columns of the tail submatrix that need to be updated to determine the actual execution range.
[0047] In practice, after generating the block partitioning strategy, the system enters the fusion kernel design and execution optimization phase. This phase addresses the key computational bottlenecks in the LU decomposition of banded matrices by employing kernel fusion technology and multi-level parallel strategies to significantly improve computational efficiency.
[0048] The system identifies computationally intensive and memory-intensive operations during the decomposition process and focuses on in-depth optimization of the column vector scaling (SCAL) and rank-1 update (GER) operations in the Panel decomposition stage. In traditional implementations, these two closely related computational operations are split into independent GPU kernel functions executed sequentially: the SCAL kernel function is called first to scale the pivot column, and after its execution and synchronization, the GER kernel function is launched to perform the matrix update operation. This separate execution mode leads to frequent kernel function startup overhead, device synchronization waiting, and repeated global memory reads and writes of intermediate results, severely limiting overall computational performance.
[0049] To address the aforementioned issues, this embodiment provides a unified "SCAL+GER" fused kernel design scheme. The core idea of this scheme is to integrate the originally separate computational stages into a single kernel function, achieving performance optimization by eliminating unnecessary kernel function boundaries. In the specific implementation, multiple threads within the first thread block (Block0) process each element in the current pivot column in parallel, completing the SCAL operation and achieving row-wise scaling and normalization. Within each block, through dim3 threads(km,1) configuration, each thread corresponds to an element in the pivot column to be scaled or updated, achieving column-level parallelism (element-wise processing). Subsequently, the GER operation stage is executed in parallel through multiple thread blocks: each thread block corresponds to a column in the tail submatrix, and its threads process each element in that column in parallel, thereby achieving column-level parallel updates.
[0050] In the data processing flow of the fused kernel, the system employs an efficient data reuse strategy. After a thread bundle reads the pivot column data from global memory, it immediately performs a SCAL operation within the kernel function, temporarily storing the scaled result in a high-speed register instead of writing it back to global memory. Subsequently, the intermediate result stored in the register is used directly for GER update calculation, effectively avoiding the redundant memory access overhead of writing the SCAL result back to global memory and then rereading it for the GER operation, as in traditional schemes. This design reduces the operation that originally required two global memory accesses to one, significantly reducing memory bandwidth pressure. To further optimize execution efficiency, the system also designs a hierarchical thread cooperation mechanism. Within the thread bundle, thread index mapping ensures that access to matrix elements conforms to memory merging requirements, maximizing memory access efficiency. Simultaneously, leveraging the thread-level parallelism of the GPU, vector scaling and matrix update operations can be pipelined and executed within the same batch of threads, reducing thread scheduling overhead and improving the utilization of computing units.
[0051] Regarding the optimization of the computational range of the fusion kernel, the system dynamically determines the actual execution range of the GER operation by precisely calculating the number of columns that need to be updated, col_offset = jm - jj - 1. This optimization ensures that the system only performs update operations on valid columns within the non-zero region of the striped matrix, completely breaking away from the indiscriminate processing of the entire matrix range in traditional dense matrix update modes. Through this precise range control, not only are the number of floating-point operations significantly reduced, but unnecessary memory accesses are also greatly reduced.
[0052] S3: Based on the block partitioning strategy and fusion kernel function, generate and execute the LU decomposition process of the strip matrix. The execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, uniformly calling the fusion kernel to complete the panel decomposition, and calling the optimized matrix update kernel based on the block partitioning strategy to complete the tail matrix update; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed. Wherein, when the total size of the matrix is less than 2048, the block size is 16; when the total size of the matrix is greater than or equal to 2048, the block size is 32; the optimized matrix update kernel includes a TRSM kernel for trigonometric solving and a GEMM kernel for general matrix multiplication.
[0053] In this embodiment, based on the preprocessing results of steps S1 and S2, the system completes the final computational scheme deployment through the execution plan generation module. First, the system determines the optimal block size based on the matrix size: when the matrix size is less than 2048, a block partitioning scheme of NB=16 is used; when the matrix size is greater than or equal to 2048, a block partitioning scheme of NB=32 is used. Second, during the decomposition process, a fusion kernel technology combining SCAL and GER operations is uniformly applied, merging column vector scaling and rank-1 updates into a single GPU kernel function for execution.
[0054] During the performance verification phase, the system compared and evaluated this embodiment with traditional implementations through a standardized testing process. Specifically, the method described in this embodiment was implemented and its performance verified on a domestic DCU platform (ZIFANG Z100SM). Experimental results show that, under fixed block size (NB=32) and fusion kernel optimization conditions, the method described in this embodiment significantly outperforms traditional LAPACK and MKL implementations under various matrix sizes and bandwidth configurations, with performance improvements of 20 to 40 times. Compared with the highly optimized ROCSOLVER dense matrix factorization algorithm, the method described in this embodiment also exhibits superior sustainability performance in large-scale, high-bandwidth scenarios, reducing runtime by approximately 2 to 2.8 times, fully demonstrating its practical value in the field of high-performance sparse computing. Therefore, this embodiment demonstrates significant performance advantages in various test scenarios, especially under large-scale, high-bandwidth conditions, verifying the effectiveness and reliability of the generated execution plan.
[0055] Figure 2 This invention illustrates a strip matrix LU decomposition and fusion optimization system 100 according to another embodiment of the present invention. The system 100 is used to implement the methods described in the above embodiments and includes a block partitioning strategy generation module 10, a fusion kernel execution module 20, and a process execution control module 30, wherein:
[0056] The block partitioning strategy generation module 10 is used to generate a block partitioning strategy based on a right-looking structure according to the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix. The block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size. Furthermore, an auxiliary buffer is used to transfer and calculate the out-of-bandwidth data involved in the update. The fusion kernel execution module 20 is used to integrate the SCAL and GER operations of the Panel decomposition stage in each iteration into a single GPU kernel function for execution. The execution of the fusion kernel function includes: the first thread block performing the SCAL operation on the pivot column in parallel, and then... The GER operation is executed in parallel by multiple thread blocks to update the tail submatrix, with each thread block responsible for updating one column in the tail submatrix. During execution, the intermediate results generated by the SCAL operation are temporarily stored in registers and used for subsequent GER update calculations to reduce global memory access. The process execution control module 30 is used to generate and execute the strip matrix LU decomposition process based on the block partitioning strategy and the fusion kernel function. The execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, the fusion kernel is uniformly called to complete the panel decomposition, and the optimized matrix update kernel is called based on the block partitioning strategy to complete the tail matrix update; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed.
[0057] The specific implementation and operation process of each module in the system 100 described in this embodiment can be understood by referring to the relevant descriptions in the foregoing method embodiments, and all of them can achieve the functions and effects achieved by the corresponding method steps. For the sake of simplicity and to avoid repetition, they will not be described again here.
[0058] In summary, the strip matrix LU decomposition fusion optimization method and system described in this invention first adopts a block partitioning strategy based on a right-looking structure as the overall framework, dividing the matrix into blocks along the main diagonal, and controlling each iteration to only update the local region in the lower right corner of the current block; this range is precisely constrained by the variable ju within the strip region defined by the upper and lower bandwidths of the matrix, thereby fundamentally avoiding redundant calculations and accesses to out-of-band zero elements; for out-of-band data that is unavoidable in the update operation, it is transferred and calculated through an auxiliary buffer, ensuring data integrity and calculation correctness under the compressed storage format; secondly, to address the performance bottleneck of panel decomposition during the decomposition process, an innovative fusion kernel design is proposed: the two core operations, SCAL and GER, which were originally executed serially, are merged into a single GPU kernel function for parallel execution; this design, through the combination of column-level and thread-level parallelism and adapting to the boundary control of the strip structure, significantly improves the computational throughput and resource utilization of the panel decomposition stage. In summary, this invention effectively solves the problems of computational redundancy and low parallel efficiency faced by traditional methods on strip matrices by combining macroscopic constrained update strategies with microscopic fusion kernel optimization.
[0059] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0061] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.
Claims
1. A method for optimizing the LU decomposition of a strip matrix, characterized in that, Including the following steps: S1. Based on the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix, a block partitioning strategy based on a right-looking structure is generated; the block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size; and the data outside the bandwidth involved in the update is transferred and calculated through an auxiliary buffer. S2. In each iteration, the SCAL and GER operations of the Panel decomposition phase are integrated into a single GPU kernel function for execution. The execution of its fusion kernel function includes: the first thread block performs the SCAL operation on the pivot column in parallel, and then multiple thread blocks perform the GER operation in parallel to update the tail submatrix, wherein each thread block is responsible for updating one column in the tail submatrix; during the execution, the intermediate results generated by the SCAL operation are temporarily stored in a register and used for subsequent GER update calculations to reduce global memory access. S3. Based on the block partitioning strategy and the fusion kernel function, generate and execute the LU decomposition process of the strip matrix; the execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, uniformly calling the fusion kernel to complete the panel decomposition, and calling the optimized matrix update kernel to complete the tail matrix update based on the block partitioning strategy; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed.
2. The method according to claim 1, characterized in that, The block partitioning strategy also includes: during the block decomposition phase, a fine-grained thread allocation rule is adopted to dynamically configure thread resources according to the size of the currently processed column block; for strip matrix structures, by analyzing the distribution of elements to be calculated, only the corresponding number of threads are started for the regions containing non-zero elements, and each thread is responsible for processing the calculation task of one valid matrix element.
3. The method according to claim 1, characterized in that, The block partitioning strategy also includes: in the tail matrix update stage, a coarse-grained parallel rule is used to divide the update region into several sub-blocks, and each thread block is responsible for solving the triangular matrix or general matrix of one sub-block.
4. The method according to claim 1, characterized in that, The process of transferring and calculating the out-of-bandwidth data involved in the update through an auxiliary buffer specifically includes: Data outside the bandwidth that cannot be directly accessed due to the compressed storage format is copied to the work13 and work31 workspaces, and the results are written back to the main matrix after the calculation is completed.
5. The method according to claim 1, characterized in that, The update scope of each iteration is restricted to the strip region, specifically including: in each iteration, only the submatrix located in the lower right corner of the current processing block and within the strip region is updated.
6. The method according to claim 1, characterized in that, Step S2 further includes: before performing the GER operation, the fusion kernel function dynamically calculates the number of columns of the tail submatrix that need to be updated to determine the actual execution range.
7. The method according to claim 1, characterized in that, When the total size of the matrix is less than 2048, the block size is 16; when the total size of the matrix is greater than or equal to 2048, the block size is 32.
8. The method according to claim 1, characterized in that, The optimized matrix update kernel described in step S3 includes a TRSM kernel for trigonometric solving and a GEMM kernel for general matrix multiplication.
9. A strip matrix LU decomposition and fusion optimization system for implementing the method as described in any one of claims 1 to 8, characterized in that, Including: The block partitioning strategy generation module is used to generate a block partitioning strategy based on a right-looking structure according to the hardware characteristics of the target graphics processor and the upper and lower bandwidths of the strip matrix. The block partitioning strategy is used to control the iterative calculation along the main diagonal of the strip matrix, wherein the processing and update range of each iteration is limited to the strip region defined by the upper and lower bandwidths and the block size. Furthermore, an auxiliary buffer is used to transfer and calculate the out-of-bandwidth data involved in the update. The fusion kernel execution module is used to integrate the SCAL and GER operations of the Panel decomposition phase in each iteration into a single GPU kernel function for execution. The execution of its fusion kernel function includes: the first thread block performs the SCAL operation on the pivot column in parallel, and then multiple thread blocks perform the GER operation in parallel to update the tail submatrix, wherein each thread block is responsible for updating one column in the tail submatrix; during the execution, the intermediate results generated by the SCAL operation are temporarily stored in a register and used for subsequent GER update calculations to reduce global memory access. The process execution control module is used to generate and execute the LU decomposition process of the strip matrix based on the block partitioning strategy and the fusion kernel function. The execution of the process includes: determining the block size value according to the total size of the matrix; in each iteration of the decomposition, uniformly calling the fusion kernel to complete the panel decomposition, and calling the optimized matrix update kernel to complete the tail matrix update based on the block partitioning strategy; iteratively advancing along the main diagonal of the matrix until the matrix is completely decomposed.